An IP integrated system

Abstract

The present application relates to the field of chip design technology, and in particular to an IP integration system, the system comprising: a main module as an integrated target module and several submodules to be integrated, a database, a processor, and a memory storing a computer program, and when the computer program is executed by the processor, the following steps are implemented: determining an object module from a submodule, determining a mapping statement sequence corresponding to the object module from a database, for a connection line name corresponding to each port in the object module, sequentially using mapping statements in the mapping statement sequence to perform mapping condition detection and mapping instruction processing, updating the connection line name, and after processing all submodules, logically automatically connecting the ports with the same connection line name to obtain an integrated result. The connection line names of the submodule ports are mapped by the mapping statement sequence, so that the port connection line names of the submodules are the same, and multiple submodules are integrated into the main module, thereby improving the efficiency of IP integration.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to an IP integration system. Background Art

[0002] In the chip design scenario, it is usually necessary to integrate multiple IP cores in the chip so that the chip can realize diversified functions. IP cores can be understood as mature circuit design modules. Applying IP cores in the chip design process can effectively reduce redundant design costs, reduce the risk of errors, and improve chip design efficiency.

[0003] IP cores usually include multiple ports. When an IP core is integrated into a chip design, the ports of the IP core and the ports with which it has a signal communication relationship need to be connected through connecting wires. During the IP integration process, since there is no unified format for naming the ports of the IP core, the port naming methods of IP cores from different sources often differ. Therefore, it is usually necessary to manually determine the connection relationship between the ports, and then write the same connection line name for the ports with a connection relationship to achieve the connection between the ports. Obviously, the manual writing method will introduce additional human resource consumption, and the manual method is less efficient. Therefore, how to improve the efficiency of IP integration has become an urgent problem to be solved. Summary of the invention

[0004] In view of the above technical problems, the technical solution adopted by the present invention is:

[0005] An IP integration system, the system comprising: a main module a as an integration target module, a submodule set B to be integrated = {b1, b2, ..., b n , …, b N}, a database, a processor and a memory storing a computer program, wherein b n is the nth submodule, n is an integer in the range of [1, N], N is the number of submodules included in the submodule set B, and the database includes the port name set Pa of the main module a = {pa1, pa2, ..., pa m ,…,pa M}, submodule b n The port name set Pb n ={pb n 1, pb n 2, ..., pb n q(n) , …, pb n Q(n)} and b n The corresponding mapping statement sequence C n , C n =[c n 1, c n2, …, c n r(n) , …, c n R(n) ],pa m is the port name of the mth port of the main module a, m is an integer in the range of [1, M], M is the number of port names contained in Pa, pa m Corresponds to the connection line name wa m , pb n q(n) is the port name of the q(n)th port of the nth submodule, q(n) is an integer in the range [1, Q(n)], and Q(n) is Pb n The number of port names contained in pb n q(n) Corresponds to the connection line name wb n q(n) , C n is the mapping statement sequence corresponding to the nth submodule, c n r(n) is the r(n)th mapping statement in the nth mapping statement sequence, r(n) is an integer in the range [1, R(n)], and R(n) is C n contains the number of mapping statements, c n r(n) =[c n r(n)1 , c n r(n)2 ], c n r(n)1 C n The mapping condition in the r(n)th mapping statement, c n r(n)2 C n The mapping instruction in the r(n)th mapping statement in the computer program, when the computer program is executed by the processor, implements the following steps:

[0006] Step S101, initializing module identifier i=1.

[0007] Step S102, with b i As an object module, determine b i The corresponding mapping statement sequence C i , i is an integer in the range [1, N].

[0008] Step S103, initializing execution flag j=1.

[0009] Step S104, detect wb i q(i) Whether the mapping condition c is satisfied j i(j)1 .

[0010] Step S105, if wb i q(i) Satisfy the mapping condition c j i(j)1 , then execute step S106, otherwise, execute step S107.

[0011] Step S106, execute mapping instruction c j i(j)2 About wb i q(i) Map and get the mapping result wd i q(i) , use wd i q(i) Update wb i q(i) .

[0012] Step S107, update j=j+1, return to execute steps S104 to S106, until j=R(i)+1, and execute step S108.

[0013] Step S108, update i=i+1, return to execute steps S102 to S107, until i=N+1, and execute step S109.

[0014] Step S109, ports with the same connection line name are automatically connected logically to obtain an integration result.

[0015] Compared with the prior art, the present invention has obvious beneficial effects. By means of the above technical solution, an IP integration system provided by the present invention can achieve considerable technical advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects:

[0016] The present invention provides an IP integration system, which comprises: a main module as an integration target module and a plurality of submodules to be integrated, a database, a processor and a memory storing a computer program. When the computer program is executed by the processor, the following steps are implemented: an object module is determined from a plurality of submodules, a mapping statement sequence corresponding to the object module is determined from a database, for a connection line name corresponding to each port in the object module, mapping statements in the mapping statement sequence are used in turn to perform mapping condition detection and mapping instruction processing, the connection line name is updated, and after all submodules are processed, ports with the same connection line name are automatically connected logically to obtain an integration result.

[0017] It can be seen that the connection line names of the sub-module ports are mapped through a mapping statement sequence containing multiple mapping statements, so that the port connection line names of each sub-module are the same as the port connection line names of the main module, thereby realizing the integration of the main module and multiple sub-modules. Moreover, the mapping statement includes mapping conditions and mapping instructions. The mapping instructions are executed only when the mapping conditions are met, and the mapping conditions and mapping instructions can be flexibly configured, thereby improving the flexibility of name mapping. In addition, by using multiple mapping statements in sequence, name mapping can be achieved through multiple mappings, that is, it can be compatible with complex scenarios, thereby greatly improving the efficiency of IP integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 A flowchart of a computer program executed by a processor in an IP integration system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0021] This embodiment provides an IP integration system, which includes: a main module a as an integration target module, a submodule set B to be integrated = {b1, b2, ..., b n , …, b N}, a database, a processor and a memory storing a computer program, wherein b n is the nth submodule, n is an integer in the range of [1, N], N is the number of submodules included in the submodule set B, and the database includes the port name set Pa of the main module a = {pa1, pa2, ..., pa m ,…,pa M}, submodule b n The port name set Pb n ={pb n 1, pb n 2, ..., pb n q(n) , …, pbn Q(n)} and b n The corresponding mapping statement sequence C n , C n =[c n 1, c n 2, …, c n r(n) , …, c n R(n) ],pa m is the port name of the mth port of the main module a, m is an integer in the range of [1, M], M is the number of port names contained in Pa, pa m Corresponds to the connection line name wa m , pb n q(n) is the port name of the q(n)th port of the nth submodule, q(n) is an integer in the range [1, Q(n)], and Q(n) is Pb n The number of port names contained in pb n q(n) Corresponds to the connection line name wb n q(n) , C n is the mapping statement sequence corresponding to the nth submodule, c n r(n) is the r(n)th mapping statement in the nth mapping statement sequence, r(n) is an integer in the range [1, R(n)], and R(n) is C n contains the number of mapping statements, c n r(n) =[c n r(n)1 , c n r(n)2 ], c n r(n)1 C n The mapping condition in the r(n)th mapping statement, c n r(n)2 C n The mapping instructions in the r(n)th mapping statement in Figure 1 , is a flowchart of a computer program executed by a processor in an IP integration system provided by an embodiment of the present invention. When the computer program is executed by the processor, the following steps are implemented:

[0022] Step S101, initialization module identification i=1;

[0023] Step S102, with b i As an object module, determine b i The corresponding mapping statement sequence C i, i is an integer in the range [1, N];

[0024] Step S103, initializing execution flag j=1;

[0025] Step S104, detect wb i q(i) Whether the mapping condition c is satisfied j i(j)1 ;

[0026] Step S105, if wb i q(i) Satisfy the mapping condition c j i(j)1 , then execute step S106, otherwise, execute step S107;

[0027] Step S106, execute mapping instruction c j i(j)2 About wb i q(i) Map and get the mapping result wd i q(i) , use wd i q(i) Update wb i q(i) ;

[0028] Step S107, update j=j+1, return to execute steps S104 to S106, until j=R(i)+1, execute step S108;

[0029] Step S108, update i=i+1, return to execute steps S102 to S107, until i=N+1, execute step S109;

[0030] Step S109, ports with the same connection line name are automatically connected logically to obtain an integration result.

[0031] Among them, the main module a can refer to a module in which the connection line name corresponding to the port can be used as a reference naming method, and the sub-module can refer to a module that needs to map the connection line name corresponding to the port to a module that conforms to the reference naming method. The main module or any sub-module can include multiple ports, each port has a corresponding port name and connection line name. It should be noted that the implementer can flexibly determine the main module and sub-module according to actual conditions. For example, if the connection line names corresponding to the ports of several modules are the same or similar, then any module can be selected as the main module, thereby reducing the number of mappings of the connection line names corresponding to the sub-module ports, so as to further improve the IP integration efficiency.

[0032] The object module may refer to a module that is currently performing port connection line name mapping, and the mapping statement sequence corresponding to the object module may be used to map the connection line names corresponding to each port of the object module.

[0033] Specifically, for the connection line name corresponding to any port of the object module, the mapping statements in the mapping statement sequence corresponding to the object module are used in turn to process the connection line name. The processing process of the mapping statement includes mapping condition detection and mapping instruction execution. When the connection line name meets the mapping condition, the corresponding mapping instruction is executed, otherwise jump to the next mapping statement. It should be noted that after the connection line name executes the mapping instruction, the connection line name is updated with the result after executing the mapping instruction, so that when the next mapping statement is executed, the mapping condition detection is performed with the updated connection line name. The above method can be used to convert a single complex connection line name mapping into multiple simple connection line name mappings, so that this embodiment can simplify the setting of the mapping statement sequence as much as possible while being compatible with complex scenarios.

[0034] In a specific embodiment, c n r(n)1 Use the regular expression form.

[0035] Among them, the regular expression can be a set of special texts composed of letters and symbols. The regular expression can be used to find a string that meets the corresponding format. In this embodiment, c n r(n)1 Use the regular expression form to determine the connection line names that meet the corresponding format.

[0036] In this embodiment, the mapping statement sequence can use the connection relationship between the main module port and the sub-module port, and the name of the port connection line with the connection relationship as prior information, and determine the mapping statements in the mapping statement sequence by counting the prior information. Among them, if the mapping method and format of the connection line names corresponding to some ports are the same, they can be expressed by regular expressions.

[0037] Specifically, c n r(n)2 It can also be in the form of a regular expression, which means that it will match c n r(n)1 The format of the conditional connection line name is mapped to c n r(n)2 The corresponding format.

[0038] It should be noted that implementers can also use a preset string to represent c n r(n)1 , at this time, the connection line name needs to be exactly the same as c n r(n)1 Only when they are consistent, execute cn r(n)2 Similarly, implementers can also use a preset string to represent c n r(n)2 , at this time, satisfy c n r(n)1 The connection line names are directly converted to c n r(n)2 Similarly, implementers can also use a preset string to represent c n r(n)1 and c n r(n)2 , I will not go into details here.

[0039] In a specific embodiment, wa m With pa m Same, wb n q(n) Initial and pb n q(n) same.

[0040] The port name is initially used as the port connection line name. Since the port connection line name of the main module is not mapped, m Always with pa m The port connection line name of the submodule only needs to be consistent with the port name before mapping, that is, wb n q(n) Initial and pb n q(n) same.

[0041] In a specific embodiment, c n r(n)2 The corresponding mapping methods include at least: n q(n) Perform uppercase and lowercase conversion.

[0042] The mapping method may also include wb n q(n) Swap some characters in wb n q(n) The mapping method can be set by the implementer according to the c n r(n)2 Flexible determination can improve the generalization of this embodiment in application.

[0043] In a specific embodiment, when wb n q(n) When it is the first preset symbol, pb n q(n) The corresponding port is not connected to other ports.

[0044] Among them, some ports in the module may not be connected to other ports, so a first preset symbol is set to represent such ports, so that when the names of the connection lines corresponding to the ports are all the first preset symbols, the ports are not connected.

[0045] In a specific implementation, a belongs to the first level, B belongs to the second level, when wb n q(n) When it is the second preset symbol, pb n q(n) As the first level port, otherwise, pb n q(n) As the second level port.

[0046] Among them, since the chip design is usually multi-layered, this embodiment takes the level to which a belongs as the first level and the level to which B belongs as the second level. For the case where some ports of the sub-module need to be connected to the ports of the first level, a second preset symbol is set to represent such ports.

[0047] In a specific embodiment, the database also includes b n The corresponding module usage times g n , accordingly, the mapping instruction c n r(n)2 The corresponding mapping method is included in wb n q(n) Insert reference designator in .

[0048] Wherein, multiple identical submodules may be used during IP integration, and the reference identifier may be used to distinguish different usage times of the same submodule to avoid errors during connection.

[0049] Specifically, the implementer can set the reference identifier to x, where x can be [1, g n ], which can distinguish the different usage times of the same submodule.

[0050] Furthermore, when there are connections between corresponding ports of multiple identical submodules, a connection relationship can be established through a reference identifier. For example, after inserting the reference identifier x, mapping x=x+1, the submodule used last time can be connected to the submodule used next time by port.

[0051] In this embodiment, the connection line names of the sub-module ports are mapped through a mapping statement sequence including multiple mapping statements, so that the port connection line names of each sub-module are the same as the port connection line names of the main module, thereby realizing the integration of the main module and multiple sub-modules. Moreover, the mapping statement includes mapping conditions and mapping instructions. The mapping instructions are executed only when the mapping conditions are met, and the mapping conditions and mapping instructions can be flexibly configured, thereby improving the flexibility of name mapping. In addition, by using multiple mapping statements in sequence, name mapping can be achieved through multiple mappings, that is, it can be compatible with complex scenarios, thereby greatly improving the efficiency of IP integration.

[0052] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. An IP integration system, characterized in that: The system comprises: a main module a as an integrated target module, a submodule set B to be integrated = {b1, b2, ..., b n , …, b N }, a database, a processor and a memory storing a computer program, wherein b n is the nth submodule, n is an integer in the range of [1, N], N is the number of submodules included in the submodule set B, and the database includes the port name set Pa of the main module a = {pa1, pa2, ..., pa m ,…,pa M }, submodule b n The port name set Pb n ={pb n 1, pb n 2, ..., pb n q(n) , …, pb n Q(n) } and b n The corresponding mapping statement sequence C n , C n =[c n 1, c n 2, …, c n r(n) , …, c n R(n) ],pa m is the port name of the mth port of the main module a, m is an integer in the range of [1, M], M is the number of port names contained in Pa, pa m Corresponds to the connection line name wa m , pb n q(n) is the port name of the q(n)th port of the nth submodule, q(n) is an integer in the range [1, Q(n)], and Q(n) is Pb n The number of port names contained in pb n q(n) Corresponds to the connection line name wb n q(n) , C n is the mapping statement sequence corresponding to the nth submodule, c n r(n) is the r(n)th mapping statement in the nth mapping statement sequence, r(n) is an integer in the range [1, R(n)], and R(n) is C n contains the number of mapping statements, c n r(n) =[c n r(n)1 , c n r(n)2 ], c n r(n)1 C n The mapping condition in the r(n)th mapping statement, c n r(n)2 C n The mapping instruction in the r(n)th mapping statement in the computer program, when the computer program is executed by the processor, implements the following steps: Step S101, initialization module identification i=1; Step S102, with b i As an object module, determine b i The corresponding mapping statement sequence C i , i is an integer in the range [1, N]; Step S103, initializing execution flag j=1; Step S104, detect wb i q(i) Whether the mapping condition c is satisfied j i(j)1 ; Step S105, if wb i q(i) Satisfy the mapping condition c j i(j)1 , then execute step S106, otherwise, execute step S107; Step S106, execute mapping instruction c j i(j)2 About wb i q(i) Map and get the mapping result wd i q(i) , use wd i q(i) Update wb i q(i) ; Step S107, update j=j+1, return to execute steps S104 to S106, until j=R(i)+1, execute step S108; Step S108, update i=i+1, return to execute steps S102 to S107, until i=N+1, execute step S109; Step S109, ports with the same connection line name are automatically connected logically to obtain an integration result.

2. The IP integration system according to claim 1, characterized in that: c n r(n)1 Use the regular expression form.

3. The IP integration system according to claim 1, characterized in that: w m With pa m Same, wb n q(n) Initial and pb n q(n) same.

4. The IP integration system according to claim 1, characterized in that: c n r(n)2 The corresponding mapping methods include at least: n q(n) Perform uppercase and lowercase conversion.

5. The IP integration system according to claim 1, characterized in that: When wb n q(n) When it is the first preset symbol, pb n q(n) The corresponding port is not connected to other ports.

6. The IP integration system according to claim 1, characterized in that: a belongs to the first level, B belongs to the second level, when wb n q(n) When it is the second preset symbol, pb n q(n) As the first level port, otherwise, pb n q(n) As the second level port.

7. The IP integration system according to claim 1, characterized in that: The database also includes b n The corresponding module usage times g n , accordingly, the mapping instruction c n r(n)2 The corresponding mapping method is included in wb n q(n) Insert reference designator in .

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