Packaging substrate and manufacturing method thereof

Abstract

The present invention provides a packaging substrate and a method for manufacturing the same. The packaging substrate includes a first circuit structure and a second circuit structure with the same circuit specifications formed on opposite sides of a core board, and a wiring structure with another circuit specification formed on the first circuit structure, and the number of wiring layers of the second circuit structure is greater than the number of wiring layers of the first circuit structure, so as to form an asymmetric packaging substrate, so that the configuration of the wiring structure can avoid the problem of warping of the packaging substrate due to uneven force.

Description

Technical Field

[0001] The invention relates to a packaging substrate for carrying a chip, and in particular to an asymmetric packaging substrate and a manufacturing method thereof. Background Art

[0002] The technologies currently used in the field of chip packaging include packaging modules such as chip scale packaging (CSP), direct chip attached packaging (DCA) or multi-chip module packaging (MCM). As the functional requirements of terminal products increase, semiconductor chips need to have more input / output (I / O) contacts, so the number of external pads on the packaging substrate used to carry semiconductor chips also increases accordingly.

[0003] Figure 1 FIG. 1 is a cross-sectional view of an existing packaging substrate 1. Figure 1 As shown, the packaging substrate 1 includes a core board 10 having a first side 10a and a second side 10b opposite to each other, and a first circuit structure 11 is formed on the first side 10a of the core board 10, and a second circuit structure 12 is formed on the second side 10b of the core board 10, wherein the core board 10 has a plurality of conductive through holes 100 connecting the first side 10a and the second side 10b to electrically connect the first circuit structure 11 and the second circuit structure 12, and the first circuit structure 11 and the second circuit structure 12 are both manufactured by a conventional build-up process to manufacture circuits with the same line width / line spacing, but the number of wiring layers of the first circuit structure 11 is different from the number of wiring layers of the second circuit structure 12 to form an asymmetric packaging substrate 1.

[0004] Since the number of wiring layers of the first circuit structure 11 is less than the number of wiring layers of the second circuit structure 12, the coefficient of thermal expansion (CTE) of the second circuit structure 12 is greater than the CTE of the first circuit structure 11, causing the package substrate 1 to be easily warped. Therefore, the first circuit structure 11 is configured with a buffer layer as the first insulating layer 110 to balance the stress distribution of the second insulating layer 120 made of conventional dielectric material used in the second circuit structure 12, so that the package substrate 1 will not be excessively warped.

[0005] However, in the existing packaging substrate 1, a buffer material is required to be used to make the first insulating layer 110, which not only increases the production cost, but also the roughness and flatness of the buffer material are different from the roughness and flatness of conventional dielectric materials. Therefore, when using the same equipment, the flatness of the first and second insulating layers 110, 120 cannot meet the requirements at the same time, resulting in poor accuracy of the wiring position, thereby affecting the reliability of the subsequent packaging of the semiconductor chip.

[0006] Furthermore, the first insulating layer 110 and the second insulating layer 120 are smoothed by brushing, but the overall structure is easily deformed during the brushing process, and the surface circuits are easily brushed and disconnected, and even the stress generated by brushing may cause internal circuits to break.

[0007] Therefore, how to overcome the various problems of the above-mentioned existing manufacturing methods has become a topic that is urgently needed to be solved. Summary of the invention

[0008] In view of the various defects of the above-mentioned prior art, the present invention provides a packaging substrate, including: a core board body, having a first side and a second side opposite to each other and at least one conductive through hole connecting the first side and the second side; a first circuit structure, arranged on the first side of the core board body and electrically connected to the conductive through hole; a second circuit structure, arranged on the second side of the core board body and electrically connected to the conductive through hole, wherein the circuit specification of the first circuit structure is the same as the circuit specification of the second circuit structure, and the number of wiring layers of the first circuit structure is less than the number of wiring layers of the second circuit structure; and a wiring structure, arranged on the first circuit structure and electrically connected to the first circuit structure, wherein the circuit specification of the wiring structure is different from the circuit specification of the first circuit structure.

[0009] The present invention also provides a method for manufacturing a packaging substrate, comprising: forming a first circuit layer on a carrier; sequentially forming a first insulating layer and a core board on the carrier, so that the first insulating layer is combined with the carrier and covers the first circuit layer, so that the first circuit layer is embedded in the first insulating layer, wherein the core board has a first side and a second side opposite to each other, so that the core board is combined with the first insulating layer with its first side, and the core board has at least one conductive through hole connecting the first side and the second side; forming a second circuit structure on the second side of the core board, wherein the second circuit structure has at least one second insulating layer and a conductive through hole connected to the second side. A second circuit layer is formed so that the second circuit layer is electrically connected to the conductive through hole; the carrier is removed to expose the first circuit layer and the first insulating layer; a first circuit structure electrically connected to the conductive through hole is formed by the first insulating layer and the first circuit layer, wherein the specification of the first circuit layer is the same as the specification of the second circuit layer, and the number of wiring layers of the first circuit layer is less than the number of wiring layers of the second circuit layer; and a wiring structure is formed on the first circuit structure, wherein the wiring structure has at least one dielectric layer and a wiring redistribution layer combined with the dielectric layer and electrically connected to the first circuit layer, so that the specification of the wiring redistribution layer is different from the specification of the first circuit layer.

[0010] In the aforementioned packaging substrate and the manufacturing method thereof, the core board, the first insulating layer and the second insulating layer are formed on the carrier in a pressing manner.

[0011] In the aforementioned packaging substrate and its manufacturing method, the surface of the first insulating layer is flush with the surface of the first circuit layer.

[0012] In the aforementioned packaging substrate and its manufacturing method, the specification is line width and / or line spacing.

[0013] In the aforementioned packaging substrate and manufacturing method thereof, the thermal expansion coefficient of the second circuit structure is greater than the thermal expansion coefficient of the first circuit structure.

[0014] From the above, it can be seen that the packaging substrate and its manufacturing method of the present invention mainly replace the existing buffer layer with the wiring structure to produce a line redistribution layer with extremely small line width / line spacing. Therefore, the packaging substrate of the present invention can have an ultra-fine pitch (Ultra-FinePitch) wiring specification to facilitate external miniaturized semiconductor chips with multiple contacts.

[0015] Furthermore, through the design of the wiring structure, the CTE of the overall structure on the first side of the core board and the CTE of the overall structure on the second side of the core board can be balanced. Therefore, compared with the prior art, the present invention can not only avoid warping of the packaging substrate, but also only need to use conventional dielectric materials to make the first insulating layer and the second insulating layer, without the need to use buffer materials to make the first insulating layer or to add a buffer layer on the first side. Therefore, it can not only save material costs, but also when using the same equipment, the flatness of the first insulating layer and the second insulating layer can meet the requirements at the same time, so as to improve the accuracy of the wiring position.

[0016] In addition, the manufacturing method of the present invention combines the first insulating layer and the second insulating layer of the same material with the core board by pressing, so as to form the first insulating layer and the second insulating layer with consistent surface flatness. Therefore, compared with the prior art, the manufacturing method of the present invention does not require brushing and grinding operations, thereby not only avoiding the problem of structural deformation of the packaging substrate during the process, but also avoiding the problem of internal circuit breakage caused by the stress generated by brushing and grinding, and reducing the production cost because there is no need to purchase brushing and grinding equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A cross-sectional view of a conventional packaging substrate.

[0018] Figures 2A to 2G It is a cross-sectional schematic diagram of a method for manufacturing a packaging substrate of the present invention.

[0019] The reference numerals are as follows:

[0020] 1,2 Package substrate

[0021] 10,20 core board

[0022] 10a, 20a First side

[0023] 10b, 20b Second side

[0024] 100,200 conductive vias

[0025] 11,21 First Line Structure

[0026] 110,211 first insulating layer

[0027] 12,22 Second line structure

[0028] 120,221,223,225 Second insulation layer

[0029] 2a Asymmetric substrate structure

[0030] 201 Plug material

[0031] 21b First conductive blind via

[0032] 210 First inner circuit layer

[0033] 211a,212a surface

[0034] 212 First circuit layer

[0035] 22a Metal layer

[0036] 22b Second conductive blind via

[0037] 220 Second inner circuit layer

[0038] 222,224,226 Second circuit layer

[0039] 23 Wiring Structure

[0040] 230 Dielectric layer

[0041] 231 Line Rerouting Layer

[0042] 232 Blind hole conductor

[0043] 233 Electrical contact pads

[0044] 9 Bearing

[0045] 9a First surface

[0046] 9b Second surface

[0047] 90 Copper Foil

[0048] 91 plate body DETAILED DESCRIPTION

[0049] The following describes the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0050] It should be noted that the structures, proportions, sizes, etc. shown in the attached drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects and purposes that can be produced by the present invention, should still fall within the scope of the technical contents disclosed in the present invention. At the same time, the terms such as "on", "first", "second", "one", etc. quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0051] Figures 2A to 2GIt is a cross-sectional schematic diagram of a method for manufacturing a package substrate 2 of the present invention.

[0052] like Figure 2A As shown, a carrier 9, a plurality of core boards 20, a plurality of first insulating layers 211 and a plurality of second insulating layers 221 having metal layers 22a are provided, wherein the carrier 9 has a first surface 9a and a second surface 9b opposite to each other.

[0053] In this embodiment, the carrier 9 is a temporary carrier, and the plate body 91 thereof can be an organic polymer plate such as bismaleimide triazine (BT) or a copper foil substrate. For example, the carrier 9 is a copper foil substrate, which includes a copper foil 90, and a peeling layer (not shown) can be provided on the copper foil 90 as required.

[0054] Furthermore, a first circuit layer 212 may be formed on the first surface 9 a and the second surface 9 b of the carrier 9 .

[0055] Furthermore, the core board 20 is a single core layer specification, which has a first side 20a and a second side 20b opposite to each other, and a first inner circuit layer 210 and a second inner circuit layer 220 are arranged on the first side 20a and the second side 20b of the core board 20, and the core board 20 has a plurality of conductive through holes 200 connecting the first side 20a and the second side 20b to electrically connect the first inner circuit layer 210 and the second inner circuit layer 220.

[0056] In addition, the conductive via 200 is a hollow column, and the hollow part thereof can be filled with a plugging material 201, wherein the plugging material 201 can be of various types, such as conductive glue, ink, etc., and is not particularly limited. It should be understood that in other embodiments, the conductive via 200 can also be a solid metal column without being filled with the plugging material 201.

[0057] In addition, the first and second insulating layers 211 , 221 are dielectric layers, such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials, and the metal layer 22 a is a copper layer.

[0058] like Figure 2B As shown, the core board 20, the first insulating layer 211 and the second insulating layer 221 are symmetrically formed on the first surface 9a and the second surface 9b of the carrier 9 by pressing, so that the core board 20 is combined with the first insulating layer 211 with its first side 20a and combined with the second insulating layer 221 with its second side 20b, and the metal layer 22a is located at the outermost side.

[0059] In this embodiment, the first insulating layer 211 is combined on the first surface 9 a and the second surface 9 b of the carrier 9 to cover the first circuit layer 212 , so that the first circuit layer 212 is embedded in the first insulating layer 211 .

[0060] like Figure 2C As shown, the metal layer 22 a is patterned to form a second circuit layer 222 , and a plurality of second conductive blind vias 22 b electrically connecting the second inner circuit layer 220 and the second circuit layer 222 are formed in the second insulating layer 221 .

[0061] In this embodiment, the second circuit layer 222 and the second insulating layer 221 can be used as the second circuit structure 22 , so that a second circuit structure 22 is formed on the second side 20 b of each core board 20 .

[0062] like Figure 2D As shown, the number of wiring layers of the second circuit structure 22 can be designed according to demand, so a second insulating layer 223 having a metal layer can be laminated on the second circuit layer 222 and the second insulating layer 221 to manufacture a second circuit layer 224 and form an asymmetric substrate structure 2a.

[0063] In this embodiment, in order to protect the second circuit layer 224 , a second insulating layer 225 having a metal layer 22 a is laminated on the second circuit layer 224 , so that the metal layer 22 a is presented on the outer side of the second circuit structure 22 .

[0064] Furthermore, the first insulating layer 211 and the second insulating layers 221 , 223 , 225 are made of the same material to facilitate being manufactured to have the same roughness and flatness.

[0065] like Figure 2E As shown, the carrier 9 is removed to expose the first circuit layer 212 and the first insulating layer 211 .

[0066] In this embodiment, the surface 212 a of the first circuit layer 212 is flush with the surface 211 a of the first insulation layer 211 .

[0067] like Figure 2F As shown, a plurality of first conductive blind holes 21b electrically connecting the first inner wiring layer 210 and the first wiring layer 212 are formed in the first insulating layer 211 to form a first wiring structure 21, and the metal layer 22a can be patterned as required to form a second wiring layer 226 of the second wiring structure 22, wherein the number of wiring layers of the first wiring structure 21 is less than the number of wiring layers of the second wiring structure 22.

[0068] In this embodiment, the first circuit structure 21 includes the first insulating layer 211 and the first circuit layer 212 combined with the first insulating layer 211, and the second circuit structure 22 includes multiple second insulating layers 221, 223, 225 and second circuit layers 222, 224, 226 combined with the multiple second insulating layers 221, 223, 225. Therefore, the number of wiring layers of the second circuit structure 22 is three, which is one more than the number of wiring layers of the first circuit structure 21, that is, the number of wiring layers of the first circuit layer 212 is less than the number of wiring layers of the second circuit layers 222, 224, 226.

[0069] Furthermore, the specifications (eg, line width / line spacing) of the first circuit layer 212 are the same as the specifications (eg, line width / line spacing) of the second circuit layers 222 , 224 , 226 .

[0070] In addition, the coefficient of thermal expansion (CTE) of the second circuit structure 22 is greater than the CTE of the first circuit structure 21 .

[0071] In addition, the materials of the insulating layers of the first circuit structure 21 and the second circuit structure 22 include inorganic materials (such as silicon oxide, silicon nitride, silicon oxynitride or other suitable materials), organic materials (such as polyimide (PI), polybenzazole (PBO), prepreg (PP), epoxy resin (Epoxy), benzocyclobutene (BCB) or other suitable materials), and the materials of the circuit layers of the first circuit structure 21 and the second circuit structure 22 are copper or other metals.

[0072] like Figure 2G As shown, a wiring structure 23 is formed on the first wiring structure 21 by a redistribution layer (RDL) process, which includes at least one dielectric layer 230, a wiring redistribution layer 231 arranged on the dielectric layer 230, and a plurality of blind hole-shaped conductors 232 arranged in the dielectric layer 230 and electrically connecting the wiring redistribution layer 231 and the first wiring layer 212, and the outermost wiring redistribution layer 231 has a plurality of electrical contact pads 233 to obtain the packaging substrate 2 of the present invention.

[0073] In this embodiment, the circuit redistribution layer 231 may be a fan-out type, and the specifications (such as line width / line spacing) of the circuit redistribution layer 231 are different from the specifications (such as line width / line spacing) of the first circuit layer 212. For example, the line width / line spacing of the circuit redistribution layer 231 is smaller than the line width / line spacing of the first circuit layer 212.

[0074] Furthermore, the coefficient of thermal expansion (CTE) of the second circuit structure 22 is equal to the overall CTE of the first circuit structure 21 and the wiring structure 23, that is, the CTE of the overall structure on the first side 20a of the core board 20 is equal to the CTE of the overall structure on the second side 20b of the core board 20.

[0075] In addition, the material forming the circuit redistribution layer 231 is copper, and the material forming the dielectric layer 230 is polybenzoxazole (PBO), polyimide (PI), prepreg (PP), etc. It should be understood that the material of the dielectric layer 230 can be the same as or different from the material of the first insulating layer 211 and the second insulating layers 221, 223, 225.

[0076] Therefore, the manufacturing method of the present invention uses the RDL process to manufacture the wiring structure 23, so as to facilitate the formation of a line redistribution layer 231 with extremely small line width / line spacing. Therefore, the packaging substrate 2 of the present invention can have an ultra-fine pitch (Ultra-Fine Pitch) wiring specification, so as to facilitate the external connection of a miniaturized semiconductor chip with multiple contacts.

[0077] Furthermore, the manufacturing method of the present invention can effectively balance the CTE of the overall structure on the first side 20a of the core board 20 and the CTE of the overall structure on the second side 20b of the core board 20 through the design of the wiring structure 23. Therefore, compared with the prior art, the manufacturing method of the present invention can not only avoid the warping of the packaging substrate 2, but also only needs to use conventional dielectric materials to make the first insulating layer 211 and the second insulating layer 221, 223, 225, without using buffer materials to make the first insulating layer 211 or adding a buffer layer on the first side 20a. Therefore, it can not only save material costs, but also when using the same equipment, the flatness of the first insulating layer 211 and the second insulating layer 221, 223, 225 can meet the requirements at the same time, so as to improve the accuracy of the wiring position, thereby improving the reliability of the subsequent packaged semiconductor chips.

[0078] In addition, the manufacturing method of the present invention combines the first insulating layer 211 and the second insulating layer 221, 223, 225 of the same material with the core board 20 by pressing, so as to form the first insulating layer 211 and the second insulating layer 221, 223, 225 with consistent surface flatness. Therefore, compared with the prior art, the manufacturing method of the present invention does not require brushing and grinding operations, thereby not only avoiding the problem of structural deformation of the packaging substrate 2 during the process, but also avoiding the problem of internal circuit breakage caused by the stress generated by brushing and grinding, and reducing the production cost because there is no need to purchase brushing and grinding equipment.

[0079] In addition, in the manufacturing method of the present invention, the first insulating layer 211 covers the first wiring layer 212 in a pressing manner, so that the first wiring layer 212 is embedded in the first insulating layer 211, so that after removing the carrier 9, the surface 212a of the first wiring layer 212 is flush with the surface 211a of the first insulating layer 211. Therefore, the manufacturing method of the present invention is advantageous for performing the RDL process by taking advantage of the flat surface property of the embedded wiring structure. For example, when the surface 212a of the first wiring layer 212 is flush with the surface 211a of the first insulating layer 211, the photosensitive PI film or liquid PI material used in the dielectric layer 230 can be easily formed on the flat surfaces 211a, 212a of the first wiring structure 21, and the flatness of the dielectric layer 230 meets the requirements.

[0080] The present invention also provides a packaging substrate 2, comprising: a core board 20 having a first side 20a and a second side 20b opposite to each other, a first circuit structure 21 arranged on the first side 20a of the core board 20, a second circuit structure 22 arranged on the second side 20b of the core board 20, and a wiring structure 23 arranged on the first circuit structure 21.

[0081] The core board 20 has a plurality of conductive through holes 200 connecting the first side 20 a and the second side 20 b .

[0082] The first circuit structure 21 has at least a first insulating layer 211 and a first circuit layer 212 embedded in the first insulating layer 211 , so that the first circuit layer 212 is electrically connected to the conductive via 200 .

[0083] The second circuit structure 22 has at least one second insulating layer 221, 223, 225 and a second circuit layer 222, 224, 226 combined with the second insulating layer 221, 223, 225, so that the second circuit layer 222, 224, 226 is electrically connected to the conductive through hole 200, wherein the circuit specification of the first circuit structure 21 is the same as the circuit specification of the second circuit structure 22, and the number of wiring layers of the second circuit structure 22 is greater than the number of wiring layers of the first circuit structure 21.

[0084] The wiring structure 23 has at least one dielectric layer 230 and a circuit redistribution layer 231 combined with the dielectric layer 230 , so that the circuit redistribution layer 231 is electrically connected to the first wiring structure 21 , wherein the circuit specification of the wiring structure 23 is different from the circuit specification of the first wiring structure 21 .

[0085] In one embodiment, the specification of the redistribution layer 231 is different from that of the first circuit layer 212 , and the specifications of the second circuit layers 222 , 224 , and 226 are the same as that of the first circuit layer 212 .

[0086] Furthermore, the surface 211 a of the first insulating layer 211 is flush with the surface 212 a of the first wiring layer 212 .

[0087] In one embodiment, the specification is line width and / or line spacing.

[0088] In one embodiment, the thermal expansion coefficient of the second circuit structure 22 is greater than the thermal expansion coefficient of the first circuit structure 21 .

[0089] In summary, the packaging substrate and the manufacturing method thereof of the present invention, by setting the RDL type wiring structure on the first circuit structure, can avoid the problem of warping of the asymmetric packaging substrate due to uneven force distribution. Therefore, the present invention can not only meet the requirements of fine pitch and fine circuits, but also improve reliability, so as to improve the yield of terminal electronic products and reduce production costs.

[0090] The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Those skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. A packaging substrate, comprising: The core board has a first side and a second side opposite to each other and at least one conductive through hole connecting the first side and the second side; A first circuit structure is disposed on a first side of the core board and electrically connected to the conductive through hole; A second circuit structure is disposed on the second side of the core board and electrically connected to the conductive through hole, and the number of wiring layers of the second circuit structure is greater than the number of wiring layers of the first circuit structure, wherein the circuit specification of the first circuit structure is the same as the circuit specification of the second circuit structure; and A wiring structure is disposed on the first circuit structure and electrically connected to the first circuit structure, wherein the circuit specification of the wiring structure is different from the circuit specification of the first circuit structure, wherein: The thermal expansion coefficient of the second circuit structure is equal to the thermal expansion coefficient of the first circuit structure and the wiring structure as a whole.

2. The packaging substrate according to claim 1, wherein: The first circuit structure has at least one first insulating layer and a first circuit layer embedded in the first insulating layer, and the second circuit structure has at least one second insulating layer and a second circuit layer combined with the second insulating layer, and the wiring structure has at least one dielectric layer and a circuit redistribution layer combined with the dielectric layer, so that the specifications of the circuit redistribution layer are different from the specifications of the first circuit layer, and the specifications of the second circuit layer are the same as the specifications of the first circuit layer.

3. The packaging substrate according to claim 2, wherein: The surface of the first insulating layer is flush with the surface of the first circuit layer.

4. The packaging substrate according to claim 1, wherein: The specification is line width and / or line spacing.

5. The packaging substrate according to claim 1, wherein: The thermal expansion coefficient of the second circuit structure is greater than the thermal expansion coefficient of the first circuit structure.

6. A method for manufacturing a packaging substrate, comprising: forming a first circuit layer on a carrier; A first insulating layer and a core board are sequentially formed on the carrier, so that the first insulating layer is combined with the carrier to cover the first circuit layer, and the first circuit layer is embedded in the first insulating layer, wherein the core board has a first side and a second side opposite to each other, so that the core board is combined with the first insulating layer with its first side, and the core board has at least one conductive through hole connecting the first side and the second side; Forming a second circuit structure on the second side of the core board, wherein the second circuit structure has at least a second insulating layer and a second circuit layer combined with the second insulating layer, so that the second circuit layer is electrically connected to the conductive through hole; removing the carrier to expose the first circuit layer and the first insulating layer; A first circuit structure electrically connected to the conductive via is formed by the first insulating layer and the first circuit layer, wherein the specification of the first circuit layer is the same as that of the second circuit layer, and the number of wiring layers of the first circuit layer is less than the number of wiring layers of the second circuit layer; and A wiring structure is formed on the first wiring structure, wherein the wiring structure has at least one dielectric layer and a circuit redistribution layer combined with the dielectric layer and electrically connected to the first wiring layer, so that the specification of the circuit redistribution layer is different from that of the first wiring layer, wherein: The thermal expansion coefficient of the second circuit structure is equal to the thermal expansion coefficient of the first circuit structure and the wiring structure as a whole.

7. The method for manufacturing a packaging substrate according to claim 6, wherein: The core board, the first insulating layer and the second insulating layer are formed on the carrier in a pressing manner.

8. The method for manufacturing a packaging substrate according to claim 6, wherein: The surface of the first insulating layer is flush with the surface of the first circuit layer.

9. The method for manufacturing a packaging substrate according to claim 6, wherein: The specification is line width and / or line spacing.

10. The method for manufacturing a packaging substrate according to claim 6, wherein: The thermal expansion coefficient of the second circuit structure is greater than the thermal expansion coefficient of the first circuit structure.

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