Combinatorial logic multi-fault diagnosis method and system based on graph convolutional neural network

Abstract

The present invention discloses a combinational logic multi-fault diagnosis method and system based on a graph convolutional neural network, which belongs to the field of circuit fault diagnosis technology and includes the following steps: obtaining a netlist file of a combinational logic circuit to be diagnosed and converting it into a directed graph of a logic circuit, and extracting the characteristics of each node. Injecting a random number of faults into random nodes and generating random test vectors, and obtaining failure response data through a circuit simulation model. Based on the failure response data, a fault element graph set is constructed through a fault element graph method, the fault score is calculated, and fault training data is generated. The fault training data is input into a graph convolutional neural network model for iterative training to construct a fault diagnosis model. The real-time failure response data is diagnosed using the fault diagnosis model to obtain the failure probability of each node. This scheme performs fault diagnosis on the combinational logic circuit by considering the situation where multiple combinational logic faults exist at the same time, thereby improving the accuracy of fault diagnosis.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit fault diagnosis, and in particular, relates to a combinational logic multi-fault diagnosis method and system based on graph convolutional neural network. Background Art

[0002] With the increasing scale of chips, electronic design automation (EDA) tools are indispensable in the field of chip design. In order to detect defects in chip manufacturing as early as possible, design for testability (DFT) has become an important process. Among them, fault diagnosis in the yield learning stage is a key step, and analyzing defects in mass-produced chips is of great significance to improving yield. Early fault diagnosis methods are mainly based on fault dictionaries and fault failure response analysis. In recent years, AI technology has also been applied to fault diagnosis. For example, random vectors are input into neural network models and test circuits, and the output results are compared to score faults; artificial neural networks (ANNs) are used to learn the relationship between input vectors and fault types and leads. Recent studies use ANNs to train fault diagnosis models to learn the relationship between input vectors and fault detection, but fail to effectively handle the enhancement and shielding relationship of multiple faults in combinational logic. Therefore, the training data model generated based on the simulation fault dictionary cannot learn the relationship between multiple faults, resulting in inaccurate diagnosis when multiple faults in combinational logic exist at the same time. Summary of the invention

[0003] Based on the above problems, the present invention provides a combinational logic multi-fault diagnosis method and system based on a graph convolutional neural network that overcomes the above problems or at least partially solves the above problems. The randomly generated multi-fault data are analyzed by the fault element graph method, and the situation where multiple combinational logic faults exist at the same time is considered. The analysis results are sent to the graph convolutional neural network for training to obtain a fault diagnosis model, so that relatively accurate fault diagnosis data can be obtained within a very short running time, thereby improving the accuracy of predicting the probability of fault occurrence through the fault diagnosis model.

[0004] According to a first aspect of the present invention, a combinational logic multi-fault diagnosis method based on a graph convolutional neural network is provided, comprising the following steps:

[0005] Obtaining a netlist file of a combinational logic circuit to be diagnosed and converting it into a directed graph of a logic circuit, and extracting node features corresponding to each node in the directed graph of the logic circuit;

[0006] Injecting a random number of faults into random node positions of the combinational logic circuit to be diagnosed to generate a random test vector, and acquiring failure response data through a circuit simulation model based on the random test vector;

[0007] Based on the failure response data, a fault element graph set is constructed by a fault element graph method, and a fault score is calculated based on the fault element graph set and associated with the corresponding fault to generate fault training data;

[0008] Inputting the fault training data into a graph convolutional neural network model for iterative training to construct a fault diagnosis model;

[0009] The real-time failure response data of the combinational logic circuit to be diagnosed is diagnosed based on the fault diagnosis model to obtain the failure probability of each node.

[0010] In the above technical solution, by converting the netlist file of the combinational logic circuit into a directed graph of the logic circuit and extracting the features of each node, the structure and properties of the circuit can be efficiently represented. In addition, the use of graph convolutional neural networks for fault diagnosis can make full use of the structural information of the combinational logic circuit and improve the accuracy and efficiency of diagnosis. By randomly selecting node positions for fault injection and generating random test vectors, various possible fault conditions can be simulated, thereby constructing a rich and diverse fault training data, so that the fault diagnosis model can adapt to different types of faults and have good generalization capabilities. Based on the fault element graph method, the fault element graph set is iteratively updated, and the fault score is calculated and associated with the corresponding fault, so that the fault node and fault type can be accurately identified. Based on the trained fault diagnosis model, the failure response data of the combinational logic circuit can be diagnosed in real time, and the fault probability of each node can be quickly obtained, so that a quick response can be made when a circuit fault occurs, reducing the impact of the fault on the system.

[0011] Optionally, in the method according to the present invention, obtaining a netlist file of the combinational logic circuit to be diagnosed and converting it into a directed graph of a logic circuit, and extracting node features corresponding to each node in the directed graph of the logic circuit, include:

[0012] Obtaining a netlist file corresponding to the combinational logic circuit to be diagnosed;

[0013] Constructing a corresponding logic circuit directed graph based on the netlist file of the combinational logic circuit to be diagnosed;

[0014] Classifying all nodes in the directed graph of the logic circuit to obtain corresponding node types, and marking the nodes based on the node types, wherein the node types include input nodes, output nodes, and intermediate nodes;

[0015] The node features of each node are extracted and normalized to construct a node feature matrix.

[0016] In the above technical solution, by converting the netlist file into a directed graph of logic circuits, a structured way can be provided to understand and analyze combinational logic circuits, which helps to capture the logical relationships and signal flow paths in the circuits. By classifying the nodes in the directed graph and marking them based on the node type, it helps to distinguish different types of nodes in subsequent fault diagnosis. By extracting the features of each node and normalizing them, the dimensional differences between the features can be eliminated, making different features numerically comparable, which helps the graph convolutional neural network model to better learn and understand the characteristics of the nodes and improve the accuracy and efficiency of diagnosis.

[0017] Optionally, in the method according to the present invention, constructing a corresponding logic circuit directed graph based on the netlist file of the combinational logic circuit to be diagnosed includes:

[0018] Reading the netlist file to identify the components in the combinational logic circuit to be diagnosed and the connection relationship between the components;

[0019] Initialize directed data structures for storing nodes and directed edges;

[0020] Traversing each component in the netlist file, and mapping each component to a corresponding node of the directed data structure to obtain an intermediate directed graph;

[0021] The connection relationship between the components is added to the corresponding edge of the intermediate directed graph to obtain a logic circuit directed graph.

[0022] In the above technical solution, by mapping the components and their connection relationships in the netlist file to a directed data structure, the structure and signal flow of the combinational logic circuit can be intuitively displayed, which helps to better understand the working principle of the circuit and the location where the fault may occur. In the process of constructing the directed graph of the logic circuit, directed edges are added according to the signal flow from input to output, ensuring that the directed graph of the logic circuit can accurately reflect the actual working conditions of the combinational logic circuit. By traversing the components in the netlist file and mapping them to the nodes in the directed data structure, the efficiency of constructing the directed graph of the logic circuit is greatly improved. In addition, since the directed graph of the logic circuit is constructed based on the data structure, the subsequent analysis and diagnosis of the circuit can also be carried out efficiently.

[0023] Optionally, in the method according to the present invention, extracting the node features of each node and normalizing them to construct a node feature matrix includes:

[0024] Extracting structural features and functional features corresponding to each node, wherein the structural features at least include the degree of the node, the type of adjacent nodes, and the node level, and the functional features at least include the logical function;

[0025] Respectively converting the structural features and the functional features into corresponding feature codes;

[0026] Normalizing the numerical features in the feature codes to eliminate the dimensional differences between the feature codes;

[0027] A feature matrix is ​​constructed based on the normalized feature codes as columns and the corresponding nodes as rows.

[0028] In the above technical solution, by extracting structural features and functional features and converting them into corresponding feature codes, the digitization and processability of the features are ensured, so that the subsequent graph convolutional neural network model can directly use the obtained features. Providing multi-dimensional information of nodes helps to more comprehensively understand the nature of nodes and their roles in the network. Constructing a feature matrix with feature codes as columns and corresponding nodes as rows allows the data structure of the entire network to be represented in an easy-to-process matrix form, and the feature representation in matrix form facilitates the corresponding graph analysis.

[0029] Optionally, in the method according to the present invention, injecting a random number of faults into random node positions of the combinatorial logic circuit to be diagnosed to generate a random test vector, and acquiring failure response data through a circuit simulation model based on the random test vector includes:

[0030] Constructing a circuit simulation model corresponding to the combinational logic circuit to be diagnosed based on the node characteristics;

[0031] generating a random number representing a random number of failures through a Poisson distribution;

[0032] Traversing all nodes in the directed graph of the logic circuit, and selecting a corresponding number of nodes according to the random number to inject fault signals into the circuit simulation model;

[0033] A random test vector is generated based on a uniform random distribution method, and a circuit simulation model is run in combination with the random test vector and an injected fault signal to obtain failure response data corresponding to each random test vector.

[0034] In the above technical solution, random numbers used to represent the random number of faults are generated through Poisson distribution, which can simulate the randomness of faults in the real environment. At the same time, all nodes in the directed graph of the logic circuit are traversed, and the corresponding number of nodes are selected for fault injection, which can fully cover the potential fault points of the circuit. Compared with the traditional fixed fault injection method, this random fault injection method can more effectively discover faults in the circuit and improve the efficiency of fault diagnosis. Combined with the random test vectors generated by the uniform random distribution method, a variety of input conditions can be provided for the circuit, thereby triggering more circuit state changes. The diversified test vectors can cover a wider range of circuit behaviors, making the failure response data more comprehensive and accurate, thereby enhancing the accuracy of fault diagnosis. Fault injection and testing through circuit simulation models can avoid the high cost and high risk of testing on real hardware.

[0035] Optionally, in the method according to the present invention, a fault element graph set is constructed based on the failure response data by a fault element graph method, a fault score is calculated based on the fault element graph set, and fault training data is generated by associating the fault with the corresponding fault, including:

[0036] Initialize an empty set of fault element graphs corresponding to each failure response data;

[0037] Based on the fault element graph method, iterative analysis is performed on the fault corresponding to each failure response data to obtain the corresponding fault element graph;

[0038] Add the fault element graph to the empty set of fault element graphs according to the current failure response data to obtain a set of fault element graphs;

[0039] determining a fault score in combination with the fault element graph and adding the fault score to a corresponding node;

[0040] The fault score of each node and the node feature are integrated to obtain fault training data.

[0041] In the above technical solution, the fault element graph method is used to iteratively analyze the fault corresponding to each failure response data, so that the fault element (such as a specific node or component) that causes the circuit failure can be accurately identified, which helps to improve the accuracy of fault diagnosis and ensure the reliability of the diagnosis result. By constructing a corresponding fault element graph for each failure response data and integrating these fault element graphs into a set of fault element graphs, a rich data set containing various fault modes can be formed. This data set can provide sufficient training data for subsequent machine learning or deep learning models to improve the generalization ability and fault identification ability of the model. By combining the fault element graph to determine the fault score and adding these scores to the corresponding nodes, a quantitative evaluation of the fault can be achieved, and the quantitative evaluation helps to more accurately compare the degree of influence of different faults on circuit performance. Integrating the fault scores and node features of each node to obtain fault training data can realize the fusion of fault features and circuit structure features, which helps to more comprehensively describe the fault state of the circuit and improve the ability of the machine learning model to recognize the fault mode.

[0042] Optionally, in the method according to the present invention, the fault training data is input into a graph convolutional neural network model for iterative training to construct a fault diagnosis model, comprising:

[0043] Set the network structure and model parameters of the graph convolutional neural network model, and initialize the weights and bias parameters. The model parameters include the number of layers, node feature dimensions, and hidden layer dimensions.

[0044] Inputting the fault training data into the graph convolutional neural network model for forward propagation to obtain a predicted fault score;

[0045] Calculate a corresponding loss function based on the predicted fault score combined with the fault score on the node;

[0046] Perform back propagation based on the gradient descent method to calculate the gradient of the loss function relative to the model parameters, and update the weights and bias parameters of the graph convolutional neural network model according to the gradient;

[0047] Iterate the process from forward propagation to back propagation until a maximum number of iterations is reached to obtain a fault diagnosis model, and evaluate the fault diagnosis model based on evaluation indicators, including accuracy, recall rate and F1 score.

[0048] In the above technical solution, the graph convolutional neural network model can capture the connection information and dependencies between nodes. In fault diagnosis, the model can learn the fault characteristics of nodes in the circuit diagram and the propagation mode between them, so as to more accurately identify faults. Through iterative training, the graph convolutional neural network model can gradually optimize its weights and bias parameters to minimize the gap between the predicted fault score and the actual fault score, improve the prediction ability of the model, and improve the accuracy of fault diagnosis. The graph convolutional neural network model has the ability to process complex graph structures and can cope with various complex fault modes that may occur in combinational logic circuits. The training model can learn the characteristics of these fault modes and accurately identify them in actual diagnosis.

[0049] Optionally, in the method according to the present invention, inputting the fault training data into the graph convolutional neural network model for forward propagation to obtain a predicted fault score includes:

[0050] Input the node feature matrix and the corresponding adjacent nodes in the fault training data into the graph convolution layer of the graph convolutional neural network model;

[0051] Performing a graph convolution operation on the node feature matrix and the corresponding adjacent nodes through a graph convolution layer to aggregate the information of the adjacent nodes, and updating the node feature matrix;

[0052] The updated node feature matrix is ​​input into the fully connected layer of the graph convolutional neural network model and converted into a predicted fault score.

[0053] In the above technical solution, by inputting the node feature matrix and the corresponding adjacent nodes in the fault training data into the graph convolution layer, the graph convolution neural network model can make full use of the structure of the circuit diagram to perform graph convolution operations on the node feature matrix and adjacent nodes, effectively aggregating the information of adjacent nodes. The characteristics of each node not only depend on its own attributes, but also are affected by its neighboring nodes, so that the model can learn richer feature representations, thereby improving the accuracy of fault diagnosis. After the graph convolution operation, the feature matrix of the node is updated, reflecting the interaction between the node and its adjacent nodes, so that the model can better understand the fault mode in the circuit. The updated node feature matrix is ​​input into the fully connected layer, and through the action of nonlinear transformation and activation function, it is finally converted into a predicted fault score, which can convert the feature representation learned by the model into a specific diagnostic result, so that the model can be directly used for fault detection and location.

[0054] Optionally, in the method according to the present invention, diagnosing the real-time failure response data of the combinational logic circuit to be diagnosed based on the fault diagnosis model to obtain the failure probability of each node includes:

[0055] Acquire real-time failure response data of the combinational logic circuit to be diagnosed;

[0056] Inputting the real-time failure response data into a fault diagnosis model, and obtaining a fault score corresponding to the real-time failure response data based on the fault diagnosis model;

[0057] The failure probability of the node corresponding to the real-time failure response data is calculated based on the failure score.

[0058] In the above technical solution, by inputting the real-time failure response data of the combinational logic circuit to be diagnosed into the trained fault diagnosis model, since the model has learned the mapping relationship between fault characteristics and fault scores during the training stage, it can quickly give the fault score of each node and then calculate the fault probability. Since the fault diagnosis model is obtained by iterative training through a graph convolutional neural network based on a large amount of fault training data, it has learned the propagation law of the fault in the circuit and the fault characteristics of the node. When the real-time failure response data is input into the fault diagnosis model, the fault mode can be accurately identified and the corresponding fault score can be given. The fault probability calculated based on these fault scores has a high accuracy.

[0059] According to another aspect of the present invention, a combinational logic multi-fault diagnosis system based on a graph convolutional neural network is provided, comprising:

[0060] A data preprocessing module is configured to obtain a netlist file of a combinational logic circuit to be diagnosed and convert it into a directed graph of a logic circuit, and extract node features corresponding to each node in the directed graph of the logic circuit;

[0061] A fault injection simulation module is configured to inject a random number of faults into random node positions of the combinational logic circuit to be diagnosed to generate a random test vector, and obtain failure response data through a circuit simulation model based on the random test vector;

[0062] a fault training data generating module, configured to construct a fault element graph set based on the failure response data by a fault element graph method, calculate a fault score based on the fault element set, and generate fault training data by associating with corresponding faults;

[0063] A model training module is configured to input fault training data into a graph convolutional neural network model for iterative training to build a fault diagnosis model;

[0064] The fault diagnosis module is configured to diagnose the real-time failure response data of the combinational logic circuit to be diagnosed based on the fault diagnosis model to obtain the fault probability of each node.

[0065] According to another aspect of the present invention, there is provided a computing device, comprising: at least one processor; and a memory storing program instructions, wherein the program instructions are configured to be suitable for being executed by the at least one processor, and the program instructions include instructions for executing the method.

[0066] According to another aspect of the present invention, a readable storage medium storing program instructions is provided. When the program instructions are read and executed by a computing device, the computing device executes the method.

[0067] According to the solution of the present invention, the netlist file of the combinational logic circuit is converted into a directed graph of the logic circuit, and the features of each node are extracted, so that the structure and properties of the circuit can be efficiently represented. The graph convolutional neural network is used for fault diagnosis, and the structural information of the circuit is used to improve the accuracy and efficiency of diagnosis. The node position is randomly selected for fault injection, random test vectors are generated, various fault conditions are simulated, and rich fault training data are constructed, so that the model can adapt to different faults and have good generalization ability. The fault element graph set is iteratively updated based on the fault element graph method, the fault score and association are calculated, and the fault node and type are accurately identified. The trained model can diagnose the circuit failure response data in real time, quickly obtain the fault probability of each node, and reduce the impact of the fault on the system. By mapping the components and connection relationships in the netlist file to the directed data structure, the circuit structure and signal flow are intuitively displayed, and the working principle and fault location are understood. The features are extracted and normalized to eliminate the feature dimension differences, which facilitates the graph convolutional neural network model to learn node characteristics. Random fault injection and test vector generation simulate the real environment and improve the efficiency of fault diagnosis. The graph convolutional neural network model captures node connection information and dependencies, learns fault characteristics and propagation patterns, improves recognition accuracy, optimizes parameters through training, enhances model prediction capabilities, and achieves fault detection and location.

[0068] The above invention content is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] Other features, objects and advantages of the present invention will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings. The drawings are only for the purpose of illustrating preferred embodiments and are not to be considered as limiting the present invention. Also, the same reference symbols are used throughout the drawings to represent the same parts.

[0070] Figure 1 It is a flow chart of a combinational logic multi-fault diagnosis method based on graph convolutional neural network disclosed by the present invention;

[0071] Figure 2 The present invention discloses a structural schematic diagram of a combinational logic multi-fault diagnosis system based on a graph convolutional neural network. DETAILED DESCRIPTION

[0072] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific implementation method described herein is only an optimal embodiment of the present invention, which is only used to explain the present invention and does not limit the scope of protection of the present invention. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0073] Before discussing the exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe the operations (or steps) as sequential processes, many of the operations (or steps) therein may be performed in parallel, concurrently, or simultaneously. In addition, the order of the operations may be rearranged. A process may be terminated when its operations are completed, but may also have additional steps not included in the accompanying drawings; a process may correspond to a method, function, procedure, subroutine, subprogram, etc.

[0074] Example:

[0075] like Figure 1 As shown, a combinational logic multi-fault diagnosis method based on graph convolutional neural network includes the following steps:

[0076] S1. Obtain a netlist file of the combinational logic circuit to be diagnosed and convert it into a directed graph of the logic circuit, and extract node features corresponding to each node in the directed graph of the logic circuit.

[0077] Specifically, S1 includes the following steps:

[0078] S11, obtaining a netlist file corresponding to the combinational logic circuit to be diagnosed;

[0079] S12, constructing a corresponding logic circuit directed graph based on the netlist file of the combinational logic circuit to be diagnosed;

[0080] S13, classifying all nodes in the directed graph of the logic circuit to obtain corresponding node types, and marking the nodes based on the node types, wherein the node types include input nodes, output nodes, and intermediate nodes;

[0081] S14. Extract node features of each node and normalize them to construct a node feature matrix.

[0082] It can be understood that this embodiment mainly performs multi-fault diagnosis on combinational logic circuits. This embodiment first obtains the netlist file of the combinational logic circuit to be diagnosed. The obtained netlist file includes the logic gate type, input pin information, output pin information and the connection relationship between each logic gate of the combinational logic circuit to be diagnosed.

[0083] Specifically, S12 includes the following steps:

[0084] S121, reading a netlist file to identify components in the combinational logic circuit to be diagnosed and the connection relationship between the components;

[0085] S122, initializing a directed data structure for storing nodes and directed edges;

[0086] S123, traversing each component in the netlist file, and mapping each component to a corresponding node of the directed data structure to obtain an intermediate directed graph;

[0087] S124. Add the connection relationship between the components to the corresponding edge of the middle directed graph to obtain a logic circuit directed graph.

[0088] In this embodiment, a file reading function is used to read a netlist file containing a description of a combinational logic circuit in a netlist file, and a parser is written according to the syntax and format information of the netlist file to extract component information in the netlist file, and the component information includes logic gate type, pin information, and logic gate connection relationship. The component information obtained by parsing is stored in a corresponding data structure, and a data structure suitable for storing a directed graph is selected. In this embodiment, an adjacency list is used. An empty node set is initialized to store nodes in a directed graph, and an empty edge set is initialized similarly to store directed edges. The component information list obtained by parsing is traversed, and for each logic gate, a new node instance is created in the node set according to its type and pin information, and a corresponding node ID is set for the node, so as to obtain an intermediate directed graph with only node information added, and the connection relationship between each logic gate in the component list information is traversed to determine the starting component (i.e., the component where the output pin is located) and the ending component (i.e., the component where the input pin is located). In the adjacency list, an edge pointing to the ending node is added to the entry of the starting node. After traversing all connection relationships and adding all edges, a complete logic circuit directed graph is obtained, which includes all components in the combinational logic circuit to be diagnosed and the connection relationships between the components.

[0089] Specifically, S14 includes the following steps:

[0090] S141, extracting structural features and functional features corresponding to each node, wherein the structural features at least include the degree of the node, the type of adjacent nodes, and the node level, and the functional features at least include the logical function;

[0091] S142, converting the structural features and the functional features into corresponding feature codes respectively;

[0092] S143, normalizing the numerical features in the feature codes to eliminate the dimensional differences between the feature codes;

[0093] S144. Construct a feature matrix based on the normalized feature codes as columns and the corresponding nodes as rows.

[0094] In this embodiment, the directed graph of the combinatorial logic circuit to be diagnosed is traversed, and the number of adjacent edges of each node is counted, which is the degree of the corresponding node. For example, for node A, if there are 3 edges connected to it, the degree of node A is 3. Simultaneously, the types of all adjacent nodes of each node (such as AND gate, OR gate, etc.) are recorded, and these types are encoded as one-hot vectors to represent different types of adjacent nodes. Starting from the output node of the logic circuit, traverse inward layer by layer, assign a level to each node, the output node is the first level, the node directly connected to the output node is the second level, and so on. According to the type of the node (such as AND gate, OR gate, etc.), its logical function is determined. Encode the logical function into an appropriate representation form, and use binary encoding or one-hot encoding for encoding. Structural feature encoding: For the degree of the node, its numerical value can be directly used as the feature encoding. For the type of adjacent node, one-hot encoding is used to represent different types of adjacent nodes. For the node level, its numerical value can be used or appropriate encoding (such as binary encoding) can be performed. For the logical function, binary encoding or one-hot encoding is used according to the specific logical function. For example, if there are only three logical functions, AND, OR, and NOT, a 3-bit binary code is used (such as 001 for AND, 010 for OR, and 100 for NOT). Use the min-max normalization method to find the minimum and maximum values ​​of each numerical feature in all nodes, and then map the value of the feature to between 0 and 1. Create an empty feature matrix with the same number of rows as the number of nodes in the logic circuit and the same number of columns as the number of normalized features. Traverse each node in the logic circuit, add its corresponding normalized feature code as a row to the empty feature matrix, and ensure that the feature code of each node corresponds correctly to the column in the feature matrix. The feature matrix finally obtained for subsequent fault diagnosis will be used in the subsequent fault diagnosis process. This embodiment traverses the logic circuit diagram and extracts the structure and logical function characteristics of the node, encodes the node features and normalizes them to form a feature matrix, thereby improving the accuracy and efficiency of fault diagnosis, making the fault location and repair of the logic circuit faster and more accurate.

[0095] S2. Injecting a random number of faults into random node positions of the combinational logic circuit to be diagnosed to generate a random test vector, and obtaining failure response data through a circuit simulation model based on the random test vector.

[0096] Specifically, S2 includes the following steps:

[0097] S21, constructing a circuit simulation model corresponding to the combinational logic circuit to be diagnosed based on the node characteristics;

[0098] S22, generating a random number for representing a random number of faults through Poisson distribution;

[0099] S23, traversing all nodes in the directed graph of the logic circuit, and selecting a corresponding number of nodes according to the random number to inject fault signals into the circuit simulation model;

[0100] S24. Generate a random test vector based on a uniform random distribution method, run a circuit simulation model in combination with the random test vector and the injected fault signal, and obtain failure response data corresponding to each random test vector.

[0101] In this embodiment, first, the type, connection relationship and other features of each node are extracted from the node features of the combinational logic circuit to be diagnosed. A circuit simulation algorithm is used to build a circuit simulation model based on the extracted node features. Ensure that the simulation model can accurately reflect the actual behavior of the logic circuit. Determine the parameter λ of the Poisson distribution (indicating the average number of faults per unit time) based on historical fault data. Use a random number generator to generate a random number N based on the Poisson distribution, which represents the number of faults that currently need to be injected. The corresponding faults include. Use the depth-first search (DFS) algorithm to traverse all nodes in the directed graph of the logic circuit, and randomly select N nodes from the traversed nodes as fault nodes, with the same probability of each node being selected. In the simulation model, the outputs of these faulty nodes are set to fixed values ​​(such as 0 or 1), indicating that According to the number of input bits of the logic circuit, a set of random test vectors are generated using the uniform random distribution method. . The generated random test vector Input into the simulation model, and run the simulation model in combination with the previously injected fault signal, and for each random test vector, record the output result of the simulation model. If the output result is different from the expected result in the fault-free situation, the response data corresponding to the test vector is considered to be failure response data. Repeat the steps of generating random test vectors, running the simulation model, and recording failure response data until the preset number of tests is reached or other termination conditions are met. This embodiment realizes fault injection and detection of combinational logic circuits by constructing a circuit simulation model, random fault injection, generating random test vectors, and simulation running, which can effectively simulate actual fault conditions and improve the accuracy and coverage of fault diagnosis.

[0102] S3. Construct a fault element graph set based on the failure response data by using the fault element graph method, calculate the fault score based on the fault element graph set, and associate it with the corresponding fault to generate fault training data.

[0103] Specifically, S3 includes the following steps:

[0104] S31, initializing an empty set of fault element graphs corresponding to each failure response data;

[0105] S32, iteratively analyzing the fault corresponding to each failure response data based on the fault element graph method to obtain a corresponding fault element graph;

[0106] S33, adding the fault element graph to the fault element graph empty set according to the current failure response data to obtain a fault element graph set;

[0107] S34, determining a fault score in combination with the fault element graph and adding the fault score to the corresponding node;

[0108] S35. Integrate the fault score and node features of each node to obtain fault training data.

[0109] In this embodiment, first, for each failure response data, an empty set of fault element graphs is created to store all possible fault element graphs obtained after the failure response data is analyzed. Each failure response data is read one by one from the failure response data set, and based on the fault propagation model, the fault source that may cause the failure response data is analyzed. The determined fault sources and the logical relationships between them (such as AND, OR relationships) are represented in a graphical manner to form a fault element graph.

[0110] If the fault element graph contains multiple possible fault sources, iterative analysis is performed on each possible fault source to form multiple different fault element graphs. All fault element graphs obtained based on the current failure response data analysis are added to the corresponding fault element graph empty set to form the fault element graph set of the failure response data. :

[0111] . Calculate a fault score for each fault source (i.e., node) based on the frequency of occurrence, impact range, and other factors of each fault source in the fault element graph. Calculate the fault score of each node where the fault is failure response data. If the gate does not appear in any fault element, the score is 0. Add the calculated fault score to the corresponding node as one of the node's attributes. Extract the features of each node, such as node type, connection relationship, etc., from the circuit simulation model of the combinational logic circuit to be diagnosed. Integrate the fault score of each node with the extracted node features to form complete fault training data , where there are g gates in the combinational logic circuit to be diagnosed. The obtained fault training data is used for subsequent machine learning model training to realize automatic diagnosis of combinational logic circuit faults. This embodiment effectively improves the accuracy and efficiency of fault diagnosis by constructing a fault element graph, iteratively analyzing the fault source, calculating the fault score, and integrating the node features and the fault score to form fault training data, which can realize automatic diagnosis of combinational logic circuit faults and improve the intelligent level of fault detection.

[0112] S4. Input the fault training data into the graph convolutional neural network model for iterative training to build a fault diagnosis model.

[0113] Specifically, S4 includes the following steps:

[0114] S41. Setting the network structure and model parameters of the graph convolutional neural network model, and initializing the weights and bias parameters. The model parameters include the number of layers, node feature dimensions, and hidden layer dimensions.

[0115] S42, inputting the fault training data into the graph convolutional neural network model for forward propagation to obtain a predicted fault score;

[0116] S43, calculating a corresponding loss function based on the predicted fault score combined with the fault score on the node;

[0117] S44. Perform back propagation based on the gradient descent method, calculate the gradient of the loss function relative to the model parameters, and update the weights and bias parameters of the graph convolutional neural network model according to the gradient;

[0118] S45, iteratively running the process from forward propagation to backward propagation until a maximum number of iterations is reached to obtain a fault diagnosis model, and evaluating the fault diagnosis model based on evaluation indicators, where the evaluation indicators include accuracy, recall rate, and F1 score.

[0119] In this embodiment, a multi-layer graph convolutional neural network model is first designed, for example, including 2 graph convolutional layers and 1 fully connected layer. The number of layers is set to 3 (including 2 graph convolutional layers and 1 fully connected layer), and is set according to the dimension of the node features in the fault training data, assuming 64 dimensions. For the graph convolutional layer, the hidden layer dimension is set to 128; for the fully connected layer, it is assumed that the output layer is a single node, so the output dimension is 1 (indicating the predicted fault score). Use a random initialization method (such as Xavier initialization or He initialization) to assign values ​​to the weights and bias parameters in the model. The fault element graph in the fault training data is converted into a form that can be processed by the graph convolutional neural network model, including an adjacency matrix and a node feature matrix. The preprocessed data is input into the model, feature extraction and aggregation are performed through the graph convolutional layer, and finally the predicted fault score is output through the fully connected layer. The error between the predicted fault score and the actual node fault score is calculated using the mean square error loss function. Based on the calculated loss function value, the chain rule is used to calculate the gradient of the loss function relative to the model parameters. The gradient descent method is used to update the weights and bias parameters of the model based on the calculated gradient. The forward propagation, loss calculation, back propagation and parameter update process are repeated until the preset maximum number of iterations is reached. The trained fault diagnosis model is evaluated, and the evaluation indicators include accuracy, recall and F1 score. The accuracy rate indicates the proportion of the number of correctly predicted faults to the total number of predicted faults, the recall rate indicates the proportion of the number of correctly predicted faults to the actual number of faults, and the F1 score indicates the harmonic mean of the accuracy and recall rate, which is used to comprehensively evaluate the performance of the fault diagnosis model. This embodiment realizes the automatic diagnosis of combinational logic circuit faults by designing a multi-layer graph convolutional neural network model and training it in combination with a fault element graph. It can effectively extract node features, improve the accuracy of fault diagnosis, and comprehensively evaluate the model performance through comprehensive evaluation indicators, providing an efficient and intelligent solution for circuit fault detection.

[0120] Specifically, S42 includes the following steps:

[0121] S421, inputting the node feature matrix and the corresponding adjacent nodes in the fault training data into the graph convolution layer of the graph convolutional neural network model;

[0122] S422, performing a graph convolution operation on the node feature matrix and the corresponding adjacent nodes through a graph convolution layer to aggregate the information of the adjacent nodes, and updating the node feature matrix;

[0123] S423. Input the updated node feature matrix into the fully connected layer of the graph convolutional neural network model and convert it into a predicted fault score.

[0124] In this embodiment, the node feature matrix and the adjacency matrix are used as input and passed into the first graph convolution layer of the graph convolutional neural network model. In the graph convolution layer, a graph convolution operation is performed to aggregate the information of the adjacent nodes of each node. This is done by defining a graph convolution kernel that slides within the neighborhood of each node and weights the features of the aggregated adjacent nodes according to the weights in the adjacency matrix. The formula corresponding to the convolution operation is as follows:

[0125] ;

[0126] Where: represents the adjacency matrix plus the identity matrix to include self-loops; N Indicates the number of nodes; represents the degree matrix after adding the self-loop; Indicates l The node feature matrix of the layer; Indicates l The trainable weight matrix of the layer; Represents the activation function.

[0127] After being processed by the graph convolutional layer, the updated node feature matrix is ​​obtained, which is then flattened, converted into a one-dimensional vector, and then input into the fully connected layer. The fully connected layer is a simple neural network layer in which each node is connected to all nodes in the input layer. In the fully connected layer, the input features are further transformed through the weight matrix and bias terms, and the predicted fault score is finally output. Assuming that the output layer of the fully connected layer has only one node, the output of this node is the predicted fault score. The sigmoid activation function is used to ensure that the output value is between 0 and 1 to represent the probability of a fault.

[0128] S5. Based on the fault diagnosis model, the real-time failure response data of the combinational logic circuit to be diagnosed is diagnosed to obtain the failure probability of each node.

[0129] Specifically, S5 includes the following steps:

[0130] S51, obtaining real-time failure response data of the combinational logic circuit to be diagnosed;

[0131] S52, inputting the real-time failure response data into a fault diagnosis model, and obtaining a fault score corresponding to the real-time failure response data based on the fault diagnosis model;

[0132] S53. Calculate the failure probability of the node corresponding to the real-time failure response data based on the failure score.

[0133] In this embodiment, firstly, the real-time failure response data of the combinational logic circuit to be diagnosed is obtained, and the real-time failure response data is input into the fault diagnosis model. Based on the fault diagnosis model, the fault score corresponding to the real-time failure response data is obtained, and a fault score threshold is set. When the fault score output by the fault diagnosis model exceeds this threshold, the node corresponding to the combinational logic circuit to be diagnosed has a fault. For each node, its failure probability is estimated according to its contribution in the fault score calculation process. The dependence of the node in the internal calculation process of the analysis model is calculated.

[0134] Another embodiment of the present invention provides a combinational logic multi-fault diagnosis system based on graph convolutional neural network, Figure 2 The corresponding system block diagram is as follows: Figure 2 As shown, the system includes:

[0135] The data preprocessing module M01 is configured to obtain a netlist file of the combinational logic circuit to be diagnosed and convert it into a directed graph of the logic circuit, and extract node features corresponding to each node in the directed graph of the logic circuit;

[0136] The fault injection simulation module M02 is configured to inject a random number of faults into random node positions of the combinational logic circuit to be diagnosed to generate a random test vector, and obtain failure response data through a circuit simulation model based on the random test vector;

[0137] A fault training data generating module M03 is configured to construct a fault element graph set based on the failure response data by using a fault element graph method, calculate a fault score based on the fault element graph set, and generate fault training data by associating the fault with the corresponding fault;

[0138] The model training module M04 is configured to input the fault training data into the graph convolutional neural network model for iterative training to build a fault diagnosis model;

[0139] The fault diagnosis module M05 is configured to diagnose the real-time failure response data of the combinational logic circuit to be diagnosed based on the fault diagnosis model to obtain the fault probability of each node.

[0140] In the description provided herein, algorithms and displays are not inherently related to any particular computer, virtual system or other device. Various general purpose systems can also be used together with the examples of the present invention. According to the above description, it is obvious that the structure required for constructing such systems. In addition, the present invention is not directed to any specific programming language either. It should be understood that various programming languages ​​can be utilized to implement the content of the present invention described herein, and the above description of specific languages ​​is for the purpose of disclosing the preferred embodiment of the present invention.

[0141] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0142] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the following intention: that the claimed invention requires more features than the features explicitly recited in each claim. More specifically, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Therefore, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, with each claim itself serving as a separate embodiment of the present invention.

[0143] Those skilled in the art will appreciate that the modules or units or components of the devices in the examples disclosed herein may be arranged in the devices described in the embodiment, or alternatively may be located in one or more devices different from the devices in the examples. The modules in the foregoing examples may be combined into one module or may be divided into multiple submodules.

[0144] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and further may be divided into a plurality of submodules or subunits or subcomponents. All features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device so disclosed may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0145] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present invention and form different embodiments. For example, in the claims below, any one of the claimed embodiments may be used in any combination.

[0146] In addition, some of the embodiments are described herein as a combination of methods or method elements that can be implemented by a processor of a computer system or by other devices that perform the functions. Therefore, a processor with necessary instructions for implementing the method or method elements forms a device for implementing the method or method elements. In addition, the elements described herein of the device embodiments are examples of devices that are used to implement the functions performed by the elements for implementing the purpose of the invention.

[0147] As used herein, unless otherwise specified, the use of ordinal numbers "first," "second," "third," etc. to describe common objects merely indicates that different instances of similar objects are involved, and is not intended to imply that the objects so described must have a given order in time, space, order, or in any other manner.

[0148] Although the present invention has been described according to a limited number of embodiments, it will be apparent to those skilled in the art, with the benefit of the above description, that other embodiments may be envisioned within the scope of the invention thus described. In addition, it should be noted that the language used in this specification is selected primarily for readability and teaching purposes, rather than for explaining or defining the subject matter of the present invention. Therefore, many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the appended claims. The disclosure of the present invention is illustrative and not restrictive with respect to the scope of the present invention, and the scope of the present invention is defined by the appended claims.

[0149] The above specific implementation is a preferred implementation of a combinational logic multi-fault diagnosis method and system based on a graph convolutional neural network of the present invention. It is not intended to limit the specific implementation scope of the present invention. The scope of the present invention includes but is not limited to this specific implementation. All equivalent changes made in accordance with the shape and structure of the present invention are within the protection scope of the present invention.

Claims

1. A combinational logic multi-fault diagnosis method based on graph convolutional neural network, characterized in that: The steps include: Obtaining a netlist file of a combinational logic circuit to be diagnosed and converting it into a directed graph of a logic circuit, and extracting node features corresponding to each node in the directed graph of the logic circuit; Injecting a random number of faults into random node positions of the combinational logic circuit to be diagnosed to generate a random test vector, and acquiring failure response data through a circuit simulation model based on the random test vector; Based on the failure response data, a fault element graph set is constructed by a fault element graph method, and a fault score is calculated based on the fault element graph set and associated with the corresponding fault to generate fault training data; Inputting the fault training data into a graph convolutional neural network model for iterative training to construct a fault diagnosis model; Based on the fault diagnosis model, the real-time failure response data of the combinational logic circuit to be diagnosed is diagnosed to obtain the failure probability of each node; The method of inputting the fault training data into the graph convolutional neural network model for iterative training to construct a fault diagnosis model includes: setting the network structure and model parameters of the graph convolutional neural network model, and initializing weights and bias parameters, wherein the model parameters include the number of layers, node feature dimensions, and hidden layer dimensions; inputting the fault training data into the graph convolutional neural network model for forward propagation to obtain a predicted fault score; calculating a corresponding loss function based on the predicted fault score combined with the fault score on the node; performing back propagation based on the gradient descent method to calculate the gradient of the loss function relative to the model parameters, and updating the weights and bias parameters of the graph convolutional neural network model according to the gradient; iteratively running the process from forward propagation to back propagation until the maximum number of iterations is reached to obtain a fault diagnosis model, and evaluating the fault diagnosis model based on evaluation indicators, wherein the evaluation indicators include accuracy, recall rate, and F1 score; The inputting of the fault training data into the graph convolutional neural network model for forward propagation to obtain a predicted fault score includes: inputting a node feature matrix and corresponding adjacent nodes in the fault training data into a graph convolutional layer of the graph convolutional neural network model; performing a graph convolution operation on the node feature matrix and the corresponding adjacent nodes through the graph convolutional layer to aggregate information of adjacent nodes, and updating the node feature matrix; and inputting the updated node feature matrix into a fully connected layer of the graph convolutional neural network model to convert it into a predicted fault score.

2. The combinational logic multi-fault diagnosis method based on graph convolutional neural network according to claim 1 is characterized in that: Obtaining a netlist file of a combinational logic circuit to be diagnosed and converting it into a directed graph of a logic circuit, and extracting node features corresponding to each node in the directed graph of the logic circuit, including: Obtaining a netlist file corresponding to the combinational logic circuit to be diagnosed; Constructing a corresponding logic circuit directed graph based on the netlist file of the combinational logic circuit to be diagnosed; Classifying all nodes in the directed graph of the logic circuit to obtain corresponding node types, and marking the nodes based on the node types, wherein the node types include input nodes, output nodes, and intermediate nodes; The node features of each node are extracted and normalized to construct a node feature matrix.

3. The combinational logic multi-fault diagnosis method based on graph convolutional neural network according to claim 2 is characterized in that: Constructing a corresponding logic circuit directed graph based on the netlist file of the combinational logic circuit to be diagnosed, including: Reading the netlist file to identify the components in the combinational logic circuit to be diagnosed and the connection relationship between the components; Initialize directed data structures for storing nodes and directed edges; Traversing each component in the netlist file, and mapping each component to a corresponding node of the directed data structure to obtain an intermediate directed graph; The connection relationship between the components is added to the corresponding edge of the intermediate directed graph to obtain a logic circuit directed graph.

4. The combinational logic multi-fault diagnosis method based on graph convolutional neural network according to claim 2 is characterized in that: The node features of each node are extracted and normalized to construct a node feature matrix, including: Extracting structural features and functional features corresponding to each node, wherein the structural features at least include the degree of the node, the type of adjacent nodes, and the node level, and the functional features at least include the logical function; Respectively converting the structural features and the functional features into corresponding feature codes; Normalizing the numerical features in the feature codes to eliminate the dimensional differences between the feature codes; A feature matrix is ​​constructed based on the normalized feature codes as columns and the corresponding nodes as rows.

5. The combinational logic multi-fault diagnosis method based on graph convolutional neural network according to claim 1 is characterized in that: Injecting a random number of faults into random node positions of the combinatorial logic circuit to be diagnosed to generate a random test vector, and acquiring failure response data through a circuit simulation model based on the random test vector, including: Constructing a circuit simulation model corresponding to the combinational logic circuit to be diagnosed based on the node characteristics; generating a random number representing a random number of failures through a Poisson distribution; Traversing all nodes in the directed graph of the logic circuit, and selecting a corresponding number of nodes according to the random number to inject fault signals into the circuit simulation model; A random test vector is generated based on a uniform random distribution method, and a circuit simulation model is run in combination with the random test vector and an injected fault signal to obtain failure response data corresponding to each random test vector.

6. The combinational logic multi-fault diagnosis method based on graph convolutional neural network according to claim 1 is characterized in that: Constructing a fault element graph set based on the failure response data by using a fault element graph method, calculating a fault score based on the fault element graph set and associating the fault with the corresponding fault to generate fault training data, including: Initialize an empty set of fault element graphs corresponding to each failure response data; Based on the fault element graph method, iterative analysis is performed on the fault corresponding to each failure response data to obtain the corresponding fault element graph; Add the fault element graph to the empty set of fault element graphs according to the current failure response data to obtain a set of fault element graphs; determining a fault score in combination with the fault element graph and adding the fault score to a corresponding node; The fault score of each node and the node feature are integrated to obtain fault training data.

7. The combinational logic multi-fault diagnosis method based on graph convolutional neural network according to claim 1 is characterized in that: Based on the fault diagnosis model, the real-time failure response data of the combinational logic circuit to be diagnosed is diagnosed to obtain the failure probability of each node, including: Acquire real-time failure response data of the combinational logic circuit to be diagnosed; Inputting the real-time failure response data into a fault diagnosis model, and obtaining a fault score corresponding to the real-time failure response data based on the fault diagnosis model; The failure probability of the node corresponding to the real-time failure response data is calculated based on the failure score.

8. A combinational logic multi-fault diagnosis system based on graph convolutional neural network, applicable to the combinational logic multi-fault diagnosis method based on graph convolutional neural network as claimed in any one of claims 1 to 7, characterized in that: include: A data preprocessing module is configured to obtain a netlist file of a combinational logic circuit to be diagnosed and convert it into a directed graph of a logic circuit, and extract node features corresponding to each node in the directed graph of the logic circuit; A fault injection simulation module is configured to inject a random number of faults into random node positions of the combinational logic circuit to be diagnosed to generate a random test vector, and obtain failure response data through a circuit simulation model based on the random test vector; A fault training data generating module is configured to construct a fault element graph set based on the failure response data by a fault element graph method, calculate a fault score based on the fault element graph set, and generate fault training data by associating with a corresponding fault; A model training module is configured to input fault training data into a graph convolutional neural network model for iterative training to build a fault diagnosis model; The fault diagnosis module is configured to diagnose the real-time failure response data of the combinational logic circuit to be diagnosed based on the fault diagnosis model to obtain the fault probability of each node.

Images