SPI interface chip configuration system and method

Abstract

The present invention discloses a SPI interface chip configuration system and method, which is implemented based on a field programmable gate array (FPGA), and includes: a command execution module for detecting and reading the output of an instruction code table using a state machine, performing command recognition on the output instruction code according to the agreed format in the instruction code table, jumping to the corresponding state, and extracting the corresponding operand, interacting with an SPI timing control module based on the recognized instruction code and the extracted operand, and completing the jump to the next state according to the jump condition in the current state; and an SPI timing control module for configuring the SPI interface chip according to the instruction code and the operand. For different chips with a standard SPI serial universal interface, the present invention only needs to maintain a ROM instruction code table and some macro definition parameters. The design difficulty and time cost of developers are greatly reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of interface configuration, and in particular to a SPI interface chip configuration system and method. Background Art

[0002] With the rapid development of the electronics industry, the integration of electronic chips is getting higher and higher, and the functions are becoming more and more powerful. Usually, chips such as AD / DA have a four-wire or three-wire serial SPI (Serial Peripheral Interface) interface, which allows programming and reading back of the internal register parameters of the chip. However, there are many registers in the chip (dozens or even hundreds), and the control is complex. The existing configuration method requires a lot of modification of the design code each time for different chips, with poor portability, inflexible configuration, and single function. It is necessary to design a flexible and universal configuration method. Summary of the invention

[0003] The purpose of the present invention is to overcome the defects of the prior art, and proposes a SPI interface chip configuration system and a SPI interface chip configuration method to achieve flexibility and versatility of SPI interface chip configuration.

[0004] To achieve the above object, the present invention provides a SPI interface chip configuration system, which is implemented based on a field programmable gate array (FPGA), and includes: a command execution module and a SPI timing control module; wherein,

[0005] The command execution module is used to detect and read the output of the instruction code table using the state machine, perform command recognition on the output instruction code according to the agreed format in the instruction code table, jump to the corresponding state, and extract the corresponding operand, interact with the SPI timing control module based on the recognized instruction code and the extracted operand, and complete the jump to the next state according to the jump condition in the current state, wherein the instruction code table is pre-stored in the ROM, and the bit width of the instruction code and the operand and the depth of the instruction code table are defined according to the SPI interface chip type and project requirements;

[0006] The SPI timing control module is used to interact with the command execution module and configure the SPI interface chip according to the instruction code and the operand.

[0007] As an improvement of the above system, the instruction codes in the instruction code table include part or all of: a write register command, a wait command, a read back monitoring command, a read back verification command and a jump command.

[0008] As an improvement of the above system, the command execution module is specifically used to initiate an SPI configuration request to the SPI timing control module when the instruction code is a write register command, a readback verification command or a readback monitoring command, and perform ROM addressing after receiving a notification that the current register configuration is completed;

[0009] The SPI timing control module is specifically used to interact with the SPI interface chip when an SPI configuration request is detected to complete the read and write operations on the current register, and to notify the command execution module when the current register configuration is completed.

[0010] As an improvement of the above system, the system further includes: a data selector and a serial port online debugging module; wherein,

[0011] The data selector is used to receive a serial port online debugging enable signal, and when a cyclic refresh configuration is required, the serial port online debugging module is not enabled; when the configuration needs to be modified online, the serial port online debugging module is enabled;

[0012] The serial port online debugging module is used to complete the writing and reading back of registers through the serial port, and to modify some registers online in real time;

[0013] The command execution module is also used to interact with the SPI timing control module through the data selector. When a cyclic refresh configuration is required, after the last register is configured, a wait command is executed. After the waiting time reaches a preset value, a jump command is executed to jump to the address in the ROM where the required refresh register is located to complete the cyclic refresh operation. When the configuration needs to be modified online, the instruction code table in the ROM is read, detected and executed until the last register configuration of the SPI interface chip is completed, and then the serial port online debugging mode is switched.

[0014] As an improvement of the above system, the command execution module includes multiple ROMs, each ROM stores an instruction code table, and one transmission mode matches one instruction code table;

[0015] The command execution module is also used to detect a reconfiguration request and a current transmission mode. When a reconfiguration request is detected, the state machine is reset, and the matching instruction code table is enabled according to the current transmission mode, and the instruction code table of other modes is reset, wherein the current transmission mode is the transmission mode to be switched.

[0016] The present invention also provides a SPI interface chip configuration method, based on the above SPI interface chip configuration system, comprising:

[0017] The state machine of the command execution module detects and reads the output of the ROM instruction code table, performs command recognition on the output instruction code according to the agreed format in the instruction code table, jumps to the corresponding state, and extracts the corresponding operand;

[0018] The command execution module interacts with the SPI timing control module based on the identified instruction code and the extracted operands, so that the SPI timing control module configures the SPI interface chip;

[0019] The state machine of the command execution module completes the jump to the next state according to the jump condition in the current state.

[0020] As an improvement of the above method, the instruction codes in the instruction code table include part or all of: a write register command, a wait command, a read back monitoring command, a read back verification command and a jump command.

[0021] As an improvement of the above method, based on the identified instruction code and the extracted operand, the command execution module interacts with the SPI timing control module, including:

[0022] When the instruction code is a write register command, a readback verification command or a readback monitoring command, the command execution module initiates an SPI configuration request to the SPI timing control module;

[0023] When the SPI timing control module detects the SPI configuration request, it interacts with the SPI interface chip to complete the read and write operations on the current register. When the current register configuration is completed, it notifies the command execution module.

[0024] The command execution module performs ROM addressing.

[0025] As an improvement of the above method, the method further comprises:

[0026] When a cyclic refresh configuration is required, the data selector does not enable the serial port online debugging enable signal. After the state machine configures the last register, it executes the wait command. After the waiting time reaches the preset value, it executes the jump command to jump to the address in the ROM where the register to be refreshed is located, completing the cyclic refresh operation.

[0027] When the configuration needs to be modified online, the command execution module uses the state machine to read, detect and execute the instruction code table in the ROM until the last register configuration of the SPI interface chip is completed. The data selector receives the serial port online debugging enable signal and switches to the serial port online debugging mode.

[0028] As an improvement of the above method, the method further includes: the command execution module includes a plurality of ROMs, each ROM stores an instruction code table, and one transmission mode matches one instruction code table; the method further includes:

[0029] The command execution module detects the reconfiguration request and the current transmission mode, wherein the current transmission mode is the transmission mode to be switched;

[0030] When the command execution module detects a reconfiguration request, the state machine is reset, and the matching instruction code table is enabled according to the current transmission mode, and the instruction code tables of other modes are reset.

[0031] Compared with the prior art, the advantages of the present invention are:

[0032] 1. The solution of the embodiment of the present invention proposes storing an instruction code table including instruction codes and operands in a ROM, and then using a state machine to execute the instructions and operands in the instruction code table to implement the SPI configuration solution. Since when configuring different SPI interface chips, it is only necessary to re-make an instruction code table according to the agreed instruction code table format based on the project requirements and the SPI interface chip type, and then hand it over to the state machine to use this instruction code table to complete the configuration of the SPI interface chip. Therefore, it has strong portability and high reusability, which can greatly reduce the design difficulty and time cost of developers.

[0033] 2. The solution of the embodiment of the present invention selects functions such as cyclic refresh configuration of registers or online modification after configuration is completed according to the actual operating environment requirements, taking into account different operating environment requirements.

[0034] 3. The solution of the embodiment of the present invention completes the switching selection of the instruction code table according to different transmission modes to adapt to the shortcomings of inconsistent performance of analog devices in different modes and meet the index requirements of the project. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a design principle diagram of the SPI interface chip configuration system of embodiment 1 of the present invention;

[0036] Figure 2 is a flow chart of a method for configuring an SPI interface chip according to Embodiment 2 of the present invention;

[0037] Figure 3 is the SPI timing diagram of AD9144 in Embodiment 3 of the present invention;

[0038] Figure 4 This is the FPGA state machine diagram in Example 3 of the present invention. DETAILED DESCRIPTION

[0039] The technical solution of the present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0040] Example 1

[0041] like Figure 1As shown, it is a design schematic diagram of the SPI interface chip configuration system of the embodiment of the present application, which is implemented based on FPGA (Field Programmable Gate Array). The FPGA is connected to the SPI interface chip through the SPI bus to complete the complex configuration of the internal registers of the SPI interface device in the FPGA. The system includes: a command execution module and a SPI timing control module.

[0042] The command execution module includes: ROM (Read-only Memory) and a state machine.

[0043] ROM is used to store pre-agreed instruction code tables. Each row of the instruction code table includes an instruction code and a corresponding operand. The bit width of the instruction code and the operand and the depth of the instruction code table are defined according to the SPI interface chip type and project requirements. Specifically, the instruction code table can be stored in the coe file of the ROM, and the control logic such as the state machine can be described by HDL (Hardware Description Language) instruction-type conditional loop statements.

[0044] The command execution module is used to use the state machine to detect and read the output of the instruction code table, identify the output instruction code according to the agreed format in the instruction code table, jump to the corresponding state, and extract the corresponding operand. Based on the identified instruction code and the extracted operand, it interacts with the SPI timing control module and completes the jump to the next state according to the jump condition in the current state.

[0045] The SPI timing control module is used to interact with the command execution module and configure the SPI interface chip according to the instruction code and operand.

[0046] Specifically, the SPI timing control module is used to receive the read and write commands and configuration content of the command execution module or the serial port online debugging module, complete the writing to the SPI interface chip according to the timing of the SPI interface chip manual; read back the register content returned by SPI and send it to the command execution module or the serial port online debugging module.

[0047] The above state machine can continuously read, parse and execute the instruction code table, and is used to perform command recognition, state jump and operation execution according to the agreed format in the instruction code table, and complete the write programming, readback verification and real-time monitoring of the internal register parameters of the SPI interface chip.

[0048] Preferably, the instruction codes in the instruction code table include part or all of: a write register command, a wait command, a read back monitoring command, a read back verification command and a jump command.

[0049] Specifically, the command execution module is specifically used to initiate an SPI configuration request to the SPI timing control module when the instruction code is a write register command, a readback verification command or a readback monitoring command, and perform ROM addressing after receiving a notification that the current register configuration is completed;

[0050] The SPI timing control module is specifically used to interact with the SPI interface chip when an SPI configuration request is detected to complete the read and write operations on the current register, and to notify the command execution module when the current register configuration is completed.

[0051] Preferably, when debugging is required, the SPI interface chip configuration system may further include: a serial port online debugging module and a data selector MUX;

[0052] The data selector is used to receive the serial port online debugging enable signal. When the configuration needs to be refreshed cyclically, the serial port online debugging module is disabled; when the configuration needs to be modified online, the serial port online debugging module is enabled.

[0053] The command execution module is also used to interact with the SPI timing control module through the data selector. When a cyclic refresh configuration is required, after the last register is configured, a wait command is executed. After the waiting time reaches a preset value, a jump command is executed to jump to the address in the ROM where the required refresh register is located to complete the cyclic refresh operation. When the configuration needs to be modified online, the instruction code table in the ROM is read, detected and executed until the last register configuration of the SPI interface chip is completed, and then the serial port online debugging mode is switched;

[0054] The serial port online debugging module is used to complete the writing and reading of registers through the serial port, and to modify some registers online in real time.

[0055] Specifically, the serial port online debugging module includes serial port receiving, serial port parsing and serial port sending;

[0056] Serial port receiving, used to receive serial port command frames sent by the serial port debugging assistant;

[0057] Serial port parsing, used to parse serial port command frames and extract read and write commands and configuration content;

[0058] Serial port sending is used to send the SPI read-back content to the serial port debugging assistant for display.

[0059] Preferably, the command execution module includes one or more ROMs. When multiple ROMs are included, each ROM may store an instruction code table, and one transmission mode matches one instruction code table.

[0060] The command execution module is also used to detect a reconfiguration request and a current transmission mode. When a reconfiguration request is detected, the state machine is reset, and the matching instruction code table is enabled according to the current transmission mode, and the instruction code table of other modes is reset, wherein the current transmission mode is the transmission mode to be switched.

[0061] In the scheme of Example 1 of the present invention, for different chips with standard SPI serial universal interface, only one instruction code table and some macro definition parameters need to be maintained. The state machine performs command recognition, state jump and operation execution according to the agreed format in the instruction code table, completes the functions of writing programming, readback verification and real-time monitoring of internal register parameters, greatly reducing the design difficulty and time cost of developers. According to the actual operating environment requirements, the registers can be refreshed and configured in a loop or modified online after the configuration is completed, taking into account the different operating environment requirements. The switching selection of the instruction code table is completed according to different transmission modes to adapt to the shortcomings of inconsistent performance of analog devices in different modes and meet the index requirements of the project.

[0062] Example 2

[0063] Based on the SPI interface chip configuration system described in Example 1, this Example 2 describes a SPI interface chip configuration method. Figure 2 As shown, the following steps are included:

[0064] Step 201: The state machine of the command execution module detects and reads the output of the ROM instruction code table, performs command recognition on the output instruction code according to the agreed format in the instruction code table, jumps to the corresponding state, and extracts the corresponding operand.

[0065] Step 202: The command execution module interacts with the SPI timing control module based on the identified instruction code and the extracted operands.

[0066] Step 203: The SPI timing control module configures the SPI interface chip according to the instruction code and the operand.

[0067] Specifically, when the instruction code involves a read / write command, the SPI timing control module configures the SPI interface chip according to the contents of the operands, that is, the register address and the register contents.

[0068] The instruction codes in the above instruction code table include: some or all of the write register command, wait command, read back monitoring command, read back verification command and jump command, which can be used based on actual needs.

[0069] Step 204: The state machine completes the jump to the next state according to the jump condition in the current state.

[0070] The following are the instructions for each of the above commands:

[0071] Write register command: configure the corresponding address and content to the SPI register. When the configuration is completed, the state machine returns to the initial state.

[0072] Waiting command: During the waiting period, no SPI register configuration is performed. When the waiting time reaches the preset value (for example, N ms), it returns to the initial state and prepares to execute the next instruction. The purpose of the waiting command is that some registers in the device cannot respond immediately after writing, so it is necessary to wait for a while before executing the configuration of the next register. At the same time, the time interval for the cyclic refresh of the on-board register is also completed by the waiting command. The preset value N here can be defined using the macro definition parameter;

[0073] Readback monitoring command: write the corresponding address to the SPI register, and the content is DNC (Do not Care). When the configuration is completed, it returns to the initial state. The function of the readback monitoring command is that some registers can reflect whether the working status of the device is normal. These registers can be written into the dual-port RAM and monitored in real time by the host computer.

[0074] Readback verification command: Write the corresponding address to the SPI register, and perform bitwise AND on the mask and the readback content. If the result of the bitwise AND is the same as the "expected value", it returns to the initial state and continues to execute the next command; if the result of the bitwise AND is different from the "expected value", it is necessary to perform another verification until the verification is successful or the number of verifications reaches the upper limit of the set number of verifications (for example, M times), the state machine returns to the initial state and prepares to execute the next instruction. The M times here can be defined using macro definition parameters.

[0075] Jump command: When a jump command is detected, the ROM address is set to the jump address, and the state machine returns to the initial state, ready to execute the command at the jump address.

[0076] It should be noted that the above instruction codes are the focus of the present invention. Using these instruction codes individually or in combination to implement the configuration of the SPI interface chip reflects the versatility and reliability of the configuration method of the present invention.

[0077] The existing configuration method only provides a write register command and a read register command, but after some registers are written, the SPI interface chip will not respond immediately and needs to wait for a while. Therefore, the present invention designs a wait command, and the wait command also guarantees the refresh requirement.

[0078] For some registers, such as register A, after writing register A, register B should be equal to C0, but when reading back register B, it is equal to 00, which means that register B does not get a correct response and needs to write register A again. This is repeated, which generates the need for a readback verification command, so the present invention designs a readback verification command.

[0079] Certain registers can monitor whether the entire chip or link is working properly. The readback contents of these registers can be sent to the CPU host computer as telemetry for real-time monitoring, which generates the need for readback monitoring commands. Therefore, the present invention designs a readback monitoring command.

[0080] The existing configuration method usually ends after one configuration. However, due to the influence of the radiation environment, some registers need to be constantly refreshed and some registers cannot be refreshed in response to the needs on the satellite. This generates the need for wait commands and jump commands. Therefore, the present invention designs wait commands and jump commands to jointly complete the refresh requirements. For example, there are ABCDEF registers, and register CD needs to be refreshed every 5s. The 5s is controlled by the wait command, and how to refresh CD after configuring F is controlled by the jump command.

[0081] Specifically, in the above step 202, based on the identified instruction code and the extracted operand, the command execution module interacts with the SPI timing control module, specifically including: when the instruction code is a write register command, a readback verification command or a readback monitoring command, the command execution module initiates an SPI configuration request to the SPI timing control module; when the SPI timing control module detects the SPI configuration request, it interacts with the SPI interface chip to complete the read and write operations on the current register, and when the current register configuration is completed, notifies the command execution module; the command execution module performs ROM addressing.

[0082] Preferably, according to different operating environments, the configuration mode can be divided into a cyclic refresh configuration mode and an online modification configuration mode. The former is suitable for the on-orbit operation stage, and the latter is suitable for the ground test and debugging stage.

[0083] When a cyclic refresh configuration is required, the data selector does not enable the serial port online debugging enable signal. After the state machine configures the last register, it executes the wait command. After the waiting time reaches the preset value, it executes the jump command to jump to the address in the ROM where the register to be refreshed is located, completing the cyclic refresh operation.

[0084] When the configuration needs to be modified online: the state machine reads, detects and executes the instruction code table in the ROM until the last register configuration of the SPI interface chip is completed. The MUX receives the serial port online debugging enable signal and switches to the serial port online debugging mode.

[0085] In actual operation, for the configuration in the ground test phase, in the early stage of debugging, you can choose to complete the writing and reading back of the registers through the serial port or the VIO debugging IP core that comes with the compilation tool, that is, to modify certain registers online in real time; in the later stage of debugging, you can choose to fine-tune certain registers after the ROM configuration is completed once.

[0086] By using the solution of the embodiment of the present invention, functions such as cyclic refresh configuration of registers can be realized during the on-orbit operation stage on the satellite, and functions such as one-time ROM configuration and subsequent online modification can be realized during the ground test and debugging stage.

[0087] In some projects, there are multiple transmission modes, and different transmission modes have different modulation methods and transmission rates. However, analog devices (such as transformers, filters, modulators, etc.) can only perform well at high speed or low speed, and cannot take into account all transmission modes at the same time, resulting in EVM (vector amplitude error) and power under a single configuration failing to meet project index requirements. In order to solve this problem, the present invention stores multiple instruction code tables in multiple ROMs included in the command execution module according to the needs of the transmission mode, and one transmission mode matches one instruction code table; the configuration method of the SPI interface chip at this time is:

[0088] The command execution module detects the reconfiguration request and the current transmission mode, wherein the current transmission mode is the transmission mode to be switched;

[0089] When the command execution module detects a reconfiguration request, the state machine is reset, and the matching instruction code table is enabled according to the current transmission mode, and the instruction code tables of other modes are reset.

[0090] After the instruction code table is matched, step 201 to step 204 are executed to complete the configuration of the SPI interface chip.

[0091] In the above scheme, the instruction code table is switched and selected according to different transmission modes. When the transmission mode switch is detected, the state machine is reset, and the corresponding ROM configuration parameters are selected according to the current mode to complete the reconfiguration of the SPI register to adapt to the characteristics of analog devices such as modulators and meet the project's index requirements.

[0092] The solution of Example 2 of the present invention is described in detail below through a specific example in Example 3.

[0093] Example 3

[0094] This embodiment 3 takes a project as an example to illustrate the method of configuring the SPI interface chip in embodiment 1. There are three transmission modes in this project, namely: 8PSK modulation, dual-channel rate 2*900Mbps; QPSK modulation, single-channel rate 300Mbps; QPSK modulation, single-channel rate 30Mbps. The chip used is AD9144, and the SPI timing of AD9144 is as follows: Figure 3 shown.

[0095] The communication cycle of the AD9144 can be divided into two phases. Figure 3 In the first stage, the instruction cycle is to write the register address to the device, which is synchronized with the first 16 rising edges of the serial clock SCLK. This stage clearly indicates whether the operation is a read operation (logic 1) or a write operation (logic 0), as well as the register address A[14:0]. The second stage is the data transmission cycle, and the instruction word provides information about the register contents to the serial port controller. The serial port supports a three-wire or four-wire interface. The present invention selects a four-wire interface by configuring the register, where SDIO is the input of AD9144 and SDO is the output of AD9144. Indicates chip select enable, low level is valid.

[0096] Since the project has three modes, in order to ensure good consistency of the output power of the data transmission in various modes and meet the EVM indicators, the state machine and certain key registers need to be reset and reconfigured each time a different transmission mode is enabled.

[0097] According to the definition of the AD9144 configuration register, the format of the coe instruction code table in the ROM can be agreed upon as shown in Table 1. Of course, different chips can agree on different instruction code tables.

[0098] Table 1 Format of instruction code table

[0099]

[0100] When it is detected that the reconfiguration Cfg_Start is valid, the ROM instruction code table in the current mode is enabled and the ROM instruction code table in other modes is reset.

[0101] Assume that the instruction code table matching in the ROM in the current mode is as follows:

[0102] 0x01 spi_rw+spi_addr[14:0]spi_wr_data[7:0]

[0103] 0x02 spi_rw+spi_addr[14:0]chk_pos[7:0]exp_val[7:0]jump_addr[11:0]

[0104] Next, the AD9144 chip is configured according to steps 201 to 204 in Example 2 using the above instruction code table:

[0105] Step 1: The state machine reads 0x01, and according to the format in Table 1 above, recognizes 0x01 as a write register command, jumps to the REG_WRITE write state, and extracts the operand spi_rw+spi_addr[14:0]spi_wr_data[7:0];

[0106] Step 2: The command execution module sends a configuration request signal to the SPI timing control module and sends spi_rw+spi_addr[14:0]spi_wr_data[7:0] to the SPI timing control module.

[0107] Step 3: When the SPI timing control module detects that the SPI configuration request signal spi_req sent by the command execution module is valid, the SPI read and write operation signal spi_rw, SPI register address spi_addr[14:0], and SPI register content spi_wr_data[7:0] are spliced ​​into a 24-bit register, shifted left, and serially output to SDIO. When the current register is written, the spi_done signal is enabled to indicate the end of this transmission, and the spi_done signal is output to the command execution module.

[0108] Step 4: If the state machine detects that the jump condition spi_done is valid, the ROM address is incremented by 1 to prepare for addressing the next instruction code, and the state machine returns to IDLE, otherwise it continues in the REG_WRITE state.

[0109] Step 5: The command execution module continues to address the ROM. The state machine determines that the current command type is a read-back verification command based on the ROM output 0x02, jumps to the REG_READ_CHK state, extracts the operand spi_rw+spi_addr[14:0], and spi_wr_data[7:0] is DNC.

[0110] Step 6 (same as step 2): The command execution module sends a configuration request signal to the SPI timing control module, and sends spi_rw+spi_addr[14:0]spi_wr_data[7:0] to the SPI timing control module.

[0111] Step 7: When the SPI timing control module detects that the SPI configuration request signal spi_req sent by the command execution module is valid, the SPI read and write operation signal spi_rw, SPI register address spi_addr[14:0], and SPI register content spi_wr_data[7:0] are spliced ​​into a 24-bit register, and shifted left and serially output to SDIO. When the chip select signal is valid and the second phase of the data transmission cycle is currently in progress, SDO is shifted and registered to obtain the 8-bit readback content spi_rd_data[7:0]. If the current spi_rw is a read operation, the readback content spi_rd_data[7:0] and the readback enable spi_rd_dv are sent to the command execution module.

[0112] Step 8: The state machine reads back the jump condition in the REG_READ_CHK readback check state to enable spi_rd_dv, jumps to the VALUE_CHECK_PRE state, the ROM address remains unchanged, and the state machine jumps to the VALUE_CHECK state unconditionally. In the VALUE_CHECK state, if the check passes, the ROM address is increased by 1 to prepare for addressing the next instruction code, and the state machine returns to IDLE; if the check fails but the number of checks reaches the upper limit of the number of checks, the ROM address is increased by 1 to prepare for addressing the next instruction code, and the state machine returns to IDLE; if the check fails, but the number of checks does not meet the upper limit of the number of checks, the ROM address is equal to the jump address jump_addr, which means that the jump_addr line instruction is re-executed.

[0113] The state machine has 8 states in total, such as Figure 4 As shown, they are: idle state IDLE, write state REG_WRITE, wait state WAIT_MS, read back check state REG_READ_CHK, check preparation state VALUE_CHECK_PRE, check in progress VALUE_CHECK, read back monitoring state REG_READ_BACK and jump state JUMP.

[0114] When the state machine is in IDLE, it indicates that the current state is idle and can be addressed from the ROM. The state machine detects the high 8 bits of the ROM output data, which is the instruction code in Table 1.

[0115] If the instruction code is 0x01, the state machine jumps to REG_WRITE. In this state, if spi_done is detected to be valid, the ROM address is increased by 1 to prepare for addressing the next instruction code, and the state machine returns to IDLE, otherwise it continues in the REG_WRITE state.

[0116] If the instruction code is 0x02, the state machine jumps to REG_READ_CHK. In this state, the ROM address remains unchanged. If the read-back enable spi_rd_dv is detected to be valid, the state machine jumps to VALUE_CHECK_PRE, otherwise it continues in REG_READ_CHK; in the VALUE_CHECK_PRE state, the ROM address remains unchanged, and the state machine jumps to the VALUE_CHECK state unconditionally. In the VALUE_CHECK state, if the check passes, the ROM address is increased by 1 to prepare for addressing the next instruction code, and the state machine returns to IDLE; if the check fails but the number of checks reaches the upper limit of the number of checks, the ROM address is increased by 1 to prepare for addressing the next instruction code, and the state machine returns to IDLE; if the check fails, but the number of checks does not meet the upper limit of the number of checks, the ROM address is equal to the jump address jump_addr, which means that the jump_addr line instruction is re-executed.

[0117] If the instruction code is 0x04, the state machine jumps to REG_READ_BACK. In this state, if the read back enable spi_rd_dv is detected to be valid, the ROM address is increased by 1 to prepare for addressing the next instruction code, and the state machine returns to IDLE, otherwise it continues in REG_READ_BACK.

[0118] If the instruction code is 0x08, the state machine jumps to WAIT_MS. In this state, if the waiting time reaches the preset value, the ROM address is increased by 1 to prepare for addressing the next instruction code, and the state machine returns to IDLE, otherwise it continues in WAIT_MS.

[0119] If the instruction code is 0x10, the state machine jumps back to the IDLE state unconditionally, and the ROM address is equal to the jump address jump_addr.

[0120] When the state machine is in the waiting state WAIT_MS, the ms timing counter is started, and when the timing counter value reaches the preset value, the counting is stopped.

[0121] When the state machine is in the readback check state REG_READ_CHK, it determines whether the check result is equal to the expected result and gives the check passed flag check_passed. If the check passes and the state machine is in VALUE_CHECK_PRE, the check times are cleared; if the check times reach the upper limit of the check times and the state machine is in VALUE_CHECK, the check times are cleared; if the check fails and the state machine is in VALUE_CHECK_PRE, the check times are accumulated. Otherwise, the check times remain unchanged. The upper limit of the check times MAX_CHECK_TIMES is a macro definition parameter.

[0122] When the instruction code is SPI_WRITE / SPI_READ_CHECK / SPI_READ_BACK, enable spi_req to initiate a request to the SPI configuration module.

[0123] Taking into account the different requirements of the on-orbit operation stage and the ground test stage, the chip configuration of the present invention also provides that in the on-orbit stage, some registers in the chip need to be refreshed, and the status of some registers needs to be monitored in real time. After all registers are configured, the state machine completes the refresh operation through the waiting command SPI_WAIT and the jump command SPI_JUMP, and the waiting time is the refresh time interval; after all registers are configured, the state machine completes the register monitoring through the readback monitoring command SPI_READ_BACK and the jump command SPI_JUMP, and writes the monitored content and address into the dual-port RAM for real-time monitoring by the CPU.

[0124] During the ground test and debugging phase, the early designers need to be familiar with the chip configuration process and methods. In the later stage, they need to continuously calibrate the EVM, adjust the output power and other requirements, so it is necessary to write and read back the registers in real time. Considering the design versatility and implementation complexity, a simple and universal serial communication is used to realize the function of online modification of registers. The host computer only needs to install a serial port assistant, and the online modification of the registers can be completed according to the agreed serial port format. Considering the reliability of transmission, in order to prevent the serial port from being mis-entered and causing subsequent instructions to fail to parse or parse incorrectly, the serial port data needs to have a frame header for synchronization.

[0125] The present invention has the following advantages:

[0126] (1) The present invention has strong portability and high reusability. For different chips with standard SPI serial universal interface, the present invention only needs to maintain a ROM instruction code table and some macro definition parameters, which greatly reduces the design difficulty and time cost of developers.

[0127] (2) The present invention takes into account different operating environment requirements. During the on-orbit operation phase, the configuration can be refreshed cyclically; during the ground verification and debugging phase, the configuration can be modified online after the configuration is completed.

[0128] (3) The present invention can adapt to the inconsistency of analog devices in different modes. Different configuration parameters are selected for different modes to compensate for the inconsistency of analog devices.

[0129] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention is described in detail with reference to the embodiments, it should be understood by those skilled in the art that any modification or equivalent replacement of the technical solutions of the present invention does not depart from the spirit and scope of the technical solutions of the present invention and should be included in the scope of the claims of the present invention.

Claims

1. A SPI interface chip configuration system, based on a field programmable gate array FPGA, characterized in that: include: Command execution module and SPI timing control module; among them, The command execution module is used to detect and read the output of the instruction code table using a state machine, perform command recognition on the output instruction code according to the agreed format in the instruction code table, jump to the corresponding state, and extract the corresponding operand, interact with the SPI timing control module based on the recognized instruction code and the extracted operand, and complete the jump to the next state according to the jump condition in the current state, wherein the instruction code table is pre-stored in the ROM, and the bit width of the instruction code and the operand and the depth of the instruction code table are defined according to the SPI interface chip type and project requirements; the command execution module includes multiple ROMs, each ROM stores an instruction code table, and one transmission mode matches an instruction code table; The SPI timing control module is used to interact with the command execution module and configure the SPI interface chip according to the instruction code and the operand; The instruction codes in the instruction code table include: part or all of a write register command, a wait command, a readback monitoring command, a readback verification command, and a jump command; the system uses a single instruction code or a combination of them to implement the configuration of the SPI interface chip; The command execution module is specifically used to initiate an SPI configuration request to the SPI timing control module when the instruction code is a write register command, a readback verification command or a readback monitoring command, and perform ROM addressing after receiving a notification that the current register configuration is completed; The SPI timing control module is specifically used to interact with the SPI interface chip when an SPI configuration request is detected to complete the read and write operations on the current register, and notify the command execution module when the current register configuration is completed; The system also includes: a data selector and a serial port online debugging module; wherein, The data selector is used to receive a serial port online debugging enable signal, and when a cyclic refresh configuration is required, the serial port online debugging module is not enabled; when the configuration needs to be modified online, the serial port online debugging module is enabled; The serial port online debugging module is used to complete the writing and reading back of registers through the serial port, and to modify some registers online in real time; The command execution module is also used to interact with the SPI timing control module through the data selector. When a cyclic refresh configuration is required, after the last register is configured, a wait command is executed. After the waiting time reaches a preset value, a jump command is executed to jump to the address in the ROM where the required refresh register is located to complete the cyclic refresh operation. When the configuration needs to be modified online, the instruction code table in the ROM is read, detected and executed until the last register configuration of the SPI interface chip is completed, and then the serial port online debugging mode is switched.

2. The SPI interface chip configuration system as claimed in claim 1, characterized in that: The command execution module is also used to detect a reconfiguration request and a current transmission mode. When a reconfiguration request is detected, the state machine is reset, and the matching instruction code table is enabled according to the current transmission mode, and the instruction code table of other modes is reset, wherein the current transmission mode is the transmission mode to be switched.

3. A SPI interface chip configuration method, implemented based on the SPI interface chip configuration system of claim 1, comprising: The state machine of the command execution module detects and reads the output of the ROM instruction code table, performs command recognition on the output instruction code according to the agreed format in the instruction code table, jumps to the corresponding state, and extracts the corresponding operand; The command execution module interacts with the SPI timing control module based on the identified instruction code and the extracted operands, so that the SPI timing control module configures the SPI interface chip; The state machine of the command execution module completes the jump to the next state according to the jump condition in the current state.

4. The SPI interface chip configuration method as claimed in claim 3, characterized in that: The instruction codes in the instruction code table include: a write register command, a wait command, a read back monitoring command, a read back verification command and part or all of a jump command.

5. The SPI interface chip configuration method as claimed in claim 4, characterized in that: Based on the identified instruction code and the extracted operands, the command execution module interacts with the SPI timing control module, including: When the instruction code is a write register command, a readback verification command or a readback monitoring command, the command execution module initiates an SPI configuration request to the SPI timing control module; When the SPI timing control module detects the SPI configuration request, it interacts with the SPI interface chip to complete the read and write operations on the current register. When the current register configuration is completed, it notifies the command execution module. The command execution module performs ROM addressing.

6. The SPI interface chip configuration method as claimed in claim 3, characterized in that: Also includes: When a cyclic refresh configuration is required, the data selector does not enable the serial port online debugging enable signal. After the state machine configures the last register, it executes the wait command. After the waiting time reaches the preset value, it executes the jump command to jump to the address in the ROM where the register to be refreshed is located, completing the cyclic refresh operation. When the configuration needs to be modified online, the command execution module uses the state machine to read, detect and execute the instruction code table in the ROM until the last register configuration of the SPI interface chip is completed. The data selector receives the serial port online debugging enable signal and switches to the serial port online debugging mode.

7. The SPI interface chip configuration method as claimed in claim 3, characterized in that: Also includes: The command execution module includes multiple ROMs, each ROM stores an instruction code table, and one transmission mode matches one instruction code table; The method further comprises: The command execution module detects the reconfiguration request and the current transmission mode, wherein the current transmission mode is the transmission mode to be switched; When the command execution module detects a reconfiguration request, the state machine is reset, and the matching instruction code table is enabled according to the current transmission mode, and the instruction code tables of other modes are reset.

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