Voltage drop processing method, device, electronic device and storage medium

Abstract

The present invention provides a voltage drop processing method, device, electronic device and storage medium. In the layout planning stage, the layout information of each module is determined, the layout of the power supply network is determined in the pre-layout stage, and each module is placed in the formal layout stage, that is, a voltage drop test is performed based on the layout after layout to obtain a first test result. If the first test result does not meet the first preset requirement, the layout planning stage and the pre-layout stage are returned to perform iterations until it meets the first preset requirement, and the layout is subjected to clock tree synthesis and wiring to obtain a wiring diagram. Then, a voltage drop test is performed based on the wiring diagram to obtain a second test result. If the second test result does not meet the second preset requirement, the pre-layout stage is returned to perform iterations until it meets the second preset requirement. In this way, a voltage drop test is performed after the layout stage and after the wiring, so as to timely discover the existing voltage drop problem, thereby reducing the number of chip iterations and shortening the chip design and development time.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a voltage drop processing method, device, electronic device and storage medium. Background Art

[0002] As chip process sizes enter deep submicron and nanometer process nodes, the difficulty of chip design has reached a new height, and higher requirements have been placed on chip design methods, production tools, chip performance, etc. In the entire chip design process, a series of processes from architecture to packaging will be comprehensively considered around performance (Performance), power consumption (Power), area (Area) and many other aspects. When designing chips, chip designers need to find the best balance between the above three to meet specific application needs and market requirements. Design optimization is required for different scenarios, such as focusing on the balance between power consumption and performance on mobile devices, and focusing more on the balance between performance and area in data centers.

[0003] With the emergence of a large number of portable devices, low-power design has also emerged. Power consumption affects not only the ultra-long standby time and energy consumption of the device, but also the voltage drop (IR Drop). Voltage drop refers to a phenomenon in which the voltage drops or rises on the power supply and ground network in an integrated circuit. In the field of chip design, due to the continuous evolution of technology, the width of metal interconnects is getting narrower, the resistance value is getting larger, and the power supply voltage is getting smaller, the effect of voltage drop is becoming more and more obvious. Therefore, how to solve the problem of voltage drop is an important issue in the field of chip design.

[0004] At present, voltage drop detection is mainly carried out at the final stage of signoff. Signoff refers to the review of design data before handing it over to chip manufacturers for production to confirm whether the design data meets the inspection and confirmation included in the standard. However, in the chip design process, especially in the low-power chip design process, the requirements for chip voltage drop are relatively high. If voltage drop detection is carried out at the final stage of signoff, and then the purpose of correcting the voltage drop is achieved by modifying the chip power planning and layout planning, it will have an immeasurable impact on the design. For example, it may cause violations of timing and physical rule checks that have already met the requirements. In addition, it will take a lot of time to iterate the design and perform design iteration repair (Engineer Change Order, ECO). In this way, the chip design cycle will be greatly extended, and there will be defects such as waste of manpower and material resources. Summary of the invention

[0005] The objects of the present invention include, for example, providing a voltage drop processing method, device, electronic device and storage medium, which can reduce the number of chip iterations and shorten the chip design and development time.

[0006] The embodiments of the present invention can be implemented as follows:

[0007] In a first aspect, the present invention provides a voltage drop processing method, the method comprising:

[0008] In the layout planning stage, the placement information of each module is determined based on the obtained system parameters and constraint parameters;

[0009] In the pre-layout stage, layout information of the power supply network is determined according to the acquired power supply planning information, and the layout of the power supply network is performed according to the layout information;

[0010] In the formal layout stage, the modules are placed according to the layout information to obtain a layout after layout;

[0011] Performing a first voltage drop test based on the layout after layout to obtain a first test result, and if the first test result does not meet the first preset requirement, returning to the layout planning stage and the pre-layout stage to perform at least one iteration until the first test result obtained after the iteration meets the first preset requirement;

[0012] Perform clock tree synthesis and routing based on the layout that meets the first preset requirement to obtain a wiring diagram, perform a second voltage drop test based on the wiring diagram to obtain a second test result, and if the second test result does not meet the second preset requirement, return to the pre-layout stage to perform at least one iteration until the second test result obtained after the iteration meets the second preset requirement.

[0013] In an optional embodiment, the method further comprises:

[0014] Performing timing analysis on a netlist corresponding to the wiring diagram that meets the second preset requirement based on a timing analysis tool to obtain a timing analysis result;

[0015] If the timing analysis result does not meet the preset timing requirement, modify the netlist corresponding to the wiring diagram based on the acquired repair information until the timing analysis result obtained after the modification meets the preset timing requirement;

[0016] A third voltage drop test is performed based on the wiring diagram that meets the preset timing requirements to obtain a third test result. If the third test result does not meet the third preset requirement, the wiring diagram is adjusted based on the obtained adjustment information until the third test result obtained after adjustment meets the third preset requirement.

[0017] In an optional embodiment, the method further comprises:

[0018] Extracting a standard delay information file of a netlist based on a wiring diagram that meets the third preset requirement, and performing logic simulation based on the standard delay information file to obtain signal change information;

[0019] The final voltage drop of the chip is calculated according to the signal change information.

[0020] In an optional implementation, the constraint parameters include data flow direction information and power point location information;

[0021] The step of determining the placement information of each module according to the acquired system parameters and constraint parameters in the layout planning stage includes:

[0022] In the layout planning stage, each module is planned to obtain placement information based on the acquired system parameters, data flow direction information and power point location information, wherein the module connected to the power point is planned at a preset adjacent position to the power point.

[0023] In an optional implementation, the step of performing a first voltage drop test based on the layout after layout to obtain a first test result includes:

[0024] Performing a first voltage drop test based on the layout after layout to obtain a voltage drop value of each module in the layout after layout;

[0025] An average of the voltage drop values ​​of the modules is calculated according to the voltage drop values ​​of the modules, and the first test result is obtained based on the average and the voltage drop values ​​of the modules.

[0026] In an optional embodiment, the module includes a power shutoff device;

[0027] The step of determining the layout information of the power supply network according to the acquired power supply planning information in the pre-layout stage includes:

[0028] In the pre-layout stage, multiple circuit areas in the layout are determined according to the acquired power planning information, wherein each of the circuit areas corresponds to a different voltage domain;

[0029] adding different power lines to each of the circuit areas;

[0030] The power connection relationship between each power shutoff device and each circuit area is arranged, and the logic connection relationship between different power shutoff devices is arranged.

[0031] In an optional implementation, the step of laying out the power connection relationship between each of the power shutdown devices and each of the circuit regions, and laying out the logical connection relationship between different power shutdown devices, includes:

[0032] Connecting the first power pin of each power shutdown device to the normally open area in each circuit area, and connecting the second power pin of each power shutdown device to the shutdown area in each circuit area, wherein the first power pin is a power pin for controlling the normally open, and the second power pin is a power pin connected to the power network of the shutdown area;

[0033] Connect the pins of all power shutdown devices that control whether to shut down in series.

[0034] In an optional embodiment, the step of returning to the layout planning stage and the pre-layout stage to perform at least one iteration includes:

[0035] Returning to the layout planning stage and the pre-layout stage, and iteratively adjusting the placement information and the layout information of the power network at least once based on a first adjustment strategy;

[0036] Among them, the first adjustment strategy includes at least one of the following: adjusting the selection of each module, adjusting the layout position of each module, adjusting the width of the power line in the power network, and adjusting the spacing between the power lines.

[0037] In an optional embodiment, the module includes a decoupling capacitor device and a buffer;

[0038] The step of adjusting the selection of each module includes at least one of the following:

[0039] Increase the number of decoupling capacitor devices in the selected module;

[0040] Replacing the standard cells in the selected module with standard cells of smaller multiples and / or replacing the low-threshold devices in the selected module with high-threshold devices;

[0041] In an area where the length of the power line exceeds a predetermined length, a buffer is selected to be inserted into the area.

[0042] In an optional embodiment, the module includes a clock device and a power shutdown device;

[0043] The step of adjusting the placement position of each module includes at least one of the following:

[0044] For the area where clock devices are concentrated, the placement of the clock devices is adjusted by manual adjustment or unit filling method, so that the spacing between the adjusted clock devices meets the preset spacing requirement;

[0045] Reduce the spacing between power-off devices.

[0046] In an optional embodiment, the power line includes a power ring line and a power strip line, the power ring line is located in the edge area of ​​the chip, and the power strip line is located in the central area surrounded by the edge area of ​​the chip;

[0047] The step of adjusting the width of the power line includes:

[0048] Increase the width of the power loop.

[0049] In a second aspect, the present invention provides a voltage drop processing device, the device comprising:

[0050] The planning module is used to determine the placement information of each module according to the acquired system parameters and constraint parameters during the layout planning stage;

[0051] A pre-layout module, used to determine the layout information of the power supply network according to the acquired power supply planning information in the pre-layout stage, and perform the layout of the power supply network according to the layout information;

[0052] A formal layout module, used to place the modules according to the placement information in the formal layout stage to obtain a layout after layout;

[0053] An analysis module, configured to perform a first voltage drop test based on the layout after layout to obtain a first test result, and if the first test result does not meet a first preset requirement, return to the layout planning stage and the pre-layout stage to perform at least one iteration until the first test result obtained after the iteration meets the first preset requirement;

[0054] The analysis module is further used to perform clock tree synthesis and routing based on the layout that meets the first preset requirement to obtain a wiring diagram, and perform a second voltage drop test based on the wiring diagram to obtain a second test result. If the second test result does not meet the second preset requirement, return to the pre-layout stage to perform at least one iteration until the second test result obtained after the iteration meets the second preset requirement.

[0055] In a third aspect, the present invention provides an electronic device, comprising: a processor, a storage medium and a bus, wherein the storage medium stores program instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium through the bus, and the processor executes the program instructions to implement the voltage drop processing method as described in any one of the aforementioned embodiments.

[0056] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the voltage drop processing method as described in any one of the aforementioned embodiments.

[0057] The beneficial effects of the embodiments of the present invention include, for example:

[0058] The present invention provides a voltage drop processing method, device, electronic device and storage medium. In the layout planning stage, the layout information of each module is determined, in the pre-layout stage, the layout information of the power supply network is determined and the power supply network is laid out, and in the formal layout stage, each module is placed, so as to obtain the layout after layout. A voltage drop test is performed based on the layout after layout to obtain a first test result. If the first test result does not meet the first preset requirement, the layout planning stage and the pre-layout stage are returned to perform iterations until it meets the first preset requirement, and the layout is subjected to clock tree synthesis and wiring to obtain a wiring diagram. Then, a voltage drop test is performed based on the wiring diagram to obtain a second test result. If the second test result does not meet the second preset requirement, the pre-layout stage is returned to perform iterations until it meets the second preset requirement. In this way, a voltage drop test is performed after the layout stage and after wiring, so as to timely discover the existing voltage drop problem, thereby reducing the number of chip iterations and shortening the chip design and development time. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0060] Figure 1 A flow chart of a voltage drop processing method provided by an embodiment of the present invention;

[0061] Figure 2 A schematic diagram of a voltage drop problem existing in a chip provided by an embodiment of the present invention;

[0062] Figure 3 Another schematic diagram of the voltage drop problem existing in the chip provided by the embodiment of the present invention;

[0063] Figure 4 Another schematic diagram of the voltage drop problem existing in the chip provided by the embodiment of the present invention;

[0064] Figure 5 Another flow chart of the voltage drop processing method provided by an embodiment of the present invention;

[0065] Figure 6Another flow chart of the voltage drop processing method provided by the embodiment of the present invention;

[0066] Figure 7 A schematic diagram of the overall process of the voltage drop processing method provided by an embodiment of the present invention;

[0067] Figure 8 A functional module block diagram of a voltage drop processing device provided by an embodiment of the present invention;

[0068] Fig. 9 This is a structural block diagram of an electronic device provided by an embodiment of the present invention.

[0069] Icons: 11- planning module; 12- pre-layout module; 13- formal layout module; 14- analysis module; 21- processor; 22- storage medium. DETAILED DESCRIPTION

[0070] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0071] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0072] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0073] In the description of the present invention, it should be noted that the terms "first", "second", "third", etc., if used, are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0074] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.

[0075] The current mainstream voltage drop analysis method is to conduct a specific analysis of the voltage drop at the final stage of signoff. However, due to the characteristics of the process, the lower the metal layer, the greater the resistance, and the same is true for the power line. Therefore, the voltage drop of the bottom power network (power net) accounts for a high proportion.

[0076] In the design of low-power chips, since a power shutdown device is added to the low-power chip, the resistance of the power shutdown device is very large, which has a great impact on the voltage drop. Therefore, the low-power chip has a relatively higher requirement for the voltage drop.

[0077] In the final stage of sign-off, most of the bottom-level wiring resources are occupied by signal lines, and the power-off devices are also laid out. If the voltage drop problem is solved at this stage, it is necessary to delete the signal lines in the original position, strengthen the power lines, and adjust the layout of the power-off devices. This method requires major adjustments to the previously laid-out bottom-level wiring resources, and adjustments to the selection and location of the power-off devices. It is very likely to cause violations of the timing and physical rule checks that have already met the requirements.

[0078] In view of this, in order to solve the above problems, the present invention provides a voltage drop processing method, which performs voltage drop detection after the layout stage to promptly solve the existing voltage drop problem, and performs voltage drop detection again after wiring to further solve the existing voltage drop problem. In this way, the existing voltage drop problem is discovered in time, thereby reducing the number of chip iterations and shortening the chip design and development time.

[0079] Figure 1 This is a flowchart of a voltage drop processing method provided by an embodiment of the present invention. The execution subject of the voltage drop processing method can be a computer, a server, etc., and a program script for implementing the voltage drop processing method of this solution is deployed in the computer, the server, etc. Figure 1 As shown, the method may include:

[0080] Step 101, in the layout planning stage, the placement information of each module is determined according to the acquired system parameters and constraint parameters.

[0081] Step 102 , in the pre-layout stage, layout information of the power supply network is determined according to the acquired power supply planning information, and the power supply network is laid out according to the layout information.

[0082] Step 103, in the formal layout stage, the modules are placed according to the layout information to obtain a layout after layout.

[0083] Step 104, performing a first voltage drop test based on the layout after layout to obtain a first test result. If the first test result does not meet the first preset requirement, returning to the layout planning stage and the pre-layout stage to perform at least one iteration until the first test result obtained after the iteration meets the first preset requirement.

[0084] Step 105, perform clock tree synthesis and routing based on the layout that meets the first preset requirement to obtain a wiring diagram, perform a second voltage drop test based on the wiring diagram to obtain a second test result, and if the second test result does not meet the second preset requirement, return to the pre-layout stage to perform at least one iteration until the second test result obtained after the iteration meets the second preset requirement.

[0085] In the chip design process, the main process nodes involved include: data preparation stage - layout planning stage - layout stage - clock tree synthesis stage - wiring stage - timing verification stage - iterative repair stage, etc.

[0086] The system parameters and constraint parameters in this embodiment can be obtained in the data preparation stage, wherein the system parameters include gate-level netlist, database file, process file, etc., and the constraint parameters include timing constraint file (Standard Design Constraints, SDC), etc.

[0087] The gate-level netlist is obtained based on the real-time language (RTL) code of the front-end design. Specifically, after obtaining the RTL code, the back-end performs RTL code synthesis and converts the RTL code into a gate-level netlist through a synthesis tool. The gate-level netlist includes the modules to be used in the back-end design and the connection relationship between the modules.

[0088] Modules include macro cells, standard cells and IO cells. Macro cells are predefined logic function implementation units composed of triggers, arithmetic logic units, hardware registers, etc., which are at a higher level of abstraction than logic gates. These logic cells are placed on the silicon wafer as a macro cell. Standard cells are solidified basic units, including logic gates, drive units, timing units, operation units, etc. IO units are used to connect the inside of the chip with the package pins, and can be roughly divided into signal IO units and power IO units.

[0089] The database file mainly includes the information of the hard core (Intelligent Property, IP) used in chip design, including the port information, timing information and power consumption information of the hard core. A hard core refers to a fully designed and verified module with fixed functions and completed physical design. Its design parameters, such as size, power consumption and performance, are predetermined and cannot be changed. It should be noted that a hard core can be used as a special macro unit. The difference between it and an ordinary macro unit is that an ordinary macro unit has some configurable parameters that can be modified during the design process, while a hard core is final and cannot be modified in design.

[0090] The process files are usually provided by the integrated circuit manufacturer and include parameters of the manufacturing process, such as the number of metal layers, metal layer thickness, metal layer capacitance, minimum metal line spacing, etc.

[0091] The timing constraint file includes the constraint information to be met in the back-end design, including clock information, pseudo-clock paths, multi-clock cycle paths, etc.

[0092] After obtaining the above system parameters and constraint parameters in the data preparation stage, enter the layout planning stage of the next process node. In the layout planning stage, the main task is to plan the placement information of each module. The placement information of each module includes the arrangement of macro cells, standard cells, and IO cells on the layout. When planning the placement information of each module, multiple factors must be considered, including that the placement of IO cells must meet the requirements of chip packaging, and the design of the printed circuit board for chip packaging must be considered. The placement of macro cells should take into account the functions of the macro cells, and consider their interactions with other IO cells or macro cells, as well as the impact on the area where the standard cells are located and the overall layout of the chip, to avoid deep wells, diagonals, etc.

[0093] In addition, chip size planning and power network planning are also required in the layout planning stage. Reasonable chip size is directly related to the cost of the chip. If the chip utilization is too low, the cost will be too high, while if the chip utilization is too high, it may cause wiring failure in the later stage. When planning the power network, the planning can be carried out through circuit power consumption calculation, so that it can meet the normal operation requirements of the chip without occupying too many wiring resources due to excessive margin.

[0094] After completing the above layout planning, enter the layout stage of the next process node.

[0095] In this embodiment, the layout stage is divided into a pre-layout stage and a formal layout stage, wherein the pre-layout stage mainly plans the power network to determine the layout information of the power network and performs the layout of the power network. The power planning information in the pre-layout stage includes a Unified Power Format (UPF) file. The Unified Power Format file is used to specify and simulate low-power design indicators, including voltage domains, power networks, power states, power switches, and reserved register measurements.

[0096] The formal layout stage mainly involves placing each module based on its placement information.

[0097] It should be noted that there is no clear dividing line between the pre-layout stage and the formal layout stage, and between the pre-layout stage and the layout planning stage. They can be divided according to the relevant requirements in the specific implementation scenario. For example, the determination of the layout information of the power network in the pre-layout stage can also be performed in the layout planning stage. The pre-layout stage and the layout planning stage can be regarded as a whole.

[0098] After the layout is completed, the layout after layout is obtained, and the voltage drop test is performed based on the layout after layout. In this embodiment, in order to facilitate distinction, the voltage drop tests performed at different stages and the test results obtained are named with "first", "second", and "third" as prefixes. Therefore, the first voltage drop test is performed based on the layout after layout to obtain the first test result. The power rail analysis (Rail Analysis, RA) tool can be used to perform the voltage drop test.

[0099] Based on the RA tool, the first test result of the layout after layout can be analyzed. From one perspective, the first test result includes static voltage drop and dynamic voltage drop. Among them, static voltage drop refers to the voltage drop of power supply and ground caused by the resistance of power supply and ground when the current in the chip flows through the power line and ground line under steady-state conditions (static state). The main reason for the static voltage drop is the voltage division of the metal connection of the power network, which is caused by the resistance voltage division of the metal connection itself. The static voltage drop is usually related to the static power consumption of the chip, and is also related to the current distribution in the chip and the layout of the power line / ground line. The static voltage drop mainly considers the resistance effect and is used to analyze the influence of resistance.

[0100] Dynamic voltage drop refers to the instantaneous drop in voltage between the power supply and the ground due to the resistance of the power supply and ground wires when a transient event (such as a transient current change) occurs in the chip. Dynamic voltage drop is usually related to transient power consumption in the chip, such as clock switching, large-scale switching transients, timing changes, etc. The reason for dynamic voltage drop is the voltage drop caused by the current fluctuation when the power supply switches the circuit, which occurs at the trigger edge of the clock.

[0101] In addition, from another perspective, the first test result includes the voltage drop value on each module in the chip and the average of the voltage drop values ​​of all modules in the chip as a whole. Specifically, the first voltage drop test is performed based on the layout after layout to obtain the voltage drop value of each module in the layout after layout, and the average of the voltage drop values ​​of multiple modules is calculated based on the voltage drop value of each module, and the first test result is obtained based on the average and the voltage drop value of each module.

[0102] After obtaining the first test result, it is detected whether the first test result meets the first preset requirement, and the first preset requirement can be set according to the relevant requirements in the sign-off.

[0103] Specifically, from one perspective, the static voltage drop and dynamic voltage drop in the first test result are respectively detected to see whether they both meet the requirements for static voltage drop and dynamic voltage drop in the sign-off. If both meet, the subsequent process nodes can be entered. If any one of them does not meet, it is necessary to return to the above-mentioned layout planning stage and pre-layout stage to perform iteration.

[0104] From another perspective, the voltage drop values ​​of each module in the first test result are respectively checked to see whether they meet the voltage drop requirements for a single module in the sign-off, and whether the average of multiple modules meets the voltage drop requirements for the entire module in the sign-off. If both are met, then the subsequent process nodes are entered. If any of them is not met, then it is necessary to return to the above-mentioned layout planning stage and pre-layout stage to perform iterations.

[0105] The number of iterations is at least one, and the specific number of iterations is determined based on the first test result obtained after the iteration. The so-called iteration means returning to the layout planning stage and the pre-layout stage, adjusting the placement information planned in the layout planning stage and the layout information planned in the pre-layout stage, and then executing the layout to obtain the layout after layout.

[0106] Since all modules, including macro cells, standard cells, IO cells, etc., have been reasonably placed in the layout after layout, it is possible to estimate whether there are major voltage drop problems in the layout. Therefore, the first voltage drop test is performed after layout, so that the voltage drop problem in the layout after layout can be discovered in time and then solved.

[0107] After the first test result of the voltage drop test of the layout after layout meets the first preset requirement, the subsequent process nodes are entered to perform clock tree synthesis and routing in sequence. After clock tree synthesis and routing, the voltage drop in the chip is further affected, such as possibly reducing the voltage drop in the chip.

[0108] After the wiring diagram is obtained, a second voltage drop test is performed based on the RA tool to obtain a second test result, and then it is determined whether the second test result meets the second preset requirement. Similarly, the second preset requirement is set based on the relevant requirements for voltage drop in the sign-off.

[0109] In this embodiment, the first preset requirement and the second preset requirement include a preset voltage drop, which can be a voltage drop value or a voltage drop range. The first preset requirement includes a first preset voltage drop, and the second preset requirement includes a second preset voltage drop, and the second preset voltage value is lower than the first preset voltage drop. Among them, the second preset requirement is more stringent than the first preset requirement regarding voltage drop. On the one hand, it is considered that since the first voltage drop test is conducted on the layout after layout, at this time, the chip has not yet been processed by clock tree synthesis, wiring, etc., and the chip actually has some voltage drop problems. Therefore, the first preset voltage drop is set higher, which meets the voltage drop problem of the chip targeted during the first voltage drop test. On the other hand, the first preset voltage drop is set higher, which meets the voltage drop specification requirements during the first voltage drop test. In this way, when iterative repair is performed in the layout planning stage and the pre-layout stage after the first voltage drop test, the iteration can be completed within the set limited iteration time, avoiding the situation where the iteration time is too long and the number of iterations is too large due to the traditional iterative repair of the voltage drop requirement at the final stage of the sign-off.

[0110] In addition, during the second voltage drop test, since the voltage drop test is performed on the wiring diagram after wiring, the chip design has been basically completed at this time, and some voltage drop problems have been solved compared to the layout targeted during the first voltage drop test. Therefore, the second preset voltage drop is set lower, so that the voltage drop in the final chip can be guaranteed to meet the requirements.

[0111] In this embodiment, the voltage drop detection is performed on the layout after layout according to the first preset requirement, and the voltage drop detection is performed on the wiring diagram after wiring according to the second preset requirement, and the first preset requirement and the second preset requirement have different requirements for voltage drop. In other words, different voltage drop requirements are adopted in different detection stages, which can ensure that the problem of excessively long iterative repair time is avoided while meeting the voltage drop problems actually existing in each stage of chip design, and ensure that the voltage drop of the final chip can meet the requirements.

[0112] In this embodiment, the specific information included in the second test result is consistent with the specific information included in the first test result, and the method of judging whether the second test result meets the second preset requirement is consistent with the method of judging whether the first test result meets the first preset requirement, which is not elaborated in this embodiment.

[0113] If the second test result does not meet the second preset requirement, the process returns to the pre-layout stage for iteration. Specifically, the process returns to the pre-layout stage to adjust the layout information of the power network. The number of iterations is one or more until the second test result obtained after the iteration meets the second preset requirement.

[0114] At this point, the wiring diagram can be obtained in which the second test result of the voltage drop test meets the second preset requirement. On this basis, subsequent steps such as the timing verification phase and the iterative repair phase are performed.

[0115] The voltage drop processing method provided in this embodiment performs voltage drop detection after the formal layout stage to promptly solve the existing voltage drop problem, and performs voltage drop detection again after wiring to further solve the existing voltage drop problem. In this way, the existing voltage drop problem is discovered in time, thereby reducing the number of chip iterations and shortening the chip design and development time.

[0116] Compared with the existing technology, it can avoid the situation that the voltage drop test is performed at the final stage of the sign-off, which causes the timing and physical rule checks that have already met the requirements to be violated again due to the need to make major adjustments to the laid-out underlying wiring resources, and to adjust the selection and position of various devices. In addition, since the voltage drop test is performed at the final stage of the sign-off, when adjustments are made based on the test results, the chip has completed layout, wiring, etc. at this time, and the devices and wiring are related to each other. When adjusting wiring resources, devices, etc., other parts of the chip will also be affected. Therefore, from the comprehensive consideration of performance and adjustment workload, in order to avoid excessive adjustment workload and other problems caused by the adjustment, the requirements for voltage drop may be reduced, which may result in the voltage drop of the final chip not being a better value. For example, the dynamic voltage drop reaches 12% and the static voltage drop reaches 4%, which determines that the requirements are met.

[0117] In this embodiment, the voltage drop test is performed on the layout after the layout is completed, and adjustments are made based on the test results. At this time, the chip has not yet been wired. When the devices on the chip are adjusted, the adjustment action has little impact on other parts. Therefore, at this time, how to reduce the voltage drop can be the primary task. Therefore, the voltage drop of the final chip can be at an optimal value. For example, when the dynamic voltage drop reaches 10% and the static voltage drop reaches 3%, it is determined that the requirements are met.

[0118] It can be seen that, compared with the prior art, the solution in this embodiment can reduce the number of chip iterations, shorten the chip design and development time, and the voltage drop of the final chip is lower and has a better voltage drop.

[0119] In this embodiment, the constraint parameters obtained include the timing constraint file, and also include the data flow direction information and the position information of the power pad. In the above layout planning stage, the placement of each module should meet the data flow direction requirements, and the relative position relationship between the module and the power pad will also affect the overall voltage drop of the chip.

[0120] Based on this, in the above layout planning stage, the placement information of each module is determined according to the obtained system parameters and constraint information, which can be achieved in the following ways:

[0121] In the layout planning stage, each module is planned to obtain placement information based on the obtained system parameters, data flow direction information and power contact location information, wherein the module connected to the power contact is planned at a preset adjacent position to the power contact.

[0122] In this embodiment, when planning the placement information of each module, the module connected to each power contact should be placed as close to the power contact as possible, and the module can be placed at a preset adjacent position of the power contact. The preset adjacent position may refer to a position where the distance from the power contact is less than a preset distance.

[0123] In addition, the placement of macro cells and standard cells must meet the requirements of data flow direction, that is, macro cells and standard cells must be placed following the position of the corresponding IO cells. For example, if the output signal of a macro cell is communicated to the outside through a certain IO cell, the macro cell should be placed close to the IO cell to avoid data or signal transmission distance being too long, which may lead to congestion, excessive area, and timing violations in the back-end design.

[0124] In chip design, the design of the power network has a great impact on voltage drop, especially in low-power chip design. In low-power chips, the module includes a power shutdown device, and the resistance of the power shutdown device is very large, which in turn has a great impact on voltage drop. Therefore, low-power chips have relatively higher requirements for voltage drop, and the design of the power network is very important in low-power chips.

[0125] Based on this, in this embodiment, in the above-mentioned pre-layout stage, the layout information of the power supply network is determined according to the acquired power supply planning information, which can be achieved in the following manner:

[0126] In the pre-layout stage, multiple circuit areas in the layout are determined based on the acquired power planning information, where each circuit area corresponds to a different voltage domain. Different power lines are added to each circuit area. The power connection relationship between each power shutdown device and each circuit area is laid out, and the logical connection relationship between different power shutdown devices is laid out.

[0127] In this embodiment, different circuit areas refer to areas corresponding to different voltage domains. Different areas in the chip have different requirements for voltage based on their functions, performance requirements, and power consumption optimization goals. For example, the processor core area usually requires a higher voltage to maintain a faster switching speed and processing power, and the input / output area may require a specific voltage level compatible with external devices. Through multi-voltage domain design, each voltage domain can be provided with a voltage suitable for its specific needs, thereby optimizing overall energy efficiency and performance. During implementation, different voltage domains can be defined and managed based on the obtained unified power format file.

[0128] For circuit areas corresponding to different voltage domains, the power lines required to be laid out are also different. Therefore, different power lines are added to each circuit area. In this process, the power line design is mainly based on the width of the power line, the inter-layer layout and the number of vias.

[0129] Specifically, different voltage domains may carry different currents, so the width of the power line is designed according to the current size of the different voltage domains. For example, a larger current requires a wider power line to reduce resistance and voltage drop.

[0130] When a chip includes multiple metal layers, power lines of different voltage domains may need to be distributed on different metal layers to reduce inter-layer coupling and improve power integrity.

[0131] Vias are required when the power line passes through different metal layers. The number and layout of vias need to be determined based on the current size and the width of the power line.

[0132] In addition to the above layout of power lines, it is also necessary to layout the power connection relationship between the power shutdown device and each circuit area, and layout the logical connection relationship between different power shutdown devices. These power connection relationships and logical connection relationships will directly affect the voltage drop of the chip. In this embodiment, this step can be achieved by:

[0133] Connect the first power pin of each power-off device to the normally-on area in each circuit area, and connect the second power pin of each power-off device to the shut-off area in each circuit area. The first power pin is the power pin that controls the normally-on, and the second power pin is the power pin that connects the power network of the shut-off area. Connect the pins that control whether all power-off devices are shut down in series.

[0134] The power shutdown device generally includes four pins: a first power pin (VDD), a second power pin (VDDG), a first enable pin (IN), and a second enable pin (OUT). The first power pin is connected to the normally open area of ​​each circuit area, and the second power pin is connected to the shutdown area of ​​each circuit area.

[0135] The first enable pin and the second use pin are pins for controlling whether to shut down. In the case of multiple power shut-off devices, the second enable pin of the previous power shut-off device is connected to the first enable pin of the next power shut-off device according to the placement positions of the multiple power shut-off devices, so as to connect the pins for controlling whether to shut down the multiple power shut-off devices in series. The unified control based on the control signal can be realized through this logical connection relationship.

[0136] In addition to the above-mentioned power network planning having a great impact on voltage drop, the type and multiple of power shutdown devices, and the layout spacing between power shutdown devices may also have an impact on voltage drop. Therefore, in the layout planning stage, the type, multiple and layout spacing of power shutdown devices must also be planned.

[0137] After completing the above-mentioned layout information planning of the power supply network, in the formal layout stage, each module is placed according to the placement information of each module to obtain a layout after layout.

[0138] In this embodiment, the placement and routing (PR) tool can be used to achieve local placement. In this process, checks can be performed based on indicators such as transition time, cell density, and congestion. If the chip size is small, the density is too high, or the congestion in the local area or near the hard core is serious, voltage drop problems are very likely to occur. Therefore, it is necessary to reasonably plan the number of modules in the area. If the number is too large, they can be placed in sequence along the border, and the position of the power contacts can be optimized and adjusted accordingly.

[0139] In the traditional voltage drop analysis method, the data needs to be read into the RA tool to analyze the voltage drop after the wiring is completed. In this way, if a voltage drop problem is found, the iterative process needs to be repeated from the layout planning stage to the wiring stage, and the iteration cycle is very long.

[0140] Based on this, in this embodiment, after the layout is completed to obtain the layout after layout, the first voltage drop test is performed to obtain the first test result. If the first test result does not meet the first preset requirement, the layout planning stage and the pre-layout stage are returned to perform at least one iteration. In this way, the voltage drop problem can be discovered in time and the length of the iteration cycle can be shortened. In this embodiment, returning to the layout planning stage and the pre-layout stage to perform at least one iteration can be achieved in the following way:

[0141] Returning to the layout planning stage and the pre-layout stage, at least one iterative adjustment is performed on the layout information and the layout information of the power lines based on the first adjustment strategy.

[0142] The first adjustment strategy includes at least one of the following: adjusting the selection of each module, adjusting the placement of each module, adjusting the width of the power line in the power network, and adjusting the spacing between the power lines.

[0143] If the layout after layout does not meet the voltage drop requirements, you can go back to analyze the placement information and layout information in the layout planning stage and the pre-layout stage. For example, analyze whether the placement of the hard core is unreasonable, resulting in the power supply network not being strong enough and thus the voltage drop not meeting the requirements. For another example, analyze whether the power shutdown device has too small a multiple and the resistance is too large, resulting in a natural voltage drop in the shutdown area. For another example, analyze whether there is a problem with the planning of the power supply network that causes the voltage drop to not meet the requirements. Make corresponding adjustments based on the analysis results obtained.

[0144] In this embodiment, the modules include decoupling capacitors and buffers. When adjusting the selection of each module, the adopted method may include at least one of the following:

[0145] 1. Increase the number of decoupling capacitor devices in the selected module.

[0146] In the chip, the decoupling capacitor device plays the role of a battery. On the basis of meeting the current changes of the driving circuit, increasing the number of deployed decoupling capacitor devices can avoid coupling interference between modules and achieve the effect of reducing dynamic voltage drop.

[0147] 2. Replace the standard cells in the selected module with standard cells of smaller multiples and / or replace the low-threshold devices in the selected module with high-threshold devices.

[0148] Since the smaller the multiple of the standard cell, the lower the power consumption, therefore, if the chip design timing meets the requirements, the standard cell in the chip can be replaced with a standard cell with a smaller multiple. In addition, since the lower the threshold voltage of the standard cell, the faster the speed and the greater the power consumption, and vice versa, the power consumption is lower. Therefore, the low threshold device in the standard cell can be replaced with a high threshold device, thereby reducing power consumption and achieving the effect of reducing voltage drop.

[0149] 3. In the area where the length of the power cord exceeds the preset length, select the buffer to insert into the area.

[0150] Since there is resistance in the power line, if the power line is too long, the resistance is too large, and the chip load is greater. The greater the chip load, the greater the chip dynamic power consumption, and dynamic power consumption is positively correlated with dynamic voltage drop, so the greater the dynamic voltage drop. Therefore, for areas where the power line is too long, a buffer can be inserted to cut off the long power line to achieve the purpose of reducing the load, thereby achieving the effect of reducing the local dynamic voltage drop.

[0151] In addition, in this embodiment, the module further includes a clock device and a power off device. When adjusting the placement position of each module, the method adopted may include at least one of the following:

[0152] 1. For areas where clock devices are concentrated, use manual adjustment or unit filling method to adjust the placement of clock devices so that the spacing between the adjusted clock devices meets the preset spacing requirements.

[0153] Since the flip rate of clock devices is very high, if the clock devices on the chip are clustered, the voltage drop in the local area may be too high. Therefore, it is necessary to avoid the clustering of clock devices in a certain area. If the clock devices are clustered in a certain area, if the number of clustered clock devices is not large, manual adjustment can be used to move some clock devices to other areas. If the number of clustered clock devices is large, the cell padding method can be used to adjust it. The cell padding method can push the clock devices apart at a certain distance, so that the distance between the clock devices meets the preset spacing requirements.

[0154] 2. Reduce the spacing between power-off devices.

[0155] The reduced spacing between power-off devices means that the resistance of the power and ground wires will decrease, and the resistance is proportional to the length of the wire. The reduced resistance can reduce the voltage loss of current passing through, that is, reduce the voltage drop.

[0156] In addition, in this embodiment, the power line includes a power ring line and a power strip line. The power ring line is located at the edge area of ​​the chip. For example, if the chip is a quadrilateral structure, the power ring line is located around the quadrilateral structure. The power strip line is located in the central area surrounded by the edge area of ​​the chip.

[0157] When adjusting the width of the power line, the width of the power loop line can be increased. Since the power contact is connected to the power loop line, and the power loop line is connected to the power line, increasing the width of the power loop line can reduce the resistance on the current path, thereby achieving the effect of reducing the voltage drop.

[0158] In addition, in this embodiment, the purpose of reducing the voltage drop can also be achieved by adjusting the power lines on each metal layer. For example, when the global voltage drop is too high, the width of the power lines in the high-level metal layer can be increased and the spacing between the power lines can be reduced. In addition, some power lines can also be laid out in the low-level metal layer, and the method of using too many holes to lead the power lines from the high-level metal layer to the low-level metal layer can be avoided, because the vias themselves have a large resistance, which will lead to an increase in the voltage drop. Therefore, properly laying out the power lines in the low-level metal layer can reduce the voltage drop to a certain extent.

[0159] In addition, it is also possible to consider increasing the number of power contacts to reduce the voltage drop. If more power contacts are added, the power lines can be laid out more reasonably, thereby achieving the purpose of reducing the voltage drop.

[0160] Generally, the above adjustment process involves multiple iterations. When the first test result obtained after the iteration meets the first preset requirement, the subsequent clock tree synthesis stage and routing stage can be entered.

[0161] Please refer to Figure 2 , is a schematic diagram of the voltage drop problem existing in the chip provided in an embodiment of the present invention, Figure 2 The figure shows the voltage drop problem in the chip after the layout planning stage, pre-layout stage and formal layout stage. The left and right sides and the top area of ​​the chip are hard core modules. Since there is no power connection, the voltage drop is basically 99.99%. In this embodiment, the core area where the standard units are placed in the middle of the chip is mainly studied.

[0162] Depend on Figure 2 It can be seen that there are large areas of severe voltage drop violations in the shutdown area of ​​the middle core area (for example, when the voltage drop is greater than the first set value, it is determined to be a severe voltage drop violation), and small areas of slight voltage drop violations (for example, when the voltage drop is greater than the second set value and less than the first set value, it is determined to be a slight voltage drop violation). Among them, there may be scattered severe voltage drop violations in the area with slight voltage drop violations ( Figure 2 black dots in areas with slight violations of medium voltage drop).

[0163] If we follow the traditional voltage drop handling method, we will deal with the voltage drop problem at the final stage of sign-off, such as Figure 2 In the situation shown in , iterative adjustments are required on a large scale, which incurs large costs in terms of iteration cycle and design time.

[0164] According to the solution provided in this embodiment, after the formal layout stage, it can be found that Figure 2 On this basis, if a serious violation of voltage drop is found, adjustments can be made back to the layout planning stage and pre-layout stage, including adjusting the width and density of the power network in the shutdown area and the normally open area, adjusting the multiples, types, and spacing of the power shutdown devices, etc., and after several rounds of iterations, the following can be achieved. Figure 3 The situation shown in . Figure 3 Another schematic diagram of the problem of voltage drop in a chip provided by an embodiment of the present invention. Figure 3 As shown in Figure 2 The serious violation of voltage drop in a large area has been basically solved and improved to a minor violation of voltage drop. Figure 2The area where the voltage drop slightly violates the requirement is improved to a situation where the voltage drop meets the requirement (for example, the voltage drop is determined to meet the requirement when the voltage drop is less than the second set value).

[0165] In this embodiment, after obtaining the wiring diagram that meets the first preset requirement, the subsequent clock tree synthesis processing and wiring processing are entered. During the clock tree synthesis processing and wiring processing, it can be determined whether congestion, density, area, power supply, design rule violation, design rule constraint and timing indicators are met in the processing of each stage.

[0166] After completing the wiring and obtaining the wiring diagram, a second voltage drop test is performed on the wiring diagram to obtain a second test result. If the second test result does not meet the second preset requirement, the process returns to the pre-layout stage for adjustment. When returning to the pre-layout stage for adjustment, the layout information of the planned power network is mainly adjusted. This process may involve multiple iterations until the second test result obtained after the iteration meets the second preset requirement.

[0167] On the basis of the above, the schematic diagram of the voltage drop problem obtained based on the wiring diagram that meets the second preset requirement is as follows: Figure 4 as shown in . Figure 4 Another schematic diagram of the voltage drop problem in the chip provided by the embodiment of the present invention. Figure 3 The situation shown in the figure shows a slight violation of the voltage drop. At this time, it has been improved to a situation where the voltage drop meets the requirements.

[0168] In this embodiment, after the wiring design is completed, the voltage drop has basically converged, which can greatly improve the work efficiency of digital backend engineers.

[0169] During the routing process, design rule violations may occur in some areas of the chip, so timing repair is required. During the timing repair process, a small number of voltage drop violations may occur. Based on this consideration, please refer to Figure 5 Another flow chart of the voltage drop processing method provided in this embodiment is shown. The voltage drop processing method provided in this embodiment may also include the following steps:

[0170] Step 106: Perform timing analysis on the netlist corresponding to the wiring diagram that meets the second preset requirement based on a timing analysis tool to obtain a timing analysis result.

[0171] Step 107: If the timing analysis result does not meet the preset timing requirement, the netlist corresponding to the wiring diagram is modified based on the acquired repair information until the timing analysis result obtained after the modification meets the preset timing requirement.

[0172] Step 108, performing a third voltage drop test based on the wiring diagram that meets the preset timing requirements to obtain a third test result. If the third test result does not meet the third preset requirement, adjusting the wiring diagram based on the obtained adjustment information until the third test result obtained after adjustment meets the third preset requirement.

[0173] In this embodiment, a timing analysis tool is used to perform timing analysis on the netlist corresponding to the wiring diagram obtained above to detect the timing path in the design and verify whether the setup time and hold time of the signal meet the timing requirements to determine whether such timing problems exist.

[0174] If the above timing problems occur, indicating that the timing analysis results do not meet the preset timing requirements, then repair information is obtained, which can be generated by the timing analysis tool or input by the engineer. Based on the timing analysis tool and according to the repair information, the corresponding netlist of the wiring diagram is modified until the obtained timing analysis results meet the preset timing requirements.

[0175] When the timing meets the requirements, since the timing repair may cause voltage drop problems, the wiring diagram after the timing repair is subjected to a third voltage drop test to obtain a third test result. When the third test result does not meet the third preset requirement, the wiring diagram is adjusted based on the obtained adjustment information.

[0176] After the above two voltage drop tests and iterations, the voltage drop problem has been basically solved, and the timing repair may only cause a few voltage drop problems. Therefore, there is no need to return for iteration at this time. You can make local adjustments based on the adjustment information entered by the engineer.

[0177] In this way, through the above three voltage drop detection and adjustment, there is basically no voltage drop violation in the chip. In order to obtain the final accurate voltage drop of the chip and display it intuitively, please refer to Figure 6 FIG. 2 is another flow chart of the voltage drop processing method provided in the present embodiment. The voltage drop processing method provided in the present embodiment may further include the following steps:

[0178] Step 109: extracting a standard delay information file of the netlist based on the wiring diagram that meets the third preset requirement, and performing logic simulation based on the standard delay information file to obtain signal change information.

[0179] Step 110, calculating and obtaining the final voltage drop of the chip according to the signal change information.

[0180] In this embodiment, the simulation software can be used to perform logic simulation, and the obtained signal change information can be presented in the form of a signal change record (Value Change Dump, VCD) waveform file. Specifically, the system function or command provided by the software is used in the simulation software to specify the generation of the VCD waveform file. Subsequently, the VCD file can be opened and the waveform can be viewed using a waveform viewing tool.

[0181] The VCD waveform file records the signal change information of each node during the simulation process, including logic level change information, signal edge change information, clock signal change information, power and ground signal change information, etc. These signal change information can reflect the dynamic power consumption in the chip, and voltage drop is closely related to power consumption. Therefore, the final voltage drop can be analyzed based on the signal change information and using the power integrity analysis tool.

[0182] In addition, in this embodiment, the corresponding standard delay information (Standard Delay Format, SDF) file and static timing analysis data (Static Timing AnalysisTiming, STA Timing) file can be obtained based on the wiring diagram that meets the third preset requirement, and the SDF file and the STA Timing file are read into the RA tool. The RA tool can obtain the precise voltage drop of the chip based on the SDF file and the STA Timing file.

[0183] In this embodiment, by generating a VCD waveform file, the voltage drop can be obtained accurately and the voltage drop can be displayed intuitively. The final voltage drop of the chip can meet the relevant requirements for voltage drop in the sign-off stage.

[0184] In order to enable those skilled in the art to have a clearer understanding of the overall process of the voltage drop processing method provided in this embodiment, the following is combined with Figure 7 The overall process diagram of the voltage drop processing method shown in the figure introduces the overall process of the voltage drop processing method provided in this embodiment.

[0185] Step 201, in the layout planning stage, the placement information of each module is determined according to the acquired system parameters and constraint parameters.

[0186] Step 202 , in the pre-layout stage, layout information of the power supply network is determined according to the acquired power supply planning information, and the power supply network is laid out according to the layout information.

[0187] Step 203, in the formal layout stage, the modules are placed according to the placement information to obtain a layout after layout.

[0188] Step 204 , performing a first voltage drop test based on the laid-out layout to obtain a first test result.

[0189] Step 205 , detecting whether the first test result meets the first preset requirement, if not, returning to the above step 202 , if satisfied, proceeding to step 206 .

[0190] Step 206 , performing clock tree synthesis and routing based on the layout that meets the first preset requirement to obtain a routing diagram.

[0191] Step 207: Perform a second voltage drop test based on the wiring diagram to obtain a second test result.

[0192] Step 208 , detecting whether the second test result meets the second preset requirement, if not, returning to the above step 202 , if satisfied, proceeding to step 209 .

[0193] Step 209: Perform timing analysis on the netlist corresponding to the wiring diagram that meets the second preset requirement based on a timing analysis tool to obtain a timing analysis result.

[0194] Step 210 , checking whether the timing analysis result meets the preset timing requirement, if not, executing step 211 , if satisfied, proceeding to step 212 .

[0195] Step 211, modifying the netlist corresponding to the wiring diagram based on the acquired repair information, until the timing analysis result obtained after the modification meets the preset timing requirement.

[0196] Step 212: Perform a third voltage drop test based on the wiring diagram that meets the preset timing requirement to obtain a third test result.

[0197] Step 213, detect whether the third test result meets the third preset requirement, if not, execute step 214, if satisfied, enter step 215.

[0198] Step 214, adjusting the wiring diagram based on the acquired adjustment information until a third test result obtained after the adjustment meets a third preset requirement.

[0199] Step 215: extracting a standard delay information file of the netlist based on the wiring diagram that meets the third preset requirement, and performing logic simulation based on the standard delay information file to obtain signal change information.

[0200] Step 216, calculating and obtaining the final voltage drop of the chip according to the signal change information.

[0201] The voltage drop processing method provided in this embodiment continuously detects and iteratively optimizes the voltage drop from the early stage of design during the digital back-end implementation process. By adjusting the placement information in the layout planning, the power network planning information in the pre-layout stage, etc., the purpose of making the voltage drop converge in the design process is achieved.

[0202] By performing voltage drop detection after the formal layout, the voltage drop problem can be estimated in advance. At this time, the layout planning can be iteratively adjusted, which has little impact on the design and a short iteration cycle. The voltage drop problem can be located and solved quickly and accurately.

[0203] After routing, the voltage drop is analyzed again, the voltage drop problem is estimated again, and then the power network planning is adjusted to make the voltage drop meet the requirements. In this way, the number of chip iterations can be reduced and the chip design and development time can be shortened.

[0204] The following describes the devices, equipment, storage media, etc. used to execute the voltage drop processing method provided in this application. The specific implementation process and technical effects are described above and will not be repeated below.

[0205] Figure 8 This is a functional module block diagram of a voltage drop processing device provided in an embodiment of the present application. The functions implemented by the voltage drop processing device correspond to the steps performed by the above method. The device can be understood as the above-mentioned computer device or server, or the processor of the server, or can also be understood as a component independent of the above-mentioned server or processor that implements the functions of the present application under the control of the server, such as Figure 8 As shown, the device may include: a planning module 11, a pre-layout module 12, a formal layout module 13 and an analysis module 14.

[0206] The planning module 11 is used to determine the placement information of each module according to the acquired system parameters and constraint parameters during the layout planning stage;

[0207] A pre-layout module 12 is used to determine the layout information of the power supply network according to the acquired power supply planning information in the pre-layout stage, and to perform the layout of the power supply network according to the layout information;

[0208] The formal layout module 13 is used to place each module according to the layout information in the formal layout stage to obtain a layout after layout;

[0209] The analysis module 14 is used to perform a first voltage drop test based on the layout after layout to obtain a first test result. If the first test result does not meet the first preset requirement, the analysis module 14 returns to the layout planning stage and the pre-layout stage to perform at least one iteration until the first test result obtained after the iteration meets the first preset requirement.

[0210] The analysis module 14 is further used to perform clock tree synthesis and routing based on the layout that meets the first preset requirement to obtain a wiring diagram, and to perform a second voltage drop test based on the wiring diagram to obtain a second test result. If the second test result does not meet the second preset requirement, return to the pre-layout stage to perform at least one iteration until the second test result obtained after the iteration meets the second preset requirement.

[0211] As a possible implementation, the analysis module 14 may also be used to:

[0212] Performing timing analysis on a netlist corresponding to the wiring diagram that meets the second preset requirement based on a timing analysis tool to obtain a timing analysis result;

[0213] If the timing analysis result does not meet the preset timing requirement, the netlist corresponding to the wiring diagram is modified based on the acquired repair information until the timing analysis result obtained after the modification meets the preset timing requirement;

[0214] A third voltage drop test is performed based on a wiring diagram that meets the preset timing requirements to obtain a third test result. If the third test result does not meet the third preset requirement, the wiring diagram is adjusted based on the obtained adjustment information until the third test result obtained after adjustment meets the third preset requirement.

[0215] As a possible implementation, the analysis module 14 may also be used to:

[0216] Extracting a standard delay information file of a netlist based on a wiring diagram that meets a third preset requirement, and performing logic simulation on the standard delay information file to obtain signal change information;

[0217] The final voltage drop of the chip is calculated based on the signal change information.

[0218] As a possible implementation, the constraint parameters include data flow direction information and power point location information. The planning module 11 can be specifically used for:

[0219] In the layout planning stage, each module is planned to obtain placement information based on the obtained system parameters, data flow direction information and power contact location information, wherein the module connected to the power contact is planned at a preset adjacent position to the power contact.

[0220] As a possible implementation, the analysis module 14 may be specifically used for:

[0221] Performing a first voltage drop test based on the layout after layout to obtain the voltage drop value of each module in the layout after layout;

[0222] An average of the voltage drop values ​​of the plurality of modules is calculated according to the voltage drop values ​​of the modules, and a first test result is obtained based on the average and the voltage drop values ​​of the modules.

[0223] As a possible implementation, the module includes a power shutoff device, and the pre-layout module 12 can be specifically used for:

[0224] In the pre-layout stage, multiple circuit areas in the layout are determined according to the acquired power planning information, wherein each circuit area corresponds to a different voltage domain;

[0225] Add different power lines to each circuit area;

[0226] The power connection relationship between each power shutdown device and each circuit area is laid out, and the logical connection relationship between different power shutdown devices is laid out.

[0227] As a possible implementation, the pre-layout module 12 may be specifically used for:

[0228] Connecting the first power pin of each power shutdown device to the normally open area in each circuit area, and connecting the second power pin of each power shutdown device to the shutdown area in each circuit area, wherein the first power pin is a power pin for controlling the normally open, and the second power pin is a power pin connected to the power network of the shutdown area;

[0229] Connect the pins of all power shutdown devices that control whether to shut down in series.

[0230] As a possible implementation, the analysis module 14 may be specifically used for:

[0231] Returning to the layout planning stage and the pre-layout stage, the layout information and the layout information of the power network are iteratively adjusted at least once based on the first adjustment strategy;

[0232] The first adjustment strategy includes at least one of the following: adjusting the selection of each module, adjusting the placement position of each module, adjusting the width of the power line in the power network, and adjusting the spacing between the power lines.

[0233] As a possible implementation, the module includes a decoupling capacitor device and a buffer, and the analysis module 14 can be specifically used for:

[0234] Increase the number of decoupling capacitor devices in the selected module;

[0235] Replacing the standard cells in the selected module with standard cells of smaller multiples and / or replacing the low-threshold devices in the selected module with high-threshold devices;

[0236] In an area where the length of the power line exceeds a predetermined length, a buffer is selected to be inserted into the area.

[0237] As a possible implementation, the module includes a clock device and a power-off device, and the analysis module 14 can be specifically used for:

[0238] For the area where clock devices are concentrated, the placement of the clock devices is adjusted by manual adjustment or unit filling method, so that the spacing between the adjusted clock devices meets the preset spacing requirement;

[0239] Reduce the spacing between power-off devices.

[0240] As a possible implementation, the power line includes a power ring line and a power strip line, the power ring line is located in the edge area of ​​the chip, and the power strip line is located in the central area surrounded by the edge area of ​​the chip. The analysis module 14 can be specifically used for:

[0241] Increase the width of the power loop.

[0242] The above-mentioned device is used to execute the method provided by the aforementioned embodiment, and its implementation principle and technical effect are similar, which will not be repeated here.

[0243] The above modules may be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASIC), or one or more digital signal processors (DSP), or one or more field programmable gate arrays (FPGA). For another example, when a module is implemented in the form of a processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0244] The above modules can be connected or communicated with each other via a wired connection or a wireless connection. The wired connection may include a metal cable, an optical cable, a hybrid cable, etc., or any combination thereof. The wireless connection may include a connection in the form of a LAN, a WAN, Bluetooth, a ZigBee, or NFC, or any combination thereof. Two or more modules may be combined into a single module, and any module may be divided into two or more modules. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application.

[0245] Fig. 9 This is a structural block diagram of an electronic device provided in an embodiment of the present application, and the electronic device may be a computing device with a data processing function. The electronic device includes a processor 21 and a storage medium 22.

[0246] The storage medium 22 is used to store programs, and the processor 21 calls the programs stored in the storage medium 22 to execute the above method embodiment. The specific implementation method and technical effect are similar and will not be repeated here.

[0247] The processor 21 may be a general-purpose processor, such as a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The processor 21 may implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application may be directly embodied as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor 21.

[0248] The storage medium 22 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs and modules. The storage medium 22 may include at least one type of storage medium 22, such as a flash memory, a hard disk, a multimedia card, a card-type storage medium, a random access storage medium (Random Access Memory, RAM), a static random access storage medium (Static Random Access Memory, SRAM), a programmable read-only storage medium (Programmable Read Only Memory, PROM), a read-only storage medium (Read Only Memory, ROM), an electrically erasable programmable read-only storage medium (Electrically Erasable Programmable Read-Only Memory, EEPROM), a magnetic storage medium, a disk, an optical disk, etc. The storage medium 22 is any other medium that can be used to carry or store a desired program code in the form of an instruction or data structure and can be accessed by a computer, but is not limited thereto. The storage medium 22 in the embodiment of the present application can also be a circuit or any other device that can realize a storage function, for storing program instructions and / or data.

[0249] Optionally, the present application also provides a program product, such as a computer-readable storage medium, including a program, which is used to execute the above method embodiment when executed by a processor.

[0250] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of modules is only a logical function division, and there may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0251] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A voltage drop processing method, characterized in that: The method comprises: In the layout planning stage, the placement information of each module is determined according to the obtained system parameters and constraint parameters, wherein the module includes a power-off device, and the type, multiple and placement spacing of the power-off device are planned in the layout planning stage; In the pre-layout stage, layout information of the power supply network is determined according to the acquired power supply planning information, and the layout of the power supply network is performed according to the layout information, wherein the power supply planning information includes a unified power supply format file, and the unified power supply format file is used to specify and simulate low power consumption design indicators; In the formal layout stage, the modules are placed according to the layout information to obtain a layout after layout; Performing a first voltage drop test based on the layout after layout to obtain a first test result, and if the first test result does not meet the first preset requirement, returning to the layout planning stage and the pre-layout stage to perform at least one iteration until the first test result obtained after the iteration meets the first preset requirement; Perform clock tree synthesis and routing based on the layout that meets the first preset requirement to obtain a wiring diagram, perform a second voltage drop test based on the wiring diagram to obtain a second test result, and if the second test result does not meet the second preset requirement, return to the pre-layout stage to perform at least one iteration until the second test result obtained after the iteration meets the second preset requirement; The first preset requirement includes a first preset voltage drop, the second preset requirement includes a second preset voltage drop, and the second preset voltage drop is lower than the first preset voltage drop; The step of determining the layout information of the power supply network according to the acquired power supply planning information in the pre-layout stage includes: In the pre-layout stage, multiple circuit areas in the layout are determined according to the acquired power planning information, wherein each circuit area corresponds to a different voltage domain, and different power lines are added to each circuit area; Connect the first power pin of each power shutdown device to the normally open area in each circuit area, and connect the second power pin of each power shutdown device to the shutdown area in each circuit area, wherein the first power pin is a power pin for controlling the normally open, and the second power pin is a power pin connected to the power network of the shutdown area, and connect the pins of all power shutdown devices that control whether to shut down in series; The step of returning to the floorplanning stage and the pre-layout stage to perform at least one iteration comprises: Returning to the layout planning stage and the pre-layout stage, the placement information and the layout information of the power network are iteratively adjusted at least once based on a first adjustment strategy; wherein the first adjustment strategy includes adjusting the width of the power line in the power network; The power line includes a power loop line and a power strip line, the power loop line is located in the edge area of ​​the chip, and the power strip line is located in the central area surrounded by the edge area of ​​the chip; the step of adjusting the width of the power line includes: increasing the width of the power loop line; The method further comprises: Based on the timing analysis tool, a timing analysis is performed on the netlist corresponding to the wiring diagram that meets the second preset requirement to obtain a timing analysis result; if the timing analysis result does not meet the preset timing requirement, the netlist corresponding to the wiring diagram is modified based on the acquired repair information until the timing analysis result obtained after the modification meets the preset timing requirement; based on the wiring diagram that meets the preset timing requirement, a third voltage drop test is performed to obtain a third test result; if the third test result does not meet the third preset requirement, the wiring diagram is adjusted based on the acquired adjustment information until the third test result obtained after the adjustment meets the third preset requirement.

2. The voltage drop processing method according to claim 1, characterized in that: The method further comprises: Extracting a standard delay information file of a netlist based on a wiring diagram that meets the third preset requirement, and performing logic simulation based on the standard delay information file to obtain signal change information; The final voltage drop of the chip is calculated according to the signal change information.

3. The voltage drop processing method according to claim 1, characterized in that: The constraint parameters include data flow direction information and power point location information; The step of determining the placement information of each module according to the acquired system parameters and constraint parameters in the layout planning stage includes: In the layout planning stage, each module is planned to obtain placement information based on the acquired system parameters, data flow direction information and power point location information, wherein the module connected to the power point is planned at a preset adjacent position to the power point.

4. The voltage drop processing method according to claim 1, characterized in that: The step of performing a first voltage drop test based on the layout after layout to obtain a first test result includes: Performing a first voltage drop test based on the layout after layout to obtain a voltage drop value of each module in the layout after layout; An average of the voltage drop values ​​of the modules is calculated according to the voltage drop values ​​of the modules, and the first test result is obtained based on the average and the voltage drop values ​​of the modules.

5. The voltage drop processing method according to any one of claims 1 to 4, characterized in that: The first adjustment strategy also includes at least one of the following: adjusting the selection of each of the modules, adjusting the placement position of each of the modules, and adjusting the spacing between the power lines.

6. The voltage drop processing method according to claim 5, characterized in that: The module includes a decoupling capacitor device and a buffer; The step of adjusting the selection of each of the modules includes at least one of the following: Increase the number of decoupling capacitor devices in the selected module; Replacing the standard cells in the selected module with standard cells of smaller multiples and / or replacing the low-threshold devices in the selected module with high-threshold devices; In an area where the length of the power line exceeds a predetermined length, a buffer is selected to be inserted into the area.

7. The voltage drop processing method according to claim 5, characterized in that: The module includes a clock device and a power shutdown device; The step of adjusting the placement position of each module includes at least one of the following: For the area where clock devices are concentrated, the placement of the clock devices is adjusted by manual adjustment or unit filling method, so that the spacing between the adjusted clock devices meets the preset spacing requirement; Reduce the spacing between power-off devices.

8. A voltage drop processing device, characterized in that: Used to implement the voltage drop processing method according to any one of claims 1 to 7, the device comprises: A planning module, used to determine the placement information of each module according to the acquired system parameters and constraint parameters in the layout planning stage, wherein the module includes a power-off device, and the type, multiple and placement spacing of the power-off device are planned in the layout planning stage; A pre-layout module, used to determine the layout information of the power supply network according to the acquired power supply planning information in the pre-layout stage, and perform the layout of the power supply network according to the layout information; A formal layout module, used to place the modules according to the placement information in the formal layout stage to obtain a layout after layout; An analysis module, configured to perform a first voltage drop test based on the layout after layout to obtain a first test result, and if the first test result does not meet a first preset requirement, return to the layout planning stage and the pre-layout stage to perform at least one iteration until the first test result obtained after the iteration meets the first preset requirement; The analysis module is further configured to perform clock tree synthesis and routing based on the layout that meets the first preset requirement to obtain a wiring diagram, perform a second voltage drop test based on the wiring diagram to obtain a second test result, and if the second test result does not meet the second preset requirement, return to the pre-layout stage to perform at least one iteration until the second test result obtained after the iteration meets the second preset requirement; The first preset requirement includes a first preset voltage drop, the second preset requirement includes a second preset voltage drop, and the second preset voltage drop is lower than the first preset voltage drop.

9. An electronic device, characterized in that: include: A processor, a storage medium and a bus, wherein the storage medium stores program instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the program instructions to implement the voltage drop processing method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by the processor, the voltage drop processing method according to any one of claims 1 to 7 is implemented.

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