Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for preparing the same. The first semiconductor substrate of two adjacent semiconductor substrates is bonded to the back of the second semiconductor substrate, and the external lead-out terminal is electrically connected to the adjacent second semiconductor substrate. Each first dielectric layer between the two adjacent semiconductor substrates has a plug structure, and the two adjacent semiconductor substrates can be electrically connected through the plug structure. An external power supply can supply power to each semiconductor substrate through the plug structure to form a power transmission path. At least part of the first dielectric layer has a deep trench capacitor structure, and the deep trench capacitor structure is electrically connected to the second end of the plug structure in the corresponding first dielectric layer. The electrical signal passing through the plug structure will first pass through the deep trench capacitor structure before entering the next semiconductor substrate, thereby improving the power supply of the next semiconductor substrate, reducing the voltage drop, and creating conditions for stacking more sheets.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] With the development of integration technology, stacked semiconductor devices (such as 3D integrated circuits) are widely used due to their small size and good performance. In stacked semiconductor devices, logic circuit modules, storage modules, processing modules, etc. are manufactured on different semiconductor substrates, and then multiple semiconductor substrates are stacked and packaged. Two adjacent semiconductor substrates are electrically connected through TSV (Through Silicon Via). Conventional stacked semiconductor devices include 3D DRAM (Dynamic Random Access Memory), etc.

[0003] Since TSV will bring inductive parasitics, the more the number of stacked semiconductor substrates is, the longer the power transmission path is, the more inductive parasitics TSV brings, the greater the impedance in the power transmission path, the more obvious the voltage drop in the power transmission path, the power supply integrity of the semiconductor substrate is difficult to guarantee, and even the last one or several semiconductor substrates may fail to supply power. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to solve the problem that the power supply consistency of the existing stacked semiconductor devices cannot be guaranteed.

[0005] In order to achieve the above-mentioned object, the present invention provides a semiconductor device, comprising an external lead-out terminal and at least two stacked semiconductor substrates, each of the semiconductor substrates having a power supply metal layer, and in two adjacent semiconductor substrates, the first semiconductor substrate is bonded to the back surface of the second semiconductor substrate, and a first dielectric layer is provided between the first semiconductor substrate and the second semiconductor substrate, and the external lead-out terminal is electrically connected to the power supply metal layer of the adjacent second semiconductor substrate;

[0006] The first dielectric layer has a plug structure, the plug structure also extends into the corresponding second semiconductor substrate, and the first end and the second end of the plug structure are electrically connected to the power supply metal layer of the corresponding first and second semiconductor substrates respectively;

[0007] At least a portion of the first dielectric layer has a deep trench capacitor structure, the deep trench capacitor structure also extends into the corresponding second semiconductor substrate, and the deep trench capacitor structure is electrically connected to the second end of the corresponding plug structure.

[0008] Optionally, the power supply metal layer of each of the semiconductor substrates includes a first power supply metal layer and a second power supply metal layer, and each of the plug structures includes a first plug structure and a second plug structure; and,

[0009] The first end and the second end of the first plug structure are electrically connected to the corresponding first power supply metal layer, respectively, and the first end and the second end of the second plug structure are electrically connected to the corresponding second power supply metal layer, respectively.

[0010] Optionally, the deep trench capacitor structure comprises first conductive layers and second conductive layers that are alternately stacked, and a dielectric layer is provided between adjacent first conductive layers and second conductive layers; and,

[0011] The first conductive layer is electrically connected to the second end of the corresponding first plug structure, and the second conductive layer is electrically connected to the second end of the corresponding second plug structure.

[0012] Optionally, each of the first dielectric layers further comprises an interconnect structure, wherein the interconnect structure comprises a first interconnect structure and a second interconnect structure; and,

[0013] The first conductive layer is electrically connected to the second end of the corresponding first plug structure through the first interconnect structure, and the second conductive layer is electrically connected to the second end of the corresponding second plug structure through the second interconnect structure.

[0014] Optionally, the first dielectric layer includes a first mask layer and a first sub-dielectric layer sequentially stacked on the back side of the corresponding second semiconductor substrate;

[0015] The plug structure is located in the first sub-dielectric layer, and extends into the corresponding second semiconductor substrate after penetrating the first mask layer; and,

[0016] The deep trench capacitor structure is located between the first sub-dielectric layer and the first mask layer, and extends into the corresponding second semiconductor substrate after penetrating the first mask layer.

[0017] Optionally, the first dielectric layer includes a second mask layer, a first mask layer and a second sub-dielectric layer stacked in sequence on the back side of the corresponding second semiconductor substrate;

[0018] The plug structure is located in the second mask layer, and extends into the corresponding second semiconductor substrate after penetrating the second mask layer; and,

[0019] The deep trench capacitor structure is located between the second sub-dielectric layer and the first mask layer, and extends into the corresponding second semiconductor substrate after penetrating the first mask layer and the second mask layer.

[0020] Optionally, a hybrid bonding structure is further provided between each of the first dielectric layers and the corresponding first semiconductor substrate, wherein the hybrid bonding structure includes a first bonding dielectric layer, a second bonding dielectric layer, a first bonding metal layer and a second bonding metal layer;

[0021] The first bonding dielectric layer is bonded to the surface of the corresponding first dielectric layer, the second bonding dielectric layer is bonded to the front surface of the corresponding first semiconductor substrate, the first bonding metal layer is located in the first bonding dielectric layer and is electrically connected to the plug structure in the corresponding first dielectric layer, the second bonding metal layer is located in the second bonding dielectric layer and is electrically connected to the power supply metal layer of the corresponding first semiconductor substrate; and,

[0022] At least a portion of the surface of the first bonding metal layer exposes the first bonding medium layer, and at least a portion of the surface of the second bonding metal layer exposes the second bonding medium layer. The surfaces of the first bonding medium layer and the second bonding medium layer are bonded to each other, and the surfaces of the first bonding metal layer and the second bonding metal layer are bonded to each other, so that the first and second semiconductor substrates are bonded together through the hybrid bonding structure.

[0023] Optionally, one of the semiconductor substrates in the semiconductor device is a logic substrate, and the other semiconductor substrates are device substrates, and the logic substrate is located at the outermost side of all the semiconductor substrates.

[0024] The present invention also provides a method for preparing a semiconductor device, comprising:

[0025] Providing at least two semiconductor substrates, each of which has a power supply metal layer;

[0026] All the semiconductor substrates are stacked together to form an external lead-out terminal. Among the two adjacent semiconductor substrates, the first semiconductor substrate is bonded to the back side of the second semiconductor substrate, and a first dielectric layer is provided between the first semiconductor substrate and the second semiconductor substrate. The external lead-out terminal is electrically connected to the power supply metal layer of the adjacent second semiconductor substrate. The first dielectric layer has a plug structure, which also extends into the corresponding second semiconductor substrate. The first end and the second end of the plug structure are electrically connected to the power supply metal layers of the corresponding first and second semiconductor substrates respectively. At least a portion of the first dielectric layer has a deep trench capacitor structure, which also extends into the corresponding second semiconductor substrate. The deep trench capacitor structure is electrically connected to the second end of the corresponding plug structure.

[0027] Optionally, when all the semiconductor substrates are stacked, the first semiconductor substrate is stacked on the second semiconductor substrate in sequence, and when two adjacent semiconductor substrates are stacked, the first dielectric layer, the plug structure, the deep trench capacitor structure and the first hybrid bonding structure are first formed on the back side of the second semiconductor substrate, and the second hybrid bonding structure is formed on the front side of the first semiconductor substrate, and then the first hybrid bonding structure and the second hybrid bonding structure are used to bond the front side of the first semiconductor substrate to the back side of the second semiconductor substrate; and,

[0028] After all the semiconductor substrates are stacked, the external lead-out terminal is formed on the front surface of the second semiconductor substrate at the beginning.

[0029] Optionally, when all the semiconductor substrates are stacked, the second semiconductor substrate is stacked on the first semiconductor substrate in sequence, and before stacking two adjacent semiconductor substrates, the first dielectric layer, the plug structure, the deep trench capacitor structure and the first hybrid bonding structure are first formed on the back side of the second semiconductor substrate, and the second hybrid bonding structure is formed on the front side of the first semiconductor substrate, and then the second semiconductor substrate is bonded to the first semiconductor substrate using the first hybrid bonding structure and the second hybrid bonding structure; and,

[0030] After all the semiconductor substrates are stacked, the external lead-out terminal is formed on the front surface of the second semiconductor substrate at the end.

[0031] Optionally, the step of forming the first dielectric layer, the plug structure and the deep trench capacitor structure on the back side of the semiconductor substrate includes:

[0032] forming a first mask layer on the back side of the semiconductor substrate, and etching a portion of the thickness of the first mask layer and the semiconductor substrate to form at least one deep trench;

[0033] forming the deep trench capacitor structure on the first mask layer, wherein the deep trench capacitor structure covers a portion of the surface of the first mask layer and extends to fill the deep trench;

[0034] forming a first sub-dielectric layer on the first mask layer and the deep trench capacitor structure, and etching a portion of the thickness of the first sub-dielectric layer, the first mask layer and the semiconductor substrate to form a contact hole exposing the power supply metal layer;

[0035] filling the contact hole with a conductive material to form the plug structure; and,

[0036] A second sub-dielectric layer is formed on the first sub-dielectric layer. The first mask layer, the first sub-dielectric layer and the second sub-dielectric layer constitute the first dielectric layer.

[0037] Optionally, the step of forming the first dielectric layer, the plug structure and the deep trench capacitor structure on the back side of the semiconductor substrate includes:

[0038] forming a second mask layer on the back side of the semiconductor substrate, and etching a portion of the thickness of the second mask layer and the semiconductor substrate to form a contact hole exposing the power supply metal layer;

[0039] Filling the contact hole with a conductive material to form the plug structure;

[0040] forming a first mask layer on the second mask layer, and etching the first mask layer, the second mask layer and a portion of the thickness of the semiconductor substrate to form at least one deep trench;

[0041] forming the deep trench capacitor structure on the first mask layer, wherein the deep trench capacitor structure covers a portion of the surface of the first mask layer and extends to fill the deep trench; and,

[0042] A second sub-dielectric layer is formed on the first mask layer and the deep trench capacitor structure. The first mask layer, the second mask layer and the second sub-dielectric layer constitute the first dielectric layer.

[0043] Optionally, when forming the first dielectric layer, an interconnect structure is also formed in the first dielectric layer, wherein the interconnect structure electrically connects the second end of the plug structure and the deep trench capacitor structure.

[0044] Optionally, the step of forming the first hybrid bonding structure on the first dielectric layer includes:

[0045] forming a first bonding dielectric layer on the first dielectric layer;

[0046] forming a first bonding metal layer in the first bonding dielectric layer, wherein the first bonding metal layer is electrically connected to the plug structure through the interconnect structure, and at least a portion of the surface of the first bonding metal layer is exposed from the first bonding dielectric layer;

[0047] The step of forming the second hybrid bonding structure on the front surface of the semiconductor substrate comprises:

[0048] forming a second bonding dielectric layer on the front surface of the semiconductor substrate;

[0049] A second bonding metal layer is formed in the second bonding dielectric layer, the second bonding metal layer is electrically connected to the power supply metal layer of the semiconductor substrate, and at least a portion of the surface of the second bonding metal layer is exposed to the second bonding dielectric layer.

[0050] In the semiconductor device provided by the present invention, it includes an external lead-out terminal and at least two stacked semiconductor substrates, the first semiconductor substrate of the two adjacent semiconductor substrates is bonded to the back of the second semiconductor substrate, the external lead-out terminal is electrically connected to the adjacent second semiconductor substrate, each first dielectric layer between the two adjacent semiconductor substrates has a plug structure, and the two adjacent semiconductor substrates can be electrically connected through the plug structure. After the external lead-out terminal is connected to an external power source, the external power source can supply power to each semiconductor substrate through the plug structure to form a power transmission path. Since at least part of the first dielectric layer has a deep trench capacitor structure, and the deep trench capacitor structure is electrically connected to the second end of the plug structure in the corresponding first dielectric layer, the electrical signal passing through the plug structure will first pass through the deep trench capacitor structure before entering the next semiconductor substrate, and the inductive parasitic generated by the plug structure can be filtered by the deep trench capacitor structure connected to it, thereby improving the power supply of the next semiconductor substrate, reducing the impedance in the power transmission path and thus reducing the voltage drop, creating conditions for stacking more sheets. Accordingly, the present invention also provides a method for preparing a semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 A flowchart of a method for preparing a semiconductor device provided in Embodiment 1 of the present invention;

[0052] Figure 2~Figure 14 The schematic diagram of the structure corresponding to the corresponding steps of the method for preparing a semiconductor device provided in the first embodiment of the present invention, wherein:

[0053] Figure 2 A schematic structural diagram of a semiconductor substrate provided in Embodiment 1 of the present invention;

[0054] Figure 3 A schematic diagram of a structure in which a support substrate is bonded to the front surface of a second semiconductor substrate provided in the first embodiment of the present invention;

[0055] Figure 4 A schematic structural diagram of forming a first mask layer and a deep trench on the back side of a second semiconductor substrate provided in the first embodiment of the present invention;

[0056] Figure 5 A schematic diagram of a structure in which an isolation layer is conformally formed on a first mask layer provided in Embodiment 1 of the present invention;

[0057] Figure 6 A schematic diagram of a structure of a deep trench capacitor structure formed in a deep trench provided in Embodiment 1 of the present invention;

[0058] Figure 7 A schematic structural diagram of forming a first sub-dielectric layer, a first contact hole, and a second contact hole on an isolation layer and a deep trench capacitor structure provided in the first embodiment of the present invention;

[0059] Figure 8 A schematic structural diagram of forming a first plug structure and a second plug structure in a first contact hole and a second contact hole provided in the first embodiment of the present invention;

[0060] Fig. 9 A schematic structural diagram of forming a second sub-dielectric layer on a first sub-dielectric layer provided in Embodiment 1 of the present invention;

[0061] Fig.10 A schematic structural diagram of forming a first hybrid bonding structure on a second sub-dielectric layer provided in Embodiment 1 of the present invention;

[0062] Fig.11 A schematic structural diagram of a first hybrid bonding structure on the front surface of a first semiconductor substrate provided in Embodiment 1 of the present invention;

[0063] Fig.12 A schematic diagram of a structure in which the front surface of a first semiconductor substrate is bonded to the back surface of a second semiconductor substrate provided in Embodiment 1 of the present invention;

[0064] Fig.13 A schematic diagram of a structure in which all semiconductor substrates can be stacked together provided in the first embodiment of the present invention;

[0065] Fig.14 A schematic diagram of the structure of a semiconductor device provided in Embodiment 1 of the present invention;

[0066] Fig.15 An equivalent connection diagram of a semiconductor device provided in Embodiment 1 of the present invention;

[0067] Figure 16~Figure 24 A schematic structural diagram corresponding to some steps of a method for manufacturing a semiconductor device provided in Embodiment 2 of the present invention; wherein:

[0068] Fig.16 A schematic structural diagram of forming a second mask layer, a first contact hole, and a second contact hole on the back side of a second semiconductor substrate provided in the second embodiment of the present invention;

[0069] Fig.17 A schematic structural diagram of forming a first plug structure and a second plug structure in a first contact hole and a second contact hole provided in a second embodiment of the present invention;

[0070] Fig.18 A schematic structural diagram of forming a first mask layer and deep trenches on a second mask layer provided in Embodiment 2 of the present invention;

[0071] Fig.19 A schematic structural diagram of forming an isolation layer on a first mask layer provided in Embodiment 2 of the present invention;

[0072] Fig. 20 A schematic diagram of a structure for forming a deep trench capacitor in a deep trench provided in the second embodiment of the present invention;

[0073] Fig.21 A schematic diagram of a structure in which a second sub-dielectric layer is formed on an isolation layer and a deep trench capacitor structure provided in a second embodiment of the present invention;

[0074] Fig. 22 A schematic structural diagram of forming a first hybrid bonding structure on a second sub-dielectric layer provided in Embodiment 2 of the present invention;

[0075] Fig.23 A schematic diagram of a structure in which the front surface of a first semiconductor substrate is bonded to the back surface of a second semiconductor substrate provided in Embodiment 2 of the present invention;

[0076] Fig.24 A schematic diagram of the structure of a semiconductor device provided in Embodiment 2 of the present invention;

[0077] Figure 25~Figure 28 This is a schematic structural diagram corresponding to some steps of a method for manufacturing a semiconductor device provided in Embodiment 3 of the present invention; wherein:

[0078] Fig.25 A schematic diagram of a structure for bonding the back surface of a second semiconductor substrate to the front surface of a first semiconductor substrate provided in a third embodiment of the present invention;

[0079] Fig.26 A schematic structural diagram of removing the supporting substrate and forming a second hybrid bonding structure on the front surface of the first semiconductor substrate provided in the third embodiment of the present invention;

[0080] Fig. 27 A schematic diagram of a structure for bonding the back surface of a second semiconductor substrate to the front surface of a first semiconductor substrate provided in a third embodiment of the present invention;

[0081] Fig.28 A schematic diagram of the structure of a semiconductor device provided in Embodiment 3 of the present invention;

[0082] Wherein, the accompanying drawings are marked as follows:

[0083] 100-semiconductor substrate; 101a-first power supply metal layer; 101b-second power supply metal layer; 102-deep trench; 200-support substrate; 300-temporary bonding layer; 401-first mask layer; 402-isolation layer; 403-second mask layer; 500-deep trench capacitor structure; 501-first conductive layer; 502-second conductive layer; 503-dielectric layer; 601-first sub-dielectric layer; 601a-first contact hole; 601b-second contact hole; 602-second Two sub-dielectric layers; 701a-first interconnection structure; 701b-second interconnection structure; 702a-first plug structure; 702b-second plug structure; 801a-first sub-bonding metal layer; 801b-second sub-bonding metal layer; 802-first bonding dielectric layer; 803-second bonding dielectric layer; 804a-third sub-bonding metal layer; 804b-fourth sub-bonding metal layer; 805-second dielectric layer; 806a-first external lead-out terminal; 806b-second external lead-out terminal. DETAILED DESCRIPTION

[0084] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0085] Embodiment 1

[0086] Fig.14 Schematic diagram of the structure of the semiconductor device provided in this embodiment. Fig.14 As shown, in this embodiment, the semiconductor device includes at least two stacked semiconductor substrates 100. Fig.14 Schematically showing three semiconductor substrates 100, the other semiconductor substrates 100 are Fig.14 It is replaced by an ellipsis.

[0087] Each of the semiconductor substrates 100 includes a substrate and an insulating layer located on a first surface of the substrate (the substrate and the insulating layer are Fig.14). A device structure is arranged on the first surface of the substrate, and the device structure may be an active device (e.g., a transistor, a diode, a triode, etc.), a passive device (e.g., a capacitor, a resistor, an inductor, etc.), etc., or a combination thereof. A power supply metal layer electrically connected to the device structure is formed in the insulating layer, and the power supply metal layer includes a first power supply metal layer 101a and a second power supply metal layer 101b, and the first power supply metal layer 101a and the second power supply metal layer 101b are electrically connected to the device structure for supplying power to the device structure in the semiconductor substrate 100. The semiconductor device may be a stacked semiconductor device such as a 3D DRAM.

[0088] The material of the substrate may be a semiconductor material, glass, ceramic or other material. When the material of the substrate is a semiconductor material, it may include but is not limited to doped or undoped silicon, doped or undoped germanium, semiconductor on insulator (SOI), silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP, etc. or a combination thereof. The semiconductor substrate 100 may have a wafer-level size or a chip-level size. For example, the semiconductor substrate 100 may be a wafer or a chip, such as an optoelectronic wafer / chip, a biological wafer / chip, a storage wafer / chip, a logic wafer / chip, a computing wafer / chip, etc. Exemplarily, the stacked structure in this embodiment is a combination of a logic chip and a plurality of storage chips.

[0089] The insulating layer may include a single layer or a multilayer film, and its material may include but is not limited to low-k dielectric materials, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, silicon nitride, silicon oxynitride compounds, silicon carbide or carbon-doped silicon dioxide, etc.

[0090] In this embodiment, the side of the semiconductor substrate 100 corresponding to the insulating layer is its front side (i.e., the side where the insulating layer is exposed), and the side corresponding to the substrate is its back side (i.e., the second surface of the substrate). When two adjacent semiconductor substrates 100 are stacked, the first semiconductor substrate 100 is bonded to the back side of the second semiconductor substrate 100, specifically, the front side of the first semiconductor substrate 100 is bonded to the back side of the second semiconductor substrate 100.

[0091] It should be noted that the “first semiconductor substrate 100” and “the second semiconductor substrate 100” herein refer to two adjacent semiconductor substrates 100 , for example, in order from top to bottom. Fig.14The semiconductor substrates 100 in the embodiment are numbered to obtain semiconductor substrate No. 1 100, semiconductor substrate No. 2 100, semiconductor substrate No. 3 100, ... semiconductor substrate No. n 100, semiconductor substrate No. 1 100 is adjacent to semiconductor substrate No. 2 100, semiconductor substrate No. 2 100 is adjacent to semiconductor substrate No. 3 100, .... For semiconductor substrate No. 1 100 and semiconductor substrate No. 2 100, "the first semiconductor substrate 100" is semiconductor substrate No. 2 100, and "the second semiconductor substrate 100" is semiconductor substrate No. 1 100; for semiconductor substrate No. 2 100 and semiconductor substrate No. 3 100, "the first semiconductor substrate 100" is semiconductor substrate No. 3 100, and "the second semiconductor substrate 100" is semiconductor substrate No. 2 100, ....

[0092] It can be understood that after all the semiconductor substrates 100 are stacked, there are two semiconductor substrates 100 on the outermost side, one of which is the first semiconductor substrate 100 (with the back side facing outward), and the other semiconductor substrate 100 is the second semiconductor substrate 100 (with the front side facing outward).

[0093] The semiconductor device further includes a second dielectric layer 805 and an external lead-out terminal located in the second dielectric layer 805. The second dielectric layer 805 is located at the outermost side of the semiconductor device and covers the front side of the adjacent second semiconductor substrate 100 (i.e., the outermost second semiconductor substrate 100). The external lead-out terminal includes a first external lead-out terminal 806a and a second external lead-out terminal 806b, wherein the first external lead-out terminal 806a is electrically connected to the corresponding first power supply metal layer 101a, and the second external lead-out terminal 806b is electrically connected to the corresponding second power supply metal layer 101b.

[0094] Furthermore, there is a first dielectric layer between two adjacent semiconductor substrates 100, and the first dielectric layer is located between the front surface of the first semiconductor substrate 100 and the back surface of the second semiconductor substrate 100. The first dielectric layer may include a single layer or a multilayer film, and its material may include but is not limited to low-k dielectric materials, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, silicon nitride, silicon oxynitride, silicon carbide or carbon-doped silicon dioxide, etc.

[0095] Each of the first dielectric layers has a plug structure, and the plug structure also extends into the corresponding second semiconductor substrate 100, and the first end and the second end of the plug structure are respectively electrically connected to the corresponding first and second power supply metal layers of the semiconductor substrate 100. Specifically, each of the plug structures includes a first plug structure 702a and a second plug structure 702b, and the first end and the second end of the first plug structure 702a are respectively electrically connected to the corresponding first power supply metal layer 101a, and the first end and the second end of the second plug structure 702b are respectively electrically connected to the corresponding second power supply metal layer 101b.

[0096] Further, at least part of the first dielectric layers has a deep trench capacitor structure 500, the deep trench capacitor structure 500 also extends into the corresponding second semiconductor substrate 100, and the deep trench capacitor structure 500 is electrically connected to the second end of the plug structure. In this embodiment, each of the first dielectric layers has the deep trench capacitor structure 500, and in some embodiments, the deep trench capacitor structure 500 may be provided only in part of the first dielectric layers.

[0097] Specifically, the deep trench capacitor structure 500 includes a first conductive layer 501 and a second conductive layer 502 that are alternately stacked, a dielectric layer 503 is provided between the adjacent first conductive layers 501 and second conductive layers 502, and the first conductive layer 501 is closer to the second semiconductor substrate 100 than the second conductive layer 502. The first conductive layer 501 is electrically connected to the second end of the corresponding first plug structure 702a, and the second conductive layer 502 is electrically connected to the second end of the corresponding second plug structure 702b. In this way, the deep trench capacitor structure 500 is equivalent to being connected in parallel to the plug structure.

[0098] In this embodiment, the first conductive layer 501, the second conductive layer 502 and the dielectric layer 503 each have only one layer. In other embodiments, the first conductive layer 501, the second conductive layer 502 and the dielectric layer 503 may have multiple layers.

[0099] Furthermore, each of the first dielectric layers also has an interconnection structure, and the interconnection structure includes a first interconnection structure 701a and a second interconnection structure 701b. The first conductive layer 501 is electrically connected to the second end of the corresponding first plug structure 702a through the first interconnection structure 701a, and the second conductive layer 502 is electrically connected to the second end of the corresponding second plug structure 702b through the second interconnection structure 701b.

[0100] Specifically, the first dielectric layer includes a first mask layer 401, an isolation layer 402, a first sub-dielectric layer 601, and a second sub-dielectric layer 602, and the first mask layer 401, the isolation layer 402, the first sub-dielectric layer 601, and the second sub-dielectric layer 602 are sequentially stacked on the back side of the corresponding second semiconductor substrate 100. The first plug structure 702a and the second plug structure 702b are located in the first sub-dielectric layer 601, and penetrate the isolation layer 402 and the first mask layer 401 to extend into the corresponding second semiconductor substrate 100, and the first plug structure 702a and the second plug structure 702b are also electrically connected to the first power supply metal layer 101a and the second power supply metal layer 101b of the second semiconductor substrate 100, respectively.

[0101] The deep trench capacitor structure 500 is located between the isolation layer 402 and the first sub-dielectric layer 601, penetrates the first mask layer 401 and extends into the second semiconductor substrate 100, and the isolation layer 402 also wraps the portion of the deep trench capacitor structure 500 located in the second semiconductor substrate 100. The first interconnect structure 701a and the second interconnect structure 701b are located in the second sub-dielectric layer 602, the first interconnect structure 701a electrically connects the second end of the first plug structure 702a and the first conductive layer 501, and the second interconnect structure 701b electrically connects the second end of the second plug structure 702b and the second conductive layer 502.

[0102] Optionally, the first interconnect structure 701a and the second interconnect structure 701b may include a plurality of stacked metal layers and conductive plugs connecting adjacent metal layers. The first interconnect structure 701a and the second interconnect structure 701b may include conductive materials such as tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc. or a combination thereof.

[0103] Furthermore, a hybrid bonding structure is provided between each second sub-dielectric layer 602 and the front surface of the corresponding first semiconductor substrate 100. The hybrid bonding structure includes a first bonding dielectric layer 802, a second bonding dielectric layer 803, a first bonding metal layer and a second bonding metal layer, wherein the first bonding dielectric layer 802 is attached to the surface of the corresponding second sub-dielectric layer 602, and the second bonding dielectric layer 803 is attached to the front surface of the corresponding first semiconductor substrate 100.

[0104] The first bonding metal layer is located in the first bonding dielectric layer 802, and includes a first sub-bonding metal layer 801a and a second sub-bonding metal layer 801b. The first sub-bonding metal layer 801a is electrically connected to the corresponding first interconnection structure 701a, thereby being electrically connected to the corresponding first plug structure 702a; the second sub-bonding metal layer 801b is electrically connected to the corresponding second interconnection structure 701b, thereby being electrically connected to the corresponding second plug structure 702b. The second bonding metal layer is located in the second bonding dielectric layer 803, and includes a third sub-bonding metal layer 804a and a fourth sub-bonding metal layer 804b. The third sub-bonding metal layer 804a is electrically connected to the first power supply metal layer 101a of the corresponding first semiconductor substrate 100, and the fourth sub-bonding metal layer 804b is electrically connected to the second power supply metal layer 101b of the corresponding first semiconductor substrate 100.

[0105] At least part of the surface of the first sub-bonding metal layer 801a and the second sub-bonding metal layer 801b exposes the first bonding medium layer 802, and at least part of the surface of the third sub-bonding metal layer 804a and the fourth sub-bonding metal layer 804b exposes the second bonding medium layer 803. The surfaces of the first bonding medium layer 802 and the second bonding medium layer 803 are bonded to each other, the surfaces of the first sub-bonding metal layer 801a and the third sub-bonding metal layer 804a are bonded to each other, and the surfaces of the second sub-bonding metal layer 801b and the fourth sub-bonding metal layer 804b are bonded to each other, so that the first semiconductor substrate 100 and the second semiconductor substrate 100 are bonded together through the hybrid bonding structure.

[0106] Fig.15 FIG. 1 is an equivalent connection diagram of the semiconductor device provided in this embodiment. Fig.15 As shown, the external power supply inputs an electrical signal to the semiconductor device through the external lead-out terminal. At this time, the second semiconductor substrate 100 adjacent to the external lead-out terminal is directly powered by the electrical signal input from the external lead-out terminal. After the electrical signal passes downward through the plug structure, it first passes through the deep trench capacitor structure 500 and then enters the next semiconductor substrate 100. The inductive parasitics generated by the plug structure can be filtered out by the deep trench capacitor structure 500, thereby improving the power supply condition of the next semiconductor substrate 100, reducing the impedance in the power supply transmission path, thereby reducing the voltage drop, and creating conditions for stacking more sheets.

[0107] It should be noted that, in some embodiments, one of the semiconductor substrates 100 in the semiconductor device may be a logic substrate (logic wafer or logic chip), and the other semiconductor substrates 100 may be device substrates (device wafers or device chips), and the logic substrate is located at the outermost side of all the semiconductor substrates 100. In this embodiment, the logic substrate is the semiconductor substrate 100 adjacent to the external lead-out terminal, but it should not be limited to this.

[0108] Based on this, this embodiment also provides a method for preparing a semiconductor device. Figure 1 A flow chart of a method for preparing a semiconductor device provided in this embodiment, such as Figure 1 As shown, the method for preparing the semiconductor device includes:

[0109] Step S1: providing at least two semiconductor substrates, each of which has a power supply metal layer;

[0110] Step S2: stacking all the semiconductor substrates together to form an external lead-out terminal, wherein the first semiconductor substrate is bonded to the back surface of the second semiconductor substrate in two adjacent semiconductor substrates, and a first dielectric layer is provided between the first semiconductor substrate and the second semiconductor substrate, and the external lead-out terminal is electrically connected to the power supply metal layer of the adjacent second semiconductor substrate, each of the first dielectric layers has a plug structure, and the plug structure also extends into the corresponding second semiconductor substrate, and the first end and the second end of the plug structure are electrically connected to the power supply metal layers of the corresponding first and second semiconductor substrates respectively, and at least part of the first dielectric layer has a deep trench capacitor structure, and the deep trench capacitor structure also extends into the corresponding second semiconductor substrate, and the deep trench capacitor structure is electrically connected to the second end of the corresponding plug structure.

[0111] Figure 2~Figure 14 The schematic diagram of the structure corresponding to the corresponding steps of the method for preparing the semiconductor device provided in this embodiment. Next, Figure 2~Figure 14 The method for preparing the semiconductor device provided in this embodiment is described in detail.

[0112] Step S1 is performed to provide at least two semiconductor substrates 100, each of which is as follows: Figure 2 As shown, each of the semiconductor substrates 100 includes a substrate, an insulating layer, and a first power supply metal layer 101a and a second power supply metal layer 101b located in the insulating layer (the substrate and the insulating layer are located in the insulating layer). Figure 2 Each of the semiconductor substrates 10 has a front side and a back side.

[0113] Execute step S2, such as Figure 3 As shown, an operation is performed on the second semiconductor substrate 100, specifically, a supporting substrate 200 is bonded to the front side of the second semiconductor substrate 100, and the supporting substrate 200 may not include a functional structure; or, the supporting substrate 200 may include a functional structure. In some embodiments, the functional structure included in the supporting substrate 200 may be located inside and / or on the surface of the interior and / or edge of the supporting substrate 200.

[0114] In this embodiment, a temporary bonding layer 300 is formed on the support substrate 200, and the second semiconductor substrate 100 can be bonded to the support substrate 200 through the temporary bonding layer 300. The bonding method between the second semiconductor substrate 100 and the support substrate 200 may include melt bonding, thermal compression bonding, low temperature vacuum bonding, anodic bonding, eutectic bonding or hybrid bonding.

[0115] like Figure 4 As shown, the back side of the semiconductor substrate 100 is ground to remove a portion of the thickness of the second semiconductor substrate 100. Next, a first mask layer 401 is formed on the back side of the second semiconductor substrate 100, and the first mask layer 401 completely covers the back side of the second semiconductor substrate 100. Then, the first mask layer 401 and a portion of the depth of the second semiconductor substrate 100 are etched to form at least one deep trench 102 that penetrates the first mask layer 401 and exposes the interior of the second semiconductor substrate 100.

[0116] like Figure 5 As shown, an isolation layer 402 is conformally formed on the first mask layer 401 , and the isolation layer 402 also extends into the deep trench 102 to cover the inner wall of the deep trench 102 .

[0117] like Figure 6 As shown, a first conductive layer 501, a dielectric layer 503 and a second conductive layer 502 are sequentially formed on a portion of the surface of the isolation layer 402, and the first conductive layer 501, the second conductive layer 502 and the dielectric layer 503 also extend into the deep trench 102, and the first conductive layer 501, the second conductive layer 502 and the dielectric layer 503 jointly fill the deep trench 102 and jointly constitute the deep trench capacitor structure 500. In this embodiment, the first conductive layer 501 and the dielectric layer 503 cover a portion of the surface of the isolation layer 402, and the second conductive layer 502 covers a portion of the surface of the dielectric layer 503, and the deep trench capacitor structure 500 is electrically isolated from the second semiconductor substrate 100 by the isolation layer 402.

[0118] like Figure 7 As shown, a first sub-dielectric layer 601 is formed on the isolation layer 402 and the deep trench capacitor structure 500, and the first sub-dielectric layer 601 covers the isolation layer 402 and the deep trench capacitor structure 500. Then, the first sub-dielectric layer 601, the isolation layer 402, the first mask layer 401 and a portion of the thickness of the second semiconductor substrate 100 are etched until the first power supply metal layer 101a and the second power supply metal layer 101b are exposed, forming a first contact hole 601a and a second contact hole 601b. The first contact hole 601a penetrates the first sub-dielectric layer 601, the isolation layer 402 and the first mask layer 401, and extends into the second semiconductor substrate 100, exposing the first power supply metal layer 101a, and the second contact hole 601b penetrates the first sub-dielectric layer 601, the isolation layer 402 and the first mask layer 401, and extends into the second semiconductor substrate 100, exposing the second power supply metal layer 101b.

[0119] like Figure 8 As shown, a conductive material is filled in the first contact hole 601a and the second contact hole 601b to form a first plug structure 702a and a second plug structure 702b. Figure 8 In the embodiment, the ends of the first plug structure 702a and the second plug structure 702b extending into the second semiconductor substrate 100 are first ends, and the ends of the first plug structure 702a and the second plug structure 702b away from the first ends are second ends.

[0120] like Fig. 9 As shown, a second sub-dielectric layer 602 is formed on the first sub-dielectric layer 601. When the second sub-dielectric layer 602 is formed, a first interconnection structure 701a and a second interconnection structure 701b are also formed in the second sub-dielectric layer 602. The first interconnection structure 701a is located above the first plug structure 702a, and is electrically connected to the second end of the first plug structure 702a and the first conductive layer 501. The second interconnection structure 701b is located above the second plug structure 702b, and is electrically connected to the second end of the second plug structure 702b and the second conductive layer 502. The isolation layer 402, the first mask layer 401, the first sub-dielectric layer 601 and the second sub-dielectric layer 602 together constitute the first dielectric layer.

[0121] like Fig.10As shown, a first bonding dielectric layer 802 is formed on the second sub-dielectric layer 602, and the first bonding dielectric layer 802 covers the second sub-dielectric layer 602. Afterwards, a first bonding metal layer is formed in the first bonding dielectric layer 802, and the first bonding metal layer includes a first sub-bonding metal layer 801a and a second sub-bonding metal layer 801b, the first sub-bonding metal layer 801a also extends into the second sub-dielectric layer 602 to be electrically connected to the first interconnect structure 701a, and the second sub-bonding metal layer 801b also extends into the second sub-dielectric layer 602 to be electrically connected to the second interconnect structure 701b. At least part of the surface of the first sub-bonding metal layer 801a and the second sub-bonding metal layer 801b needs to be exposed to the first bonding dielectric layer 802. The first bonding dielectric layer 802 and the first bonding metal layer together constitute a first hybrid bonding structure.

[0122] like Fig.11 As shown, the first semiconductor substrate 100 is operated, specifically, a second bonding dielectric layer 803 is formed on the front surface of the first semiconductor substrate 100, and the second bonding dielectric layer 803 covers the front surface of the first semiconductor substrate 100. Afterwards, a second bonding metal layer is formed in the second bonding dielectric layer 803, and the second bonding metal layer includes a third sub-bonding metal layer 804a and a fourth sub-bonding metal layer 804b, the third sub-bonding metal layer 804a also extends to the first semiconductor substrate 100 and is electrically connected to the first power supply metal layer 101a, and the fourth sub-bonding metal layer 804b also extends to the first semiconductor substrate 100 and is electrically connected to the second power supply metal layer 101b. At least part of the surface of the third sub-bonding metal layer 804a and the fourth sub-bonding metal layer 804b needs to expose the second bonding dielectric layer 803. The second bonding dielectric layer 803 and the second bonding metal layer together constitute a second hybrid bonding structure.

[0123] It should be noted that the step of operating the first semiconductor substrate 100 may also be performed at other times, for example, before operating the second semiconductor substrate 100 , or simultaneously with operating the second semiconductor substrate 100 .

[0124] See also Fig.12, attach the first hybrid bonding structure and the second hybrid bonding structure together, so that the first bonding medium layer 802 is tightly attached to the surface of the second bonding medium layer 803, the first sub-bonding metal layer 801a is tightly attached to the surface of the third sub-bonding metal layer 804a, and the second sub-bonding metal layer 801b is tightly attached to the surface of the fourth sub-bonding metal layer 804b, and the front side of the first semiconductor substrate 100 is bonded to the back side of the second semiconductor substrate 100 through the bonding force between the medium and the medium and between the metal and the metal.

[0125] Through the above steps, the stacking of the two semiconductor substrates can be completed.

[0126] Next, if Fig.13 As shown, Fig.12 The first semiconductor substrate 100 in the stack is used as the second semiconductor substrate 100, and another semiconductor substrate 100 is taken as the first semiconductor substrate 100, and the above steps are repeated to complete the stacking of the next semiconductor substrate 100. By sequentially stacking the first semiconductor substrate 100 on the second semiconductor substrate 100, when stacking two adjacent semiconductor substrates 100, the first dielectric layer, the plug structure, the deep trench capacitor structure 500 and the first hybrid bonding structure are first formed on the back side of the second semiconductor substrate 100, and the second hybrid bonding structure is formed on the front side of the first semiconductor substrate 100, and then the first hybrid bonding structure and the second hybrid bonding structure are used to bond the front side of the first semiconductor substrate 100 to the back side of the second semiconductor substrate 100, so that all the semiconductor substrates 100 can be stacked together.

[0127] like Fig.14 As shown, after all the semiconductor substrates 100 are stacked, the support substrate 200 can be debonded, so as to remove the support substrate 200 and the temporary bonding layer 300. Afterwards, a second dielectric layer 805 is formed on the front surface of the first second semiconductor substrate 100, and a first external lead-out terminal 806a and a second external lead-out terminal 806b are formed in the second dielectric layer 805. The first external lead-out terminal 806a and the second external lead-out terminal 806b also extend into the first second semiconductor substrate 100, and are electrically connected to the first power supply metal layer 101a and the second power supply metal layer 101b of the second semiconductor substrate 100, respectively. The first external lead-out terminal 806a and the second external lead-out terminal 806b together constitute the external lead-out terminal.

[0128] Embodiment 2

[0129] Fig.24Schematic diagram of the structure of the semiconductor device provided in this embodiment. Fig.24 As shown, the difference from the first embodiment is that, in this embodiment, the first dielectric layer includes a second mask layer 403, a first mask layer 401, an isolation layer 402 and a second sub-dielectric layer 602, and the second mask layer 403, the first mask layer 401, the isolation layer 402 and the second sub-dielectric layer 602 are sequentially stacked on the back side of the second semiconductor substrate 100. The first plug structure 702a and the second plug structure 702b are located in the second mask layer 403, and penetrate the second mask layer 403 to extend into the second semiconductor substrate 100, and the first plug structure 702a and the second plug structure 702b are electrically connected to the first power supply metal layer 101a and the second power supply metal layer 101b of the second semiconductor substrate 100, respectively. The deep trench capacitor structure 500 is located between the isolation layer 402 and the second sub-dielectric layer 602 , penetrates the first mask layer 401 and the second mask layer 403 and extends into the second semiconductor substrate 100 , and the isolation layer 402 also wraps the portion of the deep trench capacitor structure 500 located in the second semiconductor substrate 100 .

[0130] It can be understood that, compared with Example 1, the heights of the first plug structure 702a and the second plug structure 702b in this embodiment are smaller, which is convenient for preparation, and the height of the deep trench capacitor structure 500 is larger (the thickness of the second mask layer 403 is increased), which can increase the area of ​​the deep trench capacitor structure 500, thereby increasing the capacitance density of the deep trench capacitor structure 500.

[0131] Figure 16~Figure 24 The following is a schematic diagram of the structure corresponding to the corresponding steps of the method for preparing a semiconductor device provided in this embodiment. Figure 16~Figure 24 The method for manufacturing the semiconductor device provided in this embodiment is described in detail.

[0132] In the first embodiment, the support substrate 200 is bonded to the front surface of the second semiconductor substrate 100. Fig.16As shown, the back side of the second semiconductor substrate 100 is ground to remove part of the thickness of the second semiconductor substrate 100. Next, a second mask layer 403 is formed on the back side of the second semiconductor substrate 100, and the second mask layer 403 completely covers the back side of the second semiconductor substrate 100. Then, the second mask layer 403 and part of the depth of the second semiconductor substrate 100 are etched until the first power supply metal layer 101a and the second power supply metal layer 101b are exposed, forming a first contact hole 601a and a second contact hole 601b. The first contact hole 601a penetrates the second mask layer 403 and extends into the second semiconductor substrate 100, exposing the first power supply metal layer 101a, and the second contact hole 601b penetrates the second mask layer 403 and extends into the second semiconductor substrate 100, exposing the second power supply metal layer 101b.

[0133] like Fig.17 As shown, a conductive material is filled in the first contact hole 601a and the second contact hole 601b to form a first plug structure 702a and a second plug structure 702b. Fig.17 In the embodiment, the ends of the first plug structure 702a and the second plug structure 702b extending into the second semiconductor substrate 100 are first ends, and the ends of the first plug structure 702a and the second plug structure 702b away from the first ends are second ends.

[0134] like Fig.18 As shown, a first mask layer 401 is formed on the second mask layer 403, and the first mask layer 401 completely covers the second mask layer 403. Then, the first mask layer 401, the second mask layer 403, and a portion of the depth of the second semiconductor substrate 100 are etched to form at least one deep trench 102 that penetrates the first mask layer 401, the second mask layer 403, and exposes the interior of the second semiconductor substrate 100.

[0135] like Fig.19 As shown, an isolation layer 402 is conformally formed on the first mask layer 401 , and the isolation layer 402 also extends into the deep trench 102 to cover the inner wall of the deep trench 102 .

[0136] like Fig. 20As shown, a first conductive layer 501, a dielectric layer 503 and a second conductive layer 502 are sequentially formed on a portion of the surface of the isolation layer 402, and the first conductive layer 501, the second conductive layer 502 and the dielectric layer 503 also extend into the deep trench 102, and the first conductive layer 501, the second conductive layer 502 and the dielectric layer 503 jointly fill the deep trench 102 and jointly constitute a deep trench capacitor structure 500. In this embodiment, the first conductive layer 501 and the dielectric layer 503 cover a portion of the surface of the isolation layer 402, and the second conductive layer 502 covers a portion of the surface of the dielectric layer 503, and the deep trench capacitor structure 500 is electrically isolated from the second semiconductor substrate 100 by the isolation layer 402.

[0137] like Fig.21 As shown, a second sub-dielectric layer 602 is formed on the isolation layer 402 and the deep trench capacitor structure 500, and the second sub-dielectric layer 602 covers the isolation layer 402 and the deep trench capacitor structure 500. When the second sub-dielectric layer 602 is formed, a first interconnection structure 701a and a second interconnection structure 701b are also formed in the second sub-dielectric layer 602. The first interconnection structure 701a is located above the first plug structure 702a, and is electrically connected to the second end of the first plug structure 702a and the first conductive layer 501 of the deep trench capacitor structure 500; the second interconnection structure 701b is located above the second plug structure 702b, and is electrically connected to the second end of the second plug structure 702b and the second conductive layer 502 of the deep trench capacitor structure 500.

[0138] like Fig. 22 As shown, a first bonding dielectric layer 802 is formed on the second sub-dielectric layer 602, and the first bonding dielectric layer 802 covers the second sub-dielectric layer 602. Afterwards, a first bonding metal layer is formed in the first bonding dielectric layer 802, and the first bonding metal layer includes a first sub-bonding metal layer 801a and a second sub-bonding metal layer 801b, the first sub-bonding metal layer 801a also extends into the second sub-dielectric layer 602 to be electrically connected to the first interconnect structure 701a, and the second sub-bonding metal layer 801b also extends into the second sub-dielectric layer 602 to be electrically connected to the second interconnect structure 701b. At least part of the surface of the first sub-bonding metal layer 801a and the second sub-bonding metal layer 801b needs to be exposed to the first bonding dielectric layer 802. The first bonding dielectric layer 802 and the first bonding metal layer together constitute a first hybrid bonding structure.

[0139] Afterwards, with Fig.11The first semiconductor substrate 100 is operated similarly to the steps of FIG. 1 to form the second bonding dielectric layer 803 on the front surface of the first semiconductor substrate 100 .

[0140] like Fig.23 As shown, the front side of the first semiconductor substrate 100 is bonded to the back side of the second semiconductor substrate 100 .

[0141] Through the above steps, the stacking of the two semiconductor substrates 100 can be completed.

[0142] Next, if Fig.24 As shown, Fig.23 The first semiconductor substrate 100 in the stack is used as the second semiconductor substrate 100, and another semiconductor substrate 100 is taken as the first semiconductor substrate 100, and the above steps are repeated to complete the stacking of the next semiconductor substrate 100. By sequentially stacking the first semiconductor substrate 100 on the second semiconductor substrate 100, when stacking two adjacent semiconductor substrates 100, the first dielectric layer, the plug structure, the deep trench capacitor structure 500 and the first hybrid bonding structure are first formed on the back side of the second semiconductor substrate 100, and the second hybrid bonding structure is formed on the front side of the first semiconductor substrate 100, and then the first hybrid bonding structure and the second hybrid bonding structure are used to bond the front side of the first semiconductor substrate 100 to the back side of the second semiconductor substrate 100, so that all the semiconductor substrates 100 can be stacked together.

[0143] After all the semiconductor substrates 100 are stacked, the support substrate 200 can be debonded to remove the support substrate 200 and the temporary bonding layer 300. Afterwards, a second dielectric layer 805 is formed on the front surface of the first second semiconductor substrate 100, and a first external lead-out terminal 806a and a second external lead-out terminal 806b are formed in the second dielectric layer 805. The first external lead-out terminal 806a and the second external lead-out terminal 806b also extend into the first second semiconductor substrate 100, and are electrically connected to the first power supply metal layer 101a and the second power supply metal layer 101b of the second semiconductor substrate 100, respectively. The first external lead-out terminal 806a and the second external lead-out terminal 806b together constitute the external lead-out terminal.

[0144] Embodiment 3

[0145] Figure 25~Figure 28 This is a flow chart corresponding to the corresponding steps of the method for preparing a semiconductor device provided in this embodiment. Figure 25~Figure 28As shown, the difference from the first embodiment is that in this embodiment, when all the semiconductor substrates 10 are stacked, the second semiconductor substrate is stacked on the first semiconductor substrate in sequence.

[0146] Specifically, first refer to Figure 2~Figure 10 The first dielectric layer, the plug structure, the deep trench capacitor structure 500 and the first hybrid bonding structure are formed on the back side of the second semiconductor substrate 100 in the step of. Fig.11 The second hybrid bonding structure is formed on the front surface of the first semiconductor substrate 100 in the step of.

[0147] The specific steps of forming the first dielectric layer, the plug structure, the deep trench capacitor structure 500 , the first hybrid bonding structure and the second hybrid bonding structure have been described in detail in the first embodiment and will not be repeated here.

[0148] like Fig.25 As shown, the back side of the second semiconductor substrate 100 is bonded to the front side of the first semiconductor substrate 100 by using the first hybrid bonding structure on the back side of the second semiconductor substrate 100 and the second hybrid bonding structure on the front side of the first semiconductor substrate 100 .

[0149] Through the above steps, the stacking of the two semiconductor substrates 100 can be completed.

[0150] like Fig.26 As shown, the support substrate 200 is debonded, thereby removing the support substrate 200 and the temporary bonding layer 300. Fig.26 The second semiconductor substrate 100 in the embodiment is used as the first semiconductor substrate 100, and the first semiconductor substrate 100 (that is, Fig.26 The second hybrid bonding structure is formed on the front side of the second semiconductor substrate 100.

[0151] Take another semiconductor substrate 100 as the second semiconductor substrate 100. Repeat the above steps, referring to Figure 2~Figure 10 The first dielectric layer, the plug structure, the deep trench capacitor structure 500 and the first hybrid bonding structure are formed on the back side of the second semiconductor substrate 100 in the step of. Fig. 27 As shown, the back side of the second semiconductor substrate 100 is bonded to the front side of the first semiconductor substrate 100 by using the first hybrid bonding structure on the back side of the second semiconductor substrate 100 and the second hybrid bonding structure on the front side of the first semiconductor substrate 100. The stacking of the next semiconductor substrate 100 is completed.

[0152] like Fig.28 As shown, by stacking the second semiconductor substrate 100 on the first semiconductor substrate 100 in sequence, when stacking two adjacent semiconductor substrates 100, the first dielectric layer, the plug structure, the deep trench capacitor structure 500 and the first hybrid bonding structure are first formed on the back side of the second semiconductor substrate 100, and the second hybrid bonding structure is formed on the front side of the first semiconductor substrate 100, and then the first hybrid bonding structure and the second hybrid bonding structure are used to bond the back side of the second semiconductor substrate 100 to the front side of the first semiconductor substrate 100, so that all the semiconductor substrates 100 can be stacked together.

[0153] After all the semiconductor substrates 100 are stacked, a second dielectric layer 805 may be formed on the front surface of the second semiconductor substrate 100 at the end, and a first external lead-out terminal 806a and a second external lead-out terminal 806b may be formed in the second dielectric layer 805. The first external lead-out terminal 806a and the second external lead-out terminal 806b further extend into the second semiconductor substrate 100 at the end, and are respectively electrically connected to the first power supply metal layer 101a and the second power supply metal layer 101b of the second semiconductor substrate 100. The first external lead-out terminal 806a and the second external lead-out terminal 806b together constitute the external lead-out terminal.

[0154] In summary, in the semiconductor device provided in the embodiment of the present invention, it includes an external lead-out terminal and at least two stacked semiconductor substrates, the first semiconductor substrate of the two adjacent semiconductor substrates is bonded to the back of the second semiconductor substrate, the external lead-out terminal is electrically connected to the adjacent second semiconductor substrate, each first dielectric layer between the two adjacent semiconductor substrates has a plug structure, and the two adjacent semiconductor substrates can be electrically connected through the plug structure. After the external lead-out terminal is connected to an external power source, the external power source can supply power to each semiconductor substrate through the plug structure to form a power transmission path. Since at least part of the first dielectric layer has a deep trench capacitor structure, and the deep trench capacitor structure is electrically connected to the second end of the plug structure in the corresponding first dielectric layer, the electrical signal passing through the plug structure will first pass through the deep trench capacitor structure before entering the next semiconductor substrate, and the inductive parasitic generated by the plug structure can be filtered by the deep trench capacitor structure connected to it, thereby improving the power supply of the next semiconductor substrate, reducing the impedance in the power transmission path, thereby reducing the voltage drop, and creating conditions for stacking more sheets. Accordingly, the embodiment of the present invention also provides a method for preparing a semiconductor device.

[0155] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0156] It should also be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0157] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0158] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates otherwise. In addition, the implementation of the method and / or device in the embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims

1. A semiconductor device, characterized in that: It comprises an external lead-out terminal and at least two stacked semiconductor substrates, each of which has a power supply metal layer, and in two adjacent semiconductor substrates, the first semiconductor substrate is bonded to the back surface of the second semiconductor substrate, and a first dielectric layer is provided between the first semiconductor substrate and the second semiconductor substrate, and the external lead-out terminal is electrically connected to the power supply metal layer of the adjacent second semiconductor substrate; The first dielectric layer has a plug structure, the plug structure also extends into the corresponding second semiconductor substrate, and the first end and the second end of the plug structure are electrically connected to the power supply metal layer of the corresponding first and second semiconductor substrates respectively; At least a portion of the first dielectric layer has a deep trench capacitor structure, the deep trench capacitor structure also extends into the corresponding second semiconductor substrate, and the deep trench capacitor structure is electrically connected to the second end of the corresponding plug structure.

2. The semiconductor device according to claim 1, wherein The power supply metal layer of each semiconductor substrate includes a first power supply metal layer and a second power supply metal layer, and each plug structure includes a first plug structure and a second plug structure; as well as, The first end and the second end of the first plug structure are electrically connected to the corresponding first power supply metal layer, and the first end and the second end of the second plug structure are electrically connected to the corresponding second power supply metal layer.

3. The semiconductor device according to claim 2, wherein: The deep trench capacitor structure comprises a first conductive layer and a second conductive layer alternately stacked, with a dielectric layer between adjacent first conductive layers and second conductive layers; and The first conductive layer is electrically connected to the second end of the corresponding first plug structure, and the second conductive layer is electrically connected to the second end of the corresponding second plug structure.

4. The semiconductor device according to claim 3, characterized in that Each of the first dielectric layers also has an interconnect structure, wherein the interconnect structure includes a first interconnect structure and a second interconnect structure; and, The first conductive layer is electrically connected to the second end of the corresponding first plug structure through the first interconnect structure, and the second conductive layer is electrically connected to the second end of the corresponding second plug structure through the second interconnect structure.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that The first dielectric layer comprises a first mask layer and a first sub-dielectric layer sequentially stacked on the back side of the corresponding second semiconductor substrate; The plug structure is located in the first sub-dielectric layer, and extends into the corresponding second semiconductor substrate after penetrating the first mask layer; and, The deep trench capacitor structure is located between the first sub-dielectric layer and the first mask layer, and extends into the corresponding second semiconductor substrate after penetrating the first mask layer.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that The first dielectric layer includes a second mask layer, a first mask layer and a second sub-dielectric layer which are sequentially stacked on the back side of the corresponding second semiconductor substrate; The plug structure is located in the second mask layer, and extends into the corresponding second semiconductor substrate after penetrating the second mask layer; and, The deep trench capacitor structure is located between the second sub-dielectric layer and the first mask layer, and extends into the corresponding second semiconductor substrate after penetrating the first mask layer and the second mask layer.

7. The semiconductor device according to any one of claims 1 to 4, characterized in that A hybrid bonding structure is also provided between each of the first dielectric layers and the corresponding first semiconductor substrate, wherein the hybrid bonding structure includes a first bonding dielectric layer, a second bonding dielectric layer, a first bonding metal layer and a second bonding metal layer; The first bonding dielectric layer is bonded to the surface of the corresponding first dielectric layer, the second bonding dielectric layer is bonded to the front surface of the corresponding first semiconductor substrate, the first bonding metal layer is located in the first bonding dielectric layer and is electrically connected to the plug structure in the corresponding first dielectric layer, and the second bonding metal layer is located in the second bonding dielectric layer and is electrically connected to the power supply metal layer of the corresponding first semiconductor substrate; as well as, At least a portion of the surface of the first bonding metal layer exposes the first bonding medium layer, and at least a portion of the surface of the second bonding metal layer exposes the second bonding medium layer. The surfaces of the first bonding medium layer and the second bonding medium layer are bonded to each other, and the surfaces of the first bonding metal layer and the second bonding metal layer are bonded to each other, so that the first and second semiconductor substrates are bonded together through the hybrid bonding structure.

8. The semiconductor device according to claim 1, wherein One of the semiconductor substrates in the semiconductor device is a logic substrate, the other semiconductor substrates are device substrates, and the logic substrate is located at the outermost side of all the semiconductor substrates.

9. A method for preparing a semiconductor device, characterized in that: include: Providing at least two semiconductor substrates, each of which has a power supply metal layer; All the semiconductor substrates are stacked together to form an external lead-out terminal. Among the two adjacent semiconductor substrates, the first semiconductor substrate is bonded to the back side of the second semiconductor substrate, and a first dielectric layer is provided between the first semiconductor substrate and the second semiconductor substrate. The external lead-out terminal is electrically connected to the power supply metal layer of the adjacent second semiconductor substrate. The first dielectric layer has a plug structure, which also extends into the corresponding second semiconductor substrate. The first end and the second end of the plug structure are electrically connected to the power supply metal layers of the corresponding first and second semiconductor substrates respectively. At least a portion of the first dielectric layer has a deep trench capacitor structure, which also extends into the corresponding second semiconductor substrate. The deep trench capacitor structure is electrically connected to the second end of the corresponding plug structure.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: When stacking all the semiconductor substrates, the first semiconductor substrate is stacked on the second semiconductor substrate in sequence. When stacking two adjacent semiconductor substrates, the first dielectric layer, the plug structure, the deep trench capacitor structure and the first hybrid bonding structure are first formed on the back side of the second semiconductor substrate, and the second hybrid bonding structure is formed on the front side of the first semiconductor substrate. The first hybrid bonding structure and the second hybrid bonding structure are then used to bond the front side of the first semiconductor substrate to the back side of the second semiconductor substrate. as well as, After all the semiconductor substrates are stacked, the external lead-out terminal is formed on the front surface of the second semiconductor substrate at the beginning.

11. The method for preparing a semiconductor device according to claim 9, wherein: When stacking all the semiconductor substrates, the second semiconductor substrate is stacked on the first semiconductor substrate in sequence, and before stacking two adjacent semiconductor substrates, the first dielectric layer, the plug structure, the deep trench capacitor structure and the first hybrid bonding structure are first formed on the back side of the second semiconductor substrate, and the second hybrid bonding structure is formed on the front side of the first semiconductor substrate, and then the second semiconductor substrate is bonded to the first semiconductor substrate using the first hybrid bonding structure and the second hybrid bonding structure; as well as, After all the semiconductor substrates are stacked, the external lead-out terminal is formed on the front surface of the second semiconductor substrate at the end.

12. The method for preparing a semiconductor device according to claim 10 or 11, characterized in that: The steps of forming the first dielectric layer, the plug structure and the deep trench capacitor structure on the back side of the semiconductor substrate include: forming a first mask layer on the back side of the semiconductor substrate, and etching a portion of the thickness of the first mask layer and the semiconductor substrate to form at least one deep trench; forming the deep trench capacitor structure on the first mask layer, wherein the deep trench capacitor structure covers a portion of the surface of the first mask layer and extends to fill the deep trench; forming a first sub-dielectric layer on the first mask layer and the deep trench capacitor structure, and etching a portion of the thickness of the first sub-dielectric layer, the first mask layer and the semiconductor substrate to form a contact hole exposing the power supply metal layer; filling the contact hole with a conductive material to form the plug structure; and, A second sub-dielectric layer is formed on the first sub-dielectric layer. The first mask layer, the first sub-dielectric layer and the second sub-dielectric layer constitute the first dielectric layer.

13. The method for preparing a semiconductor device according to claim 10 or 11, characterized in that: The steps of forming the first dielectric layer, the plug structure and the deep trench capacitor structure on the back side of the semiconductor substrate include: forming a second mask layer on the back side of the semiconductor substrate, and etching a portion of the thickness of the second mask layer and the semiconductor substrate to form a contact hole exposing the power supply metal layer; Filling the contact hole with a conductive material to form the plug structure; forming a first mask layer on the second mask layer, and etching a portion of the thickness of the first mask layer, the second mask layer, and the semiconductor substrate to form at least one deep trench; forming the deep trench capacitor structure on the first mask layer, wherein the deep trench capacitor structure covers a portion of the surface of the first mask layer and extends to fill the deep trench; and, A second sub-dielectric layer is formed on the first mask layer and the deep trench capacitor structure. The first mask layer, the second mask layer and the second sub-dielectric layer constitute the first dielectric layer.

14. The method for preparing a semiconductor device according to claim 10 or 11, characterized in that: When forming the first dielectric layer, an interconnection structure is also formed in the first dielectric layer, wherein the interconnection structure electrically connects the second end of the plug structure and the deep trench capacitor structure.

15. The method for preparing a semiconductor device according to claim 14, characterized in that: The step of forming the first hybrid bonding structure on the first dielectric layer includes: forming a first bonding dielectric layer on the first dielectric layer; forming a first bonding metal layer in the first bonding dielectric layer, wherein the first bonding metal layer is electrically connected to the plug structure through the interconnect structure, and at least a portion of the surface of the first bonding metal layer is exposed from the first bonding dielectric layer; The step of forming the second hybrid bonding structure on the front surface of the semiconductor substrate comprises: forming a second bonding dielectric layer on the front surface of the semiconductor substrate; A second bonding metal layer is formed in the second bonding dielectric layer, the second bonding metal layer is electrically connected to the power supply metal layer of the semiconductor substrate, and at least a portion of the surface of the second bonding metal layer is exposed to the second bonding dielectric layer.

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