Data transmission method, device, equipment and storage medium

Abstract

The present application discloses a data transmission method, device, equipment and storage medium, which belongs to the field of communication technology. The method is executed by a first processor, the first processor and the second processor belong to the same server, the first processor and the second processor are connected through a bus in the server, and the first processor and the second processor are connected to a switch through a communication cable. The method includes: based on the bus connection in the server, the first processor sends operation data to the second processor; in the case of failure in transmission of operation data, based on the communication cable and the switch, the first processor sends operation data to the second processor. By retransmitting the operation data based on the communication cable connecting the switch and the first processor and the second processor when the operation data fails to be transmitted based on the bus connection, the problem of being unable to perform data transmission between processors in the server due to the failure of bus connection transmission is avoided, and the risk of processor calculation interruption is avoided.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a data transmission method, device, equipment and storage medium. Background Art

[0002] With the development of Internet technology, the amount of data that needs to be calculated is increasing, and there is a need to use multiple processors to collaboratively calculate data.

[0003] In the related art, taking a graphics processing unit (GPU) as an example, GPUs belonging to the same server transmit data through a high-speed interconnection communication channel to achieve information transfer between GPUs, thereby achieving collaborative computing of data.

[0004] However, in the event of a failure in the high-speed interconnect communication channel, GPUs will be unable to communicate with each other, creating the risk of computing interruption. Summary of the invention

[0005] The present application provides a data transmission method, apparatus, device and storage medium, and the technical solution is as follows:

[0006] According to one aspect of the present application, a data transmission method is provided, the method being executed by a first processor, the first processor and the second processor belonging to the same server, the first processor and the second processor being connected via a bus in the server, the first processor and the second processor being connected to a switch via a communication cable, the method comprising:

[0007] Based on the bus connection in the server, the first processor sends operation data to the second processor;

[0008] In the case where the operation data transmission fails, the first processor sends the operation data to the second processor based on the communication cable and the switch.

[0009] According to another aspect of the present application, a data transmission method is provided, the method being executed by a control device in a server, the first processor and the second processor belonging to the server, the first processor and the second processor being connected via a bus in the server, the first processor and the second processor being connected to a switch via a communication cable, the method comprising:

[0010] Controlling the first processor to send operation data to the second processor based on the bus connection in the server;

[0011] In the event that the operation data transmission fails, the first processor is controlled to send the operation data to the second processor based on the communication cable and the switch.

[0012] According to another aspect of the present application, a data transmission method is provided, the method being executed by a first processor, the first processor and the second processor belonging to the same server, the first processor and the second processor being connected via a bus in the server, the first processor and the second processor being connected to a switch via a communication cable, the method comprising:

[0013] Based on the communication cable and the switch, the first processor sends the operation data to the second processor;

[0014] In the event that the operation data transmission fails, the first processor sends the operation data to the second processor based on the bus connection in the server.

[0015] According to another aspect of the present application, a data transmission method is provided, the method being executed by a control device in a server, the first processor and the second processor belonging to the server, the first processor and the second processor being connected via a bus in the server, the first processor and the second processor being connected to a switch via a communication cable, the method comprising:

[0016] Controlling the first processor to send operation data to the second processor based on the communication cable and the switch;

[0017] In the event that the operation data transmission fails, the first processor is controlled to send the operation data to the second processor based on the bus connection in the server.

[0018] According to another aspect of the present application, a data transmission device is provided, wherein a first processor and a second processor belong to the same server, the first processor and the second processor are connected via a bus in the server, and the first processor and the second processor are connected to a switch via a communication cable, and the device comprises:

[0019] A sending module, configured to enable the first processor to send operation data to the second processor based on the bus connection in the server;

[0020] The sending module is further configured to enable the first processor to send the operation data to the second processor based on the communication cable and the switch when the operation data transmission fails.

[0021] In an optional design of the present application, the first processor and the second processor are respectively connected to a first access layer switch, and the first access layer switch is used to directly connect multiple processors; the sending module is also used to:

[0022] The first processor sends the operation data to the second processor via a first path, wherein the first path starts from the first processor and ends at the second processor, passing through the first access layer switch.

[0023] In an optional design of the present application, the first processor is connected to the second access layer switch, the second processor is connected to the third access layer switch, the first aggregation layer switch is connected to the second access layer switch and the third access layer switch respectively; the sending module is further used to:

[0024] The first processor sends the operation data to the second processor via a second path. The second path starts from the first processor and ends at the second processor, and passes through the second access layer switch, the first aggregation layer switch, and the third access layer switch in sequence.

[0025] In an optional design of the present application, the first processor is connected to the fourth access layer switch, the second processor is connected to the fifth access layer switch, the second aggregation layer switch is connected to the fourth access layer switch, the third aggregation layer switch is connected to the fifth access layer switch, and the core layer switch is connected to the second aggregation layer switch and the third aggregation layer switch respectively; the sending module is also used to:

[0026] The first processor sends the calculation data to the second processor via a third path. The third path starts from the first processor and ends at the second processor, and passes through the fourth access layer switch, the second aggregation layer switch, the core layer switch, the third aggregation layer switch, and the fifth access layer switch in sequence.

[0027] According to another aspect of the present application, a data transmission device is provided, wherein a first processor and a second processor belong to the same server, the first processor and the second processor are connected via a bus in the server, and the first processor and the second processor are connected to a switch via a communication cable, and the device comprises:

[0028] A control module, configured to control the first processor to send operation data to the second processor based on the bus connection in the server;

[0029] The control module is further configured to control the first processor to send the operation data to the second processor based on the communication cable and the switch when the operation data transmission fails.

[0030] In an optional design of the present application, the control module is also used for:

[0031] The first processor is controlled to send operation data to the second processor based on an interconnection channel provided by the bus connection in the server.

[0032] In an optional design of the present application, the control module is also used for:

[0033] The first processor is controlled to send operation data to the second processor based on the communication cable and the network channel provided by the switch.

[0034] In an optional design of the present application, the control module is also used for:

[0035] In case the operation data transmission fails, the data transmission state of the first processor is set to an initial state, and the data pointer is corrected to point to historical data before the operation data, wherein the historical data is based on data successfully transmitted through the bus connection.

[0036] According to another aspect of the present application, a data transmission device is provided, wherein a first processor and a second processor belong to the same server, the first processor and the second processor are connected via a bus in the server, and the first processor and the second processor are connected to a switch via a communication cable, and the device comprises:

[0037] A sending module, configured to enable the first processor to send the operation data to the second processor based on the communication cable and the switch;

[0038] The sending module is further configured to enable the first processor to send the operation data to the second processor based on the bus connection in the server when the operation data transmission fails.

[0039] According to another aspect of the present application, a data transmission device is provided, wherein a first processor and a second processor belong to the same server, the first processor and the second processor are connected via a bus in the server, and the first processor and the second processor are connected to a switch via a communication cable, and the device comprises:

[0040] A control module, configured to control the first processor to send operation data to the second processor based on the communication cable and the switch;

[0041] The control module is further configured to control the first processor to send the operation data to the second processor based on the bus connection in the server when the operation data transmission fails.

[0042] According to another aspect of the present application, a computer device is provided, comprising a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the data transmission method as described above.

[0043] According to another aspect of the present application, a computer-readable storage medium is provided, wherein at least one instruction, at least one program, a code set or an instruction set is stored in the computer-readable storage medium, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by a processor to implement the data transmission method as described above.

[0044] According to another aspect of the present application, a computer program product is provided, which includes computer instructions stored in a computer-readable storage medium, and a processor reads and executes the computer instructions from the computer-readable storage medium to implement the data transmission method described above.

[0045] The beneficial effects of the technical solution provided by this application include at least:

[0046] In the event that the transmission of computing data based on the bus connection fails, the computing data is retransmitted based on the communication cable connecting the switch and the first processor and the second processor, thereby realizing data transmission between two processors belonging to the same server and making full use of the bandwidth resources of the communication cable connecting the processor and the switch; avoiding the problem of being unable to execute data transmission between processors in the server due to transmission failure based on the bus connection and avoiding the risk of processor calculation interruption. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0048] Figure 1 is a schematic diagram of a computer system provided by an exemplary embodiment of the present application;

[0049] Figure 2is a schematic diagram of a processor connection relationship provided by an exemplary embodiment of the present application;

[0050] Figure 3 is a schematic diagram of an information transmission method provided by an exemplary embodiment of the present application;

[0051] Figure 4 is a flow chart of an information transmission method provided by an exemplary embodiment of the present application;

[0052] Figure 5 is a flow chart of an information transmission method provided by an exemplary embodiment of the present application;

[0053] Figure 6 is a flow chart of an information transmission method provided by an exemplary embodiment of the present application;

[0054] Figure 7 is a flow chart of an information transmission method provided by an exemplary embodiment of the present application;

[0055] Figure 8 is a schematic diagram of a connection relationship between a switch and a server provided by an exemplary embodiment of the present application;

[0056] Fig. 9 is a schematic diagram of a network channel and an interconnection channel provided by an exemplary embodiment of the present application;

[0057] Fig.10 is a schematic diagram of the performance of a single processor provided by an exemplary embodiment of the present application;

[0058] Fig.11 is a schematic diagram of the performance of a single processor provided by an exemplary embodiment of the present application;

[0059] Fig.12 is a flow chart of an information transmission method provided by an exemplary embodiment of the present application;

[0060] Fig.13 is a flow chart of an information transmission method provided by an exemplary embodiment of the present application;

[0061] Fig.14 is a structural block diagram of a data transmission device provided by an exemplary embodiment of the present application;

[0062] Fig.15 is a structural block diagram of a data transmission device provided by an exemplary embodiment of the present application;

[0063] Fig.16 It is a structural block diagram of a server provided by an exemplary embodiment of the present application.

[0064] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application. DETAILED DESCRIPTION

[0065] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0066] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0067] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. The singular forms of "a", "said" and "the" used in this disclosure and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0068] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions. For example, the bus identification and other information of the processor involved in this application are all obtained with full authorization.

[0069] It should be understood that although the terms first, second, etc. may be used in the present disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present disclosure, the first parameter may also be referred to as the second parameter, and similarly, the second parameter may also be referred to as the first parameter. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0070] Figure 1 A schematic diagram of a computer system provided by an embodiment of the present application is shown. The computer system can be implemented as a system architecture of a data transmission method.

[0071] The server 10 uses a processor as a computing core and has data processing capabilities. This embodiment is described by taking the server 10 as including four processors (a first processor 11, a second processor 12, a third processor 13, and a fourth processor 14), but it does not exclude that the processor includes a greater or lesser number of processors; optionally, the number of processors included in a server 10 is a positive integer power of 2. Exemplarily, the server 10 also includes a control device, which controls the processor in the server to perform at least one of data transmission, data operation, and data storage through signaling.

[0072] This embodiment is described by taking the example that the processor is a graphics processing unit (GPU), but does not exclude the case where in other examples, the processor is implemented as a main processor and / or other coprocessors.

[0073] Exemplarily, the main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor is implemented as a graphics processing unit (GPU) as described above; exemplarily, the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0074] Exemplarily, the multiple processors included in the server 10 are installed on the card slots, and the card slots provide hardware connections between the multiple processors in the server 10 to achieve interconnection and communication between the multiple processors in the server 10. In one example, the GPUs of the same server 10 are connected to each other through a bus to achieve interconnection and communication. Furthermore, data is transmitted based on a high-speed interconnection communication channel (such as an Nvlink channel).

[0075] Each processor included in the server 10 is connected to at least one switch 20; the switch 20 is used to connect multiple processors to achieve data exchange and forwarding for the multiple connected processors; illustratively, the switch 20 performs exchange and forwarding on data carried by Ethernet frames based on Ethernet.

[0076] In some embodiments, the switch includes an access layer switch (Access Layer, LA), a convergence layer switch (Layer Convergence, LC), and a core layer switch (Switched Gigabit Linecard, SGLC); wherein each LA can be connected to one or more processors, and each LA can be connected to one or more LCs; the core layer switch is used to connect multiple LCs; this application is not limited to this.

[0077] Exemplarily, each processor included in the server 10 is connected to a common switch. Exemplarily, the processor can be directly connected to the common switch, or can be indirectly connected to the common switch through other switches.

[0078] In some embodiments, processors communicate with each other in a ring-based manner, and communication specifically refers to data (traffic) transmission between processors. The data transmission paths between processors are connected end to end to form a ring, which is also called a communication traffic ring. Exemplarily, for any processor on the ring structure, there is a left-neighboring processor and a right-neighboring processor; the above processor receives data from the left-neighboring processor and sends data to the right-neighboring processor.

[0079] like Figure 2 As shown in the figure, taking the communication between four processors (first processor 11, second processor 12, third processor 13, fourth processor 14) based on the ring structure as an example, the above four processors communicate based on the Ring-based method, and the traffic interaction will be connected end to end to form a ring. For example, for processor 11, it receives data from its left neighbor processor, that is, processor 14; and sends data to its right neighbor processor, that is, processor 12. For example, in Figure 2 The storage space of each processor is divided into four data blocks (chunks); dividing the processor into chunks can increase the parallelism of communication. Each processor processes the corresponding data block, and different processors can perform communication operations in parallel, thereby improving the overall throughput.

[0080] Figure 3 A schematic diagram of an information transmission method provided by an embodiment of the present application is shown.

[0081] In this embodiment, the server 10 includes four GPUs (GPU0, GPU1, GPU2, GPU3) for example. It can be understood that in different examples, the server 10 may include more or fewer GPUs.

[0082] The above four GPUs are all connected to an access layer switch; specifically, LA0 is connected to GPU0 and GPU1 through communication cables, LA1 is connected to GPU1 through communication cables, LA2 is connected to GPU2 and GPU3 through communication cables, and LA3 is connected to GPU3 through communication cables.

[0083] The above four access layer switches are all connected to the aggregation layer switches; specifically, LC0 is connected to LA0 through a communication cable, LC1 is connected to LA1 through a communication cable, LC2 is connected to LA2 through a communication cable, and LC3 is connected to LA3 through a communication cable. The above four aggregation layer switches are all connected to the core layer switches through communication cables.

[0084] Based on the bus connection within the server 10, GPU0 sends computing data to GPU1; illustratively, the bus connection provides an interconnection channel, which can be specifically implemented as a high-speed interconnection communication channel (such as an Nvlink channel) to realize the transmission of computing data between GPU0 and GPU1.

[0085] In the case of a failure in the transmission of computing data, GPU0 resends the computing data to GPU1 based on the communication cable and the switch; illustratively, the communication cable and the switch provide a network channel. Further, the switch and the communication cable implement communication of the network channel based on Ethernet.

[0086] In summary, even if the operation and data transmission fails, the communication cables and switches can ensure the retransmission of the operation data, ensuring the stability of the operation and data transmission. The bandwidth resources of the communication cable connecting the processor and the switch are fully utilized; the problem of the inability to perform data transmission between processors in the server due to the failure of bus connection transmission is avoided, and the risk of processor calculation interruption is avoided.

[0087] Figure 4 A flowchart of an information transmission method provided by an exemplary embodiment of the present application is shown. The method can be executed by a first processor. The method includes:

[0088] Step 510: Based on the bus connection in the server, the first processor sends the operation data to the second processor;

[0089] The first processor and the second processor belong to the same server. In one example, the server is provided with card slots for each processor belonging to the server, or is integrated on a mainboard in the server. The first processor and the second processor are connected via a bus in the server.

[0090] Exemplarily, the transmission of the operation data may be exclusive to the bandwidth of the bus connection, or the data may be transmitted in parallel within the bus connection to share the bandwidth of the bus connection.

[0091] As introduced above, the processor in the present application can be implemented as different types of processors corresponding to different functions. In the following embodiments, the processor is implemented as a GPU as an example, but the situation of being implemented as other types of processors is not excluded.

[0092] Exemplarily, the operation data is the operation data that needs to be calculated in the process of the first processor and the second processor collaboratively performing data processing. For example, the server is used to perform training of an artificial intelligence neural network, and the operation data is the calculation result data of the first GPU. The first GPU sends the operation data to the second GPU, and the second GPU uses the operation data as an input parameter in the above-mentioned training process to enable the first GPU and the second GPU in the server to collaboratively perform training of the artificial intelligence neural network.

[0093] Step 520: In the case where the operation data transmission fails, the first processor sends the operation data to the second processor based on the communication cable and the switch;

[0094] The first processor and the second processor are connected to the switch through a communication cable. The switch is used to provide data forwarding and forward messages or data packets carrying data to the connected processors.

[0095] Similar to the bus connection transmission method mentioned above, the transmission of computing data can exclusively use the bandwidth of the communication cable, or the data can be transmitted in parallel within the communication cable to share the bandwidth of the communication cable.

[0096] Exemplarily, the operation data transmission failure is a transmission failure under the above-mentioned bus connection mode; exemplary, the operation data may be a transmission failure during the initial transmission process; or it may be a retransmission data transmission failure, such as the number of transmission failures of the operation data based on the bus connection exceeds a preset threshold, such as three times.

[0097] In one example, the situation where the operation data transmission fails includes at least one of the following: the first processor does not receive confirmation feedback of the operation data within a preset time, the first processor cannot determine the data receiving address of the second processor, and the first processor receives a retransmission request for the operation data.

[0098] Exemplarily, the reason for the failure of the operation data transmission may be that the bus connection is interrupted and the operation data cannot be transmitted, or the operation data transmission process is affected by noise and the second processor cannot obtain complete operation data. This application does not limit the reason for the failure of the operation data transmission.

[0099] To sum up, the method provided in this embodiment, when the operation data fails to be transmitted based on the bus connection, retransmits the operation data based on the communication cable connecting the switch and the first processor and the second processor, thereby realizing data transmission between two processors belonging to the same server and making full use of the bandwidth resources of the communication cable connecting the processor and the switch; avoiding the problem of being unable to execute data transmission between processors in the server due to transmission failure based on the bus connection, and avoiding the risk of processor calculation interruption.

[0100] Next, the manner in which the first processor and the second processor are connected to the switch through the communication cable is further introduced.

[0101] In one implementation, the first processor and the second processor are respectively connected to the first access layer switch, and the first access layer switch is used to directly connect multiple processors. It can be understood that the first access layer switch is usually connected to a larger number of processors. The processors connected to the first access layer switch may only include other processors in the server to which the first processor and the second processor belong, or may include other processors belonging to different servers.

[0102] Correspondingly, the transmission method of operation data can be specifically implemented as follows:

[0103] The first processor sends operation data to the second processor via a first path. The first path takes the first processor and the second processor as a starting point and an end point, and passes through a first access layer switch.

[0104] Further, the first processor sends a first message, and the first message is forwarded to the second processor via the first access layer switch;

[0105] Exemplarily, the sender address of the first message is the address of the first processor, the destination address is the address of the second processor, and the first message carries operation data.

[0106] refer to Figure 3 In one example, the computing data is sent from GPU1 to GPU0. Specifically, GPU1 sends the computing data to GPU0 via the following path: starting from GPU1, passing through LA1, and ending at GPU0.

[0107] To summarize, the method provided in this embodiment, when the transmission of computing data based on the bus connection fails, retransmits the computing data based on the communication cable connecting the switch and the first processor and the second processor, thereby realizing data transmission between two processors belonging to the same server; in addition to the bus connection within the server, a new data transmission method is expanded for the two processors that are commonly connected to the first access layer switch; the problem of being unable to execute data transmission between processors within the server due to transmission failure based on the bus connection is avoided, and the risk of processor calculation interruption is avoided.

[0108] In another implementation, the first processor is connected to the second access layer switch, the second processor is connected to the third access layer switch, and the first aggregation layer switch is connected to the second access layer switch and the third access layer switch, respectively. It can be understood that the second access layer switch and the third access layer switch are similar to the first access layer switch mentioned above, and are usually connected to a larger number of processors. The first aggregation layer switch is usually connected to a larger number of access layer switches. Exemplarily, the access layer switch can be connected to one or more aggregation layer switches.

[0109] Correspondingly, the transmission method of operation data can be specifically implemented as follows:

[0110] The first processor sends operation data to the second processor via a second path. The second path starts from the first processor and ends at the second processor, and passes through the second access layer switch, the first aggregation layer switch, and the third access layer switch in sequence.

[0111] Further, the first processor sends a second message, and the second message passes through the second access layer switch, the first aggregation layer switch, and the third access layer switch in sequence, and is forwarded to the second processor one by one;

[0112] Exemplarily, the sender address of the second message is the address of the first processor, the destination address is the address of the second processor, and the second message carries operation data.

[0113] refer to Figure 3 In one example, the computing data is sent from GPU2 to GPU1. Specifically, GPU2 sends the computing data to GPU1 via the following path: starting from GPU2, passing through LA2, LC1, LA1 in sequence, and ending at GPU1.

[0114] To summarize, the method provided in this embodiment, when the transmission of computing data based on the bus connection fails, retransmits the computing data based on the communication cable connecting the switch and the first processor and the second processor, thereby realizing data transmission between two processors belonging to the same server; in addition to the bus connection within the server, a new data transmission method is expanded for the two processors that are commonly connected to the first aggregation layer switch; the problem of being unable to execute data transmission between processors within the server due to transmission failure based on the bus connection is avoided, and the risk of processor calculation interruption is avoided.

[0115] In another implementation, the first processor is connected to the fourth access layer switch, the second processor is connected to the fifth access layer switch, the second aggregation layer switch is connected to the fourth access layer switch, the third aggregation layer switch is connected to the fifth access layer switch, and the core layer switch is connected to the second aggregation layer switch and the third aggregation layer switch, respectively; it can be understood that the fourth access layer switch and the fifth access layer switch are similar to the first access layer switch mentioned above, and are usually connected to a larger number of processors. The second aggregation layer switch and the third aggregation layer switch are usually connected to a larger number of access layer switches. Exemplarily, the access layer switch can be connected to one or more aggregation layer switches.

[0116] Correspondingly, the transmission method of operation data can be specifically implemented as follows:

[0117] The first processor sends calculation data to the second processor through the third path. The third path starts from the first processor and ends at the second processor, and passes through the fourth access layer switch, the second aggregation layer switch, the core layer switch, the third aggregation layer switch, and the fifth access layer switch in sequence.

[0118] Further, the first processor sends a third message, and the third message passes through the fourth access layer switch, the second aggregation layer switch, the core layer switch, the third aggregation layer switch, and the fifth access layer switch in sequence, and is forwarded to the second processor one by one;

[0119] Exemplarily, the sender address of the third message is the address of the first processor, the destination address is the address of the second processor, and the third message carries operation data.

[0120] refer to Figure 3 In one example, the computing data is sent from GPU3 to GPU2. Specifically, GPU3 sends the computing data to GPU2 via the following path: starting from GPU3, passing through LA3, LC3, SGLC, LC2, LA2 in sequence, and ending at GPU2.

[0121] To summarize, the method provided in this embodiment, when the transmission of computing data based on the bus connection fails, retransmits the computing data based on the communication cable connecting the switch and the first processor and the second processor, thereby realizing data transmission between two processors belonging to the same server; in addition to the bus connection within the server, a new data transmission method is expanded for the two processors that are commonly connected to the core layer switch; the problem of being unable to execute data transmission between processors within the server due to transmission failure based on the bus connection is avoided, and the risk of processor calculation interruption is avoided.

[0122] Figure 5 FIG. 1 is a flowchart of an information transmission method provided by an exemplary embodiment of the present application. The method may be executed by a first processor. Figure 4 In the illustrated embodiment, step 510 may be implemented as step 512, and step 520 may be implemented as step 522:

[0123] Step 512: Based on the interconnection channel provided by the bus connection, the first processor sends the operation data to the second processor;

[0124] The interconnection channel is used to provide a data transmission path between at least two processors in the server. Furthermore, the server also includes a larger number of processors, and the interconnection channel is also used to provide a data transmission path between any two servers in the server.

[0125] In one example, the interconnection channel provides a data transmission path such as Figure 2 The data transmission path for communication based on a ring structure (Ring-based) is introduced; if the second processor is the right neighbor processor of the first processor, the operation data is directly transmitted between the first processor and the second processor. If the second processor is the left neighbor processor of the first processor, the operation data sent by the first processor is forwarded to the second processor by at least one processor in the server.

[0126] In one example, the first processor and the second processor are image processors, and the interconnection channel is a high-speed interconnection communication channel corresponding to the image processor (such as an Nvlink channel); further, the high-speed interconnection communication channels of image processors from different manufacturers have different names, all of which are data transmission paths used to provide data transmission between image processors in the same server.

[0127] Step 522: In the case where the operation data transmission fails, the first processor sends the operation data to the second processor based on the network channel provided by the communication cable and the switch;

[0128] The network channel is used to provide a data transmission path between two processors connected by a communication cable. Furthermore, there is a commonly connected switch between any two processors belonging to the same server, and the commonly connected switch is an access layer switch directly connected to the processor, or an aggregation layer switch or a core layer switch indirectly connected through an access layer switch.

[0129] In an optional example, the server also includes a third processor, and any two of the first processor, the second processor and the third processor have a network channel provided by a communication cable and a switch, so that data can be transmitted between any two processors.

[0130] In an optional implementation, the network channel is a channel based on a ring structure; taking the case where the first processor sends operation data to the second processor as an example, if the second processor is the right neighbor of the first processor, the operation data is directly transmitted between the first processor and the second processor. If the second processor is the left neighbor of the first processor, the operation data sent by the first processor is forwarded to the second processor by at least one processor and at least one switch in the server. Exemplarily, in a network channel based on a ring structure, each processor only needs to process the corresponding data, and different processors can send or receive data at the same time and transmit data in parallel to achieve shared communication cable and switch bandwidth.

[0131] It should be noted that this embodiment only introduces the situation where step 512 and step 522 are executed simultaneously, but does not exclude the situation where the above two steps are executed separately, such as combining step 512 with step 520 in the above text, or combining step 522 with step 510 in the above text, to form a new embodiment that is implemented separately, and this application does not limit this.

[0132] To sum up, the method provided in this embodiment, when the transmission of computing data based on the bus connection fails, retransmits the computing data based on the network channel provided by the communication cable connecting the switch and the first processor and the second processor, thereby realizing data transmission between two processors belonging to the same server and making full use of the bandwidth resources of the communication cable connecting the processor and the switch; avoids the problem of failure of transmission through the interconnection channel provided by the bus connection, which causes the inability to execute data transmission between processors in the server, and avoids the risk of processor calculation interruption.

[0133] Figure 6 FIG. 1 is a flowchart of an information transmission method provided by an exemplary embodiment of the present application. The method may be executed by a first processor. Figure 5 On the basis of the illustrated embodiment, step 515, step 525, and step 526 are also included, and step 522 can be implemented as step 520a:

[0134] Step 515: Acquire a first channel resource bandwidth corresponding to the communication cable and a second channel resource bandwidth corresponding to the serial channel provided by the bus connection;

[0135] Exemplarily, the first channel resource bandwidth is the network channel resource bandwidth corresponding to the communication cable and the switch, and the second channel resource bandwidth is the bandwidth of the serial channel corresponding to the bus connection.

[0136] In one example, taking the image processor as the processor in the server, the interconnection channel in this embodiment is a high-speed interconnection communication channel (such as an Nvlink channel) corresponding to the image processor; and when the high-speed interconnection communication channel cannot successfully transmit the calculation data, the serial channel provided by the bus connection or the network channel provided by the communication cable retransmits the calculation data to ensure that the image processor in the server can realize data transmission, thereby realizing the process of collaborative data processing.

[0137] Furthermore, in order to ensure the transmission efficiency of the operation data, the first channel resource bandwidth and the second channel resource bandwidth are obtained to achieve retransmission of the operation data in a manner of adopting a higher transmission rate.

[0138] Step 520a: When the bandwidth of the first channel resource exceeds the bandwidth of the second channel resource and the operation data transmission fails, the first processor sends the operation data to the second processor based on the network channel provided by the communication cable and the switch;

[0139] When the bandwidth of the first channel resource exceeds the bandwidth of the second channel resource, the network channel provided by the communication cable and the switch can achieve the transmission of computing data at a higher transmission rate. When the bus connection cannot achieve the successful transmission of computing data, a new data transmission method is developed to avoid the problem of data transmission failure between processors in the server. At the same time, the difference in transmission rate between the network channel and the serial channel is taken into account, and the data transmission rate is improved based on the network channel with the higher transmission rate.

[0140] In an optional implementation, before the first processor sends operation data to the second processor based on the communication cable and the switch, it is necessary to determine whether the first processor and the second processor are directly connected.

[0141] In one example, when there is direct communication between the first processor, the second processor and the third processor and the operation data transmission fails, the first processor sends the operation data to the second processor based on the network channel provided by the communication cable and the switch.

[0142] Exemplarily, in the case of direct access between the first processor and the second processor, the two processors belong to the same server, and the processors use the tensor parallelism (TP) strategy for distributed computing to achieve parallel execution of data processing. This avoids the situation where there is no need to call the interconnection channel to transmit data under the data parallelism (DP) and pipeline parallelism (PP) strategies.

[0143] Furthermore, it can be implemented as follows: when any one of the first processor and the second processor obtains the bus identifier of the other processor without going through an intermediate device, and when the operation data transmission fails, the first processor sends the operation data to the second processor based on the network channel provided by the communication cable and the switch.

[0144] Exemplarily, a bus ID is a global ID of a processor in a server. Obtaining the bus ID of another processor without going through an intermediate device is also called direct reachability of the Bus ID; accordingly, the processors communicate directly through the bus without being transferred through additional devices or interfaces. Exemplarily, the bus ID is obtained by calling a Compute Unified Device Architecture (CUDA) driver function.

[0145] Step 525: When the bandwidth of the second channel resource exceeds the bandwidth of the first channel resource and the operation data transmission fails, the first processor sends the operation data to the second processor based on the serial channel provided by the bus connection;

[0146] When the bandwidth of the second channel resource exceeds the bandwidth of the first channel resource, the serial channel provided by the bus connection can achieve the transmission of operation data at a higher transmission rate. When the bus connection cannot achieve the successful transmission of operation data, a new data transmission method is developed.

[0147] Step 526: In the case where the operation data fails to be transmitted via the communication cable, the first processor sends the operation data to the second processor based on the serial channel provided by the bus connection;

[0148] Exemplarily, the failure of the operation data transmission based on the communication cable is used to indicate the failure of the operation data transmission in step 520a of this embodiment. Based on the serial channel provided by the bus connection, when both the network channel and the interconnection channel fail to transmit, an implementation method for retransmitting the operation data is provided.

[0149] In a specific example, the first processor and the second processor in the server are image processors. The interconnection channel can be specifically implemented as a high-speed interconnection communication channel (such as an Nvlink channel) to transmit operation data between two image processors in the server. The serial channel can be specifically implemented as a peripheral component interconnect express (Peripheral Component Interconnect Express, PCIE). The network channel can be specifically implemented as a wired data transmission channel provided based on Ethernet.

[0150] It should be noted that this embodiment only describes the case where all four steps are performed, but does not exclude the case where the above steps are performed separately, such as step 515, step 520a and Figure 4 or step 515, step 525 and Figure 4 The present application does not limit the situation in which the step 510 in the above-mentioned embodiment is combined to form a new embodiment which is implemented separately.

[0151] To sum up, the method provided in this embodiment, when the transmission of computing data based on the interconnection channel provided by the bus connection fails, uses the bandwidth resources of the communication cable connecting the processor and the switch, or the serial channel provided by the bus connection to retransmit the computing data; the problem of being unable to execute data transmission between processors in the server due to the failure of bus connection transmission is avoided, the data transmission rate is guaranteed during the retransmission process, and the risk of processor calculation interruption is avoided.

[0152] Figure 7 A flowchart of an information transmission method provided by an exemplary embodiment of the present application is shown. The method can be executed by a control device. The method includes:

[0153] Step 550: Control the first processor to send operation data to the second processor based on the bus connection in the server;

[0154] The first processor and the second processor belong to the same server and are connected via a bus in the server.

[0155] Exemplarily, the control device usually instructs the first processor and / or the second processor to transmit the operation data based on the control signaling. The control signaling can be used to instruct the first processor to send the operation data, and can also be used to instruct the second processor to receive the operation data. Exemplarily, the control signaling can be sent to the first processor and / or the second processor based on a bus connection (such as a PCIE channel provided by the bus connection), and it is not excluded that the control signaling is transmitted through shared memory or the like.

[0156] In an optional implementation, this step may be implemented as: controlling the first processor to send operation data to the second processor based on an interconnection channel provided by a bus connection within the server.

[0157] The interconnection channel is used to provide a data transmission path between at least two processors in the server. Further, the interconnection channel is also used to provide a data transmission path between any two servers in the server.

[0158] The control device sends an instruction signaling for calling the interconnection channel to the first processor and / or the second processor to control the transmission of the operation data.

[0159] Step 555: in the case where the operation data transmission fails, the data transmission state of the first processor is set to the initial state, and the data pointer is corrected to point to the historical data before the operation data;

[0160] Exemplarily, the initial state is a state of preparing to send the computing data, so as to control the first processor to no longer transmit the computing data in a bus connection manner, but to prepare to send the computing data through a communication cable and a switch, such as resetting the queue waiting (Queue Pair) state.

[0161] Exemplarily, the historical data is data successfully transmitted based on the bus connection. When the first processor is controlled to send data again, the data sent is the next data of the data currently pointed to by the data pointer.

[0162] Exemplarily, the operation data transmission failure is a transmission failure under the above-mentioned bus connection mode; exemplary, the operation data may be a transmission failure during the initial transmission process; or it may be a retransmission data transmission failure, such as the number of transmission failures of the operation data based on the bus connection exceeds a preset threshold, such as three times.

[0163] Step 560: In the case where the operation data transmission fails, controlling the first processor to send the operation data to the second processor based on the communication cable and the switch;

[0164] The first processor and the second processor are connected to the switch through a communication cable. The switch is used to provide data forwarding and forward messages or data packets carrying data to the connected processors.

[0165] Similar to the above bus-connection-based transmission mode of computing data, the control device usually instructs the first processor and / or the second processor to transmit computing data based on control signaling. The control signaling can be used to instruct the first processor to send computing data, and can also be used to instruct the second processor to receive computing data.

[0166] In an optional implementation, this step may be implemented as follows: in the event of a failure in transmission of computing data, controlling the first processor to send computing data to the second processor based on a network channel provided by a communication cable and a switch.

[0167] The network channel is used to provide a data transmission path between two processors connected by a communication cable. Furthermore, there is a commonly connected switch between any two processors belonging to the same server. There is a network channel provided by the communication cable and the switch between any two servers in the server.

[0168] When the bus connection cannot achieve successful transmission of computing data, the data transmission method based on communication cables and switches is expanded, avoiding the problem of being unable to execute data transmission between processors in the server and avoiding the risk of processor calculation interruption.

[0169] For example, regarding the introduction of the data transmission failure and the connection between the first processor and the second processor and the switch through the communication cable, please refer to the above Figures 3 to 6 , I will not repeat them one by one here.

[0170] It should be noted that step 550 and step 560 in this embodiment can be combined into a new embodiment and implemented separately, and this application does not limit this.

[0171] To sum up, the method provided in this embodiment, when the operation data fails to be transmitted based on the bus connection, retransmits the operation data based on the communication cable connecting the switch and the first processor and the second processor, thereby realizing data transmission between two processors belonging to the same server and making full use of the bandwidth resources of the communication cable connecting the processor and the switch; avoiding the problem of being unable to execute data transmission between processors in the server due to transmission failure based on the bus connection, and avoiding the risk of processor calculation interruption.

[0172] Figure 8 A schematic diagram showing the connection relationship between a switch and a server provided by an exemplary embodiment of the present application.

[0173] In this embodiment, the server 10 includes eight GPUs (GPU0 to GPU7) for example. The eight GPUs are all connected to access layer switches, totaling eight access layer switches; each GPU is connected to an access layer switch with the same serial number, for example: LA0 is connected to GPU1 through a communication cable; and Figure 3 Similarly, the eight GPUs included in server 10 have one-to-one corresponding NICs.

[0174] It should be noted that LA0 is also connected to GPU1 through a communication cable, LA2 is also connected to GPU3 through a communication cable, LA4 is also connected to GPU5 through a communication cable, and LA6 is also connected to GPU7 through a communication cable.

[0175] Exemplarily, the eight access layer switches are connected to the aggregation layer switches, totaling eight aggregation layer switches; each access layer switch is connected to the aggregation layer switch with the same sequence number, for example: LC0 is connected to LA0 via a communication cable. Exemplarily, the eight aggregation layer switches are all connected to the core layer switch.

[0176] In this embodiment, the candidate network channel is a channel based on a ring structure.

[0177] Specifically: GPU0 communicates with GPU1 through LA0.

[0178] GPU1 communicates with GPU2 through LA1, LC1, SGLC, LC2, LA2.

[0179] GPU2 communicates with GPU3 through LA2.

[0180] GPU3 communicates through LA3, LC3, SGLC, LC4, LA4 and GPU4.

[0181] GPU4 communicates with GPU5 through LA4.

[0182] GPU5 communicates through LA5, LC5, SGLC, LC6, LA6 and GPU6.

[0183] GPU6 communicates with GPU7 through LA6.

[0184] GPU7 communicates through LA7, LC7, SGLC, LC0, LA0 and GPU0.

[0185] Fig. 9 A schematic diagram of a network channel and an interconnection channel provided by an exemplary embodiment of the present application is shown.

[0186] Among them, the first interconnection channel 601, the second interconnection channel 602 to the Nth interconnection channel 603 are interconnection channels provided by the bus connection; as described above, the interconnection channel is a channel based on a ring structure. In the above example, the number of interconnection channels is 16, that is, the value of N is 16. Each interconnection channel is used to transmit a data block, such as transmitting the first data block 611 based on the first interconnection channel 601. It should be noted that the figure shows that the first data block 611 passes through all processors in GPU0 to GPU7, but in some examples, the first data block can pass through a smaller number of GPUs, such as transmitting the first data block 611 only between GPU0 and GPU1. Exemplarily, the data blocks transmitted on different interconnection channels are different, which can realize the parallel transmission of multiple data blocks without interfering with each other.

[0187] Exemplarily, in the event that the data block transmission of the interconnection channel fails, the data block is transmitted based on the network channel instead. Specifically, the first network channel 621, the second network channel 622 to the Nth network channel 623 are network channels provided by communication cables and switches; as described above, the network channel is a channel based on a ring structure. In this embodiment, the number of network channels is the same as the number of interconnection channels, that is, the value of N is 16. Each network channel is used to transmit a data block, such as transmitting the first data block 611 based on the first network channel 611. Exemplarily, the data blocks transmitted on different network channels are different. Exemplarily, the data blocks transmitted on different network channels are different, which can realize the parallel transmission of multiple data blocks without interfering with each other.

[0188] It should be noted that the above describes an embodiment in which the number of network channels is the same as the number of interconnection channels. In another optional implementation, when the channel resource bandwidth of the network channel is smaller than the channel resource bandwidth of the interconnection channel, in order to ensure the transmission rate of a single data, the number of network channels is smaller than the number of interconnection channels, and the number of parallel transmission data supported by the network channel is reduced compared to the interconnection channel, so as to ensure that the data transmission rate of a single network channel is the same as that of the interconnection channel.

[0189] Fig.10 A schematic diagram of the performance of a single processor provided by an exemplary embodiment of the present application is shown. It is used to indicate the data transmission rate when the processor uses the All Reduce Operation (AllReduce) to perform distributed computing. When an Nvlink channel failure occurs, the network channel is used to transmit the computing data, achieving a transmission bandwidth of 47GB / s without interrupting communication.

[0190] Fig.11A schematic diagram of the performance of a single processor provided by an exemplary embodiment of the present application is shown. It is used to indicate the data transmission rate when the processor uses data exchange between all participants (such as All to All) to perform distributed computing. When an Nvlink channel failure occurs, the network channel is used to transmit the computing data, achieving a transmission bandwidth of 28GB / s without interrupting communication.

[0191] Fig.12 A flowchart of an information transmission method provided by an exemplary embodiment of the present application is shown. The method can be executed by a first processor. The method includes:

[0192] Step 650: Based on the communication cable and the switch, the first processor sends the operation data to the second processor;

[0193] The first processor and the second processor belong to the same server. In one example, the server is provided with card slots for each processor belonging to the server, or is integrated on a mainboard in the server. The first processor and the second processor are connected to a switch via a communication cable, and the switch is used to provide data forwarding, and forward messages or data packets carrying data to the connected processors.

[0194] The transmission of computing data can exclusively use the bandwidth of the communication cable, or the data can be transmitted in parallel within the communication cable to share the bandwidth of the communication cable.

[0195] For details about how to connect the first processor and the second processor to the switch through the communication cable, please refer to the above Figure 3 The corresponding embodiments, as well as the introduction to the first access layer switch, the first aggregation layer switch, and the core layer switch are not repeated here one by one.

[0196] Step 660: In the case where the operation data transmission fails, the first processor sends the operation data to the second processor based on the bus connection in the server;

[0197] The first processor and the second processor are connected via a bus in the server.

[0198] Similar to the transmission method of the communication cables and switches mentioned above, the transmission of computing data can be exclusive to the bandwidth of the bus connection, or the data can be transmitted in parallel within the bus connection and share the bandwidth of the bus connection.

[0199] Exemplarily, the operation data transmission failure is a transmission failure in the above-mentioned communication cable and switch mode; exemplary, the operation data may be a transmission failure during the initial transmission process; or it may be a retransmission data transmission failure, such as the number of transmission failures of the operation data based on the bus connection exceeds a preset threshold, such as three times.

[0200] In this embodiment, for the unfinished matters regarding the introduction of communication cables, switches, bus connections, and transmission failures, please refer to the above Figure 4 For an introduction to the network channels provided by communication cables and switches, and the interconnection channels provided by bus connections, please refer to the above Figure 5 The corresponding embodiments will not be described in detail here.

[0201] In an optional implementation, before step 660, the following steps are further included:

[0202] Acquire a first channel resource bandwidth corresponding to an interconnection channel provided by the bus connection and a second channel resource bandwidth corresponding to a serial channel provided by the bus connection;

[0203] Accordingly, step 660 is implemented as follows: when the first channel resource bandwidth exceeds the second channel resource bandwidth and the operation data transmission fails, the first processor sends the operation data to the second processor based on the interconnection channel provided by the bus connection in the server;

[0204] In one example, taking the processor in the server as an image processor, the communication cable and switch in this embodiment provide a network channel. When the network channel cannot successfully transmit the computing data, the serial channel or interconnection channel provided by the bus connection retransmits the computing data to ensure that the image processor in the server can realize data transmission, thereby realizing the process of collaborative data processing.

[0205] Furthermore, in order to ensure the transmission efficiency of the operation data, the first channel resource bandwidth and the second channel resource bandwidth are obtained to achieve retransmission of the operation data in a manner of adopting a higher transmission rate.

[0206] It can be seen that when the bandwidth of the first channel resource exceeds the bandwidth of the second channel resource, the interconnection channel provided by the bus connection can achieve the transmission of computing data at a higher transmission rate. When the network channel provided by the communication cable and the switch cannot achieve the successful transmission of computing data, a new data transmission method is developed to avoid the problem that the data transmission cannot be performed between the processors in the server. At the same time, the difference in transmission rate between the interconnection channel and the serial channel is taken into account, and the data transmission rate is improved based on the network channel with the higher transmission rate.

[0207] Furthermore, it also includes: when the second channel resource bandwidth exceeds the first channel resource bandwidth and the operation data transmission fails, the first processor sends the operation data to the second processor based on the serial channel provided by the bus connection within the server; that is, when the second channel resource bandwidth exceeds the first channel resource bandwidth, the serial channel provided by the bus connection can achieve the transmission of operation data at a higher transmission rate.

[0208] Exemplarily, regarding the specific implementation methods of the network channel, the interconnection channel, and the serial channel, reference may be made to the introduction in step 526 above.

[0209] In an optional implementation, before the first processor sends the operation data to the second processor based on the bus connection in the server, it is necessary to determine whether the first processor and the second processor are directly connected. For an introduction to whether the first processor and the second processor are directly connected, please refer to the introduction in step 520a above, which will not be repeated here.

[0210] To sum up, the method provided in this embodiment, when the transmission of computing data based on the communication cable fails, retransmits the computing data based on the bus connection between the first processor and the second processor provided in the server, thereby realizing data transmission between two processors belonging to the same server and making full use of the bandwidth resources of the bus connection; avoiding the problem of being unable to execute data transmission between processors in the server due to transmission failure based on communication cables and switches, and avoiding the risk of processor calculation interruption.

[0211] Fig.13 A flowchart of an information transmission method provided by an exemplary embodiment of the present application is shown. The method can be executed by a control device. The method includes:

[0212] Step 670: Control the first processor to send operation data to the second processor based on the communication cable and the switch;

[0213] The first processor and the second processor belong to the same server. The first processor and the second processor are connected to a switch via a communication cable, and the switch is used to provide data forwarding and forward messages or data packets carrying data to the connected processors.

[0214] Exemplarily, the control device usually instructs the first processor and / or the second processor to transmit the operation data based on the control signaling. The control signaling can be used to instruct the first processor to send the operation data, and can also be used to instruct the second processor to receive the operation data. Exemplarily, the control signaling can be sent to the first processor and / or the second processor based on a bus connection (such as a PCIE channel provided by the bus connection), and it is not excluded that the control signaling is transmitted through shared memory or the like.

[0215] In an optional implementation, this step may be implemented as: controlling the first processor to send operation data to the second processor based on a network channel provided by a communication cable and a switch.

[0216] The network channel is used to provide a data transmission path between two processors connected by a communication cable. Furthermore, there is a commonly connected switch between any two processors belonging to the same server. There is a network channel provided by the communication cable and the switch between any two servers in the server.

[0217] Step 680: In the case where the operation data transmission fails, controlling the first processor to send the operation data to the second processor based on the bus connection in the server;

[0218] The first processor and the second processor are connected via a bus in the server.

[0219] Similar to the above transmission method of computing data based on communication cable, the control device usually instructs the first processor and / or the second processor to transmit computing data based on control signaling. The control signaling can be used to instruct the first processor to send computing data, and can also be used to instruct the second processor to receive computing data.

[0220] In an optional implementation, this step may be implemented as follows: in the event of a failure in the transmission of computing data, controlling the first processor to send computing data to the second processor based on an interconnection channel provided by a bus connection within the server.

[0221] The interconnection channel is used to provide a data transmission path between at least two processors in the server. Further, the interconnection channel is also used to provide a data transmission path between any two servers in the server.

[0222] The control device sends an instruction signaling for calling the interconnection channel to the first processor and / or the second processor to control the transmission of the operation data.

[0223] When communication cables and switches cannot successfully transmit computing data, the data transmission method based on bus connection is expanded, avoiding the problem of being unable to execute data transmission between processors in the server and avoiding the risk of processor calculation interruption.

[0224] For example, regarding the introduction of the data transmission failure and the connection between the first processor and the second processor and the switch through the communication cable, please refer to the above Figures 3 to 6 , I will not repeat them one by one here.

[0225] In an optional implementation, before step 680, the method further includes: in the case where the operation data transmission fails, setting the data transmission state of the first processor to an initial state, and correcting the data pointer to point to historical data before the operation data;

[0226] Similar to step 555 above, the initial state is a state of preparing to send the computing data, so as to control the first processor to no longer transmit the computing data via the communication cable and the switch, but to prepare to send the computing data via the bus connection, for example, resetting the queue waiting (Queue Pair) state.

[0227] Exemplarily, the historical data is data successfully transmitted by means of a communication cable and a switch. When the first processor is controlled to send data again, the data sent is the next data of the data currently pointed to by the data pointer.

[0228] To sum up, the method provided in this embodiment, when the transmission of computing data based on the communication cable fails, retransmits the computing data based on the bus connection between the first processor and the second processor provided in the server, thereby realizing data transmission between two processors belonging to the same server and making full use of the bandwidth resources of the bus connection; avoiding the problem of being unable to execute data transmission between processors in the server due to transmission failure based on communication cables and switches, and avoiding the risk of processor calculation interruption.

[0229] Those skilled in the art can understand that the above embodiments can be implemented independently, or the above embodiments can be freely combined to form new embodiments to implement the data transmission method of the present application.

[0230] Fig.14 A structural block diagram of a data transmission device provided by an exemplary embodiment of the present application is shown. A first processor and a second processor belong to the same server, the first processor and the second processor are connected via a bus in the server, the first processor and the second processor are connected to a switch via a communication cable, and the device includes:

[0231] A sending module 810, configured to cause the first processor to send operation data to the second processor based on the bus connection in the server;

[0232] The sending module 810 is further configured to, when the transmission of the operation data fails, enable the first processor to send the operation data to the second processor based on the communication cable and the switch.

[0233] In an optional design of the present application, the first processor and the second processor are respectively connected to a first access layer switch, and the first access layer switch is used to directly connect multiple processors; the sending module 810 is also used to:

[0234] The first processor sends the operation data to the second processor via a first path, wherein the first path starts from the first processor and ends at the second processor, passing through the first access layer switch.

[0235] In an optional design of the present application, the first processor is connected to the second access layer switch, the second processor is connected to the third access layer switch, the first aggregation layer switch is connected to the second access layer switch and the third access layer switch respectively; the sending module 810 is further used to:

[0236] The first processor sends the operation data to the second processor via a second path. The second path starts from the first processor and ends at the second processor, and passes through the second access layer switch, the first aggregation layer switch, and the third access layer switch in sequence.

[0237] In an optional design of the present application, the first processor is connected to the fourth access layer switch, the second processor is connected to the fifth access layer switch, the second aggregation layer switch is connected to the fourth access layer switch, the third aggregation layer switch is connected to the fifth access layer switch, and the core layer switch is connected to the second aggregation layer switch and the third aggregation layer switch respectively; the sending module 810 is further used to:

[0238] The first processor sends the calculation data to the second processor via a third path. The third path starts from the first processor and ends at the second processor, and passes through the fourth access layer switch, the second aggregation layer switch, the core layer switch, the third aggregation layer switch, and the fifth access layer switch in sequence.

[0239] In an optional design of the present application, the sending module 810 is further used for:

[0240] Based on the communication cable and the network channel provided by the switch, the first processor sends the operation data to the second processor; the network channel is used to provide a data transmission path between the two processors connected by the communication cable.

[0241] In an optional design of the present application, the server further includes a third processor, and the network channel is a channel based on a ring structure;

[0242] Among them, a transmission path based on a network channel between the first processor, the second processor, and any two of the second processors passes through at least one switch.

[0243] In an optional design of the present application, the sending module 810 is further used for:

[0244] Based on the interconnection channel provided by the bus connection, the first processor sends the operation data to the second processor; the interconnection channel is used to provide a data transmission path between at least two processors in the server.

[0245] In an optional design of the present application, the device further includes:

[0246] An acquisition module 820 is used to acquire a first channel resource bandwidth corresponding to the communication cable and a second channel resource bandwidth corresponding to the serial channel provided by the bus connection;

[0247] The sending module 810 is also used for:

[0248] When the first channel resource bandwidth exceeds the second channel resource bandwidth and the operation data transmission fails, the first processor sends the operation data to the second processor based on the communication cable and the network channel provided by the switch.

[0249] In an optional design of the present application, the sending module 810 is further used for:

[0250] When the second channel resource bandwidth exceeds the first channel resource bandwidth and the operation data transmission fails, the first processor sends the operation data to the second processor based on the serial channel provided by the bus connection.

[0251] In an optional design of the present application, the sending module 810 is further used for:

[0252] In the case where the operation data fails to be transmitted via the communication cable, the first processor sends the operation data to the second processor based on the serial channel provided by the bus connection.

[0253] Fig.15 A structural block diagram of a data transmission device provided by an exemplary embodiment of the present application is shown. A first processor and a second processor belong to the same server, the first processor and the second processor are connected via a bus in the server, the first processor and the second processor are connected to a switch via a communication cable, and the device includes:

[0254] A control module 830, configured to control the first processor to send operation data to the second processor based on the bus connection in the server;

[0255] The control module 830 is further configured to control the first processor to send the operation data to the second processor based on the communication cable and the switch when the operation data transmission fails.

[0256] In an optional design of the present application, the control module 830 is further used for:

[0257] The first processor is controlled to send operation data to the second processor based on an interconnection channel provided by the bus connection in the server.

[0258] In an optional design of the present application, the control module 830 is further used for:

[0259] The first processor is controlled to send operation data to the second processor based on the communication cable and the network channel provided by the switch.

[0260] In an optional design of the present application, the control module 830 is further used for:

[0261] In case the operation data transmission fails, the data transmission state of the first processor is set to an initial state, and the data pointer is corrected to point to historical data before the operation data, wherein the historical data is based on data successfully transmitted through the bus connection.

[0262] An exemplary embodiment of the present application provides a data transmission device. A first processor and a second processor belong to the same server, the first processor and the second processor are connected via a bus in the server, and the first processor and the second processor are connected to a switch via a communication cable, and the device includes:

[0263] A sending module, configured to enable the first processor to send the operation data to the second processor based on the communication cable and the switch;

[0264] The sending module is further configured to enable the first processor to send the operation data to the second processor based on the bus connection in the server when the operation data transmission fails.

[0265] An exemplary embodiment of the present application provides a data transmission device. A first processor and a second processor belong to the same server, the first processor and the second processor are connected via a bus in the server, and the first processor and the second processor are connected to a switch via a communication cable, and the device includes:

[0266] A control module, configured to control the first processor to send operation data to the second processor based on the communication cable and the switch;

[0267] The control module is further configured to control the first processor to send the operation data to the second processor based on the bus connection in the server when the operation data transmission fails.

[0268] One point that needs to be explained is that the device provided in the above embodiment only uses the division of the above-mentioned functional modules as an example to implement its functions. In actual applications, the above-mentioned functions can be assigned to different functional modules according to actual needs, that is, the content structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0269] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method; the technical effects achieved by each module performing operations are the same as those in the embodiment of the method, and will not be elaborated here.

[0270] An embodiment of the present application further provides a computer device, which includes: a processor and a memory, wherein a computer program is stored in the memory; the processor is used to execute the computer program in the memory to implement the data transmission method provided by the above-mentioned method embodiments.

[0271] Optionally, the computer device is a server. Fig.16 It is a structural block diagram of a server provided by an exemplary embodiment of the present application.

[0272] Typically, the server 2300 includes: a processor 2301 and a memory 2302 .

[0273] The processor 2301 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 2301 may be implemented in at least one hardware form of digital signal processing (DSP), field programmable gate array (FPGA), and programmable logic array (PLA). The processor 2301 may also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 2301 may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 2301 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0274] The memory 2302 may include one or more computer-readable storage media, which may be non-transitory. The memory 2302 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 2302 is used to store at least one instruction, which is used to be executed by the processor 2301 to implement the data transmission method provided in the method embodiment of the present application.

[0275] In some embodiments, the server 2300 may also optionally include: an input interface 2303 and an output interface 2304. The processor 2301, the memory 2302, the input interface 2303, and the output interface 2304 may be connected via a bus or a signal line. Each peripheral device may be connected to the input interface 2303 and the output interface 2304 via a bus, a signal line, or a circuit board. The input interface 2303 and the output interface 2304 may be used to connect at least one peripheral device related to input / output (I / O) to the processor 2301 and the memory 2302. In some embodiments, the processor 2301, the memory 2302, the input interface 2303, and the output interface 2304 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 2301, the memory 2302, the input interface 2303, and the output interface 2304 may be implemented on a separate chip or circuit board, which is not limited in the embodiments of the present application.

[0276] Those skilled in the art will appreciate that the structure shown above does not constitute a limitation on the server 2300 , and may include more or fewer components than shown in the figure, or combine certain components, or adopt a different component arrangement.

[0277] In an exemplary embodiment, a chip is also provided. The chip includes a programmable logic circuit and / or program instructions. When the chip runs on a computer device, it is used to implement the data transmission method described in the above aspects.

[0278] In an exemplary embodiment, a computer program product is also provided, the computer program product includes computer instructions, the computer instructions are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor reads and executes the computer instructions from the computer-readable storage medium to implement the data transmission method provided by each of the above method embodiments.

[0279] In an exemplary embodiment, a computer-readable storage medium is further provided, in which a computer program is stored. The computer program is loaded and executed by a processor to implement the data transmission method provided by the above-mentioned method embodiments.

[0280] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0281] Those skilled in the art should be aware that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented with hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein the communication media include any media that facilitates the transmission of a computer program from one place to another. The storage medium can be any available medium that a general or special-purpose computer can access.

[0282] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A data transmission method, characterized in that: The method is executed by a first processor, the first processor, the second processor, and the third processor belong to the same server, the first processor and the second processor are connected via a bus in the server, and the first processor and the second processor are connected to a switch via a communication cable, and the method includes: The first processor sends operation data to the second processor based on an interconnection channel provided by the bus connection in the server, wherein the interconnection channel is used to provide a data transmission path between at least two processors in the server, and the interconnection channel is a transmission path provided by the manufacturers of the at least two processors; Acquire a first channel resource bandwidth corresponding to the communication cable and a second channel resource bandwidth corresponding to a serial channel provided by the bus connection, wherein the serial channel includes a peripheral component interconnect express (PCIE); When the resource bandwidth of the first channel exceeds the resource bandwidth of the second channel and the operation data transmission fails, the first processor sends the operation data to the second processor based on the network channel provided by the communication cable and the switch; the network channel is used to provide a data transmission path between two processors connected by the communication cable, and the network channel is a channel based on a ring structure, and the network channel of the ring structure is used to transmit data blocks in parallel; in the network channel, the second processor is the left adjacent processor of the first processor.

2. The method according to claim 1, characterized in that The first processor and the second processor are respectively connected to a first access layer switch, and the first access layer switch is used to directly connect multiple processors; The first processor sending the operation data to the second processor includes: The first processor sends the operation data to the second processor via a first path, wherein the first path starts from the first processor and ends at the second processor, passing through the first access layer switch.

3. The method according to claim 1, characterized in that The first processor is connected to the second access layer switch, the second processor is connected to the third access layer switch, and the first aggregation layer switch is connected to the second access layer switch and the third access layer switch respectively; The first processor sending the operation data to the second processor includes: The first processor sends the operation data to the second processor via a second path. The second path starts from the first processor and ends at the second processor, and passes through the second access layer switch, the first aggregation layer switch, and the third access layer switch in sequence.

4. The method according to claim 1, characterized in that: The first processor is connected to the fourth access layer switch, the second processor is connected to the fifth access layer switch, the second aggregation layer switch is connected to the fourth access layer switch, the third aggregation layer switch is connected to the fifth access layer switch, and the core layer switch is connected to the second aggregation layer switch and the third aggregation layer switch respectively; The first processor sending the operation data to the second processor includes: The first processor sends the calculation data to the second processor via a third path. The third path starts from the first processor and ends at the second processor, and passes through the fourth access layer switch, the second aggregation layer switch, the core layer switch, the third aggregation layer switch, and the fifth access layer switch in sequence.

5. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: When the second channel resource bandwidth exceeds the first channel resource bandwidth and the operation data transmission fails, the first processor sends the operation data to the second processor based on the serial channel provided by the bus connection.

6. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: In the case that the operation data fails to be transmitted via the network channel, the first processor sends the operation data to the second processor based on the serial channel provided by the bus connection.

7. A data transmission method, characterized in that: The method is executed by a control device in a server, a first processor, a second processor, and a third processor belong to the server, the first processor and the second processor are connected via a bus in the server, and the first processor and the second processor are connected to a switch via a communication cable, and the method includes: Controlling the first processor to send operation data to the second processor based on an interconnection channel provided by the bus connection in the server, wherein the interconnection channel is used to provide a data transmission path between at least two processors in the server, and the interconnection channel is a transmission path provided by manufacturers of the at least two processors; Acquire a first channel resource bandwidth corresponding to the communication cable and a second channel resource bandwidth corresponding to a serial channel provided by the bus connection, wherein the serial channel includes a peripheral component interconnect express channel; When the resource bandwidth of the first channel exceeds the resource bandwidth of the second channel and the operation data transmission fails, the first processor is controlled to send the operation data to the second processor based on the network channel provided by the communication cable and the switch; the network channel is used to provide a data transmission path between two processors connected by the communication cable, the network channel is a channel based on a ring structure, and the network channel with a ring structure is used to transmit data blocks in parallel; in the network channel, the second processor is the left adjacent processor of the first processor.

8. The method according to claim 7, characterized in that The method further comprises: In case the operation data transmission fails, the data transmission state of the first processor is set to an initial state, and the data pointer is corrected to point to historical data before the operation data, wherein the historical data is based on data successfully transmitted through the bus connection.

9. A data transmission method, characterized in that: The method is executed by a first processor, the first processor, the second processor, and the third processor belong to the same server, the first processor and the second processor are connected via a bus in the server, and the first processor and the second processor are connected to a switch via a communication cable, and the method includes: Based on the network channel provided by the communication cable and the switch, the first processor sends operation data to the second processor; the network channel is used to provide a data transmission path between the two processors connected by the communication cable, the network channel is based on a ring structure, and the network channel of the ring structure is used to transmit data blocks in parallel; in the network channel, the second processor is the left neighbor processor of the first processor; Acquire a first channel resource bandwidth corresponding to an interconnection channel provided by the bus connection and a second channel resource bandwidth corresponding to a serial channel provided by the bus connection, wherein the interconnection channel is used to provide a data transmission path between at least two processors in the server, the interconnection channel is a transmission path provided by the manufacturers of the at least two processors, and the serial channel includes a peripheral component interconnect express channel; When the second channel resource bandwidth exceeds the first channel resource bandwidth and the operation data transmission fails, the first processor sends the operation data to the second processor based on the serial channel provided by the bus connection in the server.

10. A data transmission method, characterized in that: The method is executed by a control device in a server, a first processor, a second processor, and a third processor belong to the server, the first processor and the second processor are connected via a bus in the server, and the first processor and the second processor are connected to a switch via a communication cable, and the method includes: Control the first processor to send operation data to the second processor based on the network channel provided by the communication cable and the switch; the network channel is used to provide a data transmission path between two processors connected by the communication cable, the network channel is a channel based on a ring structure, and the network channel of the ring structure is used to transmit data blocks in parallel; in the network channel, the second processor is the left neighbor processor of the first processor; Acquire a first channel resource bandwidth corresponding to an interconnection channel provided by the bus connection and a second channel resource bandwidth corresponding to a serial channel provided by the bus connection, wherein the interconnection channel is used to provide a data transmission path between at least two processors in the server, the interconnection channel is a transmission path provided by the manufacturers of the at least two processors, and the serial channel includes a peripheral component interconnect express channel; When the second channel resource bandwidth exceeds the first channel resource bandwidth and the operation data transmission fails, the first processor is controlled to send the operation data to the second processor based on the serial channel provided by the bus connection in the server.

11. A data transmission device, characterized in that: The data transmission device is provided by a first processor, the first processor and the second processor belong to the same server, the first processor, the second processor and the third processor are connected via a bus in the server, the first processor and the second processor are connected to a switch via a communication cable, and the device includes: a sending module, configured to enable the first processor to send operation data to the second processor based on an interconnection channel provided by the bus connection in the server, wherein the interconnection channel is used to provide a data transmission path between at least two processors in the server, and the interconnection channel is a transmission path provided by manufacturers of the at least two processors; An acquisition module, configured to acquire a first channel resource bandwidth corresponding to the communication cable and a second channel resource bandwidth corresponding to a serial channel provided by the bus connection, wherein the serial channel includes a peripheral component interconnect express channel; The sending module is also used for, when the resource bandwidth of the first channel exceeds the resource bandwidth of the second channel and the transmission of the operation data fails, the first processor sends the operation data to the second processor based on the network channel provided by the communication cable and the switch; the network channel is used to provide a data transmission path between two processors connected by the communication cable, the network channel is a channel based on a ring structure, and the network channel of the ring structure is used to transmit data blocks in parallel; in the network channel, the second processor is the left adjacent processor of the first processor.

12. A data transmission device, characterized in that: The data transmission device is provided by a control device in a server, the first processor and the second processor belong to the same server, the first processor, the second processor and the third processor are connected via a bus in the server, the first processor and the second processor are connected to a switch via a communication cable, and the device includes: a control module, configured to control the first processor to send operation data to the second processor based on an interconnection channel provided by the bus connection in the server, wherein the interconnection channel is configured to provide a data transmission path between at least two processors in the server, and the interconnection channel is a transmission path provided by manufacturers of the at least two processors; An acquisition module, configured to acquire a first channel resource bandwidth corresponding to the communication cable and a second channel resource bandwidth corresponding to a serial channel provided by the bus connection, wherein the serial channel includes a peripheral component interconnect express channel; The control module is further used to control the first processor to send operation data to the second processor based on the network channel provided by the communication cable and the switch when the resource bandwidth of the first channel exceeds the resource bandwidth of the second channel and the operation data transmission fails; the network channel is used to provide a data transmission path between two processors connected by the communication cable, the network channel is a channel based on a ring structure, and the network channel of the ring structure is used to transmit data blocks in parallel; in the network channel, the second processor is the left adjacent processor of the first processor.

13. A data transmission device, characterized in that: The data transmission device is provided by a first processor, the first processor and the second processor belong to the same server, the first processor, the second processor and the third processor are connected via a bus in the server, the first processor and the second processor are connected to a switch via a communication cable, and the device includes: A sending module, configured to enable the first processor to send operation data to the second processor based on the network channel provided by the communication cable and the switch; the network channel is configured to provide a data transmission path between two processors connected by the communication cable, the network channel is a channel based on a ring structure, and the network channel of the ring structure is configured to transmit data blocks in parallel; in the network channel, the second processor is the left neighbor of the first processor; an acquisition module, configured to acquire a first channel resource bandwidth corresponding to an interconnection channel provided by the bus connection and a second channel resource bandwidth corresponding to a serial channel provided by the bus connection, wherein the interconnection channel is used to provide a data transmission path between at least two processors in the server, the interconnection channel is a transmission path provided by the manufacturers of the at least two processors, and the serial channel includes a peripheral component interconnect express channel; The sending module is further configured to enable the first processor to send the operation data to the second processor based on the serial channel provided by the bus connection in the server when the second channel resource bandwidth exceeds the first channel resource bandwidth and the operation data transmission fails.

14. A data transmission device, characterized in that: The data transmission device is provided by a control device in a server, the first processor and the second processor belong to the same server, the first processor, the second processor and the third processor are connected via a bus in the server, the first processor and the second processor are connected to a switch via a communication cable, and the device includes: A control module, used for controlling the first processor to send operation data to the second processor based on the network channel provided by the communication cable and the switch; the network channel is used for providing a data transmission path between two processors connected by the communication cable, the network channel is based on a ring structure, and the network channel of the ring structure is used for parallel transmission of data blocks; in the network channel, the second processor is the left neighbor processor of the first processor; an acquisition module, configured to acquire a first channel resource bandwidth corresponding to an interconnection channel provided by the bus connection and a second channel resource bandwidth corresponding to a serial channel provided by the bus connection, wherein the interconnection channel is used to provide a data transmission path between at least two processors in the server, the interconnection channel is a transmission path provided by the manufacturers of the at least two processors, and the serial channel includes a peripheral component interconnect express channel; The control module is further configured to control the first processor to send the operation data to the second processor based on the serial channel provided by the bus connection in the server when the second channel resource bandwidth exceeds the first channel resource bandwidth and the operation data transmission fails.

15. A computer device, characterized in that: The computer device comprises: a processor and a memory, wherein the memory stores at least one program; the processor is used to execute the at least one program in the memory to implement the data transmission method according to any one of claims 1 to 10.

16. A computer-readable storage medium, characterized in that: The readable storage medium stores executable instructions, and the executable instructions are loaded and executed by a processor to implement the data transmission method described in any one of claims 1 to 10.

17. A computer program product, characterized in that The computer program product includes computer instructions, which are stored in a computer-readable storage medium. A processor reads and executes the computer instructions from the computer-readable storage medium to implement the data transmission method according to any one of claims 1 to 10.

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