A silicon carbide device, a manufacturing method thereof, and an electronic device

Abstract

The present invention relates to the field of semiconductor technology, and particularly to a silicon carbide device, a manufacturing method thereof, and an electronic device. The silicon carbide device includes: a silicon carbide substrate layer and an epitaxial layer disposed on the silicon carbide substrate layer. A trench gate structure is provided on a side of the epitaxial layer away from the silicon carbide substrate layer. Shielding structures are provided on both sides of the trench gate structure. A first shielding region of the shielding structure extends toward a first surface side of the silicon carbide substrate layer. A second shielding region of the shielding structure is provided on a side of the first shielding region facing the first surface of the silicon carbide substrate layer. Along a first direction, a gap between two adjacent second shielding regions is smaller than a gap between two adjacent first shielding regions; a length of the first shielding region is smaller than a length of the second shielding region, and in a projection on the epitaxial layer, the second shielding region completely covers the first shielding region. Along a second direction, a depth of the trench gate structure is smaller than a depth of the shielding structure. The silicon carbide transistor in the present invention has relatively high reliability and a relatively low on-resistance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a silicon carbide device, a manufacturing method thereof and an electronic device. Background Art

[0002] As a semiconductor material with a wide bandgap, high breakdown field strength, high thermal conductivity, and mobility similar to that of silicon, silicon carbide has broad prospects in power electronics applications and is widely used in new energy vehicles, charging piles, photovoltaics and other fields.

[0003] Since the gate oxide layer at the bottom of the trench gate included in the silicon carbide device is close to the drift region, the gate oxide layer at the bottom of the trench gate needs to withstand greater electric field stress, which causes the gate oxide layer at the bottom of the trench gate to be easily broken down, thereby reducing the reliability of the silicon carbide device. Therefore, a wider shielding area is provided on both sides of the trench gate structure to protect the structure of the gate oxide layer, but this method will increase the on-resistance of the silicon carbide device. Therefore, how to improve the reliability of the silicon carbide device while reducing the on-resistance of the silicon carbide device has become a technical problem to be solved in this field. Summary of the invention

[0004] Embodiments of the present invention provide a silicon carbide device, a manufacturing method thereof, and an electronic device, which are used to improve the reliability of a silicon carbide transistor and reduce the on-resistance of the silicon carbide device.

[0005] In a first aspect, an embodiment of the present invention provides a silicon carbide device, comprising: a silicon carbide substrate layer; an epitaxial layer, wherein the epitaxial layer is arranged on a first surface of the silicon carbide substrate layer; a trench gate structure is arranged on a side of the epitaxial layer away from the first surface of the silicon carbide substrate layer, shielding structures are arranged on both sides of the trench gate structure, the shielding structure comprises a first shielding region and a second shielding region, the first shielding region extends toward the first surface of the silicon carbide substrate layer, and the first shielding region is arranged on a side of the first shielding region facing the first surface of the silicon carbide substrate layer. Along a first direction, there is a gap between two adjacent second shielding regions, the gap between two adjacent second shielding regions is smaller than the gap between two adjacent first shielding regions, the length of the first shielding region is smaller than the length of the second shielding region, and in a projection of the epitaxial layer, the second shielding region completely covers the first shielding region, and along the second direction, the depth of the trench gate structure is smaller than the depth of the shielding structure.

[0006] In one embodiment, along the first direction, a difference between a length of the first shielding region and a length of the second shielding region is 10 nanometers to 5 micrometers.

[0007] In one embodiment, the doping types of the first shielding region and the second shielding region are opposite to that of the epitaxial layer, and the doping concentrations of the first shielding region and the second shielding region are between 10 times and 1,000,000 times that of the epitaxial layer.

[0008] In one embodiment, along the second direction, the depth of the shielding structure is L, and along the first direction, the gap between two adjacent first shielding regions is d, and the value of L / d is between 0.5 and 20.

[0009] In one embodiment, along the first direction, a current conduction region is formed between two adjacent shielding structures, and a first doping region and a second doping region are arranged between the trench gate structure and the first shielding region. The first doping region and the second doping region are stacked in sequence on the side of the current conduction region facing away from the silicon carbide substrate layer, where:

[0010] The doping types of the first doping region and the second doping region are opposite, and the doping type of the first doping region is the same as that of the second shielding region.

[0011] In one embodiment, the trench gate structure includes a polysilicon gate trench and a gate dielectric. The polysilicon gate trench includes a bottom wall and a side wall. The thickness of the gate dielectric provided on the bottom wall of the polysilicon gate trench is Tb, and the thickness of the gate dielectric provided on the side wall of the polysilicon gate trench is Ts. Tb≥Ts and the value of Tb / Ts is between 1 and 3.

[0012] In one embodiment, along the second direction, the depth of the polysilicon gate trench is greater than the depth of the first doping region.

[0013] In one embodiment, the silicon carbide device further includes a covering dielectric layer. The covering dielectric layer is arranged on the side of the epitaxial layer facing away from the silicon carbide substrate layer, and the covering dielectric layer covers the polysilicon gate trench.

[0014] In a second aspect, an embodiment of the present invention provides a method for manufacturing a silicon carbide device using the medium as described in the first aspect above, including:

[0015] Form an epitaxial layer on the silicon carbide substrate layer;

[0016] Form second shielding regions of two shielding structures spaced apart along the first direction in the epitaxial layer;

[0017] Form a first shielding region of the shielding structure on the side of the second shielding region facing away from the silicon carbide substrate layer. Along the first direction, the length of the first shielding region is less than the length of the second shielding region, and the gap between the two first shielding regions is greater than the gap between the two second shielding regions. In the projection of the epitaxial layer, the second shielding region completely covers the first shielding region;

[0018] A trench gate structure is formed between the two first shielding regions. Along the second direction, the depth of the trench gate structure is less than the depth of the first shielding region.

[0019] In a third aspect, an embodiment of the present invention provides an electronic device, including the silicon carbide device introduced in the first aspect above.

[0020] In the silicon carbide device, its manufacturing method, and the electronic device provided by the embodiment of the present invention, along the first direction, the length of the first shielding region is less than the length of the second shielding region. In the projection of the epitaxial layer, the second shielding region completely covers the first shielding region. Along the second direction, the depth of the trench gate structure is less than the depth of the shielding structure. Among them, the gap between the first shielding regions determines the width of the conduction current channel and thus affects the on-resistance. And the length of the first shielding region is smaller than the length of the second shielding region, which can ensure that the on-resistance of the silicon carbide device is smaller. The width of the second shielding region determines the shielding degree of the strong electric field stress and thus affects the protection effect of the trench gate structure. The distance between two adjacent second shielding regions is smaller, so that the shielding ability of the second shielding region can be improved, and the risk that the gate oxide layer at the bottom of the trench gate structure is easily broken down can be reduced. In addition, when two shielding structures, namely the first shielding region and the two second shielding regions, are used simultaneously, a wider conduction current channel (i.e., the gap between two adjacent first shielding regions) and a better strong electric field stress shielding effect can be ensured to appear in a silicon carbide device at the same time, making the silicon carbide device more compact. Description of the Drawings

[0021] Figure 1 It is a cross-sectional view of a silicon carbide crystal device provided in an embodiment of the present invention;

[0022] Figure 2 It is a flowchart of a manufacturing method of a silicon carbide crystal device provided in an embodiment of the present invention;

[0023] Figures 3a to 3i It is a manufacturing process of a silicon carbide crystal device provided in an embodiment of the invention;

[0024] Figure 4 It is another flowchart of a manufacturing method of a silicon carbide crystal device provided in an embodiment of the present invention;

[0025] Figures 5a to 5i It is a manufacturing process of a silicon carbide crystal device provided in an embodiment of the invention;

[0026] Figure 6 It is another flowchart of a manufacturing method of a silicon carbide crystal device provided in an embodiment of the present invention;

[0027] Figures 7a to 7iThis is a manufacturing process of a silicon carbide crystal device provided in the invention embodiment.

[0028] Reference numerals:

[0029] 10 - Silicon carbide substrate layer; 11 - First surface; 12 - Second surface; 20 - Epitaxial layer; 21 - Current conduction region; 22 - First doping region; 23 - Second doping region; 30 - Polysilicon gate trench; 31 - Bottom wall; 32 - Side wall; 40 - Gate dielectric; 50 - First shielding region; 60 - Second shielding region; 70 - Covering dielectric layer. Detailed implementation manners

[0030] Next, the detailed implementation manners of a silicon carbide transistor, its manufacturing method, and an electronic device provided in the embodiments of the present invention will be described in conjunction with the accompanying drawings. It should be noted that the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0031] Figure 1 This is a schematic structural diagram of the silicon carbide device provided in the embodiments of the present application. Figure 1 In the figure, the X direction is the first direction, and the Y direction is the second direction. Refer to Figure 1 , the silicon carbide device includes a silicon carbide substrate layer 10 and an epitaxial layer 20 provided on the silicon carbide substrate layer 10. Among them, the silicon carbide substrate layer 10 can be a P-type substrate or an N-type substrate, and the epitaxial layer 20 is an N-type epitaxial layer. When the silicon carbide substrate layer 10 is a P-type substrate and the epitaxial layer 20 is an N-type epitaxial layer, the silicon carbide device provided in the present application is a MOSFET power device. When the silicon carbide substrate layer 10 is an N-type substrate and the epitaxial layer 20 is an N-type epitaxial layer, the silicon carbide device in the present application is an IGBT power device.

[0032] Along the thickness direction of the silicon carbide substrate layer 10, i.e., the second direction, the silicon carbide substrate layer 10 includes a first surface 11 and a second surface 12 that are arranged opposite to each other, the epitaxial layer 20 is arranged on the first surface 11 of the silicon carbide substrate layer 10, and the second surface 12 can be connected to a metal collector electrode or a metal drain electrode D. A trench gate structure is arranged in the epitaxial layer 20, and the trench gate structure is arranged on a side of the epitaxial layer 20 away from the silicon carbide substrate layer 10. Shielding structures are arranged on both sides of the trench gate structure, and the shielding structure includes a first shielding area 50 and a second shielding area 60. The first shielding area 50 extends toward the first surface 11 of the silicon carbide substrate layer 10, and the second shielding area 60 is arranged on the side of the first shielding area 50 facing the first surface 11 of the silicon carbide substrate layer 10. Along the first direction X, there is a gap d1 between two adjacent second shielding regions 60, the length h1 of the first shielding region 50 is less than the length h2 of the second shielding region 60, in the projection of the epitaxial layer 20, the second shielding region 60 completely covers the first shielding region 50, and along the second direction Y, the depth of the trench gate structure is less than the depth of the shielding structure. Specifically, the first direction X can also be the arrangement direction of the first shielding regions 50, the second direction Y can be a direction perpendicular to the first surface 11 and the second surface 12 of the silicon carbide substrate layer 10, and the first direction X and the second direction Y can be perpendicular to each other. Among them, the gap d between the first shielding regions 50 determines the width of the conduction current channel and thus affects the on-resistance, and the length of the first shielding region 50 is smaller than the length of the second shielding region 60, which can ensure that the on-resistance of the silicon carbide device is small, the width h2 of the second shielding region 60 determines the degree of shielding against strong electric field stress and thus affects the protection effect of the trench gate structure, and the distance between the two adjacent second shielding regions 60 is small, so that the shielding ability of the second shielding region 60 can be improved, and the risk of the gate oxide layer at the bottom of the trench gate structure being easily broken down can be reduced. In addition, using two first shielding regions 50 and two second shielding regions 60 simultaneously can ensure that a wider conduction current channel (i.e., the gap d between two adjacent first shielding regions 50) and a better strong electric field stress shielding effect appear simultaneously in a silicon carbide device, thereby making the silicon carbide device more compact.

[0033] More specifically, along the first direction, the difference between the length h1 of the first shielding area 50 and the length h2 of the second shielding area 60 is 10 nanometers to 5 micrometers, that is, the difference h2-h1 is between 10 nanometers and 5 micrometers. That is, the low on-resistance between the two first shielding areas 50 can be guaranteed, and the length of the second shielding area 60 can also be guaranteed, and the shielding effect of the first shielding area 50 and the second shielding area 60 can be guaranteed. If the difference h2-h1 is not between 10 nanometers and 5 micrometers, it can only achieve the effect of low on-resistance or protection of the gate oxide layer at the bottom of the trench gate structure, so that the low on-resistance and gate oxide layer protection of the silicon carbide device conflict with each other, and the two cannot be achieved in the same silicon carbide device.

[0034] The doping types of the first shielding region 50 and the second shielding region 60 are the same, and the doping types of the first shielding region 50 and the second shielding region 60 are opposite to the doping type of the epitaxial layer 20, that is, the doping type of the shielding structure is opposite to the doping type of the epitaxial layer 20. The first shielding region 50 and the second shielding region 60 are P-type doping regions. The doping concentration of the first shielding region 50 and the second shielding region 60 is between 10 times and 1,000,000 times the doping concentration of the epitaxial layer 20. Among them, the concentration of the first shielding region 50 and the second shielding region 60 determines the shielding effect on the strong electric field stress. The larger the concentration difference, the better the shielding effect, the smaller the electric field stress borne by the gate oxide layer in the trench gate structure, and the better the reliability performance. If the doping concentration difference between the first shielding region 50 and the second shielding region 60 is not within the range of 10 times to 1,000,000 times, the effects of the first shielding region 50 and the second shielding region 60 cannot be effectively exerted, and thus the electric field stress borne by the gate oxide layer in the trench gate structure cannot be effectively reduced.

[0035] Continue to refer to Figure 1 , along the second direction Y, the depth of the shielding structure is L, and along the first direction X, the gap between two adjacent first shielding regions is d, and L / d is between 0.5 and 20. Among them, when L / d is between 0.5 and 20, the shielding effect on the strong electric field stress borne by the gate oxide layer in the trench gate structure is better. If L / d is less than 0.5, the shielding effect cannot be achieved. If the L / d ratio is greater than 20, the on-resistance of the silicon carbide device will increase significantly.

[0036] Continue to refer to Figure 1 , along the first direction X, a current conduction region 21 is formed between two adjacent first shielding regions 50 and two adjacent second shielding regions 60, that is, a current conduction region 21 is formed between two adjacent shielding structures. The setting of the current conduction region 21 can reduce the resistance of conduction between the shielding structures. A first doping region 22 and a second doping region 23 are provided between the trench gate structure and the first shielding region 50. The first doping region 22 and the second doping region 23 are stacked in sequence on the side of the current conduction region 21 away from the silicon carbide substrate layer 10. Among them: the doping types of the first doping region 22 and the second doping region 23 are opposite, and the doping type of the first doping region 22 is the same as that of the second shielding region 60. Among them, the second shielding region 60 is a P-type doping region, then the first doping region 22 is a P-type doping region, and the second doping region 23 is an N-type doping region to ensure the stable operation of the silicon carbide device.

[0037] In the above embodiments, the trench gate structure includes a polysilicon gate trench 30 and a gate dielectric 40. The polysilicon gate trench 30 includes a bottom wall 31 and side walls 32. The thickness of the gate dielectric disposed on the bottom wall 31 of the polysilicon gate trench 30 is Tb, and the thickness of the gate dielectric disposed on the side walls 32 of the polysilicon gate trench 30 is Ts, where Tb≥Ts. The thickness of the gate dielectric 40 disposed on the bottom wall 31 being greater than the thickness of the gate dielectric 40 disposed on the side walls 32 of the polysilicon gate trench 30 can increase the stress-bearing capacity of the trench gate structure, and thus improve the stress-bearing capacity of the silicon carbide device. More specifically, Tb / Ts is equal to 1 to 3, that is, the thickness of the gate dielectric on the bottom wall 31 is 1 to 3 times the thickness of the gate dielectric on the side walls 32. If Tb / Ts is less than 1, the increased stress-bearing capacity of the trench gate structure is small, and the improvement in the stress-bearing capacity of the silicon carbide device is also small. If Tb / Ts is greater than 3, the thickness of the gate dielectric on the bottom wall is too thick, affecting the space inside the polysilicon gate trench 30. Among them, the side walls of the polysilicon gate trench 30 are aligned with any crystal plane in the {1-100} crystal plane family or the {11-20} crystal plane family. In addition, the arrangement of the polysilicon gates on the side walls of the polysilicon gate trench 30 is any one of strip arrangement, square arrangement, pin-like arrangement, hexagonal arrangement, or atomic lattice arrangement. The polysilicon gate trench 30 is connected to the gate electrode G through a metal contact.

[0038] In one embodiment, along the second direction Y, the depth of the polysilicon gate trench 30 is h3, and the depth of the first doping region 22 is h4, where h3>h4 to ensure the normal operation of the device.

[0039] Continuing to refer to Figure 1 , the silicon carbide device further includes a covering dielectric layer 70. The covering dielectric layer 70 is disposed on the side of the epitaxial layer 20 facing away from the silicon carbide substrate layer 10, and the covering dielectric layer 70 covers the trench gate structure. It can be understood that in the first direction X, the length of the covering dielectric layer 70 is greater than the length of the polycrystalline gate trench structure. More specifically, the projection of the covering dielectric layer 70 on the silicon carbide substrate layer 10 completely covers the polycrystalline gate trench structure and partially covers the two second doping regions 23, and the covering dielectric layer 70 separates the two second doping regions 23, so that after the source electrode S is connected to the two second doping regions, it is separated by the covering dielectric layer 70.

[0040] Figure 2 FIG. is a flowchart of a method for manufacturing a silicon carbide crystal device provided in an embodiment of the present invention;

[0041] Figures 3a to 3i FIG. is a manufacturing process of a silicon carbide crystal device provided in an embodiment of the invention. A method for manufacturing a silicon carbide device provided in an embodiment of the present invention, referring to Figure 2 , Figures 3a to 3i , the manufacturing method includes:

[0042] S10: Form an epitaxial layer 20 on a silicon carbide substrate layer 10. The silicon carbide substrate layer 10 is a P-type substrate or an N-type substrate, and the epitaxial layer 20 is an N-type epitaxial layer 20.

[0043] In step S10, a CVD (chemical vapor deposition) process may be adopted, using methane or propane as the material growth gas and hydrogen as the carrier gas to epitaxially grow the epitaxial layer 20. Of course, the epitaxial layer 20 may also be obtained by other methods well-known to those skilled in the art, and this is not limited herein.

[0044] S20: Form two second shielding regions 60 of a shielding structure spaced along a first direction in the epitaxial layer 20;

[0045] In step S20, a dielectric layer or polysilicon may be used as a hard mask, and an ion implantation process is adopted to implant semiconductor impurities of a conductivity type opposite to that of the silicon carbide substrate above the epitaxial layer 20 to form the second shielding regions 60;

[0046] S30: Form a first shielding region 50 of a shielding structure on a side of the second shielding region 60 away from the silicon carbide substrate layer 10. Along the first direction, the length of the first shielding region 50 is less than the length of the second shielding region 60, and the gap between the two first shielding regions 50 is greater than the gap between the two second shielding regions 60. In the projection of the epitaxial layer 20, the second shielding region 60 completely covers the first shielding region 50.

[0047] In step S30, a self-alignment process is adopted. A covering film is deposited on both sides of the ion implantation window, and then the bottom film is removed by etching to achieve the purpose of reducing the implantation window. The same doping as the first shielding region 50 is implanted via the hard mask, and two first shielding regions 50 are formed, and the two first shielding regions 50 are symmetrically arranged.

[0048] Among them, the hard mask is a dielectric layer or polysilicon.

[0049] S40: Form a current conduction region 21 between the first shielding region 50 and the second shielding region 60.

[0050] In step S40, a photolithography and ion implantation process is adopted to form a current conduction region 21 in a region between the two first shielding regions 50 and the two second shielding regions 60, that is, a current conduction region 21 is formed between the two shielding structures, and a first doping region 22 and a second doping region 23 are formed on a side of the current conduction region 21 away from the silicon carbide substrate layer 10, and the impurities implanted in each region are activated by high-temperature annealing.

[0051] S50: A trench gate structure is formed between two first shielding regions 50. Along the second direction, the depth of the trench gate structure is less than the depth of the shielding structure.

[0052] In step S50, a dielectric layer or polysilicon is used as a hard mask, and combined with an etching process, a polysilicon gate trench 30 is etched at the central position between two first shielding regions 50. The depth of the etched polysilicon gate trench 30 is greater than the depth of the first doping region 22, and the depth of the polysilicon gate trench 30 is less than the depth of the shielding structure. The bottom wall 31 of the polysilicon gate trench 30 is deeper than the bottom of the first doping region 22, and the depth difference between the two is between 10 nanometers and 5 micrometers to ensure the normal operation of the power device.

[0053] After step S50, step S51 is further included: Under a non-oxidizing and non-nitriding atmosphere, a high-temperature annealing process is adopted to make the sharp corners on the bottom wall 31 of the polysilicon gate trench 30 passivated and rounded. After deep etching of the polysilicon gate trench 30, sharp corners will appear at the bottom and top. If the angle is too sharp, the subsequent coverage effect of the gate dielectric 40 is poor, and at the same time, electric field concentration is likely to occur near the acute angle, causing premature breakdown of the silicon carbide device and deteriorating the reliability of the silicon carbide device. Therefore, an operation of rounding the acute angle is required.

[0054] Step S52: A thermal oxidation or deposition and etching process is used to produce the gate dielectric 40 material on the bottom wall 31 of the polysilicon gate trench 30, and the excess gate dielectric 40 material is etched away to obtain the gate dielectric 40. Among them, the thickness of the gate dielectric 40 provided on the bottom wall 31 of the polysilicon gate trench 30 is Tb, and the thickness of the gate dielectric 40 provided on the side wall 32 of the polysilicon gate trench 30 is Ts. Tb≥Ts and the range of Tb / Ts is between 1 and 3. If Tb / Ts is not between 1 and 3, it will lead to poor reliability of the gate dielectric 40, and at the same time, it will increase the process difficulty.

[0055] S60: A polysilicon gate is arranged inside the polysilicon gate trench 30, and a covering dielectric layer 70 is formed on the surface of the epitaxial layer 20. The polysilicon layer covers the polysilicon gate trench 30, and the covering dielectric layer 70 covers the epitaxial layer 20 and the covering dielectric layer 70.

[0056] In step S60, a deposition and etching process is adopted to deposit a layer of polysilicon on the surface of the epitaxial layer 20, etch away the excess polysilicon material, then deposit a covering dielectric layer 70, and then selectively etch away part of the covering dielectric layer 70 above the second doping layer to form a polysilicon gate surrounded by the gate dielectric layer in the polysilicon gate trench 30; the relationship between the width Di of the covering dielectric layer 70 above the polysilicon gate trench 30 and the width Dg of the polysilicon gate trench 30 is Di>Dg.

[0057] S70: Using deposition and etching processes, deposit a metal layer on the surface of the epitaxial layer 20. After etching is completed, source electrodes are formed on the surfaces of the first shielding region 50 and the second doping region 23; a gate is formed on the polysilicon gate portion; after thinning the side of the silicon carbide substrate layer 10 away from the epitaxial layer 20, a drain electrode is formed by depositing a layer of metal, and finally a silicon carbide device is fabricated.

[0058] Figure 4 Another flowchart of a manufacturing method of a silicon carbide crystal device provided in an embodiment of the present invention; Figures 5a to 5i A manufacturing process of a silicon carbide crystal device provided in an embodiment of the invention. Refer to Figure 4 、 Figures 5a to 5i A manufacturing method of a silicon carbide device provided in an embodiment of the present invention includes: S100: Form an epitaxial layer 20 on the silicon carbide substrate layer 10. Among them, the silicon carbide substrate layer 10 is a P-type substrate or an N-type substrate, and the epitaxial layer 20 is an N-type epitaxial layer 20.

[0059] In step S100, a CVD (chemical vapor deposition) process can be adopted, using methane or propane as the material growth gas and hydrogen as the carrier gas to epitaxially grow the epitaxial layer 20. Of course, the epitaxial layer 20 can also be obtained by other methods well-known to those skilled in the art, which is not limited herein.

[0060] S200: Form a first doping region 22 in the epitaxial layer 20 by ion implantation. Compared with forming the first doping region 22 after forming the shielding structure, that is, forming the first shielding region 50 and the second shielding region 60, this method can avoid the concentration deviation of the first doping region 22 caused by the deviation of the ion implantation activation rate, and further cause the deviation of the device threshold voltage.

[0061] S300: Form two second shielding regions 60 of the shielding structure spaced apart along the first direction in the epitaxial layer 20;

[0062] In step S300, a dielectric layer or polysilicon can be used as a hard mask, and an ion implantation process is adopted to implant semiconductor impurities of a conductivity type opposite to that of the silicon carbide substrate above the epitaxial layer 20 to form the second shielding region 60;

[0063] S400: Form a first shielding region 50 of the shielding structure on the side of the second shielding region 60 away from the silicon carbide substrate layer 10. Along the first direction, the length of the first shielding region 50 is less than the length of the second shielding region 60, and the gap between the two first shielding regions 50 is greater than the gap between the two second shielding regions 60. In the projection of the epitaxial layer 20, the second shielding region 60 completely covers the first shielding region 50.

[0064] In step S400, a self-alignment process is adopted. A covering film is deposited on both sides of the ion implantation window, and then the bottom film is removed by etching to achieve the purpose of reducing the implantation window. Doping the same as that of the first shielding region 50 is carried out through the hard mask, and two first shielding regions 50 are formed, and the two first shielding regions 50 are symmetrically arranged.

[0065] Among them, the hard mask is a dielectric layer or polysilicon.

[0066] S500: A current conduction region 21 is formed between the first shielding region 50 and the second shielding region 60.

[0067] In step S500, a photolithography and ion implantation process is adopted to form a current conduction region 21 and a second doping region 23 in the region between the two first shielding regions 50 and the two second shielding regions 60, that is, the region between the two shielding structures. The current conduction region 21 is located on the side of the first doping region 22 facing the silicon carbide substrate layer 10, and the second doping region 23 is located between the first doping region 22 and the current conduction region 21. The impurities implanted in each region are activated by high-temperature annealing.

[0068] S600: A trench gate structure is formed between the two shielding structures. Along the second direction, the depth of the trench gate structure is less than the depth of the shielding structure.

[0069] In step S600, a dielectric layer or polysilicon is used as the hard mask, and combined with the etching process, a polysilicon gate trench 30 is etched at the central position between the two first shielding regions 50. The depth of the obtained polysilicon gate trench 30 is greater than the depth of the first doping region 22, and the depth of the polysilicon gate trench 30 is less than the depth of the first shielding region 50. The bottom wall 31 of the polysilicon gate trench 30 is deeper than the bottom of the first doping region 22, and the depth difference between the two is between 10 nanometers and 5 micrometers.

[0070] After step S600, step S601 is further included: Under a non-oxidizing and non-nitriding atmosphere, a high-temperature annealing process is adopted to make the sharp corners on the bottom wall 31 of the polysilicon gate trench 30 be passivated and become round.

[0071] Step S602: A gate dielectric 40 material is produced on the bottom wall 31 of the polysilicon gate trench 30 by thermal oxidation or deposition and etching processes, and the redundant gate dielectric 40 material is etched away to obtain the gate dielectric 40. Among them, the thickness of the gate dielectric 40 provided on the bottom wall 31 of the polysilicon gate trench 30 is Tb, and the thickness of the gate dielectric 40 provided on the side wall 32 of the polysilicon gate trench 30 is Ts. Tb≥Ts and Tb / Ts is equal to 1 to 3.

[0072] S700: A polysilicon gate is disposed inside the polysilicon gate trench 30, and a covering dielectric layer 70 is formed on the surface of the epitaxial layer 20. The polysilicon layer covers the polysilicon gate trench 30, and the covering dielectric layer 70 covers the epitaxial layer 20 and the covering dielectric layer 70.

[0073] In step S700, a polysilicon layer is deposited on the surface of the epitaxial layer 20 by using deposition and etching processes, the excess polysilicon material is etched away, a covering dielectric layer 70 is deposited again, and then part of the covering dielectric layer 70 above the second doped layer is selectively etched away to form a polysilicon gate surrounded by a gate dielectric layer in the polysilicon gate trench 30; the relationship between the width Di of the covering dielectric layer 70 above the polysilicon gate trench 30 and the width Dg of the polysilicon gate trench 30 is Di > Dg.

[0074] S800: A metal layer is deposited on the surface of the epitaxial layer 20 by using deposition and etching processes. After etching is completed, a source electrode is formed on the surfaces of the first shielding region 50 and the second doped region 23; a gate is formed on part of the polysilicon gate; after the side of the silicon carbide substrate layer 10 away from the epitaxial layer 20 is thinned, a drain electrode is formed by depositing a layer of metal, and finally a silicon carbide device is fabricated.

[0075] Figure 6 Another flowchart of a manufacturing method of a silicon carbide crystal device provided in an embodiment of the present invention; Figures 7a to 7i It is a manufacturing process of a silicon carbide crystal device provided in an embodiment of the invention. Refer to Figure 6 、 Figures 7a to 7i , a manufacturing method of a silicon carbide device provided in an embodiment of the present invention,

[0076] Including: S1: An epitaxial layer 20 is formed on the silicon carbide substrate layer 10. Among them, the silicon carbide substrate layer 10 is a P-type substrate or an N-type substrate, and the epitaxial layer 20 is an N-type epitaxial layer 20.

[0077] In step S1, a CVD (chemical vapor deposition) process can be adopted, methane or propane is used as a material growth gas, and hydrogen is used as a carrier gas to epitaxially grow the epitaxial layer 20. Of course, the epitaxial layer 20 can also be obtained by other methods well known to those skilled in the art, which is not limited herein.

[0078] S2: Sequentially form a current conduction region 21, a first doping region 22, and a second doping region 23 in the epitaxial layer 20 by ion implantation. This method can avoid the concentration deviation of the first doping region 22 caused by the deviation of the ion implantation activation rate, thereby avoiding the deviation of the device threshold voltage. At the same time, since the second doping region 23 can be removed together with the first shielding region 50 by etching, one photolithography process can be saved, and the process flow can be further simplified. In addition, in this step, the impurities implanted in each region are activated by high-temperature annealing.

[0079] S3: Form two second shielding regions 60 of shielding structures spaced apart along the first direction in the epitaxial layer 20;

[0080] In step S3, a dielectric layer or polysilicon can be used as a hard mask, and by using an ion implantation process, semiconductor impurities of a conductive type opposite to that of the silicon carbide substrate are implanted above the epitaxial layer 20 to form the second shielding region 60;

[0081] S4: Form a first shielding region 50 of a shielding structure on the side of the second shielding region 60 facing away from the silicon carbide substrate layer 10. Along the first direction, the length of the first shielding region 50 is less than the length of the second shielding region 60, and the gap between the two first shielding regions 50 is greater than the gap between the two second shielding regions 60. In the projection of the epitaxial layer 20, the second shielding region 60 completely covers the first shielding region 50.

[0082] In step S4, a self-alignment process is adopted. A covering film is deposited on both sides of the ion implantation window, and then the bottom film is removed by etching to achieve the purpose of reducing the implantation window. Through the hard mask, the same doping as the first shielding region 50 is implanted, and two first shielding regions 50 are formed, and the two first shielding regions 50 are symmetrically arranged.

[0083] Among them, the hard mask is a dielectric layer or polysilicon. The difference in length between the first shielding region 50 and the second shielding region 60 is 10 nanometers to 5 micrometers.

[0084] S5: Form a trench gate structure between the two shielding structures. Along the second direction, the depth of the trench gate structure is less than the depth of the shielding structure.

[0085] In step S5, a dielectric layer or polysilicon is used as a hard mask, and combined with an etching process, a polysilicon gate trench 30 is etched at the central position between the two first shielding regions 50. The depth of the obtained polysilicon gate trench 30 is greater than the depth of the first doping region 22, and the depth of the polysilicon gate trench 30 is less than the depth of the first shielding region 50. The bottom wall 31 of the polysilicon gate trench 30 is deeper than the bottom of the first doping region 22, and the depth difference between the two is between 10 nanometers and 5 micrometers.

[0086] After step S5, step S510 is further included: under a non-oxidizing and non-nitriding atmosphere, a high-temperature annealing process is adopted to passivate and round the sharp corners on the bottom wall 31 of the polysilicon gate trench 30.

[0087] Step S511: By using a thermal oxidation or deposition and etching process, a gate dielectric 40 material is produced on the bottom wall 31 of the polysilicon gate trench 30, and the redundant gate dielectric 40 material is etched away to obtain the gate dielectric 40. Among them, the thickness of the gate dielectric 40 provided on the bottom wall 31 of the polysilicon gate trench 30 is Tb, and the thickness of the gate dielectric 40 provided on the side wall 32 of the polysilicon gate trench 30 is Ts, where Tb≥Ts and Tb / Ts is equal to 1 to 3.

[0088] S6: A polysilicon gate is disposed inside the polysilicon gate trench 30, and a covering dielectric layer 70 is formed on the surface of the epitaxial layer 20. The polysilicon layer covers the polysilicon gate trench 30, and the covering dielectric layer 70 covers the epitaxial layer 20 and the covering dielectric layer 70.

[0089] In step S6, by using a deposition and etching process, a layer of polysilicon is deposited on the surface of the epitaxial layer 20, the redundant polysilicon material is etched away, then a covering dielectric layer 70 is deposited, and then part of the covering dielectric layer 70 above the second doping layer is selectively etched away to form a polysilicon gate surrounded by a gate dielectric layer in the polysilicon gate trench 30; the relationship between the width Di of the covering dielectric layer 70 above the polysilicon gate trench 30 and the width Dg of the polysilicon gate trench 30 is Di>Dg.

[0090] S7: By using a deposition and etching process, a metal layer is deposited on the surface of the epitaxial layer 20. After etching is completed, a source electrode is formed on the surfaces of the first shielding region 50 and the second doping region 23; a gate is formed on part of the polysilicon gate; after thinning the side of the silicon carbide substrate layer 10 away from the epitaxial layer 20, a drain electrode is formed by depositing a layer of metal, and finally a silicon carbide device is obtained.

[0091] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. A silicon carbide device, characterized in that, Comprising: A silicon carbide substrate layer; An epitaxial layer disposed on a first surface of the silicon carbide substrate layer; A trench gate structure is provided on a side of the epitaxial layer away from the first surface of the silicon carbide substrate layer. Shielding structures are provided on both sides of the trench gate structure. The shielding structure includes a first shielding region and a second shielding region. The first shielding region extends toward the first surface of the silicon carbide substrate layer. The second shielding region is provided on a side of the first shielding region facing the first surface of the silicon carbide substrate layer. A part of the second shielding region is embedded in the epitaxial layer. Along a first direction, there is a gap between two adjacent second shielding regions. The gap between two adjacent second shielding regions is smaller than the gap between two adjacent first shielding regions; Along the first direction, the length of the first shielding region is less than the length of the second shielding region, and in the projection on the epitaxial layer, the second shielding region entirely covers the first shielding region. Along a second direction, the depth of the trench gate structure is less than the depth of the shielding structure, and the distance from the trench gate structure to the silicon carbide substrate layer is greater than the distance from the first shielding region to the silicon carbide substrate layer; The doping types of the first shielding region and the second shielding region are opposite to that of the epitaxial layer, and the doping concentration of the first shielding region and the second shielding region is between 10 times and 1,000,000 times the doping concentration of the epitaxial layer; Along the first direction, a first doping region and a second doping region are provided between the trench gate structure and the first shielding region. The first doping region and the second doping region are sequentially stacked on a side of the epitaxial layer away from the silicon carbide substrate layer, and current conduction regions are formed between the trench gate structure, the first doping region, the epitaxial layer, two adjacent first shielding regions, and two adjacent second shielding regions; wherein: The doping types of the first doping region and the second doping region are opposite, and the doping type of the first doping region is the same as that of the shielding structure; The trench gate structure includes a polysilicon gate trench and a gate dielectric. The polysilicon gate trench includes a bottom wall and side walls. The thickness of the gate dielectric provided on the bottom wall of the polysilicon gate trench is Tb, and the thickness of the gate dielectric provided on the side walls of the polysilicon gate trench is Ts. Tb > Ts and the ratio of Tb / Ts is greater than 1 and less than or equal to 3.

2. The silicon carbide device according to claim 1, wherein Along the first direction, the difference between the length of the first shielding region and the length of the second shielding region is 10 nanometers to 5 micrometers.

3. The silicon carbide device according to claim 1, wherein Along the second direction, the depth of the shielding structure is L, and along the first direction, the gap between two adjacent first shielding regions is d. The value of L / d is between 0.5 and 20.

4. The silicon carbide device according to claim 1, wherein, Along the second direction, the depth of the polysilicon gate trench is greater than the depth of the first doping region.

5. The silicon carbide device according to claim 1, wherein, The silicon carbide device further includes a covering dielectric layer disposed on a side of the epitaxial layer away from the silicon carbide substrate layer, and the covering dielectric layer covers the polysilicon gate trench.

6. A manufacturing method of a silicon carbide device, characterized in that, Comprising: Forming an epitaxial layer on the silicon carbide substrate layer; A second shielding region and a first shielding region of two shielding structures arranged at intervals in a first direction, a current conduction region, a first doping region, and a second doping region; wherein, a part of the second shielding region is embedded in the epitaxial layer, and the first shielding region is stacked on a side of the second shielding region away from the epitaxial layer; the current conduction region, the first doping region, and the second doping region are located between the two first shielding regions and the two second shielding regions; and the current conduction region is stacked on a side of the epitaxial layer away from the silicon carbide substrate layer, and the first doping region and the second doping region are sequentially stacked on a side of the current conduction layer away from the silicon carbide substrate layer; along the first direction, the length of the first shielding region is less than the length of the second shielding region, and the gap between the two first shielding regions is greater than the gap between the two second shielding regions. In the projection of the epitaxial layer, the second shielding region completely covers the first shielding region; A trench gate structure is formed between the two first doping regions and the two second doping regions on a side of the current conduction region away from the silicon carbide substrate layer. Along a second direction, the depth of the trench gate structure is less than the depth of the shielding structure; the trench gate structure includes a polysilicon gate trench and a gate dielectric. The polysilicon gate trench includes a bottom wall and side walls. The thickness of the gate dielectric provided on the bottom wall of the polysilicon gate trench is Tb, and the thickness of the gate dielectric provided on the side walls of the polysilicon gate trench is Ts, and Tb > Ts and the ratio of Tb / Ts is greater than 1 and less than or equal to 3; Forming a second shielding region and a first shielding region of two shielding structures arranged at intervals in a first direction specifically includes: Using a hard mask and forming the second shielding region by an ion implantation process; Adopting a self-alignment process, depositing a covering film on both sides of the ion implantation window of the second shielding region and etching away the bottom film, and implanting the same doping as the second shielding region through the hard mask to form two first shielding regions.

7. An electronic device, characterized in that, Including the silicon carbide device according to any one of claims 1 to 5.

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