Frequency regulation circuit, voltage converter and switching power supply

Abstract

The present application is applicable to the technical field of switching power supplies, and provides a frequency regulation circuit, a voltage converter and a switching power supply. The frequency regulation circuit includes a reference current module, a current regulation module, a voltage regulation module and a clock generation module. The current regulation module is electrically connected to the reference current module, the voltage regulation module and the clock generation module, respectively. The frequency regulation circuit provided in the embodiment of the present application can convert a current signal into a clock signal when the load is low, and transmit the clock signal to the control module so that the control module outputs a control signal according to the clock signal, thereby reducing the frequency of the control signal. During the entire frequency regulation process, since the regulation current changes continuously, the frequency of the clock signal can be continuously controlled, thereby realizing a smooth transition of the switching power supply from the PWM mode to the PFM mode, reducing the output voltage ripple, and ensuring the stability of the output voltage ripple.

Description

Technical Field

[0001] The present application belongs to the technical field of switching power supplies, and in particular relates to a frequency regulation circuit, a voltage converter and a switching power supply. Background Art

[0002] With the widespread application of wearable electronic devices, switching power supplies are an indispensable part of these devices. They control the output voltage by adjusting the on-time (pulse width) of the switching device, thereby achieving power regulation. When the load current is large, PWM (Pulse Width Modulation) technology can effectively control the power output and maintain high efficiency and stable output voltage. However, when the load current decreases, in order to further improve the efficiency of the switching power supply, the switching power supply will adopt a technology that keeps the pulse width fixed and adjusts the switching frequency, namely PFM (Pulse Frequency Modulation) technology. However, the use of PFM technology will cause the output voltage ripple to increase, thereby affecting the stability and performance of the power supply.

[0003] In order to solve the above problems, the existing technology usually adopts the method of detecting the compensation terminal voltage (COMP) and comparing it with the threshold voltage of PFM. If the voltage on COMP is lower than the threshold voltage, the switching pulse is not allowed to be generated; if the voltage on COMP is higher than the threshold voltage, the switching pulse is restored. The purpose of this technology is to enter the PFM mode when the load current is small to improve efficiency. However, since a large capacitor is usually connected to COMP, the voltage VCOMP on COMP cannot respond quickly to the feedback voltage VFB. This will cause multiple pulses in the switching pulse when entering the PFM mode, resulting in larger output voltage ripple and affecting the performance of the power supply. Therefore, the existing switching power supply has the problem of large output voltage ripple when the load current decreases and the switching power supply enters the PFM mode from the PWM mode. Summary of the invention

[0004] The embodiments of the present application provide a frequency regulation circuit, a voltage converter and a switching power supply, which can solve the problem of large output voltage ripple when the existing switching power supply enters the PFM mode from the PWM mode.

[0005] In a first aspect, an embodiment of the present application provides a frequency adjustment circuit, comprising a reference current module, a current adjustment module, a voltage adjustment module and a clock generation module, wherein the current adjustment module is electrically connected to the reference current module, the voltage adjustment module and the clock generation module respectively, the current adjustment module and the reference current module are both used to be electrically connected to a voltage clamping module, the voltage adjustment module is used to be electrically connected to an oscillator, and the clock generation module is used to be electrically connected to a control module;

[0006] The reference current module is used to generate a reference current; when the resistance of the load is less than a preset resistance, the current regulation module is used to output a regulating current according to the current signal output by the voltage clamp module and the reference current; the voltage regulation module is used to adjust the node voltage according to the pulse signal output by the oscillator and the regulating current, and the node voltage is the voltage of the common end of the current regulation module and the clock generation module; the clock generation module is used to output a clock signal according to the node voltage, and the clock signal is used to instruct the control module to output a control signal, and the frequency of the clock signal is less than the frequency of the pulse signal.

[0007] In a possible implementation manner of the first aspect, the reference current module includes a current source, a first end of the current source is electrically connected to the voltage clamping module and the current regulating module respectively, and a second end of the current source is grounded.

[0008] In a possible implementation of the first aspect, the current regulating module includes a first switch tube and a second switch tube, the gate of the first switch tube is electrically connected to the drain of the first switch tube, the gate of the second switch tube, the voltage clamping module and the reference current module, the source of the first switch tube and the gate of the second switch tube are both used to be electrically connected to a first power supply, and the drain of the second switch tube is electrically connected to the voltage regulating module and the clock generating module, respectively.

[0009] In a possible implementation manner of the first aspect, the voltage regulation module includes a switch unit and an energy storage unit, the control end of the switch unit is used to be electrically connected to the oscillator, the first end of the switch unit is electrically connected to the first end of the energy storage unit, the current regulation module and the clock generation module, and the second end of the switch unit and the second end of the energy storage unit are both grounded;

[0010] When the switch unit is turned off according to the pulse signal, the energy storage unit is used to store energy; when the switch unit is turned on according to the pulse signal, the energy storage unit is used to release energy.

[0011] In a possible implementation of the first aspect, the switching unit includes a third switching tube, a gate of the third switching tube is used to be electrically connected to the oscillator, a drain of the third switching tube is respectively electrically connected to the energy storage unit, the current regulation module and the clock generation module, and a source of the third switching tube is grounded.

[0012] In a possible implementation manner of the first aspect, the energy storage unit includes a first capacitor, a first end of the first capacitor is electrically connected to the switch unit, the current regulation module and the clock generation module respectively, and a second end of the first capacitor is grounded.

[0013] In a possible implementation manner of the first aspect, the clock generation module includes an inverter, an input end of the inverter is electrically connected to the current regulation module and the voltage regulation module respectively, and an output end of the inverter is used to be electrically connected to the control module.

[0014] In a second aspect, an embodiment of the present application provides a voltage converter, comprising a voltage clamping module, a control module, an operational amplifier module, a voltage conversion module, and the frequency adjustment circuit described in any one of the first aspects, wherein the voltage clamping module is electrically connected to the frequency adjustment circuit, the operational amplifier module, and the control module, respectively, the control module is electrically connected to the frequency adjustment circuit and the voltage conversion module, and the voltage conversion module is electrically connected to the operational amplifier module;

[0015] The operational amplifier module is used to output a reference voltage based on a feedback voltage and a reference voltage, the voltage clamp module is used to output a current signal based on the reference voltage and a first preset voltage, the frequency adjustment circuit is used to output a clock signal based on the current signal and a pulse signal, the control module is used to output a control signal based on the clock signal, the voltage conversion module is used to output a target voltage based on the control signal, and the voltage conversion module is also used to divide the target voltage and output a feedback voltage to the operational amplifier module.

[0016] In a possible implementation of the second aspect, the voltage clamping module includes an error amplifier and a fourth switch tube, the first input end of the error amplifier is used to receive the first preset voltage, the second input end of the error amplifier is electrically connected to the source of the fourth switch tube and the operational amplifier module respectively, the output end of the error amplifier is electrically connected to the gate of the fourth switch tube, and the source of the fourth switch tube is used to be electrically connected to the second power supply.

[0017] In a third aspect, an embodiment of the present application provides a switching power supply, comprising the voltage converter described in any one of the second aspects.

[0018] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0019] The frequency regulating circuit provided in the embodiment of the present application includes a reference current module, a current regulating module, a voltage regulating module and a clock generating module. When the resistance of the load is less than the preset resistance, that is, when the load current is small, the voltage clamping module can output a current signal, and the current regulating module outputs a regulating current according to the current signal output by the voltage clamping module and the reference current output by the reference current module. The oscillator can output a pulse signal, the voltage regulating module adjusts the node voltage according to the pulse signal and the regulating current, and the clock generating module is used to output a clock signal according to the node voltage, and the clock signal is used to instruct the control module to output a control signal. It can be seen from this that the frequency regulating circuit provided in the embodiment of the present application, as the resistance of the load decreases, when the resistance of the load is less than the preset resistance, that is, when the load is low, the current signal output by the voltage clamping module can be converted into a clock signal, and the clock signal is transmitted to the control module, so that the control module outputs a control signal according to the clock signal, thereby reducing the frequency of the control signal. Since the clock signal output by the frequency adjustment circuit in the present application is output when the load resistance is less than the preset resistance, the frequency of the clock signal is lower than the frequency of the pulse signal, that is, the frequency of the clock signal is lower than the frequency of the original clock signal transmitted to the control module, and the clock signal output by the frequency adjustment circuit can shield the original clock signal, thereby reducing the frequency of the control signal output by the control module. During the entire frequency adjustment process, since the adjustment current continuously changes, the frequency of the clock signal can be continuously controlled, thereby realizing a smooth transition of the switching power supply from the PWM mode to the PFM mode, reducing the output voltage ripple, ensuring the stability of the output voltage ripple, and solving the problem of large output voltage ripple when the existing switching power supply enters the PFM mode from the PWM mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0021] Figure 1 is a principle block diagram of a frequency adjustment circuit provided in an embodiment of the present application;

[0022] Figure 2 is a circuit connection diagram of a frequency adjustment circuit provided in an embodiment of the present application;

[0023] Figure 3 This is a waveform diagram of a switching power supply provided in an embodiment of the present application working in a PWM mode;

[0024] Figure 4It is a waveform diagram of a switching power supply provided by an embodiment of the present application transitioning from a PWM mode to a PFM mode;

[0025] Figure 5 is a principle block diagram of a voltage converter provided by an embodiment of the present application;

[0026] Figure 6 is a circuit connection diagram of a voltage converter provided in one embodiment of the present application;

[0027] Figure 7 Schematic diagram of circuit connection of a voltage clamping module provided in one embodiment of the present application.

[0028] In the figure, 10, frequency adjustment circuit; 101, reference current module; 102, current adjustment module; 103, voltage adjustment module; 1031, switch unit; 1032, energy storage unit; 104, clock generation module; 20, voltage clamping module; 30, oscillator; 40, control module; 50, operational amplifier module; 60, voltage conversion module. DETAILED DESCRIPTION

[0029] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0030] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0031] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0032] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0033] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0034] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0035] Existing technologies usually use a method of detecting the compensation terminal voltage (COMP) and comparing it with the threshold voltage of PFM. If the voltage on COMP is lower than the threshold voltage, the switching pulse is not allowed to be generated; if the voltage on COMP is higher than the threshold voltage, the switching pulse is restored. The purpose of this technology is to enter the PFM mode when the load current is small to improve efficiency. However, since a large capacitor is usually connected to COMP, the voltage VCOMP on COMP cannot respond quickly to the feedback voltage VFB. This will cause multiple pulses in the switching pulse when entering the PFM mode, resulting in larger output voltage ripple and affecting the performance of the power supply. Therefore, the existing switching power supply has the problem of large output voltage ripple when the load current decreases and the switching power supply enters the PFM mode from the PWM mode.

[0036] Based on the above problems, the frequency adjustment circuit provided by the embodiment of the present application includes a reference current module, a current adjustment module, a voltage adjustment module and a clock generation module. When the resistance of the load is less than the preset resistance, that is, when the load current is small, the voltage clamping module can output a current signal, and the current adjustment module outputs a regulated current according to the current signal output by the voltage clamping module and the reference current output by the reference current module. The oscillator can output a pulse signal, the voltage adjustment module adjusts the node voltage according to the pulse signal and the regulated current, the clock generation module is used to output a clock signal according to the node voltage, and the clock signal is used to instruct the control module to output a control signal. It can be seen from this that the frequency adjustment circuit provided by the embodiment of the present application, as the resistance of the load decreases, when the resistance of the load is less than the preset resistance, that is, when the load is low, the current signal output by the voltage clamping module can be converted into a clock signal, and the clock signal is transmitted to the control module, so that the control module outputs a control signal according to the clock signal, thereby reducing the frequency of the control signal. Since the clock signal output by the frequency adjustment circuit in the present application is output when the load resistance is less than the preset resistance, the frequency of the clock signal is lower than the frequency of the pulse signal, that is, the frequency of the clock signal is lower than the frequency of the original clock signal transmitted to the control module, and the clock signal output by the frequency adjustment circuit can shield the original clock signal, thereby reducing the frequency of the control signal output by the control module. During the entire frequency adjustment process, since the adjustment current continuously changes, the frequency of the clock signal can be continuously controlled, thereby realizing a smooth transition of the switching power supply from the PWM mode to the PFM mode, reducing the output voltage ripple, ensuring the stability of the output voltage ripple, and solving the problem of large output voltage ripple when the existing switching power supply enters the PFM mode from the PWM mode.

[0037] In order to illustrate the technical solution described in this application, a specific embodiment is provided below for illustration.

[0038] Figure 1 FIG. 1 shows a block diagram of a frequency adjustment circuit 10 provided in an embodiment of the present application. Figure 1 As shown, the frequency adjustment circuit 10 includes a reference current module 101, a current adjustment module 102, a voltage adjustment module 103 and a clock generation module 104. The current adjustment module 102 is electrically connected to the reference current module 101, the voltage adjustment module 103 and the clock generation module 104 respectively, the current adjustment module 102 and the reference current module 101 are both used to be electrically connected to the voltage clamping module 20, the voltage adjustment module 103 is used to be electrically connected to the oscillator 30, and the clock generation module 104 is used to be electrically connected to the control module 40.

[0039] Specifically, the reference current module 101 is used to generate a reference current. When the resistance of the load is less than the preset resistance, that is, when the load current Iload is small, the voltage clamp module 20 can output a current signal, and the current regulating module 102 outputs a regulating current according to the current signal output by the voltage clamp module 20 and the reference current output by the reference current module 101. The oscillator 30 can output a pulse signal, the voltage regulating module 103 regulates the node voltage according to the pulse signal and the regulating current, and the clock generating module 104 is used to output a clock signal according to the node voltage, and the clock signal is used to instruct the control module 40 to output a control signal. It can be seen from this that the frequency regulating circuit 10 provided in the embodiment of the present application, as the resistance of the load decreases, when the resistance of the load is less than the preset resistance, that is, when the load is low, the current signal output by the voltage clamp module 20 can be converted into a clock signal, and the clock signal is transmitted to the control module 40, so that the control module 40 outputs a control signal according to the clock signal, thereby reducing the frequency of the control signal. Since the clock signal output by the frequency adjustment circuit 10 in the present application is output when the load resistance is less than the preset resistance, the frequency of the clock signal is lower than the frequency of the pulse signal, that is, the frequency of the clock signal is lower than the frequency of the original clock signal transmitted to the control module 40, and the clock signal output by the frequency adjustment circuit 10 can shield the original clock signal, thereby reducing the frequency of the control signal output by the control module 40. During the entire frequency adjustment process, since the adjustment current continuously changes, the frequency of the clock signal can be continuously controlled, thereby realizing a smooth transition of the switching power supply from the PWM mode to the PFM mode, reducing the output voltage ripple, ensuring the stability of the output voltage ripple, and solving the problem of large output voltage ripple when the existing switching power supply enters the PFM mode from the PWM mode.

[0040] It should be noted that if the resistance of the load is greater than or equal to the preset resistance, that is, the load current Iload is large, at this time, the switching power supply operates in PWM mode, the voltage clamping module 20 cannot output the current signal, and the frequency adjustment circuit 10 does not work. It can be seen that if the resistance of the load is greater than or equal to the preset resistance, the frequency adjustment circuit 10 does not work, and the frequency of the clock signal is higher than or equal to the frequency of the original clock signal transmitted to the control module 40. Therefore, the clock signal will not shield the original clock signal, that is, it will not change the frequency of the control signal output by the control module 40.

[0041] It should be noted that the frequency adjustment circuit 10 provided in the embodiment of the present application outputs a clock signal when the load resistance is less than the preset resistance, shields the original clock signal, and thus reduces the frequency of the control signal output by the control module 40. Such a design can be applied to BOOST, BUCK, BUCK-BOOST and other circuits. The embodiment of the present application takes the BUCK step-down circuit as an example to explain in detail the working principle of the frequency adjustment circuit 10.

[0042] In one embodiment of the present application, Figure 2 As shown, the reference current module 101 includes a current source Ib, a first end of the current source Ib is electrically connected to the voltage clamping module 20 and the current regulating module 102 respectively, and a second end of the current source Ib is grounded.

[0043] Specifically, the current source Ib is a constant current output, which is used to generate a reference current. The reference current is the current signal k*i output by the voltage clamp module 20. clampl and the sum of the current flowing through the current regulating module 102. At the same time, setting the current source Ib can prevent the current regulating module 102 from being directly grounded, and prevent the current flowing through the components in the current regulating module 102 from being uncontrolled due to excessive current, which may damage the components.

[0044] It should be noted that the current signal k*i output by the voltage clamp module 20 clampl It is k times of the current iclampl output by the voltage clamping module 20 , where k is a positive number.

[0045] In one embodiment of the present application, Figure 2 As shown, the current regulating module 102 includes a first switch tube M1 and a second switch tube M2. The gate of the first switch tube M1 is electrically connected to the drain of the first switch tube M1, the gate of the second switch tube M2, the voltage clamping module 20 and the reference current module 101 respectively. The source of the first switch tube M1 and the gate of the second switch tube M2 are both used to be electrically connected to the first power supply VCC1. The drain of the second switch tube M2 is electrically connected to the voltage regulating module 103 and the clock generating module 104 respectively.

[0046] Specifically, the first switch tube M1 and the second switch tube M2 are both used as switch devices, and the gate of the first switch tube M1 and the gate of the second switch tube M2 are both used to receive the current signal k*i output by the voltage clamping module 20. clampl , and according to the current signal k*i clampl The first power supply VCC1 and the voltage regulating module 103 are turned on, thereby conducting, and the regulating current can be output to the voltage regulating module 103. At the same time, the gate of the first switch tube M1 is connected to the gate of the second switch tube M2, and the source of the first switch tube M1 is connected to the source of the second switch tube M2. Therefore, the first switch tube M1 and the second switch tube M2 form a current mirror, that is, the current flowing through the first switch tube M1 is equal to the current flowing through the second switch tube M2. According to the reference current and the current signal k*i output by the voltage clamp module 20 clampl The current flowing through the second switch tube M2 can be obtained, that is, the current flowing through the second switch tube M2 is the reference current and the current signal k*i clampl difference.

[0047] For example, the designer can select the type of the first switch tube M1 and the second switch tube M2 according to the actual situation, that is, both can use fully controlled power devices such as metal oxide field effect transistors or insulated gate bipolar transistors. For example, the first switch tube M1 and the second switch tube M2 can be selected as PMOS tubes.

[0048] In one embodiment of the present application, Figure 2 As shown, the voltage regulation module 103 includes a switch unit 1031 and an energy storage unit 1032, the control end of the switch unit 1031 is used to be electrically connected to the oscillator 30, the first end of the switch unit 1031 is electrically connected to the first end of the energy storage unit 1032, the current regulation module 102 and the clock generation module 104, and the second end of the switch unit 1031 and the second end of the energy storage unit 1032 are both grounded.

[0049] Specifically, the switch unit 1031 is used to turn on or off according to the pulse signal clk. When the switch unit 1031 is turned off according to the pulse signal clk (low level), the energy storage unit 1032 is used to store energy, and the node voltage vct gradually increases until the energy storage unit 1032 no longer stores energy. When the switch unit 1031 is turned on according to the pulse signal clk (high level), the energy storage unit 1032 is used to release energy, and the node voltage vct is pulled down. Through the synergistic effect of the switch unit 1031 and the energy storage unit 1032, the node voltage vct is regulated.

[0050] In one embodiment of the present application, Figure 2 As shown, the switch unit 1031 includes a third switch tube M3, the gate of the third switch tube M3 is used to be electrically connected to the oscillator 30, the drain of the third switch tube M3 is electrically connected to the energy storage unit 1032, the current regulation module 102 and the clock generation module 104 respectively, and the source of the third switch tube M3 is grounded.

[0051] Specifically, the third switch tube M3 is used as a switch device, and the gate of the third switch tube M3 is used to receive the pulse signal clk output by the oscillator 30. It can be turned on according to the pulse signal clk (high level), so that the node and the ground are connected, and the node voltage vct is pulled down. The third switch tube M3 can also be turned off according to the pulse signal clk (low level), so that the node and the ground are disconnected, and the energy storage unit 1032 stores energy, so that the node voltage vct increases.

[0052] It should be noted that when the third switch tube M3 is turned on, the energy storage unit 1032 can release energy through the third switch tube M3.

[0053] For example, the designer can select the type of the third switch tube M3 according to the actual situation, that is, a fully controlled power device such as a metal oxide field effect transistor or an insulated gate bipolar transistor can be used. For example, the third switch tube M3 can be selected as an NMOS tube.

[0054] In one embodiment of the present application, Figure 2 As shown, the energy storage unit 1032 includes a first capacitor C1, a first end of the first capacitor C1 is electrically connected to the switch unit 1031, the current regulation module 102 and the clock generation module 104 respectively, and a second end of the first capacitor C1 is grounded.

[0055] Specifically, the first capacitor C1, as an energy storage device, can store and release energy by charging and discharging. When the third switch tube M3 can be turned off according to the pulse signal clk, the first capacitor C1 is used to store energy, and the node voltage vct gradually increases until the first capacitor C1 is fully charged. The switch unit 1031 can also be turned on according to the pulse signal clk, and the first capacitor C1 is used to release energy, and the node voltage vct is pulled down. Through the synergistic effect of the third switch tube M3 and the first capacitor C1, the node voltage vct is regulated.

[0056] In one embodiment of the present application, Figure 2 As shown, the clock generating module 104 includes an inverter U1 , the input end of the inverter U1 is electrically connected to the current regulating module 102 and the voltage regulating module 103 , respectively, and the output end of the inverter U1 is used to be electrically connected to the control module 40 .

[0057] Specifically, the inverter U1 is used for flipping the clock signal clk-blk outputted from the output end of the inverter U1 from a high level to a low level when the node voltage vct gradually increases and the voltage is greater than the flip threshold of the inverter U1.

[0058] Combine the following Figure 3 and Figure 4 The specific working process of the frequency adjustment circuit 10 is described in detail.

[0059] Figure 3 Schematic diagram of the waveform of the switching power supply working in PWM mode. Among them, clk is the pulse signal output by the oscillator 30, which is also the original clock signal, vct is the node voltage, clk-blk is the clock signal, and sw is the voltage of the common end of the upper tube and the lower tube in the voltage conversion module 60. blkis the masking time, i.e., the pulse width of the clock signal clk-blk. Since the switching power supply operates in PWM mode, the voltage clamping module 20 cannot output a current signal, and the frequency adjustment circuit 10 does not work. The frequency of the clock signal clk-blk is equal to the frequency of the original clock signal clk transmitted to the control module 40. Therefore, the clock signal clk-blk will not mask the original clock signal clk, i.e., it will not change the frequency of the control signal output by the control module 40, and the frequency of the sw voltage will not change. Specifically, due to the masking time t blk for:

[0060]

[0061] Among them, k*i clampl is the current signal output by the voltage clamp module 20, I b is the reference current output by the current source Ib, C1 is the capacitance value of the first capacitor C1, V R is the flip voltage of inverter U1.

[0062] When the switching power supply operates in PWM mode, i clampl =0, shielding time t blk The masking time is smaller than the frequency of the oscillator 30 , that is, the masking time does not affect the operation of the external oscillator 30 . At this time, the frequency adjustment circuit 10 does not work. The frequency of the clock signal clk-blk is equal to the frequency of the original clock signal clk transmitted to the control module 40 .

[0063] like Figure 4 As shown, as the load resistance gradually decreases, that is, the load current Iload gradually decreases, the current signal k*i output by the voltage clamping module 20 clampl The regulating current output by the current regulating module 102 in the frequency regulating circuit 10 gradually decreases, so that the charging speed of the first capacitor C1 in the voltage regulating module 103 slows down and the charging time is prolonged, thereby causing the slope of the node voltage vct ramp wave to become smaller, and it takes a longer time to reach the flip voltage of the inverter U1, thereby increasing the pulse width of the clock signal clk-blk, that is, the shielding time t blk As the load current Iload continues to decrease, the shielding time t blk Will continue to increase when the shielding time t blkWhen the frequency is greater than clk, the clock signal clk-blk output by the frequency adjustment circuit 10 can shield the original clock signal clk, thereby reducing the frequency of the control signal output by the control module 40, and the frequency of the sw voltage will also be reduced. During the entire frequency adjustment process, due to the continuous change of the current signal, the frequency of the clock signal clk-blk can be continuously controlled, thereby realizing a smooth transition of the switching power supply from the PWM mode to the PFM mode. At the same time, since the present application adopts a full analog change, only one SW pulse is required to achieve the transition during the transition process, reducing the output voltage ripple, ensuring the stability of the output voltage ripple, and solving the problem of large output voltage ripple when the existing switching power supply enters the PFM mode from the PWM mode.

[0064] It should be noted that when Ib<k*i clampl When Ib≥k*i clampl , the oscillator 30 starts working again.

[0065] In one embodiment of the present application, Figure 5 As shown, the voltage converter includes a voltage clamping module 20, a control module 40, an operational amplifier module 50, a voltage conversion module 60 and the above-mentioned frequency adjustment circuit 10, the voltage clamping module 20 is electrically connected to the frequency adjustment circuit 10, the operational amplifier module 50 and the control module 40 respectively, the control module 40 is electrically connected to the frequency adjustment circuit 10 and the voltage conversion module 60 respectively, and the voltage conversion module 60 is electrically connected to the operational amplifier module 50.

[0066] Specifically, the operational amplifier module 50 is used to output a reference voltage VCOMP according to the feedback voltage VFB and the reference voltage VREF, the voltage clamp module 20 is used to output a current signal according to the reference voltage VCOMP and the first preset voltage Vclampl, and the frequency adjustment circuit 10 is used to output a current signal according to the current signal k*i clampl The control module 40 outputs a clock signal clk-blk according to the pulse signal clk, and the voltage conversion module 60 is used to output a target voltage VOUT according to the control signal. The voltage conversion module 60 is also used to divide the target voltage VOUT and output a feedback voltage VFB to the operational amplifier module 50. When the switching power supply operates in the PWM mode, the reference voltage VCOMP output by the operational amplifier module 50 is clamped between the first preset voltage Vclampl and the second preset voltage Vclamph. At this time, the current signal k*i clamplThe frequency adjustment circuit 10 does not work, and will not change the frequency of the control signal output by the control module 40, and the frequency of the sw voltage in the voltage conversion module 60 will not change. As the load current Iload gradually decreases, when the switching power supply enters the PFM mode from the PWM mode, the reference voltage VCOMP output by the operational amplifier module 50 is equal to the first preset voltage Vclampl, and the voltage clamping module 20 can output the current signal k*i clampl The frequency adjustment circuit 10 is based on the current signal k*i clampl The clock signal clk-blk is outputted to reduce the frequency of the control signal outputted by the control module 40 , and the frequency of the sw voltage in the voltage conversion module 60 will also be reduced accordingly.

[0067] It should be noted that the first preset voltage Vclampl may be a low threshold, and the second preset voltage Vclamph may be a high threshold. For example, the first preset voltage Vclampl may be 0.7V, and the second preset voltage Vclamph may be 1.5V.

[0068] In one embodiment of the present application, Figure 6 As shown, the voltage conversion module 60 includes an upper tube MNU, a lower tube MND, an inductor L, a capacitor C and a feedback unit, wherein the common end of the upper tube MNU and the lower tube MND is a SW node. The operational amplifier module 50 includes an operational amplifier U3, and the operational amplifier U3 outputs a reference voltage VCOMP according to the feedback voltage VFB and the reference voltage VREF. When the switching power supply enters the PFM mode from the PWM mode, the feedback voltage VFB is greater than the reference voltage VREF, thereby reducing the reference voltage VCOMP, that is, the reference voltage VCOMP can be reduced to be equal to the first preset voltage Vclampl, and the voltage clamping module 20 can output the current signal k*i clampl The frequency adjustment circuit 10 is based on the current signal k*i clampl The clock signal clk-blk is outputted to change the frequency of the control signal outputted by the control module 40 , thereby changing the frequency of the voltage at the SW node.

[0069] It should be noted that a loop compensation module is provided at the output end of the operational amplifier U3 to ensure the stability and reliability of the target voltage VOUT output by the switching power supply.

[0070] In one embodiment of the present application, Figure 7As shown, the voltage clamping module 20 includes an error amplifier U2 and a fourth switch tube M4, the first input end of the error amplifier U2 is used to receive a first preset voltage Vclampl, the second input end of the error amplifier U2 is electrically connected to the source of the fourth switch tube M4 and the operational amplifier module 50 respectively, the output end of the error amplifier U2 is electrically connected to the gate of the fourth switch tube M4, and the source of the fourth switch tube M4 is used to be electrically connected to the second power supply VCC2.

[0071] Specifically, the error amplifier U2 is used to compare the first preset voltage Vclampl with the reference voltage VCOMP and output the comparison voltage. The fourth switch tube M4 is turned on or off according to the comparison voltage. When the switching power supply operates in PWM mode, the reference voltage VCOMP output by the operational amplifier module 50 is clamped between the first preset voltage Vclampl and the second preset voltage Vclamph, that is, the reference voltage VCOMP is greater than the first preset voltage Vclampl, the fourth switch tube M4 is in the off state, and the current iclampl flowing through the fourth switch tube M4 is 0. The frequency adjustment circuit 10 does not work, and will not change the frequency of the control signal output by the control module 40, and the frequency of the sw voltage in the voltage conversion module 60 will not change. As the load current Iload gradually decreases, when the switching power supply enters the PFM mode from the PWM mode, the reference voltage VCOMP output by the operational amplifier module 50 is equal to the first preset voltage Vclampl, the fourth switch tube M4 is in the on state, the fourth switch tube M4 generates a current iclampl, and the frequency adjustment circuit 10 outputs the clock signal clk-blk according to the current signal k*iclampl, thereby changing the frequency of the control signal output by the control module 40, and the frequency of the sw voltage in the voltage conversion module 60 will also change accordingly.

[0072] It should be noted that when the switching power supply enters the PFM mode from the PWM mode, the current i generated by the fourth switch tube M4 clampl for:

[0073]

[0074] Among them, G m is the transconductance of the error amplifier U2, VFB is the feedback voltage, and VREF is the reference voltage.

[0075] Combine this formula with the shielding time t blk Combining the formula, we can get:

[0076]

[0077] It can be seen from this that the adjustment range of the feedback voltage VFB can be changed by setting the value of k.

[0078] The present application also discloses a switching power supply, including the above-mentioned voltage converter. The switching power supply adopts the above-mentioned voltage converter to continuously control the frequency of the clock signal, thereby realizing a smooth transition of the switching power supply from the PWM mode to the PFM mode, reducing the output voltage ripple, ensuring the stability of the output voltage ripple, and solving the problem of large output voltage ripple when the existing switching power supply enters the PFM mode from the PWM mode.

[0079] Since the processing and functions implemented by the switching power supply in this embodiment basically correspond to the embodiments, principles and examples of the aforementioned frequency regulation circuit, for the details not fully described in this embodiment, please refer to the relevant descriptions in the aforementioned embodiments, and no further elaboration will be made here.

[0080] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A frequency adjustment circuit, characterized in that: It includes a reference current module, a current regulating module, a voltage regulating module and a clock generating module, wherein the current regulating module is electrically connected to the reference current module, the voltage regulating module and the clock generating module respectively, the current regulating module and the reference current module are both used to be electrically connected to a voltage clamping module, the voltage regulating module is used to be electrically connected to an oscillator, and the clock generating module is used to be electrically connected to a control module; The reference current module is used to generate a reference current; when the resistance of the load is less than a preset resistance, the current regulating module is used to output a regulating current according to the current signal output by the voltage clamp module and the reference current; the voltage regulating module is used to adjust the node voltage according to the pulse signal output by the oscillator and the regulating current, and the node voltage is the voltage of the common end of the current regulating module and the clock generating module; the clock generating module is used to output a clock signal according to the node voltage, and the clock signal is used to instruct the control module to output a control signal, and the frequency of the clock signal is less than the frequency of the pulse signal; When the resistance of the load is greater than or equal to the preset resistance, the current signal output by the voltage clamping module is zero, and the current regulating module does not output the regulating current; The reference current module comprises a current source, a first end of the current source is electrically connected to the voltage clamping module and the current regulating module respectively, and a second end of the current source is grounded; The reference current is the sum of the current signal and the current flowing through the current regulating module; The current regulating module includes a first switch tube and a second switch tube, the gate of the first switch tube is electrically connected to the drain of the first switch tube, the gate of the second switch tube, the voltage clamping module and the reference current module respectively, the source of the first switch tube and the gate of the second switch tube are both used to be electrically connected to a first power supply, and the drain of the second switch tube is electrically connected to the voltage regulating module and the clock generating module respectively.

2. The frequency adjustment circuit according to claim 1, characterized in that: The voltage regulating module comprises a switch unit and an energy storage unit, wherein the control end of the switch unit is used to be electrically connected to the oscillator, the first end of the switch unit is electrically connected to the first end of the energy storage unit, the current regulating module and the clock generating module, and the second end of the switch unit and the second end of the energy storage unit are both grounded; When the switch unit is turned off according to the pulse signal, the energy storage unit is used to store energy; when the switch unit is turned on according to the pulse signal, the energy storage unit is used to release energy.

3. The frequency adjustment circuit according to claim 2, characterized in that: The switch unit includes a third switch tube, a gate of the third switch tube is used to be electrically connected to the oscillator, a drain of the third switch tube is electrically connected to the energy storage unit, the current regulation module and the clock generation module respectively, and a source of the third switch tube is grounded.

4. The frequency adjustment circuit according to claim 2, characterized in that: The energy storage unit includes a first capacitor, a first end of the first capacitor is electrically connected to the switch unit, the current regulating module and the clock generating module respectively, and a second end of the first capacitor is grounded.

5. The frequency adjustment circuit according to claim 1, characterized in that: The clock generation module comprises an inverter, the input end of the inverter is electrically connected to the current regulation module and the voltage regulation module respectively, and the output end of the inverter is used to be electrically connected to the control module.

6. A voltage converter, characterized in that: It comprises a voltage clamping module, a control module, an operational amplifier module, a voltage conversion module and the frequency adjustment circuit according to any one of claims 1 to 5, wherein the voltage clamping module is electrically connected to the frequency adjustment circuit, the operational amplifier module and the control module respectively, the control module is electrically connected to the frequency adjustment circuit and the voltage conversion module respectively, and the voltage conversion module is electrically connected to the operational amplifier module; The operational amplifier module is used to output a reference voltage based on a feedback voltage and a reference voltage, the voltage clamp module is used to output a current signal based on the reference voltage and a first preset voltage, the frequency adjustment circuit is used to output a clock signal based on the current signal and a pulse signal, the control module is used to output a control signal based on the clock signal, the voltage conversion module is used to output a target voltage based on the control signal, and the voltage conversion module is also used to divide the target voltage and output a feedback voltage to the operational amplifier module.

7. The voltage converter according to claim 6, characterized in that: The voltage clamping module includes an error amplifier and a fourth switch tube, the first input end of the error amplifier is used to receive the first preset voltage, the second input end of the error amplifier is electrically connected to the source of the fourth switch tube and the operational amplifier module respectively, the output end of the error amplifier is electrically connected to the gate of the fourth switch tube, and the source of the fourth switch tube is used to be electrically connected to the second power supply.

8. A switching power supply, characterized in that: Comprising the voltage converter as claimed in claim 6 or 7.

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