Gate voltage bootstrap switching circuit

Abstract

The application relates to a gate voltage self-boosting switch circuit, which comprises a clock circuit, a self-boosting path and a reset circuit; the clock circuit comprises MOS tubes MP3 and MN3, wherein the gates of MP3 and MN3 are connected with CLKS, the drains of MP3 and MN3 are connected with CLKS, the source and substrate of MP3 are both connected with VDD, and the source and substrate of MN3 are both connected with the ground; the reset circuit comprises MOS tubes MP1, MP2, MN2, MN6, MP4 and MN4, wherein the source and substrate of MP1 are both connected with VDD, the gate is connected with CLKS, and the drain is connected with VC; the source of MP2 is connected with VDD, the drain and substrate are both connected with PA, and the gate is connected with VG; the source and substrate of MN2 are both connected with the ground, the drain is connected with PB, and the gate is connected with CLKS; the gates of MP4 and MN4 are connected with CLKS, the drain is connected with the source of MOS tube MN6, the source and substrate of MP4 are both connected with VDD, the source and substrate of MN4 are both connected with the ground, the gate of MOS tube MN6 is connected with VDD, the drain is connected with VG, and the substrate is connected with the ground. The application can improve the establishment speed of the fast self-boosting path.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of analog integrated circuits, in particular to a gate voltage bootstrap switch circuit. BACKGROUND

[0002] The gate voltage bootstrap switch is one of the most important analog circuit modules in analog integrated circuits, and is widely used in AD / DA conversion systems, automotive electronics, biomedical and other fields. As an indispensable component module of the analog to digital converter (ADC), the speed and linearity of the gate voltage bootstrap switch will limit the overall performance of the ADC, therefore, it is particularly important to improve the sampling speed and linearity.

[0003] The traditional gate voltage bootstrap switch has the following problems: first, when the input signal VIN is large, the bootstrap path establishment speed is limited by the MOS tube MN0; second, when the CLKSB falls, the working state of the MS tube changes from on to off, and the charge related to the input signal VIN existing in the channel will be distributed according to the impedance size on the left and right sides of the MS tube, and the charge injected into the sampling capacitor Cs will affect the accuracy of the holding stage.

[0004] In summary, to adapt to the problems in the prior art that the bootstrap path establishment speed is limited by the MOS tube MN0, and the charge injected into the sampling capacitor Cs will affect the accuracy of the holding stage, the present applicant makes corresponding exploration for solving the problem. SUMMARY

[0005] The purpose of the present application is to solve the above-mentioned problems and provide a gate voltage bootstrap switch circuit.

[0006] In order to achieve the purpose of the present application, the present application adopts the following technical solutions:

[0007] A gate voltage bootstrap switch circuit is proposed to adapt to the purpose of the present application, which comprises a clock circuit, a bootstrap path and a reset circuit.

[0008] The clock circuit comprises a MOS tube MP3 and a MOS tube MN3, wherein the gate of the MOS tube MP3 and the MOS tube MN3 is connected to a first control signal CLKSB, the drain of the MOS tube MP3 and the MOS tube MN3 is connected to a second control signal CLKSB, the source and substrate of the MOS tube MP3 are connected to a power supply voltage VDD, and the source and substrate of the MOS tube MN3 are connected to ground.

[0009] The bootstrap path comprises a MOS transistor MS, a MOS transistor MN0, a MOS transistor MN6, a MOS transistor MP6, a bootstrap capacitor C1, a MOS transistor MP0, a MOS transistor MP5, a MOS transistor MN1 and a MOS transistor MN5, wherein the source electrode of the MOS transistor MS is connected to an input signal VIN, the gate electrode is connected to a node VG, the drain electrode is connected to an output signal VOUT, and the substrate is connected to PB; the source electrode and the substrate of the MOS transistor MN0 and the MOS transistor MN6 are both connected to a node PB, and the drain electrode is connected to the input signal VIN; the gate electrode of the MOS transistor MN0 is connected to the node VG, and the gate electrode of the MOS transistor MN6 is connected to a first control signal CLKS; the gate electrode of the MOS transistor MP6 is connected to a second control signal CLKSB, the drain electrode is connected to the input signal VIN, the source electrode is connected to the node PB, and the substrate is connected to a power supply voltage VDD; the upper plate of the bootstrap capacitor C1 is connected to a node PA, and the lower plate is connected to the node PB; the source electrode and the substrate of the MOS transistor MP0 and the MOS transistor MP5 are both connected to the node PA, and the drain electrode is connected to the node VG; the gate electrode of the MOS transistor MP0 is connected to a node VC, and the gate electrode of the MOS transistor MP5 is connected to the second control signal CLKSB; the source electrode and the substrate of the MOS transistor MN1 and the MOS transistor MN5 are both connected to the node PB, and the drain electrode is connected to the node VC; the gate electrode of the MOS transistor MN1 is connected to the first control signal CLKS, and the gate electrode of the MOS transistor MN5 is connected to the node VG.

[0010] The reset circuit comprises a MOS transistor MP1, a MOS transistor MP2, a MOS transistor MN2, a MOS transistor MN6, a MOS transistor MP4 and a MOS transistor MN4, wherein the source electrode and the substrate of the MOS transistor MP1 are both connected to a power supply voltage VDD, the gate electrode is connected to a first control signal CLKS, and the drain electrode is connected to a node VC; the source electrode of the MOS transistor MP2 is connected to the power supply voltage VDD, the drain electrode and the substrate are both connected to a node PA, and the gate electrode is connected to a node VG; the source electrode and the substrate of the MOS transistor MN2 are both connected to ground, the drain electrode is connected to the node PB, and the gate electrode is connected to a second control signal CLKSB; the gate electrode of the MOS transistor MP4 and the MOS transistor MN4 is connected to the second control signal CLKSB, the drain electrode is connected to the source electrode of the MOS transistor MN6, the source electrode and the substrate of the MOS transistor MP4 are both connected to the power supply voltage VDD, the source electrode and the substrate of the MOS transistor MN4 are both connected to ground, the gate electrode of the MOS transistor MN6 is connected to the power supply voltage VDD, the drain electrode is connected to the node VG, and the substrate is connected to ground.

[0011] Optionally, when the input signal VIN≈0 and the CLKS becomes high, a sampling stage is entered, in which the input signal VIN is first established at the PB node through the conducting MOS transistor MN6, and the input signal VIN is first established at the PA node through the bootstrap capacitor C1. At this time, the MOS transistor MN1 has been turned on, and the MP0 has the condition of being turned on, so that the VG node is rapidly established to the input signal VIN and the power supply voltage VDD, so as to realize the rapid establishment of the bootstrap path.

[0012] Optionally, when the input signal VIN≈0.5*VDD and the CLKS becomes high, the sampling stage is entered, in the sampling stage, the MOS tube MN6 and MP6 in conduction function simultaneously, first establish the input signal VIN at the PB node, the input signal VIN first establishes the input signal VIN and the power supply voltage VDD at the PA node through the bootstrap capacitor C1, at this time, the MOS tube MN1 has been turned on, and the MP0 has the conduction condition, so that the VG node is quickly established to the input signal VIN and the power supply voltage VDD, to realize the rapid establishment of the bootstrap path.

[0013] Optionally, when the input signal VIN≈0.5*VDD and the CLKS becomes high, the sampling stage is entered, in the sampling stage, the MOS tube MN6 and MP6 in conduction function simultaneously, first establish the input signal VIN at the PB node, the input signal VIN first establishes the input signal VIN and the power supply voltage VDD at the PA node through the bootstrap capacitor C1, at this time, the MOS tube MN1 has been turned on, and the MP0 has the conduction condition, so that the VG node is quickly established to the input signal VIN and the power supply voltage VDD, to realize the rapid establishment of the bootstrap path.

[0014] Optionally, when the CLKS is low, the holding stage is entered.

[0015] Compared with the prior art, the application aims at the problems in the prior art that the bootstrap path establishment speed is limited by the MOS tube MN0, and the charge injected into the sampling capacitor Cs affects the accuracy of the holding stage, and the application includes but is not limited to the following beneficial effects:

[0016] Firstly, the application establishes a fast bootstrap path by multiplexing the bootstrap capacitor C1 and adding three switch MOS tubes MN6, MP6 and MP5, to improve the establishment speed;

[0017] Secondly, the application does not significantly increase the parasitic of the VG node. Although the MOS tubes MN6, MP6 and MP5 are additionally added, it has been proved in practice that the addition of the MOS tubes MN6, MP6 and MP5 helps to reduce the size of the MOS tubes MN0, MP0, MN1 and MN5, so that the Cp does not significantly increase compared with the prior art;

[0018] Thirdly, the application reduces the influence of charge injection by multiplexing the added MOS tubes MN6 and MP6 in the sampling stage, to improve the accuracy;

[0019] Fourthly, the pre-distortion idea is adopted in the application, another distortion structure is added in the traditional distortion structure to realize the purpose of improving the linearity after the combination of the two, the correlation between the time constant on the bootstrap path and the input signal frequency is improved by adding MOS tubes MN6, MP6 and MP5, and the linearity under all input signal frequencies in the full frequency band is improved. BRIEF DESCRIPTION OF DRAWINGS

[0020] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description, taken in conjunction with the following drawings, in which:

[0021] Figure 1 The schematic diagram of the traditional gate voltage bootstrap switch circuit in the embodiment of the present application is shown in FIG. 1.

[0022] Figure 2 The schematic diagram of the high-speed high-linearity gate voltage bootstrap switch circuit in the embodiment of the present application is shown in FIG. 2.

[0023] Figure 3 The schematic diagram of the fast bootstrap path when 0<VIN<0.5*VDD in the embodiment of the present application is shown in FIG. 3.

[0024] Figure 4 The schematic diagram of the fast bootstrap path when VIN≈0.5*VDD in the embodiment of the present application is shown in FIG. 4.

[0025] Figure 5 The schematic diagram of the fast bootstrap path when 0.5*VDD<VIN<VDD in the embodiment of the present application is shown in FIG. 5.

[0026] Figure 6 The schematic diagram of the comparison of the on-resistance of MOS tube MN0 and (MOS tube MN0 / / MOS tube MN6 / / MOS tube MP6) in the embodiment of the present application is shown in FIG. 6.

[0027] Figure 7 The schematic diagram of the comparison of the on-resistance of MOS tube MP0 and (MOS tube MP0 / / MOS tube MP5) in the embodiment of the present application is shown in FIG. 7.

[0028] Figure 8 The schematic diagram of the comparison of the total on-resistance on the bootstrap path in the embodiment of the present application is shown in FIG. 8.

[0029] Figure 9 The schematic diagram of the comparison of the time-domain waveforms of the traditional bootstrap switch and the bootstrap switch of the present application in the embodiment of the present application is shown in FIG. 9.

[0030] Figure 10 The schematic diagram of the comparison of the SFDR-f IN performance of the traditional bootstrap switch and the bootstrap switch of the present application in the embodiment of the present application is shown in FIG. 10.

[0031] Figure 11Fig. 1 is a schematic diagram of ENOB ~ f in performance comparison between a conventional bootstrap switch and the bootstrap switch of the present application. DETAILED DESCRIPTION

[0032] Embodiments of the present application are described in detail below with reference to the attached drawing figures, wherein the same or like reference numerals and characters throughout the figures denote the same or like elements or elements having the same or similar functions. The embodiments described below are presented by way of example only, and are not intended to limit the present application as defined by the claims.

[0033] It should be apparent to those skilled in the art that the various methods described herein, while based on the same concept and thus having commonality with each other, are independently executable unless otherwise specified. Similarly, each of the embodiments disclosed herein is based on the same inventive concept and thus should be understood as equivalent to the same concept even if the same concept is expressed differently or is appropriately modified for convenience.

[0034] Unless explicitly stated otherwise, the various embodiments disclosed herein can be freely combined with each other to form new embodiments, provided that such combination does not depart from the spirit of the present application and meets the needs of the prior art or solves some aspect of the prior art. To this end, those skilled in the art should know.

[0035] Please refer to Figure 1 , Figure 1 The operation of the conventional bootstrap switch can be divided into two stages: a sampling stage and a holding stage. Here, the conventional bootstrap switch is discussed in two extreme cases: when the input signal VIN is small (VIN ≈ 0) and when the input signal VIN is large (VIN ≈ VDD) to illustrate the speed limitation of the conventional bootstrap switch.

[0036] When the input signal VIN ≈ 0 and the CLKs is low, the holding stage is entered. In the holding stage, the following operations are performed: ① The bootstrap capacitor C1 is charged through the MOS transistor MP2 and the MOS transistor MN2, and the PA and PB nodes are charged to VDD and 0, respectively, before the CLKs becomes high;

[0037] ② The MOS transistor MN0 gate node voltage is discharged to ground through the MOS transistor MP4, the MOS transistor MN4, and the MOS transistor MN6, and the MN0 turn-off operation is completed;

[0038] ③ The MP0 gate node voltage is charged to VDD through the MOS transistor MP1, and the MP0 turn-off operation is completed;

[0039] ④The gate node voltage of the sampling tube MS is discharged to the ground through the MOS tube MP4, the MOS tube MN4 and the MOS tube MN5, and the off operation of MS is completed.

[0040] When CLKS becomes high, the sampling stage is entered. In the sampling stage (at this time, the PA node voltage is VDD, and the PB node voltage is 0), the following operations are sequentially completed:

[0041] ①The gate node voltage of the MOS tube MP0 is discharged to VDD through the MOS tube MN1, at this time, the gate-source voltage of the MOS tube MP0 is VDD, the on operation of the MOS tube MP0 is completed, and the VG node voltage is VDD;

[0042] ②Then, the MOS tube MS, the MOS tube MN0 and the MOS tube MN5 are simultaneously turned on, and the input signal VIN is established on the PB node through the MOS tube MN0;

[0043] ③Subsequently, the input signal VIN and the power supply voltage VDD are established on the PA node through the bootstrap capacitor C1;

[0044] ④The input signal VIN and the power supply voltage VDD are established on the VG node through MP0;

[0045] ⑤The VG node voltage input signal VIN and the power supply voltage VDD act on the gate voltage of MS, and the gate-source voltage of MS is finally established to VDD, and the bootstrap path thus plays a role.

[0046] When the input signal VIN is approximately equal to VDD and CLKS is low, the holding stage is entered. The specific operation is the same as that of the conventional bootstrap switch holding stage.

[0047] When CLKS becomes high, the sampling stage is entered. In the sampling stage (at this time, the PA node voltage is VDD, and the PB node voltage is the ground), the following operations are sequentially completed:

[0048] ①The gate node voltage of MP0 is discharged to VDD through the MOS tube MN1, at this time, the gate-source voltage of MP0 is VDD, the on operation of MP0 is completed, and the VG node voltage is VDD;

[0049] ②Then, the MOS tube MN5 is turned on;

[0050] ③At this time, due to the limited on ability of the MOS tube MN0, the PB node needs a very long time to be established to the input signal VIN;

[0051] ④Subsequently, the input signal VIN builds up the input signal VIN and the power supply voltage VDD at the PA node through the bootstrap capacitor C1; ④The input signal VIN and the power supply voltage VDD build up the input signal VIN and the power supply voltage VDD at the VG node through the MOS tube MP0;

[0052] ⑤The VG node voltage input signal VIN and the power supply voltage VDD act on the gate voltage of the MS, and the gate-source voltage of the MS is finally built up to VDD, and the bootstrap path thus plays a role.

[0053] The conventional gate voltage bootstrap switch has two problems, one is that when the input signal VIN is large, the bootstrap path building speed is limited by the MOS tube MN0; the second is that when the CLKS falls, the working state of the MS tube changes from on to off, and the charge related to the input signal VIN existing in the channel will be distributed according to the impedance size on the left and right sides of the MS, and the charge injected into the sampling capacitor Cs will affect the accuracy of the holding stage.

[0054] On the basis of referring to the above exemplary scenarios, please refer to Figure 2 The gate voltage bootstrap switch circuit of the present application includes a clock circuit, a bootstrap path and a reset circuit in one embodiment thereof.

[0055] The clock circuit includes a MOS tube MP3 and a MOS tube MN3, wherein the gate of the MOS tube MP3 and the MOS tube MN3 is connected to a first control signal CLKS, the drain of the MOS tube MP3 and the MOS tube MN3 is connected to a second control signal CLKSB, the source and substrate of the MOS tube MP3 are connected to a power supply voltage VDD, and the source and substrate of the MOS tube MN3 are connected to ground.

[0056] The bootstrap path comprises a MOS transistor MS, a MOS transistor MN0, a MOS transistor MN6, a MOS transistor MP6, a bootstrap capacitor C1, a MOS transistor MP0, a MOS transistor MP5, a MOS transistor MN1 and a MOS transistor MN5, wherein the source of the MOS transistor MS is connected to an input signal VIN, the gate is connected to a node VG, the drain is connected to an output signal VOUT, and the substrate is connected to PB; the source and the substrate of the MOS transistor MN0 and the MOS transistor MN6 are both connected to a node PB, and the drain is connected to the input signal VIN; the gate of the MOS transistor MN0 is connected to the node VG, and the gate of the MOS transistor MN6 is connected to a first control signal CLKS; the gate of the MOS transistor MP6 is connected to a second control signal CLKSB, the drain is connected to the input signal VIN, the source is connected to the node PB, and the substrate is connected to a power supply voltage VDD; the upper plate of the bootstrap capacitor C1 is connected to a node PA, and the lower plate is connected to the node PB; the source and the substrate of the MOS transistor MP0 and the MOS transistor MP5 are both connected to the node PA, and the drain is connected to the node VG; the gate of the MOS transistor MP0 is connected to a node VC, and the gate of the MOS transistor MP5 is connected to the second control signal CLKSB; the source and the substrate of the MOS transistor MN1 and the MOS transistor MN5 are both connected to the node PB, and the drain is connected to the node VC; the gate of the MOS transistor MN1 is connected to the first control signal CLKS, and the gate of the MOS transistor MN5 is connected to the node VG.

[0057] The reset circuit comprises a MOS transistor MP1, a MOS transistor MP2, a MOS transistor MN2, a MOS transistor MN6, a MOS transistor MP4 and a MOS transistor MN4, wherein the source and the substrate of the MOS transistor MP1 are both connected to a power supply voltage VDD, the gate is connected to a first control signal CLKS, and the drain is connected to a node VC; the source of the MOS transistor MP2 is connected to the power supply voltage VDD, the drain and the substrate are both connected to a node PA, and the gate is connected to a node VG; the source and the substrate of the MOS transistor MN2 are both connected to ground, the drain is connected to a node PB, and the gate is connected to a second control signal CLKSB; the gates of the MOS transistor MP4 and the MOS transistor MN4 are both connected to the second control signal CLKSB, the drain of the MOS transistor MP4 is connected to the source of the MOS transistor MN6, the source and the substrate of the MOS transistor MP4 are both connected to the power supply voltage VDD, the source and the substrate of the MOS transistor MN4 are both connected to ground, the gate of the MOS transistor MN6 is connected to the power supply voltage VDD, the drain is connected to the node VG, and the substrate is connected to ground.

[0058] The working process of the high-speed high-linearity gate voltage bootstrap switch can be divided into a sampling stage and a holding stage. When CLKS is low, the holding stage is entered. In the holding stage, the following operations are completed:

[0059] ①The bootstrap capacitor C1 is charged through the MOS transistor MP2 and the MOS transistor MN2, and the nodes PA and PB are charged to VDD and 0 respectively before CLKS becomes high;

[0060] ② The gate node voltage of MOS transistor MN0 is discharged to ground through MOS transistors MP4, MOS transistor MN4, and MOS transistor MN6, completing the shutdown operation of MN0;

[0061] ③ The MP0 gate node voltage is charged to VDD through the MOS tube MP1, completing the MP0 shutdown operation;

[0062] ④ The gate node voltage of the sampling tube MS is discharged to the ground through the MOS tube MP4, the MOS tube MN4, and the MOS tube MN5, thereby completing the shutdown operation of the MS.

[0063] When CLKS goes high, the sampling phase begins. During the sampling phase (at this time, the voltage at the PA node is VDD and the voltage at the PB node is 0), the following operations are completed: the input signal VIN is first established at the PB node through the conductive MOS transistors MN6 and MP6. The input signal VIN first establishes the (VIN + VDD) signal at the PA node through the bootstrap capacitor C1. At this time, the MOS transistor MN1 is already conductive and MP0 is ready for conduction, allowing the VG node to quickly establish the (VIN + VDD) signal, thereby achieving rapid establishment of the bootstrap path. Throughout the subsequent sampling phase, the added MN6, MP6, and MP5 work together with the original transistors MN0, MP0, MN1, and MN5 to achieve the sampling function.

[0064] In some embodiments, when the input signal VIN≈0 and CLKS becomes a high level, the sampling phase begins. In the sampling phase, the input signal VIN is first established at the PB node through the turned-on MOS transistor MN6. The input signal VIN is first established at the PA node through the bootstrap capacitor C1. At this time, the MOS transistor MN1 is already turned on, and MP0 is already in the conduction condition, so that the VG node is quickly established to the input signal VIN and the power supply voltage VDD, thereby realizing rapid establishment of the bootstrap path.

[0065] Specifically, when the input signal VIN≈0 and CLKS becomes high, it enters the sampling phase, as shown in Figure 3 As shown in the figure, during the sampling phase (at this time, the voltage at the PA node is VDD and the voltage at the PB node is 0), the following operations are completed: the input signal VIN is first established at the PB node through the conductive MOS transistor MN6, and the input signal VIN is first established at the PA node through the bootstrap capacitor C1 (VIN + VDD). At this time, the MOS transistor MN1 is already conductive, and MP0 is ready for conduction, so the VG node quickly establishes the (VIN + VDD) signal, thereby achieving rapid establishment of the bootstrap path. The bootstrap path establishment process described here is faster than the bootstrap path establishment process in traditional bootstrap switches.

[0066] In some embodiments, when the input signal VIN ≈ 0.5*VDD and CLKS becomes high, the sampling phase is entered, in which the MOS transistor MN6 and MP6 that are turned on simultaneously play a role first to establish the input signal VIN at the PB node, and the input signal VIN is first established at the PA node by the bootstrap capacitor C1 to the input signal VIN and the power supply voltage VDD, at this time the MOS transistor MN1 has been turned on, and MP0 has the condition to be turned on, so that the VG node is quickly established to the input signal VIN and the power supply voltage VDD, to realize the rapid establishment of the bootstrap path.

[0067] Specifically, when the input signal VIN ≈ 0.5*VDD and CLKS becomes high, the sampling phase is entered, as shown in FIG. 4. Figure 4 In the sampling phase (at this time, the voltage at the PA node is VDD, and the voltage at the PB node is 0), the following operations are completed: the MOS transistor MN6 and MP6 that are turned on simultaneously play a role first to establish the input signal VIN at the PB node, and the input signal VIN is first established at the PA node by the bootstrap capacitor C1 to the (VIN+VDD) signal, at this time the MOS transistor MN1 has been turned on, and MP0 has the condition to be turned on, so that the VG node is quickly established to the (VIN+VDD) signal, thereby realizing the rapid establishment of the bootstrap path. The bootstrap path establishment process described herein is faster than the bootstrap path establishment process in the conventional bootstrap switch.

[0068] In some embodiments, when the input signal VIN ≈ VDD and CLKS becomes high, the sampling phase is entered, in which the MOS transistor MP6 that is turned on first establishes the input signal VIN at the PB node, and the input signal VIN is first established at the PA node by the bootstrap capacitor C1 to the input signal VIN and the power supply voltage VDD, at this time the MOS transistor MN1 has been turned on, and MP0 has the condition to be turned on, so that the VG node is quickly established to the input signal VIN and the power supply voltage VDD, to realize the rapid establishment of the bootstrap path.

[0069] Specifically, when the input signal VIN ≈ VDD and CLKS becomes high, the sampling phase is entered, as shown in FIG. 5. Figure 5 In the sampling phase (at this time, the voltage at the PA node is VDD, and the voltage at the PB node is 0), the following operations are completed: the MOS transistor MP6 that is turned on first establishes the input signal VIN at the PB node, and the input signal VIN is first established at the PA node by the bootstrap capacitor C1 to the (VIN+VDD) signal, at this time the MOS transistor MN1 has been turned on, and MP0 has the condition to be turned on, so that the VG node is quickly established to the (VIN+VDD) signal, thereby realizing the rapid establishment of the bootstrap path. The bootstrap path establishment process described herein is much faster than the bootstrap path establishment process in the conventional bootstrap switch.

[0070] In addition, the gate voltage bootstrap switch provided by the application additionally increases MN6, MP6 and MP5, but this does not mean that the parasitic capacitance C of the VG node is increased p Practical tests prove that the increase of MN6, MP6 and MP5 helps to reduce the size of MN0, MP0, MN1 and MN5, and therefore C p is not significantly increased.

[0071] The precision advantage of the gate voltage bootstrap switch provided by the application is described below. On the one hand, the application reduces the influence of charge injection and improves the precision by adding MN6 and MP6 tubes in the sampling stage.

[0072] On the other hand, the application improves the correlation between the time constant of the bootstrap path and the input signal frequency to improve the linearity at all input signal frequencies in the full frequency band. This can be explained as follows: Figure 1 The time constant τ of the bootstrap path of the conventional gate voltage bootstrap switch in the prior art BS,conventional can be expressed as

[0073] τ BS,conventional = (R MN0 + R MP0 )*(C1 / / C p ),

[0074] Figure 2 The time constant τ of the bootstrap path of the high-speed and high-linearity gate voltage bootstrap switch provided by the application BS,proposed can be expressed as:

[0075] τ BS,proposed = (R MN0 / / R MN6 / / R MP6 + R MP0 / / R MP5 )*(C1 / / C p )

[0076] Wherein, R MN0 , R MN6 , R MP6 , R MP0 , R MP5 respectively represent the resistance values of MOS tube MN0, MOS tube MN6, MOS tube MP6, MOS tube MP0 and MOS tube MP5, C1 represents the bootstrap capacitance, and C p represents the parasitic capacitance.

[0077] In order to further verify the technical effect of the application, the same simulation experiment is performed on the conventional gate voltage bootstrap switch and the high-speed and high-linearity gate voltage bootstrap switch provided by the application by using 65nm CMOS process, and the same size and the same load capacitance are used for the same part of the tubes such as input / output tubes.

[0078] Figure 6 Describes R MN0 and R MN0 / / R MN6 / / R MP6 On-resistance comparison, Figure 7 Describes R MP0 and R MP0 / / R MP5 On-resistance comparison, Figure 8 Describes (R MN0 +R MP0 ) and (R MN0 / / R MN6 / / R MP6 +R MP0 / / R MP5 ) is compared with the on-resistance of , from the figure we can draw the following conclusions:

[0079] ① Although the VGS of MN0 and MP0 in the traditional structure is designed to be VDD when they are turned on, practice has shown that factors such as leakage and parasitics will affect the time constant of the bootstrap path and the frequency of the input signal.

[0080] About sex.

[0081] ② The gate voltage bootstrap switch proposed in this application adopts the idea of ​​pre-distortion, adding another distorted structure to the traditional distorted structure to achieve the purpose of improving linearity after combining the two.

[0082] ③ Although the VGS of MN6, MP6, and MP5 added to the gate voltage bootstrap switch proposed in this application is not designed to be VDD when turned on, practice has proved that the on-resistance of MN0, MN6, and MP6 in the proposed structure after being connected in parallel is better than the on-resistance of MN0 in the traditional structure, and the on-resistance of MP0 and MP5 in the proposed structure after being connected in parallel is better than the on-resistance of MP0 in the traditional structure. ④ τ of the gate voltage bootstrap switch proposed in this application BS,proposed Compared with the traditional gate voltage bootstrap switch τ BS,conventional , which improves the problem that the time constant on the bootstrap path is related to the input signal frequency, and helps to improve the linearity at all input signal frequencies in the full band.

[0083] The frequency (fcl k) of the clock signal (CLK) is 2.5GHz, the power supply voltage is 1.0V, and the output waveforms of the conventional gate voltage bootstrap switch and the gate voltage bootstrap switch of the present application change with time as shown in the following figure: Figure 9 As shown. You can see:

[0084] ①In the sampling phase, the response speed of the bootstrap switch of the application is faster than that of the conventional bootstrap switch when the input signal VIN approaches the power supply voltage VDD, indicating that the dynamic comparator of the application has the advantage of high speed;

[0085] ②In the holding phase, the charge injection of the bootstrap switch of the application is less than that of the conventional bootstrap switch, indicating that the dynamic comparator of the application has the advantage of high precision.

[0086] The curve of the spur-free dynamic range (SFDR) of the conventional gate voltage bootstrap switch and the bootstrap switch of the application with the change of the input signal frequency (fin) is as shown in Figure 10 The curve of the effective number of bits (ENOB) with the change of the signal frequency (fin) is as shown in Figure 11 It can be seen that:

[0087] ①The linearity of the bootstrap switch of the application at all input signal frequencies in the full frequency band is better than that of the conventional bootstrap switch;

[0088] ②The effective number of bits (ENOB) of the bootstrap switch of the application at all input signal frequencies in the full frequency band is better than that of the conventional bootstrap switch.

[0089] From the above embodiment, compared with the prior art, the bootstrap path establishment speed in the prior art is limited by the MOS transistor MN0, and the charge injected into the sampling capacitor Cs affects the precision in the holding phase, and the application includes but is not limited to the following beneficial effects:

[0090] Firstly, the application establishes a fast bootstrap path by multiplexing the bootstrap capacitor C1 and adding three switch MOS transistors MN6, MP6 and MP5, thereby improving the establishment speed;

[0091] Secondly, the application does not significantly increase the parasitic of the VG node. Although the MOS transistors MN6, MP6 and MP5 are additionally added, it has been proved in practice that the addition of the MOS transistors MN6, MP6 and MP5 helps to reduce the size of the MOS transistors MN0, MP0, MN1 and MN5, so that the Cp does not significantly increase compared with the conventional bootstrap switch;

[0092] Thirdly, the application reduces the influence of charge injection by multiplexing the added MOS transistors MN6 and MP6 in the sampling phase, thereby improving the precision;

[0093] Fourth, this application employs the concept of pre-distortion, adding another distortion structure to a traditional distortion-prone structure to achieve the goal of improving linearity through the combination of the two. The added MOS transistors MN6, MP6, and MP5 improve the correlation between the time constant and the input signal frequency in the bootstrap path, thereby improving linearity across all input signal frequencies across the entire frequency band.

[0094] The above description is only part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A gate voltage bootstrap switching circuit, characterized in that: Including clock circuit, bootstrap path and reset circuit; The clock circuit includes a MOS transistor MP3 and a MOS transistor MN3, wherein the gates of the MOS transistors MP3 and MN3 are connected to a first control signal CLKS, the drains of the MOS transistors MP3 and MN3 are connected to a second control signal CLKSB, the source and substrate of the MOS transistor MP3 are both connected to a power supply voltage VDD, and the source and substrate of the MOS transistor MN3 are both grounded; The bootstrap path includes MOS transistor MS, MOS transistor MN0, MOS transistor MN6, MOS transistor MP6, bootstrap capacitor C1, MOS transistor MP0, MOS transistor MP5, MOS transistor MN1 and MOS transistor MN5, wherein the source of MOS transistor MS is connected to the input signal VIN, the gate is connected to the node VG, the drain is connected to the output signal VOUT, and the substrate is connected to PB; the source and substrate of MOS transistor MN0 and MOS transistor MN6 are both connected to the node PB, and the drain is connected to the input signal VIN, the gate of MOS transistor MN0 is connected to the node VG, the gate of MOS transistor MN6 is connected to the first control signal CLKS; the gate of MOS transistor MP6 is connected to the second control signal The MOS transistors MP0 and MP5 each have their source and substrate connected to the node PA and their drain connected to the node VG, the gate of the MOS transistor MP0 is connected to the node VC, and the gate of the MOS transistor MP5 is connected to the second control signal CLKSB; the MOS transistors MN1 and MN5 each have their source and substrate connected to the node PB and their drain connected to the node VC, the gate of the MOS transistor MN1 is connected to the node PB and their drain connected to the node VC, the gate of the MOS transistor MN1 is connected to the first control signal CLKS, and the gate of the MOS transistor MN5 is connected to the node VG; The reset circuit includes MOS transistors MP1, MP2, MN2, MN6, MP4, and MN4. The source and substrate of the MOS transistor MP1 are both connected to the power supply voltage VDD, the gate is connected to the first control signal CLKS, and the drain is connected to the node VC. The source of the MOS transistor MP2 is connected to the power supply voltage VDD, the drain and substrate are both connected to the node PA, and the gate is connected to the node VG. The source and substrate of the MOS transistor MN2 are both grounded, the drain is connected to the node PB, and the gate is connected to the second control signal CLKSB. The gates of the MOS transistors MP4 and MN4 are connected to the second control signal CLKSB, and the drains are connected to the source of the MOS transistor MN6. The source and substrate of the MOS transistor MP4 are both connected to the power supply voltage VDD, the source and substrate of the MOS transistor MN4 are both grounded, and the gate of the MOS transistor MN6 is connected to the power supply voltage VDD, the drain is connected to the node VG, and the substrate is grounded.

2. The gate voltage bootstrap switch circuit according to claim 1, characterized in that: When the input signal VIN≈0 and CLKS becomes a high level, the sampling phase begins. In the sampling phase, the input signal VIN is first established at the PB node through the turned-on MOS transistor MN6. The input signal VIN is first established at the PA node through the bootstrap capacitor C1. At this time, the MOS transistor MN1 is already turned on, and MP0 is ready for conduction, so that the VG node is quickly established to the input signal VIN and the power supply voltage VDD, thereby realizing the rapid establishment of the bootstrap path.

3. The gate voltage bootstrap switch circuit according to claim 1, characterized in that: When the input signal is approximately 0.5*VDD and CLKS becomes a high level, the sampling phase begins. During the sampling phase, the turned-on MOS transistors MN6 and MP6 work together to first establish the input signal VIN at the PB node. The input signal VIN first establishes the input signal VIN and the power supply voltage VDD at the PA node through the bootstrap capacitor C1. At this time, the MOS transistor MN1 is already turned on and MP0 is already turned on, so that the VG node is quickly established to the input signal VIN and the power supply voltage VDD, thereby realizing the rapid establishment of the bootstrap path.

4. The gate voltage bootstrap switch circuit according to claim 1, characterized in that: When the input signal VIN≈VDD and CLKS becomes a high level, the sampling phase begins. In the sampling phase, the input signal VIN is first established at the PB node through the turned-on MOS transistor MP6. The input signal VIN is first established at the PA node through the bootstrap capacitor C1. At this time, the MOS transistor MN1 is already turned on and MP0 is already in the conduction condition, so that the VG node is quickly established to the input signal VIN and the power supply voltage VDD, thereby realizing the rapid establishment of the bootstrap path.

5. The gate voltage bootstrap switch circuit according to any one of claims 1 to 4, characterized in that: When CLKS is low, it enters the hold phase.

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