Super junction IGBT device with improved switching loss and preparation method and chip thereof

Abstract

The present application belongs to the technical field of power devices, and provides a super junction IGBT device with improved switching loss, a preparation method thereof, and a chip. By arranging a first charge storage region, a P-type well region, and a first P-type heavily doped region between the emitter and the P-type drift region and on one side of the gate dielectric layer, the gate voltage can be used to deplete the P-type well region to achieve the purpose of blocking holes when the device is turned on, and the holes can be made to flow out when the device is turned off, thereby improving the conduction and turn-off losses of the super junction IGBT device.

Description

Technical Field

[0001] The present application belongs to the technical field of power devices, and in particular, relates to a super junction IGBT device with improved switching loss, a preparation method thereof, and a chip. Background Art

[0002] An insulated-gate bipolar transistor (IGBT) is a semiconductor device that combines the advantages of a power metal-oxide-semiconductor field-effect transistor (MOSFET) and a bipolar junction transistor. It has the characteristics of high input impedance and low on-state voltage drop and is typically used in medium-frequency and medium-power switching scenarios.

[0003] However, due to the conductivity modulation effect of IGBT, a large number of holes will exist in the drift region during the forward conduction process, resulting in large turn-off losses of the device. Summary of the invention

[0004] In order to solve the above technical problems, the embodiments of the present application provide a super junction IGBT device with improved switching losses, a preparation method thereof, and a chip, aiming to improve the turn-on and turn-off losses of the super junction IGBT.

[0005] A first aspect of an embodiment of the present application provides a super junction IGBT device, the super junction IGBT device comprising:

[0006] P-type substrate layer;

[0007] An N-type buffer layer, formed on the front side of the P-type substrate layer;

[0008] A P-type drift region and an N-type drift region are formed on the N-type buffer layer;

[0009] A first charge storage region and a P-type well region are formed on the P-type drift region;

[0010] A second charge storage region is formed on the N-type drift region;

[0011] A gate dielectric layer and a gate polysilicon layer, wherein the gate dielectric layer is formed on a portion of the P-type drift region and the N-type drift region, and the gate dielectric layer wraps the gate polysilicon layer;

[0012] A first P-type heavily doped region, formed on the first charge storage region and the P-type well region;

[0013] A P-type base region, formed on the second charge storage region;

[0014] An N-type heavily doped region and a second P-type heavily doped region are formed on the P-type base region;

[0015] an emitter, contacting the first P-type heavily doped region, the N-type heavily doped region, and the second P-type heavily doped region;

[0016] A collector is formed on the back side of the P-type substrate layer.

[0017] In some embodiments, the width of the P-type well region is arranged to decrease first and then increase in the direction from the collector to the emitter.

[0018] In some embodiments, the P-type well region is dumbbell-shaped.

[0019] In some embodiments, the P-type well region is composed of two stepped structures, the tops of the two stepped structures are connected to each other, and the bottoms of the two stepped structures are respectively in contact with the first P-type heavily doped region and the P-type drift region.

[0020] In some embodiments, the P-type drift region and the N-type drift region have the same width; and / or

[0021] The P-type drift region and the N-type drift region have the same thickness.

[0022] In some embodiments, the width of the P-type well region is greater than one-fifth of the width of the P-type drift region and less than one-third of the width of the P-type drift region.

[0023] In some embodiments, the doping concentration of the first P-type heavily doped region is greater than the doping concentration of the P-type well region, and the doping concentration of the P-type well region is greater than the doping concentration of the P-type drift region.

[0024] In some embodiments, the doping concentration of the first charge storage region and the second charge storage region is greater than the doping concentration of the N-type buffer layer.

[0025] A second aspect of the embodiment of the present application further provides a method for preparing a super junction IGBT device, the method comprising:

[0026] Performing N-type doping ion implantation on the front side of the single crystal silicon to form an N-type buffer layer, and sequentially epitaxially generating an N-type drift region and a P-type drift region on the N-type buffer layer;

[0027] Epitaxially growing a charge storage layer on the N-type drift region and the P-type drift region, and injecting P-type doping ions into a partial region of the charge storage layer to form a P-type well region; wherein the P-type well region divides the charge storage layer into a first charge storage region and a second charge storage region;

[0028] Epitaxially growing an N-type material on the first charge storage region, the second charge storage region, and the P-type well region, and sequentially implanting P-type doping ions and N-type doping ions into a partial region of the N-type material to form a first P-type heavily doped region, a P-type base region, an N-type heavily doped region, and a second P-type heavily doped region; wherein the P-type base region is formed on the second charge storage region, the N-type heavily doped region and the second P-type heavily doped region are formed on the P-type base region, and the first P-type heavily doped region is formed on the first charge storage region and the P-type well region;

[0029] Etching and removing the N-type material between the first P-type heavily doped region and the P-type base region to form a first deep trench, and forming a gate dielectric layer and a gate polysilicon layer in the first deep trench; wherein the gate dielectric layer includes the gate polysilicon layer;

[0030] Thinning the back side of the single crystal silicon, and implanting P-type doping ions into the back side of the single crystal silicon to form a P-type substrate layer;

[0031] An emitter is formed in contact with the first P-type heavily doped region, the N-type heavily doped region, and the second P-type heavily doped region, and a collector is formed on the back side of the P-type substrate layer.

[0032] A third aspect of the embodiments of the present application further provides a chip, comprising a super junction IGBT device as described in any of the above embodiments.

[0033] The beneficial effects of the embodiments of the present application are as follows: by arranging a first charge storage region, a P-type well region, and a first P-type heavily doped region between the emitter and the P-type drift region and on one side of the gate dielectric layer, the gate voltage can be used to deplete the P-type well region to achieve the purpose of blocking holes when the device is turned on, and the holes can be allowed to flow out when the device is turned off, thereby improving the turn-on and turn-off losses of the super junction IGBT device. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 Schematic diagram of the structure of the super junction IGBT device provided in the embodiment of the present application Figure 1 ;

[0035] Figure 2 Schematic diagram of the structure of the super junction IGBT device provided in the embodiment of the present application Figure 2 ;

[0036] Figure 3a A third structural diagram of a super junction IGBT device provided in an embodiment of the present application;

[0037] Figure 3b A fourth structural diagram of a super junction IGBT device provided in an embodiment of the present application;

[0038] Figure 4a , Figure 4b , Figure 4c , Figure 4d It is a schematic diagram of static parameter simulation of a traditional super junction IGBT and a super junction IGBT device in an embodiment of the present application;

[0039] Figure 5 Schematic diagram of switching characteristic curves of a conventional super junction IGBT and a super junction IGBT device in an embodiment of the present application;

[0040] Figure 6 It is a schematic flow chart of a method for preparing a super junction IGBT device provided in an embodiment of the present application;

[0041] Figure 7 It is a schematic diagram of forming a P-type drift region and an N-type drift region provided in an embodiment of the present application;

[0042] Figure 8 It is a schematic diagram of forming a first charge storage region, a P-type well region, and a second charge storage region provided in an embodiment of the present application;

[0043] Fig. 9 It is a schematic diagram of forming a first P-type heavily doped region, a second P-type heavily doped region, a P-type base region, and an N-type heavily doped region provided in an embodiment of the present application;

[0044] Fig.10 It is a schematic diagram of forming a gate dielectric layer and a gate polysilicon layer provided in an embodiment of the present application;

[0045] Fig.11 is a schematic diagram of forming a P-type substrate layer provided in an embodiment of the present application;

[0046] Fig.12 It is a schematic diagram of forming an emitter and a collector provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0048] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0049] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0050] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means one or more, unless otherwise clearly and specifically defined.

[0051] Due to the conductivity modulation effect of IGBT, during the forward conduction process, a large number of holes will exist in the drift region of the traditional super junction IGBT device, resulting in large turn-off losses of the device.

[0052] In order to solve the above technical problems, the present application embodiment provides a super junction IGBT device with improved switching loss, see Figure 1 As shown, the super junction IGBT device in this embodiment includes: a P-type substrate layer 110, an N-type buffer layer 120, a P-type drift region 131, an N-type drift region 132, a first charge storage region 141, a P-type well region 151, a second charge storage region 142, a gate dielectric layer 210, a gate polysilicon layer 220, a first P-type heavily doped region 161, a P-type base region 162, an N-type heavily doped region 164, a second P-type heavily doped region 163, an emitter 310, and a collector 320. The N-type buffer layer 120 is formed on the front side of the P-type substrate layer 110, and the P-type drift region 131 and the N-type drift region 132 are formed on the N-type buffer layer 120; the first charge storage region 141 and the P-type well region 151 are formed on the P-type drift region 131; and the second charge storage region 142 is formed on the N-type drift region 132. The gate dielectric layer 210 is formed on the P-type drift region 131 and the partial region of the N-type drift region 132, and the gate dielectric layer 210 wraps the gate polysilicon layer 220; the first P-type heavily doped region 161 is formed on the first charge storage region 141 and the P-type well region 151, and the P-type base region 162 is formed on the second charge storage region 142. The N-type heavily doped region 164 and the second P-type heavily doped region 163 are formed on the P-type base region 162. The emitter 310 is in contact with the first P-type heavily doped region 161, the N-type heavily doped region 164 and the second P-type heavily doped region 163, and the collector 320 is formed on the back of the P-type substrate layer 110.

[0053] In this embodiment, an insulating filling layer 330 is formed on the gate dielectric layer 210. The first charge storage area 141, the P-type well area 151, and the first P-type heavily doped area 161 are arranged between the emitter 310 and the P-type drift area 131, and on one side of the gate dielectric layer 210, the gate polysilicon layer 220 is connected to the gate electrode, and the gate electrode can apply a gate voltage to the gate polysilicon layer 220. Since the P-type well area 151 and the first charge storage area 141 are arranged in parallel, the first P-type heavily doped area 161 and the P-type drift area 131 are arranged at both ends of the P-type well area 151. When the device is turned on, the gate voltage can be used to deplete the P-type well area 151 to achieve the purpose of blocking holes, and when the device is turned off, the holes can be made to flow out, thereby improving the turn-on and turn-off losses of the super junction IGBT device.

[0054] In some embodiments, the first charge storage region 141 is located on the left side of the gate polysilicon layer 220 , and the second charge storage region 142 is located on the right side of the gate polysilicon layer 220 .

[0055] In some embodiments, the P-type drift region 131 is connected to the first P-type heavily doped region 161 via the P-type well region 151 , and the P-type well region 151 is in contact with the gate dielectric layer 210 .

[0056] In some embodiments, the P-type drift region 131 is connected to the first P-type heavily doped region 161 via the P-type well region 151. The P-type well region 151 is located in the central area of ​​the first charge storage region 141. The P-type well region 151 divides the first charge storage region 141 into two left and right parts.

[0057] In some embodiments, in combination Figure 2 As shown, the width of the P-type well region 151 is arranged to decrease first and then increase in the direction from the collector 320 to the emitter 310 .

[0058] In this embodiment, the P-type well region 151 is arranged in parallel with the first charge storage region 141, the width of the contact interface between the P-type well region 151 and the first P-type heavily doped region 161 is relatively large, and the width of the contact interface between the P-type well region 151 and the P-type drift region 131 is relatively large. With such a design, the gate polysilicon layer 220 depletes the P-type well region 151 when a voltage is applied, and the P-type well region 151 is arranged in parallel with the first charge storage region 141, which is beneficial to suppressing the outflow of holes and enhancing the conductivity modulation effect of the device.

[0059] In some embodiments, in combination Figure 3a As shown, the bottom surface of the gate polysilicon layer 220 is flush with the bottom surface of the P-type well region 151, and the gate dielectric layer 210 extends deep into the P-type drift region 131 and the N-type drift region 132, so that the P-type drift region 131 and the N-type drift region 132 are L-shaped structures.

[0060] In this embodiment, the lower bottom surface of the gate polysilicon layer 220 is set flush with the lower bottom surface of the P-type well region 151, so that the electric field generated by the gate polysilicon layer 220 when the gate voltage is connected covers the P-type well region 151, which is beneficial to the depletion of the P-type well region 151 when the gate voltage is applied to the gate polysilicon layer 220. In addition, combined with the setting that the widths of the two ends of the P-type well region 151 are larger and the width of the middle area of ​​the P-type well region 151 is smaller, the outflow of holes can be suppressed, thereby enhancing the conductivity modulation effect of the device.

[0061] In some embodiments, since the gate dielectric layer 210 extends deep into the P-type drift region 131 and the N-type drift region 132, when forming the gate dielectric layer 210, it is necessary to etch the contact area between the P-type drift region 131 and the N-type drift region 132, so that the P-type drift region 131 and the N-type drift region 132 are in an L-shaped structure, and the horizontal parts of the P-type drift region 131 and the N-type drift region 132 are in contact to form a groove, and then the gate dielectric layer 210 and the gate polysilicon layer 220 are sequentially formed in the groove.

[0062] In some embodiments, see Figure 3b As shown, a second gate polysilicon layer 221 and a second gate dielectric layer 211 are also arranged between the emitter 310 and the P-type drift region 131, the first P-type heavily doped region 161 is located between the second gate dielectric layer 211 and the gate dielectric layer 210, and P-type well regions 151 are provided on both sides of the first charge storage region 141.

[0063] In this embodiment, the second gate polysilicon layer 220 is isolated from the emitter 310 by the second gate dielectric layer 210, and the second gate polysilicon layer 220 and the gate polysilicon layer 220 can be connected to the same gate electrode. The electric field generated when the gate polysilicon layer 220 and the second gate polysilicon layer 220 are connected to the gate voltage covers the P-type well region 151, which is beneficial to the depletion of the P-type well region 151 when the gate voltage is applied to the gate polysilicon layer 220. In addition, combined with the larger widths at both ends of the P-type well region 151 and the smaller width in the middle area of ​​the P-type well region 151, the outflow of holes can be suppressed, thereby enhancing the conductivity modulation effect of the device.

[0064] In some embodiments, the width of the contact interface between the P-type well region 151 and the first P-type heavily doped region 161 is directly proportional to the width of the first P-type heavily doped region 161 .

[0065] In some embodiments, the width of the contact interface between the P-type well region 151 and the P-type drift region 131 is directly proportional to the width of the P-type drift region 131 .

[0066] In this embodiment, the widths of the two ends of the P-type well region 151 are respectively related to the widths of the first P-type heavily doped region 161 and the P-type drift region 131, which is beneficial to the hole density distribution of holes flowing out through the P-type well region 151 when the gate voltage becomes 0V after the device is turned off, thereby improving the conduction and shutdown losses of the device.

[0067] In some embodiments, the P-type well region 151 is dumbbell-shaped.

[0068] In this embodiment, the widths of the two ends of the P-type well region 151 are larger, and the width of the middle region is smaller, so that the P-type well region 151 is dumbbell-shaped. When a gate voltage is applied to the gate polysilicon layer 220, the middle region of the P-type well region 151 can be depleted first, and together with the first charge storage region 141, the outflow of holes is suppressed, thereby enhancing the conductivity modulation effect of the device. After the device is turned off, the gate voltage becomes 0V. At this time, the P-type well region 151 can allow holes to flow out, thereby improving the on- and off-loss of the device.

[0069] In some embodiments, in combination Figure 2 As shown, the P-type well region 151 is composed of two step structures, the tops of the two step structures are connected together, and the bottoms of the two step structures are respectively in contact with the first P-type heavily doped region 161 and the P-type drift region 131 .

[0070] In this embodiment, the P-type well region 151 is composed of two stepped structures. The width of the lower stepped structure in the P-type well region 151 gradually decreases from the P-type drift region 131 to the emitter 310. The stepped structure can be formed by step-by-step etching and then epitaxially generating the first charge storage region 141 and the P-type semiconductor material.

[0071] In some embodiments, the widths of the P-type drift region 131 and the N-type drift region 132 are the same.

[0072] In some embodiments, the thicknesses of the P-type drift region 131 and the N-type drift region 132 are the same.

[0073] In some embodiments, the width of the P-type well region 151 is greater than one-fifth of the width of the P-type drift region 131 and less than one-third of the width of the P-type drift region 131 .

[0074] In this embodiment, by setting the width of the P-type well region 151 to be greater than one-fifth of the width of the P-type drift region 131 and less than one-third of the width of the P-type drift region 131, the width of the P-type well region 151 will not be too small or too wide, which is beneficial to the depletion of the P-type well region 151 when the gate voltage is applied to the gate polysilicon layer 220. In addition, combined with the setting that the widths of the two ends of the P-type well region 151 are larger and the width of the middle area of ​​the P-type well region 151 is smaller, the outflow of holes can be suppressed, thereby enhancing the conductivity modulation effect of the device.

[0075] In some embodiments, the doping concentration of the first P-type heavily doped region 161 is greater than the doping concentration of the P-type well region 151 , and the doping concentration of the P-type well region 151 is greater than the doping concentration of the P-type drift region 131 .

[0076] In some embodiments, the doping concentrations of the first charge storage region 141 and the second charge storage region 142 are greater than the doping concentration of the N-type buffer layer 120 .

[0077] Figure 4a , Figure 4b , Figure 4c , Figure 4d is a schematic diagram of static simulation curves of a traditional super junction IGBT and a super junction IGBT device in an embodiment of the present application. Table 1 is characteristic parameters of a traditional super junction IGBT and a super junction IGBT device in an embodiment of the present application. Figure 4a Curve 1 and curve 2 in the figure are respectively the traditional super junction IGBT and the super junction IGBT device in the embodiment of the present application when VCE=10V, and the voltage VGE between the gate and the emitter 310 increases from 0V to 10V, VCE is the voltage between the collector 320 and the emitter 310, the change curve of the collector current Ic, and the horizontal axis Vg represents the change of the gate voltage. Figure 4b Curve 3 and curve 4 in the figure are respectively the variation curves between the collector current Ic and the collector voltage Vc of the conventional super junction IGBT and the super junction IGBT device in the embodiment of the present application when VCE=0V and the current ICE between the collector 320 and the emitter 310=250uA. Figure 4c Curve 5 and curve 6 in the figure are respectively the variation curves between the collector current Ic and the collector voltage Vc of the conventional super junction IGBT and the super junction IGBT device in the embodiment of the present application when VGE=10V and VCE increases from 0V to 5V. Figure 4d Curve 7 and curve 8 in the figure are respectively the variation curves between the collector current Ic and the collector voltage Vc of the conventional super junction IGBT and the super junction IGBT device in the embodiment of the present application when VGE=15V and VCE increases from 0V to 20V.

[0078] Table 1:

[0079]

[0080] Combination Figure 4a , Figure 4b , Figure 4c , Figure 4d As shown in Table 1, the breakdown voltage V of the super junction IGBT device in the embodiment of the present application is CES Compared with the traditional super junction IGBT, the turn-off loss has been significantly increased and the other electrical parameters such as threshold voltage VGEth , on-state voltage Von, etc. increase to a certain extent, but the difference is small, and the increase in conduction loss energy Eon is much smaller than the decrease in turn-off loss Eoff.

[0081] Figure 5 Schematic diagram of the switching curves of the conventional super junction IGBT and the super junction IGBT device in the embodiment of the present application under the conditions of VGE=300V and threshold voltage of 15V. Curve 12 represents the collector voltage Vc curve of the super junction IGBT device in the embodiment of the present application, and curve 11 represents the collector current Ic curve of the super junction IGBT device in the embodiment of the present application. Curve 9 represents the collector voltage Vc curve of the conventional super junction IGBT, and curve 10 represents the collector current Ic curve of the conventional super junction IGBT. Figure 3a , 3b , Figure 4a , Figure 4b , Figure 4c , Figure 4d As shown in Table 1, when VGE=0V and ICE=250uA, the breakdown voltage V of the super junction IGBT device in the embodiment of the present application is CES is 1354.3V, while the breakdown voltage of the conventional super junction IGBT under this condition is V CES is 1196.4V. When VCE=10V and ICE=1A, the threshold voltage V GEth is 5.9V, while the threshold voltage V GEth is 5.8V. When VCE=10V and ICE=1A, the on-state voltage Von of the super junction IGBT device in the embodiment of the present application is 1.2V, while the on-state voltage Von of the conventional super junction IGBT under this condition is 1V. When VGE=300V, the threshold voltage is 15V, and the on-resistance is 60Ω, the on-state loss energy Eon of the super junction IGBT device in the embodiment of the present application is 18mJ, and the off-state loss energy is 11mJ, while the on-state loss energy Eon of the conventional super junction IGBT under this condition is 16.8mJ, and the off-state loss energy is 59.7mJ. The increase in the on-state loss energy Eon of the super junction IGBT device in the embodiment of the present application is much less than the decrease in the off-state loss Eoff.

[0082] The present application also provides a method for preparing a super junction IGBT device, see Figure 5 As shown, the preparation method in this embodiment includes steps S100 to S600.

[0083] In step S100 , N-type doping ions are implanted on the front surface of the single crystal silicon to form an N-type buffer layer 120 , and an N-type drift region 132 and a P-type drift region 131 are sequentially epitaxially generated on the N-type buffer layer 120 .

[0084] In this embodiment, N-type doping ions are implanted on the front side of the single crystal silicon to form an N-type buffer layer 120 on the front side of the single crystal silicon, and then the single crystal silicon material is epitaxially grown. After the N-type doping ions are implanted, an N-type drift region 132 can be formed, and the N-type drift region 132 is in contact with the N-type buffer layer 120. Further, a portion of the N-type drift region 132 is etched, and then the single crystal silicon material is epitaxially grown again, and then P-type doping ions are implanted to form a P-type drift region 131.

[0085] In some embodiments, the thickness of the N-type drift region 132 is the same as the thickness of the P-type drift region 131 .

[0086] In some embodiments, a PN junction is formed between the N-type drift region 132 and the P-type drift region 131 .

[0087] In some embodiments, the doping concentration of the N-type drift region 132 is less than the doping concentration of the N-type buffer layer 120 , and the doping concentration of the N-type buffer layer 120 is at least 10 times the doping concentration of the N-type drift region 132 .

[0088] In some embodiments, the widths of the P-type drift region 131 and the N-type drift region 132 are the same.

[0089] In some embodiments, the width of the P-type well region 151 is greater than one-fifth of the width of the P-type drift region 131 and less than one-third of the width of the P-type drift region 131 .

[0090] In this embodiment, by setting the width of the P-type well region 151 to be greater than one-fifth of the width of the P-type drift region 131 and less than one-third of the width of the P-type drift region 131, the width of the P-type well region 151 will not be too small or too wide, which is beneficial to the depletion of the P-type well region 151 when the gate voltage is applied to the gate polysilicon layer 220. In addition, combined with the setting that the widths of the two ends of the P-type well region 151 are larger and the width of the middle area of ​​the P-type well region 151 is smaller, the outflow of holes can be suppressed, thereby enhancing the conductivity modulation effect of the device.

[0091] In step S200 , a charge storage layer is epitaxially grown on the N-type drift region 132 and the P-type drift region 131 , and P-type dopant ions are implanted into a portion of the charge storage layer to form a P-type well region 151 .

[0092] In this embodiment, single crystal silicon material can be epitaxially grown on the N-type drift region 132 and the P-type drift region 131, and then P-type dopant ions and N-type dopant ions are injected according to preset areas. The P-type well region 151 divides the charge storage layer into a first charge storage region 141 and a second charge storage region 142, and the P-type well region 151 is located between the first charge storage region 141 and the second charge storage region 142.

[0093] In step S300, N-type material is epitaxially grown on the first charge storage region 141, the second charge storage region 142, and the P-type well region 151, and P-type dopant ions and N-type dopant ions are sequentially implanted into partial regions of the N-type material to form a first P-type heavily doped region 161, a P-type base region 162, an N-type heavily doped region 164, and a second P-type heavily doped region 163.

[0094] In this embodiment, a P-type base region 162 is formed on the second charge storage region 142 , an N-type heavily doped region 164 and a second P-type heavily doped region 163 are formed on the P-type base region 162 , and a first P-type heavily doped region 161 is formed on the first charge storage region 141 and the P-type well region 151 .

[0095] In some embodiments, the width of the contact interface between the P-type well region 151 and the first P-type heavily doped region 161 is directly proportional to the width of the first P-type heavily doped region 161 .

[0096] In some embodiments, the width of the contact interface between the P-type well region 151 and the P-type drift region 131 is directly proportional to the width of the P-type drift region 131 .

[0097] In this embodiment, the widths of the two ends of the P-type well region 151 are respectively related to the widths of the first P-type heavily doped region 161 and the P-type drift region 131, which is beneficial to the hole density distribution of holes flowing out through the P-type well region 151 when the gate voltage becomes 0V after the device is turned off, thereby improving the conduction and shutdown losses of the device.

[0098] In some embodiments, the P-type well region 151 is dumbbell-shaped.

[0099] In this embodiment, the widths of the two ends of the P-type well region 151 are larger, and the width of the middle region is smaller, so that the P-type well region 151 is dumbbell-shaped. When a gate voltage is applied to the gate polysilicon layer 220, the middle region of the P-type well region 151 can be depleted first, and together with the first charge storage region 141, the outflow of holes is suppressed, thereby enhancing the conductivity modulation effect of the device. After the device is turned off, the gate voltage becomes 0V. At this time, the P-type well region 151 can allow holes to flow out, thereby improving the on- and off-loss of the device.

[0100] In some embodiments, in combination Figure 2As shown, the P-type well region 151 is composed of two step structures, the tops of the two step structures are connected together, and the bottoms of the two step structures are respectively in contact with the first P-type heavily doped region 161 and the P-type drift region 131 .

[0101] In this embodiment, the P-type well region 151 is composed of two stepped structures. The width of the lower stepped structure in the P-type well region 151 gradually decreases from the P-type drift region 131 to the emitter 310. The stepped structure can be formed by step-by-step etching and then epitaxially generating the first charge storage region 141 and the P-type semiconductor material.

[0102] In step S400 , the N-type material between the first P-type heavily doped region 161 and the P-type base region 162 is etched away to form a first deep trench, and a gate dielectric layer 210 and a gate polysilicon layer 220 are formed in the first deep trench.

[0103] In this embodiment, a first deep trench is formed by etching, a dielectric material is deposited to form a gate dielectric layer 210 , and then a polysilicon material is filled to form a gate polysilicon layer 220 . The gate dielectric layer 210 includes the gate polysilicon layer 220 .

[0104] In step S500 , the back side of the single crystal silicon is thinned, and P-type doping ions are implanted into the back side of the single crystal silicon to form a P-type substrate layer 110 .

[0105] In this embodiment, the back side of the single crystal silicon is thinned, and then P-type doping ions are implanted to form a P-type substrate layer 110 . A PN junction is formed between the P-type substrate layer 110 and the N-type buffer layer 120 .

[0106] In step S600 , an emitter 310 is formed to contact the first P-type heavily doped region 161 , the N-type heavily doped region 164 , and the second P-type heavily doped region 163 , and a collector 320 is formed on the back side of the P-type substrate layer 110 .

[0107] In this embodiment, the emitter 310 is formed by depositing electrode metal material on the first P-type heavily doped region 161, the N-type heavily doped region 164, the second P-type heavily doped region 163, and the gate dielectric layer 210, and the electrode metal material on the gate dielectric layer 210 is etched and removed. The collector 320 is formed by depositing electrode metal material on the back side of the P-type substrate layer 110.

[0108] An embodiment of the present application also provides a chip, comprising a super junction IGBT device as described in any of the above embodiments.

[0109] In this embodiment, the chip includes a chip substrate, on which one or more super junction IGBT devices are arranged. The super junction IGBT device can be prepared by the preparation method in any of the above embodiments, or the super junction IGBT device in any of the above embodiments can be arranged on the chip substrate.

[0110] In a specific application embodiment, other related semiconductor devices may also be integrated on the chip substrate to form an integrated circuit with the super junction IGBT device.

[0111] In a specific application embodiment, the chip may be a switch chip or a driver chip.

[0112] The beneficial effects of the embodiments of the present application are as follows: by arranging a first charge storage region, a P-type well region, and a first P-type heavily doped region between the emitter and the P-type drift region and on one side of the gate dielectric layer, the gate voltage can be used to deplete the P-type well region to achieve the purpose of blocking holes when the device is turned on, and the holes can be allowed to flow out when the device is turned off, thereby improving the turn-on and turn-off losses of the super junction IGBT device.

[0113] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned doping regions and devices is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different doping regions and devices as needed, that is, the internal structure of the device is divided into different doping regions to complete all or part of the functions described above. The doping regions and devices in the embodiments can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0114] In addition, the specific names of the doping regions and devices are only for the convenience of distinguishing each other and are not used to limit the scope of protection of the present application.

[0115] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0116] In addition, each doping region in each embodiment of the present application may be integrated into one unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0117] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A super junction IGBT device with improved switching loss, characterized in that: The super junction IGBT device comprises: P-type substrate layer; An N-type buffer layer, formed on the front side of the P-type substrate layer; A P-type drift region and an N-type drift region are formed on the N-type buffer layer; A first charge storage region and a P-type well region are formed on the P-type drift region; A second charge storage region is formed on the N-type drift region; A gate dielectric layer and a gate polysilicon layer, wherein the gate dielectric layer is formed on a portion of the P-type drift region and the N-type drift region, and the gate dielectric layer wraps the gate polysilicon layer; A first P-type heavily doped region, formed on the first charge storage region and the P-type well region; A P-type base region, formed on the second charge storage region; An N-type heavily doped region and a second P-type heavily doped region are formed on the P-type base region; an emitter, contacting the first P-type heavily doped region, the N-type heavily doped region, and the second P-type heavily doped region; A collector electrode formed on the back side of the P-type substrate layer; The width of the P-type well region is set to decrease first and then increase in the direction from the collector to the emitter; The P-type drift region is connected to the first P-type heavily doped region via the P-type well region; the P-type well region and the first charge storage region are arranged in parallel, and the bottom surface of the gate polysilicon layer is flush with the bottom surface of the P-type well region.

2. The super junction IGBT device according to claim 1, characterized in that: The P-type well region is in a dumbbell shape.

3. The super junction IGBT device according to claim 1, characterized in that: The P-type well region is composed of two step structures, the tops of the two step structures are connected to each other, and the bottoms of the two step structures are respectively in contact with the first P-type heavily doped region and the P-type drift region.

4. The super junction IGBT device according to claim 1, characterized in that: The widths of the P-type drift region and the N-type drift region are the same; and / or The P-type drift region and the N-type drift region have the same thickness.

5. The super junction IGBT device according to claim 1, characterized in that: The width of the P-type well region is greater than one-fifth of the width of the P-type drift region and less than one-third of the width of the P-type drift region.

6. The super junction IGBT device according to any one of claims 1 to 5, characterized in that: The doping concentration of the first P-type heavily doped region is greater than the doping concentration of the P-type well region, and the doping concentration of the P-type well region is greater than the doping concentration of the P-type drift region.

7. The super junction IGBT device according to any one of claims 1 to 5, characterized in that: The doping concentrations of the first charge storage region and the second charge storage region are greater than the doping concentration of the N-type buffer layer.

8. A method for preparing a super junction IGBT device, characterized in that: The preparation method comprises: Performing N-type doping ion implantation on the front side of the single crystal silicon to form an N-type buffer layer, and sequentially epitaxially generating an N-type drift region and a P-type drift region on the N-type buffer layer; Epitaxially growing a charge storage layer on the N-type drift region and the P-type drift region, and injecting P-type doping ions into a partial region of the charge storage layer to form a P-type well region; wherein the P-type well region divides the charge storage layer into a first charge storage region and a second charge storage region; Epitaxially growing an N-type material on the first charge storage region, the second charge storage region, and the P-type well region, and sequentially implanting P-type doping ions and N-type doping ions into a partial region of the N-type material to form a first P-type heavily doped region, a P-type base region, an N-type heavily doped region, and a second P-type heavily doped region; wherein the P-type base region is formed on the second charge storage region, the N-type heavily doped region and the second P-type heavily doped region are formed on the P-type base region, and the first P-type heavily doped region is formed on the first charge storage region and the P-type well region; Etching and removing the N-type material between the first P-type heavily doped region and the P-type base region to form a first deep trench, and forming a gate dielectric layer and a gate polysilicon layer in the first deep trench; wherein the gate dielectric layer wraps the gate polysilicon layer; Thinning the back side of the single crystal silicon, and implanting P-type doping ions into the back side of the single crystal silicon to form a P-type substrate layer; forming an emitter electrode in contact with the first P-type heavily doped region, the N-type heavily doped region, and the second P-type heavily doped region, and forming a collector electrode on the back side of the P-type substrate layer; Among them, the width of the P-type well region is arranged to first decrease and then increase in the direction from the collector to the emitter; the P-type drift region is connected to the first P-type heavily doped region via the P-type well region; the P-type well region and the first charge storage region are arranged in parallel, and the lower bottom surface of the gate polysilicon layer is flush with the lower bottom surface of the P-type well region.

9. A chip, characterized in that: Comprising a super junction IGBT device as described in any one of claims 1 to 7.

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