A battery

Abstract

The present invention provides a battery, which comprises a passivation layer; the passivation layer comprises a compound shown in Formula 1, wherein R1, R2, R3, and R4 are each independently selected from a substituted or unsubstituted C1-C20 alkyl group, a halogen, a substituted or unsubstituted amino group, and a substituted or unsubstituted C1-C20 alkoxy group, and at least one of R1, R2, R3, and R4 comprises the substituted or unsubstituted C1-C20 alkyl group or the substituted or unsubstituted amino group; the substituent of the alkyl group, the substituent of the amino group, and the substituent of the alkoxy group are each independently selected from a halogen, an amino group, a -Si(C x H 2x+1 )3, x is an integer between 1 and 20. The passivation layer in the battery of the present invention can reduce the parasitic absorption of the battery and improve the photoelectric conversion efficiency of the battery.

Description

Technical Field

[0001] The invention relates to a battery, in particular to a battery and application thereof, belonging to the technical field of photovoltaic batteries. Background Art

[0002] With the development of society today, non-renewable resources such as coal and oil are becoming increasingly scarce. For the development of human society, it is urgent to develop renewable energy. Solar energy is an inexhaustible new energy source, and solar cells can convert solar radiation into electrical energy. Among them, heterojunction solar (HJT) cells, Topcon cells, and heterojunction / perovskite stacked cells can achieve high photoelectric conversion efficiency, making these cells highly concerned in the solar industry and considered to be an important direction for the future development of solar cells.

[0003] At present, hydrogenated amorphous silicon is used as a passivation layer in solar cells, which can effectively recombine the dangling bonds on the surface of single-crystal silicon and reduce the recombination of carriers on the surface of single-crystal silicon, thereby obtaining a larger open circuit voltage and excellent photoelectric conversion efficiency. However, although the hydrogenated amorphous silicon layer ensures the passivation effect of the cell, the serious parasitic absorption brought by the hydrogenated amorphous silicon layer is an important factor restricting the further improvement of the efficiency of solar cells.

[0004] Therefore, those skilled in the art are in urgent need of developing a battery including a passivation layer capable of reducing parasitic absorption, so that the battery has excellent photoelectric conversion efficiency. Summary of the invention

[0005] The invention provides a battery, which comprises a passivation layer capable of reducing parasitic absorption and has excellent photoelectric conversion efficiency.

[0006] The solar cell assembly provided by the present invention comprises the above-mentioned cell and exhibits excellent photoelectric conversion performance.

[0007] The present invention provides a battery, wherein the battery comprises a passivation layer; the passivation layer comprises a compound represented by Formula 1:

[0008] Formula 1

[0009] Wherein, R1, R2, R3, and R4 are each independently selected from a substituted or unsubstituted C1-C20 alkyl group, a halogen, a substituted or unsubstituted amino group, and a substituted or unsubstituted C1-C20 alkoxy group, and at least one of R1, R2, R3, and R4 includes the substituted or unsubstituted C1-C20 alkyl group or the substituted or unsubstituted amino group;

[0010] The substituents of the alkyl group, the amino group and the alkoxy group are each independently selected from halogen, amino, -Si(C x H2x+1 )3, x is an integer from 1 to 20.

[0011] The battery as described above, wherein R1, R2, R3, and R4 are each independently selected from a substituted or unsubstituted C1-C18 alkyl, a halogen, a substituted or unsubstituted amino, and a substituted or unsubstituted C1-C18 alkoxy; the substituent of the alkyl, the substituent of the amino, and the substituent of the alkoxy are each independently selected from a halogen, an amino, -Si(C x H 2x+1 )3, x is an integer from 1 to 18.

[0012] The battery as described above, wherein the compound represented by Formula 1 includes one of octadecyltrichlorosilane, 3-aminopropyltriethoxysilane, 1H,1H,2H,2H-perfluorooctyltrichlorosilane, hexamethyldisilazane, and octadecyltrimethoxysilane.

[0013] In the battery as described above, the thickness of the passivation layer is 2-5 nm.

[0014] The battery as described above, wherein the battery comprises a first transparent conductive oxide layer, an n-type doped silicon layer, the passivation layer, a single crystal silicon layer, the passivation layer, a p-type doped silicon layer, and a second transparent conductive oxide layer stacked in sequence.

[0015] The battery as described above, wherein the thickness of the first transparent conductive oxide layer is 60-140 nm;

[0016] And / or, the thickness of the p-type doped silicon layer is 10-30 nm;

[0017] And / or, the thickness of the n-type doped silicon layer is 10-25 nm;

[0018] And / or, the thickness of the single crystal silicon layer is 50-150 μm;

[0019] And / or, the second transparent conductive oxide layer has a thickness of 60-140 nm.

[0020] The battery as described above, wherein the p-type doped silicon in the p-type doped silicon layer includes at least one of p-type doped amorphous silicon and p-type doped microcrystalline silicon;

[0021] And / or, the n-type doped silicon in the n-type doped silicon layer includes at least one of n-type doped amorphous silicon, n-type doped microcrystalline silicon and n-type oxygen-doped microcrystalline silicon;

[0022] And / or, the transparent conductive oxide in the transparent conductive oxide layer includes at least one of transparent conductive oxide ITO, aluminum-doped zinc oxide, and fluorine-doped tin oxide;

[0023] And / or, the single crystal silicon layer includes at least one of an n-type single crystal silicon layer and a p-type single crystal silicon layer.

[0024] The battery as described above, wherein the battery is prepared by a method comprising the following processes:

[0025] placing single crystal silicon in a vapor atmosphere of the compound represented by Formula 1 and performing a heating treatment to obtain single crystal silicon including the passivation layer, then depositing an n-type doped silicon layer and a p-type doped silicon layer on the front and back surfaces of the single crystal silicon including the passivation layer, respectively, and then depositing the first transparent conductive oxide layer on the side of the n-type doped silicon layer away from the passivation layer, and depositing the second transparent conductive oxide layer on the side of the p-type doped silicon layer away from the passivation layer, to obtain the battery;

[0026] The vacuum degree of the heating treatment is 10 -4 -10 -1 Pa, heating temperature is 100-180℃, heating time is 40-60min.

[0027] The battery as described above, wherein the battery comprises SiN x The anti-reflection layer, the passivation layer, the p+ doped single crystal silicon layer, the n-doped single crystal silicon layer, the tunneling oxide layer, the n+ doped polysilicon layer and the SiN x Anti-reflection layer.

[0028] The battery as described above, wherein the battery includes a transparent conductive oxide layer, an electron transport layer, a perovskite layer, a hole transport layer, the passivation layer, an n-type doped microcrystalline silicon layer, the passivation layer, an n-type single crystal silicon layer, the passivation layer, a p-type doped microcrystalline silicon layer and a transparent conductive oxide layer stacked in sequence.

[0029] The present invention provides a solar cell module comprising the cell as described above.

[0030] The battery provided by the present invention includes a passivation layer, which is composed of a compound shown in Formula 1. The compound of Formula 1 can react with dangling bonds on the surface of single-crystal silicon to generate a passivation layer, thereby achieving a high passivation effect. After the dangling bonds on the surface of the single-crystal silicon are saturated by the reaction, no dangling bonds are generated on the surface of the passivation layer, which can inhibit the further growth of the compound shown in Formula 1 on the passivation layer, thereby effectively reducing parasitic absorption and further improving the photoelectric conversion efficiency of the battery.

[0031] The solar cell module provided by the present invention is prepared based on the above-mentioned battery, has excellent photoelectric conversion performance, and can be widely used in the photovoltaic industry. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram of the structure of a heterojunction battery.

[0033] Description of reference numerals:

[0034] 1-a first transparent conductive oxide layer;

[0035] 2-n-type doped silicon layer;

[0036] 3- passivation layer;

[0037] 4- single crystal silicon layer;

[0038] 5-p-type doped silicon layer;

[0039] 6-Second transparent conductive oxide layer. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in combination with the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] The present invention provides a battery, which includes a passivation layer; the passivation layer includes a compound shown in Formula 1:

[0042] Formula 1

[0043] wherein R1, R2, R3, and R4 are each independently selected from a substituted or unsubstituted C1-C20 alkyl group, a halogen, a substituted or unsubstituted amino group, or a substituted or unsubstituted C1-C20 alkoxy group, and at least one of R1, R2, R3, and R4 includes a substituted or unsubstituted C1-C20 alkyl group or a substituted or unsubstituted amino group;

[0044] The substituents of the alkyl group, the amino group and the alkoxy group are each independently selected from halogen, amino, -Si(C x H 2x+1 )3, x is an integer from 1 to 20.

[0045] The passivation layer of the present invention is a layer covering the surface of the solar cell, which can reduce the activity of the cell surface, reduce the surface recombination rate, and improve the photoelectric conversion efficiency of the solar cell. At the same time, the passivation layer can protect the cell from erosion by the external environment and improve the stability of the cell.

[0046] The passivation layer of the present invention comprises a compound as shown in Formula 1, wherein R1, R2, R3, and R4 are each independently selected from a substituted or unsubstituted C1-C20 alkyl group, a halogen, a substituted or unsubstituted amino group, or a substituted or unsubstituted C1-C20 alkoxy group, and at least one of R1, R2, R3, and R4 comprises a substituted or unsubstituted C1-C20 alkyl group or a substituted or unsubstituted amino group; the substituent of the alkyl group, the substituent of the amino group, and the substituent of the alkoxy group are each independently selected from a halogen, an amino group, -Si(C x H 2x+1 )3, x is an integer from 1 to 20. The substituted or unsubstituted C1-C20 alkyl group of the present invention refers to a substituted or unsubstituted chain alkyl group having 1 to 20 carbon atoms or a substituted or unsubstituted cycloalkyl group having 3 to 20 carbon atoms. The substituents of the alkyl group include halogen, amino, -Si(C x H 2x+1 )3, x is an integer from 1 to 20; halogen refers to at least one of F, Cl, Br, and I; substituted or unsubstituted amino refers to an amino group in which the hydrogen ion in the amino group is replaced by a substituent, and the substituent of the amino group includes halogen, -Si(C x H 2x+1 )3; substituted or unsubstituted C1-C20 alkoxy refers to a substituted or unsubstituted alkoxy having 1 to 20 carbon atoms, and the substituents of the alkoxy include halogen, amino, -Si(C x H 2x+1 )3, x is an integer from 1 to 20. When a hydrocarbon group having a specific carbon number is specified, all geometric isomers having the carbon number are included. And at least one of R1, R2, R3, and R4 includes a substituted or unsubstituted C1-C20 alkyl group or a substituted or unsubstituted amino group, that is, R1, R2, R3, and R4 may be the same or different, but at least one of R1, R2, R3, and R4 includes a substituted or unsubstituted alkyl group or a substituted or unsubstituted amino group.

[0047] According to the above scheme provided by the present invention, the compound shown in Formula 1 is used to prepare a passivation layer, which can reduce the parasitic absorption of the battery, so that the solar cell has excellent photoelectric conversion efficiency. The inventor analyzed this principle and believed that the reason may be that the compound shown in Formula 1 can react with the dangling bonds on the surface of monocrystalline silicon to generate a passivation layer, achieving a high passivation effect, and after the dangling bonds on the surface of monocrystalline silicon are saturated by the reaction, the surface of the passivation layer no longer generates dangling bonds, which can inhibit the further growth of the compound shown in Formula 1 on the passivation layer, so that the thickness of the passivation layer is not higher than 5nm, thereby effectively reducing parasitic absorption, thereby increasing the short-circuit current of the solar cell and improving the photoelectric conversion efficiency of the battery.

[0048] In a specific embodiment, R1, R2, R3, and R4 are each independently selected from a substituted or unsubstituted C1-C18 alkyl, a halogen, a substituted or unsubstituted amino, or a substituted or unsubstituted C1-C18 alkoxy; the substituents of the alkyl, the amino, and the alkoxy are each independently selected from a halogen, an amino, -Si(C x H 2x+1 )3, x is an integer from 1 to 18. When the substituents of the compound represented by Formula 1 include the above-mentioned substituents, the compound of Formula 1 can react more fully with the dangling bonds on the surface of the single crystal silicon, so that the passivation effect of the passivation layer is better, and at the same time, a passivation layer with a lower thickness can be generated, which further reduces parasitic absorption and makes the photoelectric conversion efficiency of the battery higher.

[0049] In a specific embodiment, the compound shown in Formula 1 includes one of octadecyltrichlorosilane, 3-aminopropyltriethoxysilane, 1H,1H,2H,2H-perfluorooctyltrichlorosilane, hexamethyldisilazane, and octadecyltrimethoxysilane. When the compound of Formula 1 is selected from the above compounds, the passivation effect of the passivation layer generated by the compound of Formula 1 is better, and the further growth of the compound of Formula 1 on the passivation layer can be better suppressed, further reducing the thickness of the passivation layer, making the parasitic absorption of the battery smaller, thereby being able to obtain a higher photoelectric conversion efficiency.

[0050] In a specific embodiment, the thickness of the passivation layer is 2-5 nm, for example, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm or 5 nm, etc. When the thickness of the passivation layer is within the above range, the passivation layer can exhibit excellent passivation efficiency and can effectively reduce the parasitic absorption of the battery, thereby increasing the short-circuit current of the solar cell, thereby further increasing the photoelectric conversion efficiency of the battery.

[0051] In a specific embodiment, the cell comprises a heterojunction solar cell, such as Figure 1 As shown, the heterojunction solar cell includes a first transparent conductive oxide layer 1, an n-type doped silicon layer 2, a passivation layer 3, a single crystal silicon layer 4, a passivation layer 3, a p-type doped silicon layer 5, and a second transparent conductive oxide layer 6 which are stacked in sequence.

[0052] The present invention does not limit the specific selection of the transparent conductive oxide in the first transparent conductive oxide layer and the second transparent conductive oxide layer, as long as the conductivity of the heterojunction solar cell can be improved so that the cell can conduct electricity.

[0053] The present invention does not limit the specific selection of p-type doped silicon and n-type doped silicon in the p-type doped silicon layer and the n-type doped silicon layer, as long as the p-type doped silicon layer and the n-type doped silicon layer form a PN junction so that the heterojunction battery can perform photoelectric conversion.

[0054] The present invention does not limit the specific selection of the single crystal silicon in the single crystal silicon layer, as long as the single crystal silicon can ensure the high photoelectric conversion efficiency of the heterojunction battery.

[0055] The heterojunction battery of the present invention is obtained by stacking the above layers. The passivation layer exhibits an effective passivation effect, and the passivation layer can be well compounded with other layers to stabilize the heterojunction battery. At the same time, the parasitic absorption of the heterojunction battery is low, thereby achieving high photoelectric conversion efficiency.

[0056] In a specific embodiment, the thickness of the first transparent conductive oxide layer and the second transparent conductive oxide layer are both 60-140 nm, for example, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm or 140 nm. It is worth noting that the thickness of the first transparent conductive oxide layer and the second transparent conductive oxide layer can be the same or different, and can be selected according to actual needs. When the thickness of the transparent conductive oxide layer is within the above range, the heterojunction battery has good conductivity, and the overall thickness of the heterojunction battery is small, which is conducive to reducing the parasitic absorption of the battery, so that the photoelectric conversion efficiency of the battery is higher.

[0057] In a specific embodiment, the thickness of the p-type doped silicon layer is 10-30 nm, for example, 10 nm, 15 nm, 20 nm, 25 nm or 30 nm, etc. When the thickness of the p-type doped silicon layer is within the above range, the p-type doped silicon layer can form a PN junction with the n-type doped silicon layer, so that the heterojunction battery can perform photoelectric conversion, and the parasitic absorption of the battery can be reduced, thereby further improving the photoelectric conversion efficiency of the battery.

[0058] In a specific embodiment, the thickness of the n-type doped silicon layer is 10-25 nm, for example, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm or 25 nm, etc. When the thickness of the n-type doped silicon layer is within the above range, the n-type doped silicon layer can form a PN junction with the p-type doped silicon layer, the battery can exert the photoelectric conversion performance, and the parasitic absorption of the battery is lower, the short-circuit current of the battery is higher, so that the photoelectric conversion efficiency of the battery is higher.

[0059] In a specific embodiment, the thickness of the single crystal silicon layer is 50-150 μm, for example, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm or 150 μm, etc. When the thickness of the single crystal silicon layer is within the above range, it can ensure the absorption of light by the cell and reduce the material cost.

[0060] In a specific embodiment, the p-type doped silicon in the p-type doped silicon layer includes at least one of p-type doped amorphous silicon or p-type doped microcrystalline silicon; and / or, the n-type doped silicon in the n-type doped silicon layer includes at least one of n-type doped amorphous silicon, n-type doped microcrystalline silicon and n-type oxygen-doped microcrystalline silicon; and / or, the transparent conductive oxide in the transparent conductive oxide layer includes at least one of transparent conductive oxide ITO, aluminum-doped zinc oxide (AZO), and fluorine-doped tin oxide (FTO); and / or, the single crystal silicon layer includes at least one of an n-type single crystal silicon layer and a p-type single crystal silicon layer. When the p-type doped silicon layer, the n-type doped silicon layer and the single crystal silicon layer are selected from the above silicon materials, the p-type doped silicon layer, the n-type doped silicon layer and the single crystal silicon layer can be reasonably matched to effectively form a PN junction, and the above doped layer can improve the conductivity of the doped layer and reduce the parasitic absorption of the doped layer, thereby improving the conversion efficiency of the heterojunction battery.

[0061] In a specific embodiment, the heterojunction battery is prepared by a method comprising the following steps:

[0062] Placing single crystal silicon in a vapor atmosphere of a compound having a structural formula shown in Formula 1 and performing a heating treatment to obtain single crystal silicon including a passivation layer, and then depositing an n-type doped silicon layer and a p-type doped silicon layer on the front and back surfaces of the single crystal silicon including the passivation layer, respectively, and then depositing a first transparent conductive oxide layer on a side of the n-type doped silicon layer away from the passivation layer, and depositing a second transparent conductive oxide layer on a side of the p-type doped silicon layer away from the passivation layer, to obtain a heterojunction battery;

[0063] The vacuum degree of the heating treatment is 10 -4 -10 -1 Pa, heating temperature is 100-180℃, heating time is 40-60min.

[0064] Specifically, the single crystal silicon is placed in a sealed environment, and then the compound of formula 1 is added dropwise to the sealed environment for heating. The single crystal silicon is placed in a vapor atmosphere of the compound of formula 1 and the heating treatment is continued. The vacuum degree of the sealed environment is 10 -4 -10 -1The heating temperature is 100-180°C, for example, 100°C, 110°C, 120°C, 130°C, 140°C, 150°C, 160°C, 170°C or 180°C, and the heating time is 40-60min, for example, 40min, 42min, 44min, 46min, 5 0min, 52min, 54min, 56min, 58min or 60min, etc., to obtain a single crystal silicon including a passivation layer; subsequently, an n-type doped silicon layer is deposited on the front side of the single crystal silicon including the passivation layer, and a p-type doped silicon layer is deposited on the back side of the n-type single crystal silicon including the passivation layer, and then a first transparent conductive oxide layer is deposited on a side of the n-type doped silicon layer away from the passivation layer, and a second transparent conductive oxide layer is deposited on a side of the p-type doped silicon layer away from the passivation layer, to obtain a heterojunction battery.

[0065] The present invention can also process the monocrystalline silicon by a method including the following processes before depositing the passivation layer: cleaning the surface of the monocrystalline silicon wafer, removing pollution and line marks, using alkali solution for texturing, forming a surface pyramid anti-reflection structure, and then performing RCA cleaning (industrial standard wet cleaning process), and obtaining a texturing sheet after drying; then placing the texturing sheet in a plasma cleaning machine for plasma treatment, the processing power is 0.1-1W, for example, 0.1W, 0.2W, 0.3W, 0.4W, 0.5W, 0.6W, 0.7W, 0.8W, 0.9W or 1W, and the processing time is 1-10s, for example, 1s, 2s, 3s, 4s, 5s, 6s, 7s, 8s, 9s or 10s, etc., to obtain monocrystalline silicon. The above operation can remove organic impurities on the surface of the monocrystalline silicon, and can increase the surface hydrophilicity of the monocrystalline silicon, which is conducive to the large-area uniform growth of the compound of formula 1 on the surface of the monocrystalline silicon.

[0066] The present invention does not limit the size of the single crystal silicon, which can be selected according to actual needs. For example, a 166 mm*166 mm square silicon wafer (M6), a 182 mm*182 mm square silicon wafer, or a 210 mm*210 mm square silicon wafer (G12) can be selected. The above standard silicon wafers can also be cut into experimental pieces of any size.

[0067] The present invention does not limit the amount of the compound of Formula 1 to be added, as long as a passivation layer of sufficient thickness can be formed on the surface of the single crystal silicon.

[0068] The present invention is not limited to the specific operation of depositing n-type doped silicon layers and p-type doped silicon layers on the front and back surfaces of the single crystal silicon including the passivation layer, and can be selected according to actual needs, as long as sufficiently thick n-type doped silicon layers and p-type doped silicon layers can be deposited on the surface of the passivation layer. For example, plasma enhanced chemical vapor deposition (PECVD) can be selected for deposition.

[0069] The present invention does not limit the specific operation of depositing the transparent conductive oxide layer on the surface of the n-type doped silicon layer and the p-type doped silicon layer, and can be selected according to actual needs. For example, physical vapor deposition (PVD) can be selected, with an operating temperature of 20-180° C. and an operating pressure of 0.01-0.6 Pa.

[0070] The present invention further comprises preparing a grid line silver electrode by screen printing or preparing a copper electrode by copper electroplating after depositing the transparent conductive oxide layer.

[0071] The present invention can prepare a heterojunction battery through the above method. The heterojunction battery has high photoelectric conversion efficiency, and the preparation method is simple to operate, has low equipment requirements, is environmentally friendly, and is conducive to the large-scale production of the heterojunction battery.

[0072] In a specific embodiment, the battery comprises a Topcon battery, which comprises SiN x Anti-reflection layer, passivation layer, p+ doped single crystal silicon layer, n-doped single crystal silicon layer, tunneling oxide layer, n+ doped polysilicon layer and SiN x Anti-reflection layer.

[0073] SiN of the present invention x The anti-reflection layer is an anti-reflection film that can reduce the reflection of light on the surface of the Topcon battery, increase the amount of light penetrating into the battery, improve the utilization rate of light, and thus improve the photoelectric conversion efficiency.

[0074] The present invention does not limit the specific selection of silicon materials in the p+ doped single crystal silicon layer and the n+ doped polycrystalline silicon layer, as long as the p+ doped single crystal silicon layer and the n+ doped polycrystalline silicon layer form a PN junction so that the Topcon cell can perform photoelectric conversion.

[0075] The present invention does not limit the specific selection of materials in the tunnel oxide layer, as long as the tunnel oxide layer can prevent minority hole recombination, reduce charge carrier loss and avoid direct contact between metal and semiconductor to cause electrochemical reaction.

[0076] The Topcon battery of the present invention is obtained by stacking the above layers. The passivation layer can show an effective passivation effect, blocking the passage of minority carriers, allowing majority carriers to pass unimpeded, reducing carrier recombination, and at the same time, the parasitic absorption of the Topcon battery is low, so that the Topcon battery has a high photoelectric conversion efficiency.

[0077] In a specific embodiment, the battery includes a heterojunction / perovskite stack battery, which includes a transparent conductive oxide layer, an electron transport layer, a perovskite layer, a hole transport layer, a passivation layer, an n-type doped microcrystalline silicon layer, a passivation layer, an n-type single crystal silicon layer, a passivation layer, a p-type doped microcrystalline silicon layer and a transparent conductive oxide layer stacked in sequence.

[0078] The present invention does not limit the specific selection of the transparent conductive oxide in the transparent conductive oxide layer, as long as the conductivity of the heterojunction / perovskite stacked battery can be improved so that the battery can conduct electricity.

[0079] The present invention does not limit the specific selection of the material of the electron transport layer, as long as the electron transport layer has high electron mobility and can quickly guide the photogenerated electrons generated by the perovskite layer to reduce electron recombination.

[0080] The present invention does not limit the specific selection of the material of the perovskite layer, as long as the perovskite layer can absorb photons and generate excitons.

[0081] The present invention does not limit the specific selection of the material of the hole transport layer, as long as the hole transport layer can effectively collect and transport holes, realize the effective separation of electrons and holes and protect the perovskite layer.

[0082] The heterojunction / perovskite stacked cell of the present invention is obtained by stacking the above layers. The passivation layer achieves an effective passivation effect in the heterojunction / perovskite stacked cell. At the same time, the parasitic absorption of the heterojunction / perovskite stacked cell is low, so that the heterojunction / perovskite stacked cell exhibits high photoelectric conversion efficiency.

[0083] The present invention provides a solar cell assembly, which is prepared based on the above-mentioned battery, has excellent photoelectric conversion performance, and can be widely used in the photovoltaic industry.

[0084] Hereinafter, the present invention will be further described in detail through specific examples.

[0085] Example 1

[0086] The method for preparing the battery of this embodiment comprises the following steps:

[0087] 1. Clean the surface of an n-type doped single crystal silicon wafer with a size of 166 mm*166 mm and a thickness of 120 μm to remove contamination and line marks, use alkali solution to make a texture, form a surface pyramid anti-reflection structure, and then perform RCA cleaning to obtain a textured wafer; then perform plasma treatment on the textured wafer with a power of 0.1 W and a treatment time of 10 s to obtain an n-type doped single crystal silicon wafer;

[0088] 2. Place the n-type doped single crystal silicon wafer in a vacuum drying oven and evacuate to vacuum (10 -2 Pa), and then 5 mL of octadecyltrichlorosilane (OTS) was dripped into a vacuum drying oven for heating at a temperature of 100°C for 60 min to obtain an n-type doped single crystal silicon wafer including a passivation layer; the thickness of the passivation layer was 4 nm;

[0089] 3. Perform PECVD treatment on the front and back sides of the n-type doped single crystal silicon wafer including the passivation layer, respectively, to deposit an n-type doped amorphous silicon layer with a thickness of 18 nm and a p-type doped amorphous silicon layer with a thickness of 20 nm;

[0090] 4. The silicon wafer after PECVD treatment is subjected to magnetron sputtering coating treatment, and ITO is deposited on the surface of the n-type doped amorphous silicon layer and the p-type doped amorphous silicon layer respectively. Then, the gate line silver electrode is prepared by screen printing to obtain a heterojunction battery; the thickness of the first transparent conductive oxide layer and the second transparent conductive oxide layer are both 80nm.

[0091] Example 2

[0092] The preparation method of the battery of this embodiment is substantially the same as that of Embodiment 1, except that 3-aminopropyltriethoxysilane is used to prepare the passivation layer.

[0093] Example 3

[0094] The preparation method of the battery of this embodiment is substantially the same as that of Embodiment 1, except that 1H,1H,2H,2H-perfluorooctyltrichlorosilane is used to prepare the passivation layer.

[0095] Example 4

[0096] The preparation method of the battery of this embodiment is substantially the same as that of Embodiment 1, except that hexamethyldisilazane is used to prepare the passivation layer.

[0097] Example 5

[0098] The preparation method of the battery of this embodiment is substantially the same as that of Embodiment 1, except that octadecyltrimethoxysilane is used to prepare the passivation layer.

[0099] Example 6

[0100] The preparation method of the battery of this embodiment is substantially the same as that of the embodiment 1, except that the thickness of the passivation layer is 2 nm.

[0101] Example 7

[0102] The preparation method of the battery of this embodiment is substantially the same as that of embodiment 1, except that the thickness of the passivation layer is 5 nm.

[0103] Example 8

[0104] The preparation method of the battery of this embodiment is substantially the same as that of the embodiment 1, except that the thickness of the passivation layer is 1 nm.

[0105] Example 9

[0106] The preparation method of the battery of this embodiment is substantially the same as that of the embodiment 1, except that the thickness of the passivation layer is 6 nm.

[0107] Example 10

[0108] The preparation method of the battery in this embodiment is substantially the same as that in Embodiment 1, except that the thickness of the transparent conductive oxide layer is 60 nm.

[0109] Embodiment 11

[0110] The preparation method of the battery in this embodiment is substantially the same as that in Embodiment 1, except that the thickness of the transparent conductive oxide layer is 140 nm.

[0111] Example 12

[0112] The preparation method of the battery of this embodiment is substantially the same as that of the embodiment 1, except that the thickness of the transparent conductive oxide layer is 150 nm.

[0113] Embodiment 13

[0114] The preparation method of the battery of this embodiment is substantially the same as that of the embodiment 1, except that the thickness of the p-type doped silicon layer is 10 nm.

[0115] Embodiment 14

[0116] The preparation method of the battery of this embodiment is substantially the same as that of the embodiment 1, except that the thickness of the p-type doped silicon layer is 30 nm.

[0117] Embodiment 15

[0118] The preparation method of the battery of this embodiment is substantially the same as that of the embodiment 1, except that the thickness of the p-type doped silicon layer is 40 nm.

[0119] Example 16

[0120] The preparation method of the battery of this embodiment is substantially the same as that of the embodiment 1, except that the thickness of the n-type doped silicon layer is 10 nm.

[0121] Embodiment 17

[0122] The preparation method of the battery of this embodiment is substantially the same as that of the embodiment 1, except that the thickness of the n-type doped silicon layer is 25 nm.

[0123] Embodiment 18

[0124] The preparation method of the battery of this embodiment is substantially the same as that of the embodiment 1, except that the thickness of the n-type doped silicon layer is 30 nm.

[0125] Embodiment 19

[0126] The preparation method of the battery of this embodiment is substantially the same as that of the embodiment 1, except that p-type doped microcrystalline silicon and n-type doped microcrystalline silicon are deposited on the surface of the passivation layer, and aluminum-doped zinc oxide is used as the transparent conductive oxide.

[0127] Embodiment 20

[0128] The preparation method of the battery in this embodiment is substantially the same as that in embodiment 1, except that the vacuum degree of the heating treatment is 10 -4 Pa, heating temperature is 180℃, heating time is 40min.

[0129] Embodiment 21

[0130] The preparation method of the battery in this embodiment is substantially the same as that in embodiment 1, except that the vacuum degree of the heating treatment is 10 -1 Pa, the heating temperature is 150℃ and the heating time is 50min.

[0131] Embodiment 22

[0132] The preparation method of the battery of this embodiment is substantially the same as that of embodiment 1, except that the vacuum degree of the heating treatment is 0.2 Pa, the heating temperature is 200° C., and the heating time is 30 min.

[0133] Embodiment 23

[0134] The method for preparing the battery of this embodiment comprises the following steps:

[0135] 1. Cleaning and texturing: Clean the surface of N-type monocrystalline silicon wafers to remove contamination and line marks, use alkali solution for texturing to form a surface pyramid anti-reflection structure, and then perform RCA cleaning;

[0136] 2. Boron diffusion to prepare the front p+ emitter: Boron trichloride is used as the boron source to diffuse at high temperature in a low-pressure tube furnace to form the front p+ emitter and borosilicate glass. The diffusion temperature is 1000℃ and the time is 2h. The final diffusion depth is 1.0μm and the doping concentration is 10 19 / cm 2 , p+ emitter with square resistance of 150Ω / sq;

[0137] 3. Back alkali polishing: Use hydrofluoric acid to remove the borosilicate glass on the back, and use alkali solution to polish the back surface;

[0138] 4. Preparation of tunneling oxide layer: A tunneling oxide layer with a thickness of 2 nm was deposited on the back side by high-temperature thermal oxidation in a tubular quartz furnace at a temperature of 600 °C for 20 min.

[0139] 5. Deposition of phosphorus, carbon / nitrogen co-doped polysilicon layer: Prepared by PECVD, silane, hydrogen, phosphine, methane and ammonia are introduced during deposition to prepare phosphorus, carbon / nitrogen co-doped amorphous silicon, and then annealed and crystallized at 800℃ in a tube furnace to form a doped polysilicon layer with a thickness of 100nm and a phosphorus doping concentration of 10 19 / cm 2 , square resistance is 150Ω / sq;

[0140] 6. Cleaning: Use alkali solution to remove the polysilicon coated on the front side, use hydrofluoric acid to remove the phosphosilicate glass and borosilicate glass on the front side, perform RCA cleaning to remove the excess phosphosilicate glass on the back side;

[0141] 7. Front passivation layer: Place the cell in step 6 in a vacuum drying oven and evacuate to vacuum (10 -2 Pa), and then 5 mL of octadecyltrichlorosilane (OTS) was dripped into a vacuum drying oven for heating at a temperature of 100°C for 60 min to obtain an n-type doped single crystal silicon wafer including a passivation layer; the thickness of the passivation layer was 4 nm;

[0142] 8. Preparation of front and back anti-reflection layers: The front anti-reflection layers of silicon nitride, silicon oxynitride and silicon oxide are prepared by PECVD, with silane, ammonia and nitrous oxide as the gas source, and a 100nm thick anti-reflection layer is deposited at 500°C;

[0143] 9. Electrode metallization: Screen print silver paste and sinter at 800℃ to form front and back electrodes. The printing position is above the polysilicon.

[0144] Embodiment 24

[0145] The method for preparing the battery of this embodiment comprises the following steps:

[0146] 1. Use RCA solution to texturize an n-type doped single crystal silicon wafer with a size of 166 mm*166 mm and a thickness of 120 μm, and then perform cleaning and drying to obtain a texturized wafer; then perform plasma treatment on the texturized wafer with a power of 0.1 W and a treatment time of 10 s to obtain an n-type doped single crystal silicon wafer;

[0147] 2. Place the n-type doped single crystal silicon wafer in a vacuum drying oven and evacuate to vacuum (10 -2Pa), and then 5 mL of octadecyltrichlorosilane (OTS) was dripped into a vacuum drying oven for heating at a temperature of 100°C for 60 min to obtain an n-type doped single crystal silicon wafer including a passivation layer; the thickness of the passivation layer was 4 nm;

[0148] 3. Perform PECVD treatment on the front and back sides of the n-type doped single crystal silicon wafer including the passivation layer, respectively, to deposit an n-type doped amorphous silicon layer with a thickness of 18 nm and a p-type doped amorphous silicon layer with a thickness of 20 nm;

[0149] 4. The silicon wafer after PECVD treatment is subjected to magnetron sputtering coating treatment, and an ITO film layer with a thickness of 80 nm is deposited on the surface of the p-type doped amorphous silicon layer;

[0150] 5. Repeat step 2 to prepare a 2nm OTS passivation layer on the surface of the n-type doped amorphous silicon layer, and then use thermal evaporation to prepare NiO with a thickness of 20nm. x A hole transport layer, a perovskite layer with a thickness of 100 nm, and a SnO electron transport layer with a thickness of 20 nm;

[0151] 6. Use magnetron sputtering equipment to deposit an 80nm ITO film layer on the front side of the cell in step 5, and then use screen printing to prepare the front and back silver grid lines to form the final laminated cell.

[0152] Comparative Example 1

[0153] The preparation method of the battery of this comparative example comprises the following steps:

[0154] 1. Clean the surface of a 166 mm*166 mm, 120 μm thick n-type doped single crystal silicon wafer to remove contamination and line marks, use alkali solution to make a texture to form a surface pyramid anti-reflection structure, and then perform RCA cleaning to obtain a textured wafer;

[0155] 2. Place the n-type doped single crystal silicon textured sheet into a PECVD (plasma enhanced chemical vapor deposition) chamber, and coat the front and back surfaces of the textured sheet with a hydrogenated amorphous silicon passivation layer with a thickness of 5nm and 7nm respectively;

[0156] 3. Perform PECVD treatment on the front and back sides of the n-type doped single crystal silicon wafer including the passivation layer, respectively, to deposit an n-type doped amorphous silicon layer with a thickness of 18 nm and a p-type doped amorphous silicon layer with a thickness of 20 nm;

[0157] 4. The silicon wafer after PECVD treatment is subjected to magnetron sputtering coating treatment, and ITO is deposited on the surface of the n-type doped amorphous silicon layer and the p-type doped amorphous silicon layer respectively. Then, the gate line silver electrode is prepared by screen printing to obtain a heterojunction battery; the thickness of the transparent conductive oxide layer is 80nm.

[0158] Comparative Example 2

[0159] The preparation method of the battery of this comparative example comprises the following steps:

[0160] 1. Cleaning and texturing: Clean the surface of N-type monocrystalline silicon wafers to remove contamination and line marks, use alkali solution for texturing to form a surface pyramid anti-reflection structure, and then perform RCA cleaning;

[0161] 2. Boron diffusion to prepare the front p+ emitter: Boron trichloride is used as the boron source to form the front p+ emitter and borosilicate glass by high-temperature diffusion in a low-pressure tube furnace. The diffusion temperature is 1000 °C and the time is 2 hours. The final diffusion depth is 1.0 μm and the doping concentration is 10 19 / cm 2 , p+ emitter with square resistance of 150Ω / sq;

[0162] 3. Back alkali polishing: Use hydrofluoric acid to remove the borosilicate glass on the back, and use alkali solution to polish the back surface;

[0163] 4. Preparation of tunneling oxide layer: A tunneling oxide layer with a thickness of 2 nm was deposited on the back side by high-temperature thermal oxidation in a tubular quartz furnace at a temperature of 600 °C for 20 min.

[0164] 5. Deposition of phosphorus, carbon / nitrogen co-doped polysilicon layer: Prepared by PECVD, silane, hydrogen, phosphine, methane and ammonia are introduced during deposition to prepare phosphorus, carbon / nitrogen co-doped amorphous silicon, and then annealed and crystallized at 800℃ in a tube furnace to form a doped polysilicon layer with a thickness of 100nm and a phosphorus doping concentration of 10 19 / cm 2 , square resistance is 150Ω / sq;

[0165] 6. Cleaning: Use alkali solution to remove the polysilicon coated on the front side, use hydrofluoric acid to remove the phosphosilicate glass and borosilicate glass on the front side, perform RCA cleaning to remove the excess phosphosilicate glass on the back side;

[0166] 7. Preparation of the front passivation layer: Aluminum oxide is deposited on the front using the atomic layer deposition method. Trimethylaluminum and water are circulated at 250°C to prepare an aluminum oxide layer with a thickness of 10nm.

[0167] 8. Preparation of anti-reflection layer: The front anti-reflection layer containing silicon nitride, silicon oxynitride and silicon oxide is prepared by PECVD, and the gas source is silane, ammonia and nitrous oxide, and the anti-reflection layer with a thickness of 100nm is deposited at 500°C;

[0168] 9. Electrode metallization: Screen print silver paste and sinter at 800℃ to form front and back electrodes. The printing position is above the polysilicon layer.

[0169] Comparative Example 3

[0170] The preparation method of the battery of this comparative example comprises the following steps:

[0171] 1. Clean the surface of a 166 mm*166 mm, 120 μm thick n-type doped single crystal silicon wafer to remove contamination and line marks, use alkali solution to make a texture to form a surface pyramid anti-reflection structure, and then perform RCA cleaning to obtain a textured wafer;

[0172] 2. Place the n-type doped single crystal silicon textured sheet into a PECVD (plasma enhanced chemical vapor deposition) chamber, and coat the front and back surfaces of the textured sheet with a hydrogenated amorphous silicon passivation layer with a thickness of 5nm and 7nm respectively;

[0173] 3. Perform PECVD treatment on the front and back sides of the n-type doped single crystal silicon wafer including the passivation layer, respectively, to deposit an n-type doped amorphous silicon layer with a thickness of 18 nm and a p-type doped amorphous silicon layer with a thickness of 20 nm;

[0174] 4. The silicon wafer after PECVD treatment is subjected to magnetron sputtering coating treatment, and ITO is deposited on the surface of the n-type doped amorphous silicon layer and the p-type doped amorphous silicon layer respectively. Then, the gate line silver electrode is prepared by screen printing to obtain a heterojunction battery; the thickness of the transparent conductive oxide layer is 80nm.

[0175] Test example

[0176] The photoelectric conversion efficiency of the cells of the embodiment and the comparative example was tested using a solar cell IV test device, the national standard number of the test is IEC 61215, and the test results are shown in Table 1.

[0177] Table 1

[0178]

[0179] The above results show that the passivation layer of the present invention can significantly increase the short-circuit current (Isc) while ensuring the effect of the passivation layer, that is, ensuring that the open-circuit voltage (Voc) does not decrease, thereby improving the photovoltaic conversion efficiency of the cell. For example, the open-circuit voltages of Example 1 and Comparative Example 1 are almost the same, while the short-circuit current is increased by 0.39A. Example 23 and Comparative Example 2, and Example 24 and Comparative Example 3 can all illustrate the above conclusion.

[0180] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A battery, characterized in that: The battery comprises a passivation layer and a single crystal silicon layer, wherein the passivation layer exists on the surface of the single crystal silicon layer; and the passivation layer comprises a compound shown in Formula 1: Formula 1 Wherein, R1, R2, R3, and R4 are each independently selected from a substituted or unsubstituted C1-C20 alkyl group, a halogen, a substituted or unsubstituted amino group, and a substituted or unsubstituted C1-C20 alkoxy group, and at least one of R1, R2, R3, and R4 includes the substituted or unsubstituted C1-C20 alkyl group or the substituted or unsubstituted amino group; The substituents of the alkyl group, the amino group and the alkoxy group are each independently selected from halogen, amino, -Si(C x H 2x+1 )3, x is an integer from 1 to 20.

2. The battery according to claim 1, characterized in that R1, R2, R3, and R4 are each independently selected from a substituted or unsubstituted C1-C18 alkyl, halogen, substituted or unsubstituted amino, or a substituted or unsubstituted C1-C18 alkoxy; the substituent of the alkyl, the substituent of the amino, and the substituent of the alkoxy are each independently selected from a halogen, an amino, -Si(C x H 2x+1 )3, x is an integer from 1 to 18.

3. The battery according to claim 2, characterized in that The compound represented by Formula 1 includes one of octadecyltrichlorosilane, 3-aminopropyltriethoxysilane, 1H,1H,2H,2H-perfluorooctyltrichlorosilane, hexamethyldisilazane, and octadecyltrimethoxysilane.

4. The battery according to claim 3, characterized in that The thickness of the passivation layer is 2-5 nm.

5. The battery according to claim 4, characterized in that The battery comprises a first transparent conductive oxide layer, an n-type doped silicon layer, the passivation layer, a single crystal silicon layer, the passivation layer, a p-type doped silicon layer, and a second transparent conductive oxide layer which are stacked in sequence.

6. The battery according to claim 5, characterized in that The thickness of the first transparent conductive oxide layer is 60-140 nm; And / or, the thickness of the p-type doped silicon layer is 10-30 nm; And / or, the thickness of the n-type doped silicon layer is 10-25 nm; And / or, the thickness of the single crystal silicon layer is 50-150 μm; And / or, the second transparent conductive oxide layer has a thickness of 60-140 nm.

7. The battery according to claim 6, characterized in that The p-type doped silicon in the p-type doped silicon layer includes at least one of p-type doped amorphous silicon and p-type doped microcrystalline silicon; And / or, the n-type doped silicon in the n-type doped silicon layer includes at least one of n-type doped amorphous silicon, n-type doped microcrystalline silicon and n-type oxygen-doped microcrystalline silicon; And / or, the transparent conductive oxide in the transparent conductive oxide layer includes at least one of transparent conductive oxide ITO, aluminum-doped zinc oxide, and fluorine-doped tin oxide; And / or, the single crystal silicon layer includes at least one of an n-type single crystal silicon layer and a p-type single crystal silicon layer.

8. The battery according to claim 7, characterized in that The battery is prepared by a method comprising the following steps: placing single crystal silicon in a vapor atmosphere of the compound represented by Formula 1 and performing a heating treatment to obtain single crystal silicon including the passivation layer, then depositing an n-type doped silicon layer and a p-type doped silicon layer on the front and back surfaces of the single crystal silicon including the passivation layer, respectively, and then depositing the first transparent conductive oxide layer on the side of the n-type doped silicon layer away from the passivation layer, and depositing the second transparent conductive oxide layer on the side of the p-type doped silicon layer away from the passivation layer, to obtain the battery; The vacuum degree of the heating treatment is 10 -4 -10 -1 Pa, heating temperature is 100-180℃, heating time is 40-60min.

9. The battery according to claim 4, characterized in that The battery includes SiN x The anti-reflection layer, the passivation layer, the p+ doped single crystal silicon layer, the n-doped single crystal silicon layer, the tunneling oxide layer, the n+ doped polysilicon layer and the SiN x Anti-reflection layer.

10. The battery according to claim 4, characterized in that The battery includes a transparent conductive oxide layer, an electron transport layer, a perovskite layer, a hole transport layer, the passivation layer, an n-type doped microcrystalline silicon layer, the passivation layer, an n-type single crystal silicon layer, the passivation layer, a p-type doped microcrystalline silicon layer and a transparent conductive oxide layer which are stacked in sequence.

11. A solar cell module, characterized in that: The solar cell module comprises the cell according to any one of claims 1 to 10.

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