An integrated circuit ATE-related board-level testing method

Abstract

An integrated circuit ATE-associated board-level test method relates to the field of integrated circuit testing technology, including: S1, determining ATE test parameters; S2, determining test samples according to the test parameters; S3, numbering all test samples; S4, performing ATE tests on the test samples to obtain ATE test data; S5, selecting EVB test samples according to the ATE test data; S6, performing EVB tests to obtain EVB test data; S7, performing consistency analysis on ATE test data and EVB test data; S8, updating or setting ATE test thresholds by presetting margin strategies. The present invention uses the correlation between ATE and EVB board-level associations to adjust the ATE test threshold, reduces unnecessary yield loss, improves the rationality and accuracy of test standards, and further improves the efficiency of ATE testing.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and in particular to an integrated circuit ATE-related board-level testing method. Background Art

[0002] Integrated circuit testing plays an important role in the integrated circuit industry chain. However, there are many factors that may cause differences in test results during the testing process, such as environment, test procedures, hardware configuration, test platform, etc. If these differences are not handled, they may have a certain degree of impact on mass production yield.

[0003] A. Differences between ATE test environment and EVB test environment

[0004] Generally speaking, in the large-scale production test process of integrated circuits, dedicated ATE test platforms must be used. Such platforms are usually deployed on large-scale production lines of professional packaging plants or test manufacturers. There are significant differences between the ATE test environment and the internal EVB test environment of chip design companies:

[0005] ATE testing is mainly carried out in specialized highly automated testing factories. Multiple test stations (Sites) are configured to achieve parallel testing, thereby greatly improving test efficiency. Due to the needs of multiple sites, the LB board used by ATE often adopts a multi-layer or even dozens of layers of PCB design. At the same time, due to the requirements of sorting machine assembly, the top layer of the LB board centered on the DUT is generally not allowed to place peripheral devices. When problems occur during testing, peripheral devices need to be checked one by one as potential factors, which increases the difficulty of troubleshooting. In order to reduce potential sources of interference, unnecessary peripheral circuits are generally minimized. Although this is conducive to quickly locking the source of the problem when the yield fluctuates or problems occur, and reducing the challenges of peripheral device selection under high and low temperature test environment requirements, it is disadvantageous from the perspective of signal integrity.

[0006] In contrast, EVB testing is generally used for internal verification and comprehensive evaluation of the overall function and performance of the chip within the design company (TEST board), or for design companies to show customers the working principles and application potential of new technologies and new products, helping customers to develop prototypes, verify concepts and introduce new products faster (Demo board). Therefore, in addition to the target chip itself, the EVB test environment also integrates necessary and complete peripheral circuits, interface components and protection devices. The design purpose of these two board-level environments is to objectively evaluate or demonstrate the performance characteristics of the target chip based on the most ideal conditions possible.

[0007] The differences between ATE and EVB test results are due to many factors, including but not limited to: the difference between multi-chip parallel testing and single-chip independent testing, the difference between complex multi-layer wiring and simple single-layer or double-layer wiring, the difference between single-sided device assembly and double-sided device assembly, the difference between simplified decoupling capacitor configuration and perfect decoupling capacitor configuration, the difference between streamlined peripheral circuits and complete peripheral circuits, and the difference in electromagnetic characteristics between factory test environment and laboratory test environment. The results of these differences are obvious: although ATE testing has fast data acquisition and is suitable for AC\DC parameter measurement, the test accuracy is relatively moderate, and the accuracy of parameters of some test items may be inferior to EVB test results, and some items are even difficult to effectively test on ATE.

[0008] B. Differences caused by program and hardware iterations

[0009] During the mass production of chip products, the program and hardware will be upgraded and iterated for some reasons. These actions may also lead to some intuitive differences or some statistical differences. Similarly, when these differences cannot be ignored, ATE needs to perform correlation tests and take countermeasures to deal with these differences.

[0010] C. Differences caused by platform switching

[0011] Chip products may go through different stages from development and debugging to factory production in the early stage of mass production. The mass production process may also be transferred to the test factory or platform due to technical or commercial factors. The results of cross-platform testing of the same product may have some intuitive or statistical differences. Similarly, when these differences cannot be ignored, related activities need to be carried out to deal with them.

[0012] D. Differences caused by other factors in the product life cycle

[0013] During the mass production process of chip products throughout their life cycle, there will be changes in processes or materials, differences in consistency between batches, changes in climatic conditions, and parameter migration of the machine itself over its lifespan.

[0014] The industry's response strategies to the above phenomenon can be summarized into three levels: 1. Lack of cognition and neglect effect: Some practitioners may not be fully aware of the impact of such environmental differences on test results, or may not consider it due to limited understanding. In this case, no targeted ATE and board-level correlation analysis is carried out, and the resulting yield loss is not effectively recovered. 2. Limited experience and local optimization: Due to a lack of thorough understanding of the principles and the lack of appropriate methodological support, some practitioners only focus on iterative optimization of the software and hardware of the ATE test environment. For example, inexperienced ATE development engineers may not fully realize the inevitability of differences between the ATE environment and the board-level environment, and tend to mechanically apply product design indicators directly to ATE test threshold settings. When faced with test projects that are sensitive to environmental changes and have small margins, even if a lot of effort is invested in multiple improvements to the ATE test program and hardware facilities, the ideal effect may not be achieved due to failure to fundamentally solve the problem. 3. Lack of overall and coherent strategic planning: Some practitioners fail to comprehensively and systematically consider the above issues and formulate ATE correlation strategies covering the entire life cycle of chip products. In practice, ATE-related research has only been conducted on some cases, and no complete solution has been formed, which to some extent limits the management and control of the yield of the product throughout its life cycle.

[0015] The difference between ATE and board level is generally the most significant and influential of the aforementioned differences. As mentioned above, the first association between ATE and board level is still part of ATE development activities. The ATE program and related data and conclusions produced by it are also the baseline reference version for subsequent ATE program iteration upgrades and ATE association activities. Therefore, the association between ATE and board level is also the most important association node in the entire life cycle of the product, and therefore serves as the core research and solution object in the method of the present invention. Summary of the invention

[0016] In order to overcome the deficiencies in the background technology, the present invention discloses an integrated circuit ATE associated board-level testing method.

[0017] In order to achieve the above-mentioned invention object, the present invention adopts the following technical scheme:

[0018] An integrated circuit ATE-related board-level testing method, comprising:

[0019] S1. Determine ATE test parameters, where the test parameters are parameters associated with the ATE and the EVB board level;

[0020] S2. Determine the test conditions and sampling scheme of the integrated circuit according to the test parameters, and obtain the test samples through the sampling scheme;

[0021] S3. Number all test samples;

[0022] S4, performing ATE testing on the test sample according to the test conditions to obtain ATE test data;

[0023] S5. Selecting EVB test samples from the ATE test data according to a selection scheme, wherein the EVB test samples include boundary test samples and intermediate test samples;

[0024] S6, performing an EVB test on the EVB test sample to obtain EVB test data;

[0025] S7, performing consistency analysis on the ATE test data and the EVB test data to determine the ATE test reference benchmark and the fixed difference gap, wherein the reference benchmark includes a reference benchmark upper limit UTL' and a reference benchmark lower limit LTL';

[0026] S8. Update or set the ATE test threshold by using a preset margin strategy in combination with the reference benchmark of the ATE test and the fixed difference gap.

[0027] Specifically, the test parameters in step S1 include Class I parameters and Class II parameters, the Class I parameters include Jitter, SNR, and ENOB, and the Class II parameters include IDDQ and Vmin.

[0028] Specifically, the test conditions in step S2 include process, voltage, temperature, and different condition combinations are adopted for different test parameters; the sampling scheme is simple random sampling.

[0029] Specifically, the ATE test data in step S4 is the value corresponding to the test parameter obtained after the test sample is subjected to ATE testing.

[0030] Specifically, the selection scheme in step S5 is as follows: preferentially selecting test samples whose ATE test data are at the boundary of the performance parameters as boundary test samples, and then selecting test samples in some middle areas as middle test samples.

[0031] Specifically, the EVB test data in step S6 is a value corresponding to the test parameter obtained after the EVB test sample is subjected to an EVB test; and the board used for the EVB test is a PCB board.

[0032] Specifically, step S7 includes:

[0033] Determine the upper boundary evaluation value and the lower boundary evaluation value of the Class II parameter that the EVB test sample meets the specification requirements according to the EVB test data, and use the upper boundary evaluation value as the reference benchmark upper limit UTL' of the ATE test and use the lower boundary evaluation value as the reference benchmark lower limit LTL' of the ATE test;

[0034] The upper boundary evaluation value is a reference value corresponding to a boundary sample showing an upper boundary critical pass state in an EVB test;

[0035] The lower boundary evaluation value is a reference value corresponding to a boundary sample that exhibits a lower boundary critical pass state in an EVB test.

[0036] Specifically, step S7 further includes: the type I parameter test data in the ATE test data and the EVB test data are linearly correlated;

[0037] The Class I parameter test data in the ATE test data and the EVB test data are arranged in sequence and analyzed uniformly through Excel, and the linear relationship between the two groups of test data is tested through Excel tools. If the linear relationship between the two groups of test data is good, the difference between the two groups of test data is calculated as the fixed difference gap.

[0038] Specifically, step S7 further includes: arranging the type I parameter test data in the ATE test data and the EVB test data in order and performing unified analysis further includes:

[0039] If the linear relationship between the two sets of test data is poor, check whether there are abnormalities in the ATE and EVB environments at the same time;

[0040] If outlier data appear during the analysis process, further analysis and retesting will be performed on the outlier data until it is improved or eliminated.

[0041] Specifically, step S8 includes: the preset margin strategy includes a first margin strategy and a second margin strategy;

[0042] The first margin strategy and the second margin strategy both adopt a guard band;

[0043] The reference benchmark of the ATE test is adjusted by the safety margin introduced by the second margin strategy to obtain the test threshold of the Class II parameter;

[0044] The fixed difference gap is used as a component of the first margin strategy to adjust the specification threshold to obtain the test threshold of the Class I parameter.

[0045] The present invention provides an integrated circuit ATE-associated board-level test method, comprising the following steps: S1, determining ATE test parameters; S2, determining the test conditions and sampling scheme of the integrated circuit according to the test parameters, and obtaining test samples through the sampling scheme; S3, numbering all test samples; S4, performing ATE test on the test samples according to the test conditions to obtain ATE test data; S5, selecting EVB test samples from the ATE test data according to the selection scheme, the EVB test samples including boundary test samples and intermediate test samples; S6, performing EVB test on the EVB test samples to obtain EVB test data; S7, performing consistency analysis on the ATE test data and the EVB test data to determine the ATE test reference benchmark and the fixed difference gap; S8, updating or setting the ATE test threshold by combining the reference benchmark of the ATE test and the fixed difference gap through a preset margin strategy. The present invention uses the correlation between ATE and EVB board-level association to adjust the ATE test threshold, reduces unnecessary yield loss, improves the rationality and accuracy of the test standard, and further improves the efficiency of the ATE test.

[0046] Furthermore, the present invention distinguishes between Class I parameters and Class II parameters by analyzing the correlation between ATE and EVB board-level associations, and respectively adopts different margin strategies to adjust the two types of parameters, thereby further improving the accuracy of the test standards under different test parameters.

[0047] In addition, the present invention also systematically provides ATE-related implementation strategies for the entire life cycle of integrated circuit products.

[0048] It also provides a scientific and detailed solution process for the implementation of ATE and board-level association, balances the quality and cost requirements of the mass production process of integrated circuit products, effectively reduces testing costs, and has higher practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0050] Figure 1 It is a schematic flow chart of an integrated circuit ATE-related board-level testing method provided according to an embodiment of the present invention;

[0051] Figure 2 Schematic diagram of selection of Class II parameter EVB samples and determination of thresholds according to an embodiment of the present invention;

[0052] Figure 3 is a schematic diagram of determining a Class I parameter threshold according to an embodiment of the present invention; Figure 3 A is the first category parameter; Figure 3 B is the second category parameter;

[0053] Figure 4 1 is a schematic diagram of the relationship between the Class I parameter specification threshold, the test threshold and the protection band provided in an embodiment of the present invention;

[0054] Figure 5 It is a schematic diagram of an ATE association process of a program and hardware iteration provided in an embodiment of the present invention;

[0055] Figure 6 It is a schematic diagram of ATE association of the entire life cycle of an IC product provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0056] The present invention can be explained in detail through the following embodiments. The purpose of disclosing the present invention is to protect all technical improvements within the scope of the present invention. In the description of the present invention, it should be understood that if there are terms such as "upper", "lower", "front", "back", "left", "right", etc. indicating directions or positional relationships, they only correspond to the drawings of the present application for the convenience of describing the present invention, and do not indicate or imply that the device or element referred to must have a specific direction.

[0057] The following explains some terms involved in this embodiment:

[0058] (1) ATE

[0059] ATE is the abbreviation of Automatic Test Equipment, which is an integrated circuit (IC) automatic test machine used for large-scale integrated circuit wafer or finished product testing.

[0060] (2) EVB

[0061] EVB is the abbreviation of Evaluation Board, which is a board used to evaluate chip functions, performance and other parameters. It is used to compare design specifications and verify whether the design goals meet the requirements.

[0062] (3) Correlation

[0063] Due to the heterogeneity of the environment, test procedures, hardware configuration, test platform, etc., there may be inevitable differences between ATE test results and EVB test results, as well as between test results obtained under different conditions of ATE itself. Without proper identification and regulation, these differences may lead to unexpected yield loss in ATE testing. The purpose of correlation research is to use a series of methods to carefully examine and analyze the regularity and correlation of these differences, and then use scientific and technical means to appropriately formulate or adjust the original test parameters (such as IP performance, power consumption, AC and DC parameters) in order to determine a more reasonable ATE mass production test threshold. The purpose of this is to eliminate unnecessary yield loss, ensure product quality and take into account economic benefits.

[0064] (4) Vmin

[0065] Vmin usually refers to the minimum operating voltage threshold required in an integrated circuit to ensure the normal operation of the chip core. As time goes by and the device ages, when MOS (Metal-Oxide-Semiconductor) devices are affected by aging mechanisms such as NBTI (Negative Bias Temperature Instability) and HCI (Hot Carrier Injection), their threshold voltage will slowly rise, accompanied by changes in carrier mobility. This series of aging effects work together to cause the Vmin value to gradually increase as the device's service life continues.

[0066] (5) IDDQ

[0067] In semiconductor device research, the IDDQ parameter represents a quantitative assessment of the static drain current of the MOSFET structure under the condition of no external load on the integrated circuit. This parameter plays a vital role in the detection of manufacturing defects in CMOS integrated circuits. In theory, for CMOS circuits, when all transistors are in the off state, the expected drain current should be extremely weak, close to zero. However, in the actual production process, if manufacturing defects such as short circuits, open circuits, gate oxide layer damage, parasitic conductive paths, etc. appear in the circuit, the IDDQ current will be abnormally large. By implementing IDDQ testing, these potential defects can be quickly and effectively screened out, thereby improving the yield and overall reliability of integrated circuit products.

[0068] (6) Test threshold

[0069] Test thresholds refer to the critical values ​​or thresholds set for each test parameter of ATE to determine whether it has passed the test. These thresholds can be expressed as quantitative numerical limits or as qualitative judgment criteria. In specific applications, the setting of test thresholds is to ensure that the various performance parameters of the IC meet the preset specification requirements. By comparing the actual test results with the preset thresholds, potential faults or performance anomalies can be effectively identified, thereby strictly controlling product quality.

[0070] (7) LB

[0071] LB, or Load Board, is a printed circuit board (PCB) designed to carry the device under test (DUT) in the ATE test environment. The board integrates test sockets, test pads, and load circuit elements that simulate actual working situations, aiming to construct a suitable hardware test environment during ATE testing.

[0072] Embodiment 1

[0073] refer to Figure 1 This embodiment provides an integrated circuit ATE-related board-level testing method, comprising the following steps:

[0074] S1. Determine ATE test parameters, where the test parameters are parameters associated with the ATE and the EVB board level;

[0075] Specifically, the test parameters in step S1 include Class I parameters and Class II parameters, wherein the Class I parameters are a series of key performance parameters published in the chip data sheet; the Class II parameters are parameters that have special meanings in a specific test mode but are not reflected in the data sheet.

[0076] The chip data sheet usually publishes a series of key performance parameters and their specification ranges. These specifications have been clearly defined in the design stage. In this embodiment, such parameters are defined as Class I parameters, such as the test parameters of a single IP, such as the Jitter of Serdes, the SNR, ENOB, THD and other AC parameters of ADC. In addition, ATE will also test some parameters (such as Vmin, IDDQ) that have special significance in a specific test mode but are not reflected in the data sheet. In this embodiment, such parameters are defined as Class II parameters. For Class I parameters, the important purpose of ATE and EVB board-level association is to study the correlation between the two and make necessary adjustments to the original test threshold. In particular, for some analog parameters that are sensitive to environmental conditions and have limited design margins, considering the differences between the board-level environment and the ATE environment, if the specifications during the EVB test are directly applied to constrain the ATE test results, it may cause products that were originally qualified in the actual application of customers to be misjudged as unqualified in the ATE test, the so-called "false kill", thereby causing unnecessary yield loss. For Class II parameters, due to the lack of original design specifications as a reference, the setting of ATE test thresholds must be accurately set based on detailed board-level and ATE correlation analysis results to ensure the rationality of the test standards.

[0077] Include the key and sensitive parameters in Class I parameters in the scope of correlation research. For general integrated circuit chips such as MCU, DSP and SOC, these parameters may cover clock jitter, as well as AC performance indicators such as ADC signal-to-noise ratio (SNR) and effective number of digital bits (ENOB). For Class II parameters, such as IDDQ and Vmin, because the front end cannot give a range, the ATE test threshold must be determined through ATE and board-level correlation, so Class II parameters must be included in the ATE correlation object. This process also needs to determine the correlation and trend of ATE parameters and board-level parameters. Parameters with correlation and trend consistency have practical significance for correlation activities. This correlation can be direct or indirect.

[0078] Specifically, for example, IDDQ is a test parameter in ATE mode, but it is generally not testable in board-level functional mode and can only be approximated by the static current in the working mode (crystal oscillator short-circuited, reset state, internal logic not flipped), and IDDQ is strongly correlated with chip power consumption. Therefore, the ATE test threshold of IDDQ can be indirectly determined by the static leakage and power consumption in board-level functional mode.

[0079] Furthermore, when discussing Vmin testing, usually, the Vmin evaluation on the ATE platform is performed on some specific test vectors, while the Vmin on the EVB board level focuses on the performance of the entire system in the actual working scenario. Therefore, in the ATE testing phase, we need to perform Vmin tests on these specific test vectors and select the maximum value as a reference. In contrast, EVB requires that its Vmin value be accurately measured in a real scenario where the core system is running at full load. Despite this, there is still a certain direct correlation between the Vmin value of the ATE test vector and the EVB system-level Vmin.

[0080] In addition, for the test parameters of a single IP, such as the jitter of Serdes, the SNR, ENOB, THD and other AC parameters of ADC, since there is no big difference between ATE mode and EVB mode, the parameters in the two scenarios are directly related, so they can be tested separately and their data consistency and differences can be analyzed.

[0081] In this embodiment, the specific parameters of the specific Class I parameters and Class II parameters included in the test parameters are not limited and can be selected according to the specific requirements of the test.

[0082] Specifically, the test parameters selected in this embodiment include Jitter, SNR, ENOB, THD, and IDDQ and Vmin, which are used for subsequent research and testing.

[0083] S2. Determine the test conditions and sampling scheme of the integrated circuit according to the test parameters, and obtain the test samples through the sampling scheme;

[0084] Specifically, the test conditions in step S2 include process, voltage, and temperature, and different condition combinations are adopted for different test parameters;

[0085] Specifically, the sampling scheme is simple random sampling.

[0086] Specifically, the process includes SS process, FF process and TT process, the voltage includes high voltage, low voltage and normal voltage, and the temperature includes high temperature, low temperature and normal temperature.

[0087] For the above test parameters, a strategy for sample selection and sampling is formulated. Generally, it is required to set the test conditions of ATE and EVB for each test parameter. Usually, the selection is made from the three basic dimensions of PVT (Process, Voltage, Temperature), with a focus on extreme and boundary conditions, that is, the worst case. However, this process requires a trade-off analysis to identify and prioritize key test parameters to avoid unnecessary redundant testing.

[0088] It should be noted that this embodiment does not limit specific test conditions, and it is necessary to adopt a limited combination of conditions that distinguish key points for specific test parameters. The following takes the IDDQ test and the Vminc test as an example:

[0089] For example, during IDDQ testing, mass production testing is usually carried out under normal temperature and pressure conditions. As mentioned above, the core goal of performing ATE and EVB board-level correlation analysis on IDDQ is to determine the threshold setting of IDDQ parameters during ATE testing. Considering the close correlation between IDDQ and power consumption, and the power consumption characteristics are more prominent under high temperature, high pressure and fast process (such as FF, Fast-Fast) conditions. Therefore, in the ATE test phase, TT (Typical-Typical) typical process corner samples and FF process corner samples can be selected for normal temperature and pressure testing. When conducting EVB testing, the same samples should cover more test conditions, such as normal temperature and pressure and high temperature and high pressure. In this way, it can be ensured that the collected data includes both typical values ​​under TT process corner, normal temperature and pressure conditions, and worst case data under FF process corner, high temperature and high pressure conditions. In this way, the ATE data and the verification results of the EVB board level under the worst case can be intuitively compared to quickly define the ATE mass production test threshold of IDDQ.

[0090] For example, when testing Vmin, SS (Slow-Slow) process and TT process, low pressure and normal pressure, low temperature and normal temperature become the research focus.

[0091] The sampling scheme used in this embodiment is simple random sampling, which randomly selects a sufficient number of samples from all integrated circuit samples as test samples for testing. The specific number is determined according to the total number of samples in accordance with actual needs.

[0092] It should be pointed out that in order to ensure that the EVB board-level test can select samples at the edge, the ATE test needs to be based on a larger sample size, so that the distribution of its test results is representative of the overall distribution of the product. More representative samples can be selected for EVB board-level testing, so when determining the test samples, as many samples as possible should be selected according to the specific situation.

[0093] For example, the type of the test sample integrated circuit is DSP, and there are three types of process corners. There are 300 samples of SS type process corners, 320 samples of TT type process corners, and 350 samples of FF type process corners.

[0094] In order to ensure that the sample size is balanced and sufficient and take into account the efficiency of the test, the same number of samples are usually selected from each process angle. In this embodiment, 100 samples are randomly selected from each process angle, and the total sample size is 300.

[0095] S3. Number all test samples;

[0096] The core purpose of this step is to assign a unique number to each integrated circuit or chip in the test sample to ensure that the subsequent test data can establish a one-to-one association with the corresponding sample. This numbering system not only makes it easy to track specific chip individuals based on test results, but also provides convenience for selecting specific samples based on test data.

[0097] This embodiment does not limit the numbering method and the numbering format. As long as the subsequent test data can establish a one-to-one association with the corresponding sample, it is protected.

[0098] Preferably, this embodiment provides a numbering method, such as numbering according to the form of integrated circuit type + process type + serial number. For example: the type of the test sample integrated circuit is DSP, and there are 3 types of process corners (SS, TT, FF). There are N1, N2, and N3 samples of each type of process corner, respectively. The numbering can be DSP-SS-1, DSP-SS-2,..., DSP-SS-N1, DSP-TT-1, DSP-TT-2,..., DSP-TT-N2, DSP-FF-1, DSP-FF-2,..., DSP-FF-N3, respectively.

[0099] S4, performing ATE testing on the test sample according to the test conditions to obtain ATE test data;

[0100] Specifically, the ATE test data in step S4 is the value corresponding to the test parameter obtained after the test sample is subjected to ATE testing.

[0101] It should be noted that the ATE test described here is not the conventional ATE mass production test. Because it is of a research nature, the test conditions are limited.

[0102] For example, taking IDDQ testing as an example, it is necessary to use some external temperature control equipment, and the ATE test samples need to be systematically subjected to independent or joint voltage and temperature experiments to obtain ATE test data of product characteristics under different conditions. The obtained ATE test data needs to be preliminarily sorted to facilitate the selection of EVB board-level test samples.

[0103] The sorting is generally carried out according to the size of the numerical values ​​in the test parameters in the test data. The sorting can be carried out in order from large to small or from small to large. The specific sorting algorithm is not limited, and all those that can achieve the sorting purpose are protected. This embodiment preferably sorts the numerical values ​​in the test parameters in order from small to large.

[0104] In this way, the maximum and minimum values ​​and some intermediate value samples can be easily picked out as samples for board-level testing. Because the samples with boundary values ​​need to be explored, more samples need to be tested during ATE testing so that the distribution of the test results is representative of the whole. Board-level testing is to test boundary samples plus some intermediate typical value samples.

[0105] The ATE test data is the AC parameters mentioned above, such as IDDQ, Vmin, clock jitter (Jitter), ADC signal-to-noise ratio (SNR), effective number of bits (ENOB), etc. All parameters that need to be associated with ATE and EVB need to be tested by ATE first. The test mode and method based on ATE platform testing may be slightly different from the board level, but the data will be related to the board level data.

[0106] S5. Selecting EVB test samples from the ATE test data according to a selection scheme, wherein the EVB test samples include boundary test samples and intermediate test samples;

[0107] Specifically, the selection scheme in step S5 is as follows: preferentially selecting test samples whose ATE test data are at the boundary of the performance parameters as boundary test samples, and then selecting test samples in some middle areas as middle test samples.

[0108] In the testing of integrated circuits, the test data performance parameter boundaries refer to the parameter ranges that specify which data is considered qualified or unqualified. These boundaries are usually determined based on design specifications, industry standards, and expected application scenarios.

[0109] refer to Figure 2 ,The selection strategy of EVB test samples is crucial and its process should be ,based on a careful analysis of the ATE test data of the ,completed ATE test.,Based on the sorting of the ATE test data, a scientific selection should ,be made from this batch of samples according to the preset sampling granularity.

[0110] When selecting, we should focus on the samples at the boundary of the test data performance parameters, and moderately include samples in the middle area to ensure comprehensive representation. In particular, we must pay special attention to samples whose test data parameters are at the extreme or edge conditions after ATE testing, because they may reveal potential problems or extreme characteristics of product performance.

[0111] The preset sampling granularity can be determined according to the specific needs of sampling and is not limited here. Preferably, this embodiment can first sort the test data from large to small according to the value of a certain test parameter of the test data, and then divide the test data into N parts, and then randomly select 1 test data from each part to select the test sample corresponding to the test data. The value of N is generally 20, which can also be determined according to specific needs.

[0112] For example, assuming that the ATE test tests a total of 300 samples. After sorting, assume that 5+5 samples are selected from the boundary, and then the middle value samples are sorted by the ATE test value. According to experience, 1 sample is randomly selected from every 20 samples, and then 15 samples are selected to ensure that they are roughly uniform. Therefore, the total number of EVB tests will be less than that of ATE tests, and can be more or less, depending on specific needs.

[0113] S6, performing an EVB test on the EVB test sample to obtain EVB test data;

[0114] Specifically, the EVB test data in step S6 is a value corresponding to the test parameter obtained after performing an EVB test on the EVB test sample.

[0115] Specifically, the board used for the EVB test in step S6 is a PCB board.

[0116] Specifically, the ATE test itself is also a machine + LB board (LB is also a professional PCB board): the PCB board is used to comprehensively evaluate the overall function and performance of the chip internally, and can also be used as a demonstration board to show technical capabilities to customers and help customers quickly introduce. In addition to the target chip itself, the EVB test environment also integrates necessary and complete peripheral circuits, interface components and protection devices. The design purpose of these two board-level environments is to objectively evaluate or demonstrate the performance characteristics of the target chip based on the most ideal conditions. The EVB board is well designed to comprehensively, objectively and realistically characterize the functional and performance attributes of the target chip, and is suitable as a demonstration platform for customers to quickly evaluate and introduce new products. In order to effectively control variables and ensure the comparability of board-level test results of different samples, a PCB board equipped with a dedicated test fixture that can replace the target chip should be used. These test fixtures must be designed to ensure excellent electrical performance and stable connectivity to minimize potential interference with the parameters being tested.

[0117] When conducting board-level testing, the overall strategy should be followed: simple first, complex later, serial first, parallel later. For example, first perform serial testing on parameters with simple test methods based on an EVB board with a socket, then solder the chip to be tested to multiple EVB boards, and perform parallel testing on test parameters with relatively complex test methods and relatively long test time.

[0118] After the Class II parameter boundary samples are evaluated at the EVB board level, an evaluation conclusion will be obtained as to whether the samples meet the specification requirements in the actual application environment.

[0119] For example, for samples with class II parameters IDDQ, given that the power consumption of such samples is generally also at the borderline, in order to determine the ATE test threshold of IDDQ, its power consumption should be tested on EVB, especially the power consumption under the maximum workload scenario, to verify whether the target chip will be abnormal due to overheating. It should be pointed out that the strong correlation between IDDQ and chip power consumption is statistically significant, but it does not mean that the ATE and EVB test results are strictly consistent for each sample. Figure 2 The parameter shown is IDDQ. The situation of sample "A" shown in the figure represents that the sample with relatively small IDDQ has relatively large power consumption.

[0120] S7, performing consistency analysis on ATE test data and EVB test data to determine a reference benchmark and a fixed difference gap for ATE test, wherein the reference benchmark includes a reference benchmark upper limit UTL' and a reference benchmark lower limit LTL';

[0121] The consistency analysis and threshold decision test are the core of the entire ATE and EVB correlation evaluation. This step involves a comprehensive consistency comparison of all parameters on the two test platforms, ATE and EVB, and based on this, the final test thresholds applicable to the ATE system are established.

[0122] Specifically, step S7 specifically includes:

[0123] Determine the upper boundary evaluation value and the lower boundary evaluation value of the Class II parameter that the EVB test sample meets the specification requirements according to the EVB test data, and use the upper boundary evaluation value as the reference benchmark upper limit UTL' of the ATE test and use the lower boundary evaluation value as the reference benchmark lower limit LTL' of the ATE test;

[0124] The upper boundary evaluation value is a reference value corresponding to a boundary sample showing an upper boundary critical pass state in an EVB test;

[0125] The lower boundary evaluation value is a reference value corresponding to a boundary sample showing a lower boundary critical pass state in an EVB test;

[0126] For Class II parameters, the processing flow described in step S6 is followed, such as Figure 2As shown in the example, after the Class II parameter boundary samples are evaluated at the EVB board level, an evaluation conclusion will be obtained on whether the samples meet the specification requirements in the actual application environment. On this basis, the parameter values ​​corresponding to the boundary samples that show a critical pass state in the EVB test, that is, the EVB test OK, are used as the reference benchmark lower limit - LTL' (Lower Test Limit) and reference benchmark upper limit UTL' (Upper Test Limit) for ATE testing. In terms of this parameter, products within this parameter range are considered to be relatively safe and reliable.

[0127] Specifically, the type I parameter test data in the ATE test data and the EVB test data are linearly correlated;

[0128] Specifically, the Class I parameter test data in the ATE test data and the EVB test data are arranged in sequence and analyzed uniformly through Excel, and the linear relationship between the two groups of test data is tested through the Excel tool. If the linear relationship between the two groups of test data is good, the difference between the two groups of test data is calculated as the fixed difference gap.

[0129] Specifically, the Class I parameter test data in the ATE test data and the EVB test data are arranged in order and analyzed uniformly, and further includes:

[0130] If the linear relationship between the two sets of test data is poor, check whether there are abnormalities in the ATE and EVB environments at the same time;

[0131] If outlier data appear during the analysis process, further analysis and retesting will be performed on the outlier data until it is improved or eliminated.

[0132] For Class I parameters, statistical methods are used to process the data collected by ATE and EVB. The two sets of test data can be arranged in order and analyzed uniformly in the Excel environment. It is expected that the test results of the two will show linear correlation characteristics. The linear relationship can be tested through Excel tools. For cases with poor linear relationships, the ATE and EVB test environments should be checked for abnormalities. If there is a possibility of individual outliers, in order to ensure the accuracy and effectiveness of the analysis results, the outliers need to be further analyzed or retested until they are improved, or even temporarily removed.

[0133] Specifically, how to sort data through Excel and how to determine whether there is a linear relationship between two sets of data through Excel are common means for technical personnel in this field to perform data analysis. On the premise that the two sets of data are verified to have a good linear relationship, the difference between the two sets of data can be calculated by directly subtracting the ATE and EVB data of all DUTs and then averaging them, which will not be repeated here.

[0134] S8, updating or setting the ATE test threshold by combining the reference benchmark of the ATE test and the fixed difference gap through a preset margin strategy;

[0135] Specifically, the preset margin strategy includes a first margin strategy and a second margin strategy;

[0136] Specifically, the first margin strategy and the second margin strategy both adopt a guard band;

[0137] Specifically, the reference benchmark of the ATE test is adjusted by the safety margin introduced by the second margin strategy to obtain the test threshold of the Class II parameter;

[0138] For Class II parameters, it can be seen from the description in step S7 that the reference lower limit LTL' and the reference upper limit UTL' of the ATE test threshold can be directly obtained by comparing the EVB test results. According to engineering experience, a guard band of a certain width is introduced as a safety margin, so as to finally determine the ATE mass production test threshold, including the test threshold lower limit LTL and the test threshold upper limit UTL.

[0139] After determining the basic LTL' and UTL', in order to obtain test thresholds (LTL and UTL) with safety margins and robustness, an appropriate margin strategy is usually set based on engineering experience.

[0140] Specifically, the fixed difference gap is used as a component of the first margin strategy to adjust the specification threshold to obtain the test threshold of the Class I parameter.

[0141] For Class I parameters, the method described in step S7 is also followed. When setting the ATE test threshold, in addition to referring to the original specification threshold (specification lower limit LSL and specification upper limit USL), special attention should be paid to the results of the correlation between the ATE and EVB test results, and the fixed difference (gap) between the two. After confirming that there is a stable correlation and consistency trend between the ATE and EVB test data, it can be considered that this difference is a constant value, and this constant deviation can be used as a compensation for adjusting the original LTL and UTL. Similar to Class II parameters, the setting of the test threshold of Class I parameters will also introduce a test guard band based on engineering experience. The difference is that the constant deviation between ATE and EVB is used as a component of the guard band. The test thresholds (LTL and UTL) of Class I parameters are finally determined by combining the specification thresholds (LSL and USL) and the guard band. The relationship between the specification thresholds, test thresholds, and guard bands of these parameters can be referred to. Figure 4 , ultimately forming a closed loop of ATE and board-level related activities.

[0142] Specifically, in Figure 3 In the case shown, we first discuss the parameters of the "first category", whose performance is positively correlated with the value, that is, an increase in the value indicates an improvement in performance. This type of parameter has a clear lower specification limit (LSL) at the beginning of product development, and the test lower limit (LTL) setting on ATE is directly related to the bottom line requirement of the lower specification limit. Figure 3 In the case shown, the same chip is tested by ATE and EVB respectively, and the test results of multiple samples are listed in ascending order (or descending order) in the figure. Due to the aforementioned environmental factors, the test results of the two show a fixed difference (gap), and the performance shown by the EVB test results is better than that of the ATE test results. It is worth noting that if the ATE test threshold LTL is simply set according to the specification threshold LSL, it will be found that some boundary samples are judged as unqualified (fail) in the ATE test, but when these samples are tested in the EVB environment, their performance actually meets the qualified standard (pass), in other words, their actual application is qualified. Therefore, in the face of this mismatch phenomenon, the test threshold of ATE must be adaptively adjusted based on the results of the correlation analysis, otherwise it may lead to unnecessary yield loss.

[0143] For example, Figure 3 Taking the "first category" parameters shown in A as an example, we can see that according to the ATE test results, 4 products exceeded the ATE test lower limit and were classified as "ATE products to be eliminated". However, due to the existence of the gap, 2 of these 4 products met the test lower limit requirements in the EVB test. Finally, in order to recover these 2 chips that were misjudged as fail, ATE needs to appropriately relax the test lower limit according to the size of the gap value to complete the adjustment action.

[0144] Next consider Figure 3 The performance trend of the parameters of the "second category" presented in B is that the smaller the value, the better. Similarly, this type of parameter is also subject to the upper specification limit (USL). Similar to the first type of parameter, when it is confirmed that the ATE test results are different from the board-level test results under normal conditions, it is also required to reasonably adjust the upper limit threshold of the ATE test based on the conclusions obtained from the correlation analysis to ensure the accuracy and fairness of the test.

[0145] The setting of the guard band can be achieved by weighing the quality and cost through statistical distribution, and the decision is made after multiple reviews and discussions. Please refer to the document AEC-Q003 "Guideline For Characterization of Integrated Circuits", which will not be repeated here.

[0146] The present embodiment provides an integrated circuit ATE-associated board-level test method, comprising the following steps: S1, determining ATE test parameters; S2, determining the test conditions and sampling scheme of the integrated circuit according to the test parameters, and obtaining test samples through the sampling scheme; S3, numbering all test samples; S4, performing ATE test on the test samples according to the test conditions to obtain ATE test data; S5, selecting EVB test samples from the ATE test data according to the selection scheme, the EVB test samples including boundary test samples and intermediate test samples; S6, performing EVB test on the EVB test samples to obtain EVB test data; S7, performing consistency analysis on the ATE test data and the EVB test data to determine the ATE test reference benchmark and the fixed difference gap; S8, updating or setting the ATE test threshold by combining the reference benchmark of the ATE test and the fixed difference gap through a preset margin strategy. The present embodiment uses the correlation between the ATE and EVB board-level associations to adjust the ATE test threshold, thereby reducing unnecessary yield loss, improving the rationality and accuracy of the test standard, and further improving the efficiency of the ATE test.

[0147] Furthermore, this embodiment distinguishes between Class I parameters and Class II parameters by analyzing the correlation between ATE and EVB board-level associations, and respectively adopts different margin strategies to adjust the two types of parameters, thereby further improving the accuracy of the test standards under different test parameters.

[0148] This embodiment also provides an application solution for ATE association of program and hardware iteration;

[0149] During the mass production stage of chip products, due to the requirements of technological improvement and upgrading, chip test programs, hardware platforms and other components usually undergo continuous upgrades and iterations. The ATE associations in this category are more LB-to-LB or program-to-program. For example, considering the need to reduce costs and improve test efficiency, the LB board has been expanded from 2 sites to 4 sites, 8 sites or even more; for example, as the program shipments increase, customer-side imports continue to deepen, and in order to cope with new problems and new requirements, the program also needs to be optimized and iterated. While these update operations promote product performance optimization and quality improvement, they may also introduce potential performance differences. In the face of differences that cannot be ignored, it is necessary to ensure that no matter how the test environment evolves, it can accurately reflect the true performance of the chip through inspection and calibration, avoid potential yield losses caused by iterative upgrades, and maintain high product quality and consistency.

[0150] The specific operation of this process can be found in Figure 5 :First, based on the software and hardware environment before the upgrade iteration, a round of ATE testing is performed on the test samples to collect and analyze the benchmark data. Of course, the ATE test data of the first ATE and EVB board level association can also be used as the benchmark data. Secondly, different ATE retest strategies should be implemented according to the objects of the upgrade iteration. For the iterative upgrade of hardware, the principle of controlling variables should be followed to ensure that all other relevant variables (ATE test platform, test program, test samples, and environmental conditions such as temperature, etc.) except the hardware itself remain unchanged, so as to accurately capture the impact of hardware iteration. When iterating the software program, a similar method is also used to isolate and highlight the impact of software changes on the test results. After completing the collection of raw data, a series of analysis such as consistency analysis, statistical analysis, and Cpk (process capability index) calculations are required to evaluate the stability and performance of the system. The results of the analysis and calculation can reflect the differences before and after the iteration. Finally, based on the above analysis results, a final decision is made. This may involve further optimization, fine-tuning of parameters, or maintaining the status quo.

[0151] This embodiment also provides an application solution for ATE association of the switching platform;

[0152] Chip products may go through different stages from development and debugging to factory-scale production in the early stage of mass production. The mass production process may also transfer test plants or transfer platforms due to technical or commercial factors. The ATE association in this category is ATE to ATE. Different models of machines may have some intuitive or statistical differences in test results due to technical differences. Usually, well-designed and calibrated machines will not have large differences, but once such differences are considered to exceed a certain tolerance range, they need to be addressed. The ATE-associated process for this type of transition activity can also be referred to Figure 5 The process shown in the figure should also follow the principle of controlling variables as much as possible.

[0153] This embodiment also provides an application solution for ATE association of other variable factors in the product life cycle;

[0154] The life cycle of a chip product spans a time span ranging from several years to more than ten years. During this period, possible changes in chip processes and materials, changes in climatic conditions, and natural parameter drift of production line equipment over time may eventually manifest as parameter fluctuations between different production batches. It should be pointed out that as the shipment volume of the chip product itself increases (the statistical sample increases), the test thresholds set initially with reference to a limited number of statistical samples may need to be fine-tuned in time to adapt to a larger data population. These factors need to be given full attention and effective control in the management of the entire chip life cycle to ensure the continued stability of product performance and consistency of quality. In engineering practice, the use of statistical process control (SPC) as a process control method can monitor various types of changes in a certain stage of the chip product life cycle in real time. At the same time, the Part Average Testing (PAT) method recommended by standards such as AEC-Q can be used to implement a dynamically adjusted test threshold strategy for specific parameters to cope with potential fluctuations. This embodiment recommends the implementation of a systematic and forward-looking strategy for ATE-related activities involved in this long period of time. For example, in the foreseen process improvement or material change stage, reference should be made to similar Figure 5 The correlation process shown in the figure is used for planned comparative analysis. For performance changes that occur gradually and require long-term data accumulation to appear, the early warning advantages of SPC and other similar tools should be fully utilized. When SPC monitoring data is abnormal, correlation activities should be initiated immediately to identify and correct potential test differences. In short, in the full life cycle management of chip products, SPC control, PAT test methods and timely ATE correlation activities should be combined to ensure effective management and control of various changing factors, thereby ensuring the consistency and reliability of product performance.

[0155] Embodiment 2

[0156] The four scenarios listed in Example 1 generally occur at different stages of the entire life cycle of the integrated circuit. Their impact on the mass production yield of ATE also presents different degrees. This embodiment considers the entire life cycle of the product and formulates a comprehensive, focused, and systematic ATE association strategy with different frequencies and strategies.

[0157] At the system level, considering the entire life cycle of chip products, ATE-related activities are embedded into the IPD (Integrated Product Development) IC product development process to achieve the unification of branch tasks and project progress.

[0158] like Figure 6 The ATE association flow chart of the entire life cycle of the IC product shown in the figure shows that in the association process of the entire life cycle of the integrated circuit product, the initial ATE and board-level association test constitutes the benchmark reference point in the entire life cycle, and is also the most core link in the entire association activity chain. Figure 1 It is indicated by a solid frame in the figure. The subsequent platform transfer, test program or hardware upgrade, and continuous association activities in the mass production process will all use the ATE test environment formed after the first ATE and board level association as the reference basis for subsequent comparison and adjustment. The association activities in the subsequent stages are mainly concentrated in the cross-validation within the ATE platform (programs and hardware) or between ATEs. Most of them are of the nature of comparative inspection. Their conclusions are mostly oriented to fine-tuning and optimizing the test parameters, and sometimes no adjustment is even required. For example, when the ATE software and hardware upgrade optimization is small, the impact on the test parameters after the cross-platform is minimal, or the product is in the early stage of mass production, and the SPC (Statistical Process Control) monitoring data in the short term shows that there is no significant fluctuation in the production process parameters, the association activities may not be necessary. Therefore, for these later node association activities, they should be selectively executed according to actual conditions. Figure 6 The possible selective execution links are illustrated in the figure in the form of dotted boxes.

[0159] The beneficial effects provided by the above embodiments of the present invention include:

[0160] 1) Systematically provide ATE-related implementation strategies for the entire life cycle of integrated circuit products;

[0161] 2) Professionalism provides a scientific and detailed solution process for the implementation of ATE and board-level association;

[0162] 3) It balances the quality and cost requirements of the mass production process of integrated circuit products, effectively reduces testing costs, and has higher practicality.

[0163] This specification is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of this specification. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 Processes Multiple processes and / or boxes Figure 1 A device that has the functions specified in one or more boxes.

[0164] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0165] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0166] The parts of the present invention that are not described in detail are prior art. It is obvious to those skilled in the art that the present invention is not limited to the details of the above-mentioned exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention; therefore, no matter from which point of view, the embodiments should be regarded as exemplary and non-restrictive, and it is intended that all changes that fall within the meaning and scope of equivalent elements are included in the present invention.

Claims

1. An integrated circuit ATE-related board-level testing method, characterized in that: include: S1. Determine ATE test parameters, where the test parameters are parameters associated with the ATE and the EVB board level; The test parameters include Class I parameters and Class II parameters, the Class I parameters include Jitter, SNR, ENOB, and the Class II parameters include IDDQ and Vmin; S2. Determine the test conditions and sampling scheme of the integrated circuit according to the test parameters, and obtain the test samples through the sampling scheme; S3. Number all test samples; S4, performing ATE testing on the test sample according to the test conditions to obtain ATE test data; S5. Selecting EVB test samples from the ATE test data according to a selection scheme, wherein the EVB test samples include boundary test samples and intermediate test samples; S6, performing an EVB test on the EVB test sample to obtain EVB test data; S7, performing consistency analysis on the ATE test data and the EVB test data to determine the ATE test reference benchmark and the fixed difference gap, wherein the reference benchmark includes a reference benchmark upper limit UTL' and a reference benchmark lower limit LTL'; Determine the upper boundary evaluation value and the lower boundary evaluation value of the Class II parameter that the EVB test sample meets the specification requirements according to the EVB test data, and use the upper boundary evaluation value as the reference benchmark upper limit UTL' of the ATE test and use the lower boundary evaluation value as the reference benchmark lower limit LTL' of the ATE test; The upper boundary evaluation value is a reference value corresponding to a boundary sample showing an upper boundary critical pass state in an EVB test; The lower boundary evaluation value is a reference value corresponding to a boundary sample showing a lower boundary critical pass state in an EVB test; S8. Update or set the ATE test threshold by using a preset margin strategy in combination with the reference benchmark of the ATE test and the fixed difference gap.

2. The method according to claim 1, characterized in that: The test conditions in step S2 include process, voltage, temperature, and different condition combinations are adopted for different test parameters; the sampling scheme is simple random sampling.

3. The method according to claim 1, characterized in that The ATE test data in step S4 is the value corresponding to the test parameter obtained after the test sample is subjected to ATE testing.

4. The method according to claim 1, characterized in that The selection scheme described in step S5 is specifically as follows: preferentially selecting test samples whose ATE test data are at the boundary of the performance parameters as boundary test samples, and then selecting test samples in some middle areas as middle test samples.

5. The method according to claim 1, characterized in that The EVB test data in step S6 is the value corresponding to the test parameter obtained after the EVB test sample is subjected to the EVB test; the board used for the EVB test is a PCB board.

6. The method according to claim 1, characterized in that Step S7 also includes: the type I parameter test data in the ATE test data and the EVB test data are linearly correlated; The Class I parameter test data in the ATE test data and the EVB test data are arranged in sequence and analyzed uniformly through Excel, and the linear relationship between the two groups of test data is tested through Excel tools. If the linear relationship between the two groups of test data is good, the difference between the two groups of test data is calculated as the fixed difference gap.

7. The method according to claim 6, characterized in that Step S7 also includes: arranging the type I parameter test data in the ATE test data and the EVB test data in order and performing unified analysis, and further includes: If the linear relationship between the two sets of test data is poor, check whether there are abnormalities in the ATE and EVB environments at the same time; If outlier data appear during the analysis process, further analysis and retesting will be performed on the outlier data until it is improved or eliminated.

8. The method according to claim 1, characterized in that Step S8 includes: the preset margin strategy includes a first margin strategy and a second margin strategy; the first margin strategy and the second margin strategy both use a guard band; The reference benchmark of the ATE test is adjusted by the safety margin introduced by the second margin strategy to obtain the test threshold of the Class II parameter; The fixed difference gap is used as a component of the first margin strategy to adjust the specification threshold to obtain the test threshold of the Class I parameter.

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