A Defect Location Method for Failure Analysis of High-End Chips

Abstract

This invention relates to a defect location method for failure analysis of high-end chips, comprising the following steps: (1) For the failure analysis and location problem of chips with advanced process nodes below 16nm, transistor-level defect region location technology is carried out in collaboration with multiple devices; (2) The chip with failure problems is placed in an ATE test bench for relevant testing and analysis to find the cause of the failure; (3) After the ATE initially determines the cause of the failure, EMMI or OBIRCH is used to locate leakage current and defect location; (4) Chip defects and fault locations are accurately located using PVC, SEM, etc.; (5) Defect samples are prepared using FIB and placed under TEM to identify sample breakdown, diffusion, and elemental resolution. The failure analysis and location method proposed in this invention solves the problem of difficult location caused by the high transistor density and numerous metal wiring layers of advanced process chips, and can solve the correlation problem between defect location methods.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit testing technology, in particular to a defect positioning method applied to high-end chip failure analysis. BACKGROUND

[0002] With the higher requirements of 5G communication, Internet of Things, electronic terminal and other devices on the functional performance of chips, chip manufacturing is continuously reduced, and high-end chips of 16nm and below are gradually applied in various industries. However, due to the short application time, the reliability level of long-term service of high-end chips is not sufficient, and in addition, advanced process node chips use FinFET mechanism, the structure, material and process have changed, the failure mechanism model may have changed, and with the improvement of chip manufacturing, the chip defects and failure phenomenon will increase, so solving the failure analysis at the chip level has the advantages of optimal cost and lowest risk.

[0003] Due to the characteristics of large transistor density and multiple metal wiring layers of advanced process chips, when there is a failure point, how to accurately locate the failure point becomes the most important step in high-end chip failure analysis. The traditional positioning method is generally to locate according to the failure phenomenon and failure mode through a single device. In the prior art, the use of a single device for failure positioning of high-density, multi-wiring layer chips generally has low accuracy, and the success rate needs to be further improved.

[0004] Therefore, establishing a three-level area accurate positioning from the functional module level to the transistor level can identify defects, distinguish failure modes and confirm failure mechanisms, thereby improving the reliability of high-end chip positive design. SUMMARY

[0005] Therefore, the technical problem to be solved by the present application is to overcome the defect positioning in the failure analysis of integrated circuits and chips in the prior art. The conventional method is to position by a single device, and few defects are positioned by multiple devices in cooperation. When the transistor density of the chip is too large and the number of metal lines reaches more than 10 layers, the conventional method cannot accurately position the defects, thereby providing a defect positioning method considering the selection of multiple devices in cooperation, from surface to point, and accurate positioning.

[0006] To solve the above technical problems, the defect positioning method applied to high-end chip failure analysis comprises the following steps:

[0007] Step S1: Chip ATE test; Select the corresponding test program according to the chip type, and perform electrical performance testing and analysis using an ATE tester to preliminarily determine the chip's failure type and failure mode;

[0008] Step S2: Preliminary localization using chip EMMI or OBIRCH testing; the fault point is located by measuring the photons emitted when a bias voltage is applied to a sample of the failed chip.

[0009] Step S3: Precise PVC testing of the chip; After EMMI or OBIRCH locates the defect, it is necessary to check for defects within a specific area of ​​the chip; Among them, the PVC technology utilizes the different potentials on the sample surface to affect the secondary electron emission rate of the surface, and generates a contrast image with obvious light and dark contrast by relying on SEM and FIB equipment.

[0010] Step S4: FIB precise delamination and sample preparation; using ion beam etching and electron beam imaging techniques to analyze the physical structure of planar samples, FIB high current is used to rapidly etch away the surface metal layer, and at the same time, on the determined observation plane, a small current is used for polishing to etch out a smooth and flat internal cross section, which is then combined with SEM imaging function to observe the planar physical structure.

[0011] Step S5: TEM observation of defect region morphology; TEM combined with selected area electron diffraction or nanobeam diffraction and transmission Kikuchi diffraction is used for precise phase identification and crystal structure analysis, and scanning transmission electron energy loss spectroscopy is used for more precise composition analysis.

[0012] In defect location methods, PVC or SEM is used to accurately locate the chip, pinpointing the defect location to a specific transistor or a section of metal wire.

[0013] In one embodiment of the present invention, the defect location method uses an ATE test machine to perform electrical performance analysis on the chip, determine the approximate failure mode such as contact failure or functional failure, and determine the chip failure port.

[0014] In one embodiment of the present invention, the defect localization method uses EMMI to perform preliminary chip localization, and combines ATE test data and failure ports to achieve local localization of chip failure areas for defects caused by leakage current, hot carrier effect, latch-up effect, ESD, etc.

[0015] In one embodiment of the present invention, PVC is used to precisely position the chip. After the initial positioning by EMMI, it may contain a large number of transistors or multiple metallized wiring areas. The secondary electron emission rate of the sample surface is affected by the different potentials on the sample surface.

[0016] In one embodiment of the present application, based on SEM and FIB equipment, a contrast image with obvious light and shade contrast is generated, the defect position can be positioned to a certain transistor or a certain metal line, and accurate positioning is realized.

[0017] In one embodiment of the present application, in the method, accurate delayering and sample preparation are performed by using FIB to prepare TEM, and the micro morphology of the chip is observed under high magnification; and specifically, TEM sample preparation is performed on the chip failure position by using FIB, the sample failure position is thinned to below 100 nm, and then observation of the failure phenomenon, resolution of the failure mode, element distribution, crystal structure evolution and other tests are performed, so that observation and analysis after accurate positioning are realized.

[0018] The above technical scheme of the present application has the following advantages compared with the prior art: the defect positioning method of the present application uses a process method designed by means of the association and synergistic effect of multiple devices, a sample is prepared at the positioned defect, and the chip after the positioned defect is found is subjected to defect identification, failure mode resolution and failure mechanism confirmation through micro characterization, so that the reliability of the advanced process node chip is promoted. The method emphasizes the method for positioning the failure area of the high-end chip below 16 nm, and is from'surface' to 'point', and is strong in innovation and is not limited to a certain specific method. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to make the content of the present application more easily understood, the present application will be further described in detail below according to specific embodiments of the present application and in combination with the drawings.

[0020] Figure 1 A defect positioning flowchart for high-end chip failure analysis provided by the present application is shown in the following table:

[0021] Figure 2 An ATE test result graph provided by the present application is shown in the following table:

[0022] Figure 3 An EMMI and OBIRCH preliminary positioning result graph provided by the present application is shown in the following table:

[0023] Figure 4 A PVC accurate positioning result graph provided by the present application is shown in the following table:

[0024] Figure 5 An FIB delayering and sample preparation result graph provided by the present application is shown in the following table:

[0025] Figure 6 A chip interface defect TEM morphology graph provided by the present application is shown in the following table: DETAILED DESCRIPTION

[0026] As Figure 1As shown, the embodiment provides a defect positioning method applied to high-end chip failure analysis, which is suitable for FinFET structure advanced process chips with a process node below 16 nm, solves the correlation problem between defect positioning methods, realizes three-level area accurate positioning of functional module level-cell level-transistor level, and includes the following steps:

[0027] (1) Chip ATE test. According to the type of chip, select the corresponding test program, perform electrical performance test analysis through ATE test machine, preliminarily judge the failure type and failure mode of the chip, such as contact failure and functional failure, and roughly circulate the failure area according to the product detailed specification, layout or schematic diagram. It is worth noting that for some failure parameters, comparison with the packaging file in the product detailed specification can be positioned to the corresponding external packaging pin. After ATE test, IV electrical performance test can further confirm the external packaging pin of the failure, which is convenient for subsequent positioning analysis. The ATE test result is as shown in Figure 2 It can be clearly known that the failure parameter and the failure type.

[0028] (2) Chip EMMI or OBIRCH test preliminary positioning. The failure point can be located by measuring the light photons released by the sample under bias, which can be very sensitive to trace photons. Common failures such as leakage, hot carrier, ESD and latch can be preliminarily positioned. Most high-end chips are FinFET process, and due to the three-dimensional structure and high-density arrangement characteristics of the transistor, the positioning area of EMMI test will have the problems of too large positioning area and reduced resolution, so this step is preliminary positioning. It is worth noting that 16nm process chip usually contains more than 10 metal layers, which will cause the shielding of light points, so it is necessary to perform back-thinning of the sample to observe from the back. Figure 3 The result of the chip transistor defect test by the EMMI device.

[0029] (3) Chip PVC test precise positioning. After EMMI or OBIRCH positioning of the defect, a large number of transistors or multi-metalized wiring areas may be included, and the defect must be checked within a certain range. PVC technology uses the influence of different potentials on the surface of the sample on the secondary electron emission rate of its surface, relies on SEM and FIB equipment, and generates a contrast image with obvious light and dark contrast. The specific steps are as follows: first, the surface of the chip sample is treated, then placed in SEM or FIB, adjust the imaging mode, current voltage and other parameters, find the best working distance, output the PVC topography, and compare with the layout involved. After observation and analysis, the defect is positioned. Figure 4 The result of the chip transistor defect positioning topography by the PVC device.

[0030] (4) FIB precise delayering and sample preparation.

[0031] This technique utilizes ion beam etching and electron beam imaging to analyze the physical structure of planar samples. By selecting appropriate current, voltage, and electron gun, a high-current FIB is used for rapid etching to remove the surface metal layer. A larger beam current can be used to remove larger and deeper cross sections. On the determined observation plane, a low-current polishing process is used to etch a smooth and flat internal cross section. The planar physical structure is then observed using SEM imaging.

[0032] The method of combining FIB and TEM for observing the front-end process of FEOL includes: first, observing the vertical structure of the chip using FIB; second, preparing TEM samples of the chip's vertical structure using FIB, followed by TEM observation. Due to the limitations of FIB imaging resolution (0.6nm@2keV, 1nm@500eV), directly using FIB to observe FinFET structures at the 16 / 14nm or even 7nm level generally results in poor image quality. Therefore, TEM observation is the preferred method for observing FinFET structures. The TEM sample preparation process is as follows: First, the desired observation location is marked in the selected area, and the surface of the observation area is protected using Pt, W, etc. Then, a 1-2μm thick slice is cut from the area to be observed using a high-current ion beam, and extracted onto a microgrid using a robotic arm. The sample and microgrid are then welded together using metals such as Pt, W, etc. Finally, a low-current ion beam is used to gradually thin the central part of the sample to a thickness of less than 100nm, and finally, a low-current or argon polishing is used to remove the amorphous layer.

[0033] (5) Observation of the morphology of the TEM defect area.

[0034] TEM combined with selected area electron diffraction (SAED), nanobeam diffraction (NBD), or transmission Kikuchi diffraction (TKD) can enable precise phase identification and crystal structure analysis. Combining it with scanning transmission electron microscopy (STEM) and electron energy loss spectroscopy (EELS) allows for even more precise compositional analysis. In particular, high-resolution TEM (HRTEM) mode can be used to observe atomic-scale images, obtaining information on dislocations and planar defects. Combined with Fourier transform analysis, nanoscale phase identification can be performed.

[0035] The defect localization method described in this embodiment can solve the problem of difficult localization caused by the high transistor density and numerous metal wiring layers in advanced process chips. It has advantages such as high operability and high accuracy, and can resolve the correlation between defect localization methods, achieving precise localization at three levels: functional module level, unit level, and transistor level. This helps in identifying defects, distinguishing failure modes, and confirming failure mechanisms, thus promoting the reliability growth of chips at advanced process nodes. It is important to emphasize that this method focuses on the entire failure analysis and defect localization process, rather than targeting a single analysis method.

[0036] Obviously, the above-mentioned embodiments are only examples for clearly illustrating the present application, and are not intended to limit the present application. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, it is not necessary and also impossible to enumerate all the embodiments. The obvious changes or variations derived from the above description are still within the protection scope of the present application.

Claims

1. A defect positioning method applied to high-end chip failure analysis, the defect positioning method is for FinFET structure advanced process chip with process node below 16nm, solves the correlation problem between defect positioning methods, and realizes three-level area accurate positioning of function module level-cell level-transistor level, characterized in that, Comprising the following steps: Step S1: Chip ATE test; according to the type of chip, select the corresponding test program, through ATE test machine for electrical performance test analysis, preliminary judgment of chip failure type, failure mode; Step S2: Chip EMMI or OBIRCH test preliminary positioning; the failure point is located by measuring the photons released by the sample of the failed chip under bias; In step S2, EMMI or OBIRCH is used to preliminarily locate the chip, combined with ATE test data, failure port, for defects caused by leakage, hot carrier effect, latch effect and ESD, to find the heat point and realize the local positioning of the chip failure area; Step S3: Chip PVC test precise positioning; after the defect is located by EMMI or OBIRCH, defect checking must be carried out in a certain range of the chip; PVC technology uses the different potential of the sample surface to affect the secondary electron emission rate of its surface, relying on SEM and FIB equipment to generate a contrast image with obvious light and dark contrast; Step S4: FIB precise delayering and sample preparation; using ion beam etching and electron beam imaging technology to analyze the physical structure of the planar sample, using FIB large beam flow rapid etching to remove the surface metal layer, while on the determined observation plane, cooperate with small beam flow polishing, etch out smooth internal section, cooperate with SEM imaging function to observe the planar physical structure; Step S5: TEM defect area morphology observation; TEM combined with selected area electron diffraction or nanobeam diffraction, transmission kikuchi diffraction for accurate phase identification and crystal structure analysis, combined with scanning transmission electron energy loss spectrum for more accurate composition analysis.

2. The defect localization method of claim 1, wherein: In step S1, the ATE test machine is used to analyze the electrical performance of the chip to determine the failure mode: contact failure, functional failure, and determine the chip failure port.

3. The method of claim 1, wherein: EMMI preliminary positioning contains a large number of transistors or multi-piece metalized wiring areas.

4. The method of claim 1, wherein: In step S3, a contrast image with obvious light and dark contrast is generated, which can locate the defect position to a certain transistor or a certain metal line, realizing precise positioning.

5. The method of claim 1, wherein: TEM sample preparation is prepared for the chip failure position using FIB, which will thin the sample failure position to below 100nm, facilitating subsequent experiments and result observation.

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