Intelligent lock digital communication filtering method and system based on timer capture

Abstract

The purpose of the present invention is to disclose a digital communication filtering method and system for smart locks based on timer capture, which relates to the field of smart lock control technology, and includes the following steps: S1: encapsulating the instructions of the smart lock into a data packet, wherein the data packet consists of a data synchronization header and a number of bit data; S2: setting a digital wave with a fixed coding period of L for each bit data, and setting a minimum effective digital wave length L min and the maximum effective digital wave length L max ; S3: When the rising edge changes from low level to high level, the high level timer is started; S4: When the falling edge changes from high level to low level, the low level timer is started; S5: If the first level or the second level is less than L min If there is an interference wave, the duration of the interference wave is counted into the duration of the previous reverse level; S6: interpret the data packet of step S1 according to steps S2-step S5. Technical effect: the present invention can effectively capture the interference waves in the first level and the second level, and effectively avoid interference.

Description

Technical Field

[0001] The present invention relates to the field of intelligent lock control technology, and in particular to an intelligent lock digital communication filtering method and system based on timer capture. Background Art

[0002] The current smart locks have independent control systems, that is, one smart lock is installed on one door body, and the smart locks are controlled by the independent control system of the smart locks. However, after multiple smart locks are installed on multiple doors in the same building system, when the control instructions of the smart locks are transmitted through digital signals, the digital signals are easily affected by the power supply, inverter or other external devices when they are transmitted in the signal line. The signal line is often coupled with various clutters or white noise. The signal amplitude of white noise is generally very small, and the 0 and 1 levels in digital sampling can generally be directly filtered out without special processing. However, the pulse interference signal is random and the signal is very strong, which can be sampled, causing interference to the communication process, resulting in the inability of the smart lock to recognize or error code when receiving data.

[0003] In view of this, it is necessary to develop a digital communication filtering method and system for smart locks based on timer capture to overcome the above-mentioned defects. Summary of the invention

[0004] In order to solve the above technical problems, the purpose of the present invention is to disclose a digital communication filtering method and system for smart locks based on timer capture.

[0005] The first object of the present invention is to provide a digital communication filtering method for an intelligent lock based on timer capture.

[0006] The second object of the present invention is to provide a digital communication filtering system for smart locks based on timer capture.

[0007] To achieve the above first invention objective, the present invention provides a digital communication filtering method for smart locks based on timer capture, comprising the following steps:

[0008] S1: Encapsulate the smart lock's command into a data packet, which consists of a data synchronization header and several bits of data;

[0009] S2: Set a digital wave with a fixed coding period of L for each bit of data and set the minimum effective digital wave length L min and the maximum effective digital wave length L max , where L min >50%L,L max <200%L, the digital wave consists of a high level and a low level;

[0010] S3: When the rising edge changes from low level to high level, the high level timer is started and the low level timer is closed, and the high level timer samples and outputs the first level;

[0011] S4: At the falling edge from the high level to the low level, the low level timer is started and the high level timer is closed, and the low level timer samples and outputs the second level;

[0012] S5: If the first level or the second level is less than L min If there is an interference wave, the duration of the interference wave is counted into the duration of the previous reverse level;

[0013] If the first level or the second level has a value greater than L max The digital wave is considered invalid;

[0014] S6: Decode the data packet of step S1 according to steps S2 to S5.

[0015] Preferably, the data synchronization header is a continuous low level and the duration of the data synchronization header is between L and 2L.

[0016] Preferably, the digital wave starts with a continuous high level and ends with a continuous low level.

[0017] Preferably, if the first level or the second level has a value greater than L max If the digital wave is not received, it is deemed invalid and the next data packet containing the data synchronization header is received.

[0018] Preferably, the sampling frequency of the high-level timer is greater than 8 times / coding cycle.

[0019] Preferably, the sampling frequency of the low-level timer is greater than 8 times / coding cycle.

[0020] Based on the same inventive principle, in order to achieve the above second inventive object, the present invention provides a digital communication system for smart locks based on timer capture, comprising a control center and a plurality of smart locks controlled by the control center, wherein the control center sends instructions to the plurality of smart locks via a signal line;

[0021] The control center is provided with a first MCU controller, wherein the first MCU controller includes a high level timer and a low level timer;

[0022] The smart lock is provided with a second MCU controller;

[0023] The first MCU controller generates a control instruction and encapsulates the instruction into a data packet, wherein the data packet consists of a data synchronization header and a plurality of bit data, each bit data sets a digital wave with a fixed coding period of L, and sets a minimum effective digital wave length of Lmin and the maximum effective digital wave length L max , where L min >50%L,L max <200%L, the digital wave consists of a high level and a low level;

[0024] The high level timer is used to calculate the high level duration, and the low level timer is used to calculate the low level duration.

[0025] Preferably, when the digital wave changes from a low level to a high level at a rising edge, a high level timer is started and a low level timer is turned off, and the high level timer samples and outputs a first level;

[0026] When the digital wave changes from a high level to a low level at a falling edge, the low level timer is started and the high level timer is turned off, and the low level timer samples and outputs a second level.

[0027] Preferably, if the first level or the second level has a value less than L min If there is an interference wave, the duration of the interference wave is counted into the duration of the previous reverse level;

[0028] If the first level or the second level has a value greater than L max If the digital wave is not received, it is deemed invalid and the next data packet containing the data synchronization header is received.

[0029] Preferably, the data synchronization header is a continuous low level and the duration of the data synchronization header is between L and 2L;

[0030] The digital wave starts with a continuous high level and ends with a low continuous level;

[0031] The sampling frequency of the high level timer is greater than 8 times / coding cycle;

[0032] The sampling frequency of the low-level timer is greater than 8 times / encoding cycle.

[0033] Compared with the prior art, the technical effects of the present invention are as follows:

[0034] The instructions of the smart lock are encapsulated into a data packet consisting of a data synchronization header and several bit data. A digital wave with a fixed coding period of L is set for each bit data. The digital wave consists of continuous high level and continuous low level, and the high level timer and low level timer are used for sampling respectively. min >50%L,L max <200%L, during the sampling process of the high level timer and the low level timer, if a value less than L minThe interference wave is counted as the duration of the previous reverse level, that is, in the high-level sampling process, when a low-level interference wave is encountered, it is counted as a high level, and in the low-level sampling process, when a high-level interference wave is encountered, it is counted as a low level. The present invention can effectively capture the interference waves in the first level and the second level, and effectively avoid interference; and the corresponding time greater than L max The digital wave is considered invalid until a new data synchronization header signal arrives and is resampled. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 It is a flow chart of the digital communication filtering method of the intelligent lock based on timer capture of the present invention.

[0037] Figure 2 It is a schematic diagram of the digital wave of the present invention.

[0038] Figure 3 It is a schematic diagram of the digital communication filtering system of the intelligent lock based on timer capture of the present invention. DETAILED DESCRIPTION

[0039] The present invention is described in detail below in conjunction with the various embodiments shown in the accompanying drawings, but it should be noted that these embodiments are not limitations of the present invention, and any equivalent transformations or substitutions in functions, methods, or structures made by ordinary technicians in the field based on these embodiments are all within the scope of protection of the present invention.

[0040] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention. Example 1

[0041] Ginseng Figure 1 As shown, this embodiment discloses a specific implementation of a digital communication filtering method for a smart lock based on timer capture.

[0042] Digital communication filtering method for intelligent locks based on timer capture, Figure 1 As shown, the following steps are included:

[0043] S1: Encapsulate the instructions of the smart lock into a data packet, which consists of a data synchronization header and several bits of data; specifically, the instructions of the smart lock come from the bound control center, and the instructions contain AES128 encrypted data with the ID information of the control center and the ID information of the smart lock as seeds to ensure the uniqueness of the source of the instructions; the data synchronization header is preferably a continuous low level and the duration of the data synchronization header is between L and 2L, such as 1.5L, to distinguish between digital waves with a coding period of L and invalid waves.

[0044] S2: Set a digital wave with a fixed coding period of L for each bit of data and set the minimum effective digital wave length L min and the maximum effective digital wave length L max , where L min >50%L, such as L min =60%L,L max <200%L, such as L max =190%L, the digital wave consists of a high level and a low level; specifically, the digital wave starts with a continuous high level and ends with a low continuous level, and the digital wave consists of a continuous high level and a continuous low level, see Figure 2 The data synchronization header h, the continuous high level m of the first coding cycle, the continuous low level n of the first coding cycle, L=m+n.

[0045] S3: When the rising edge changes from low level to high level, the high level timer is started and the low level timer is turned off, and the high level timer samples and outputs the first level; specifically, when the data synchronization header is a continuous low level with a duration between L and 2L, when it jumps to a high level, the high level timer is started and the low level timer is turned off, and the high level timer samples and outputs the first level; after the continuous low level of the previous coding cycle ends, it jumps to the high level of the subsequent coding cycle, and the high level timer is also started, and the low level timer is turned off, and the high level timer samples and outputs the first level. The sampling frequency of the high level timer is greater than 8 times / coding cycle, and the sampling frequency is preferably 30 times / coding cycle. The specific frequency can be adjusted according to the size of the coding cycle. When the coding cycle is longer, the sampling frequency can be 50 times / coding cycle.

[0046] S4: At the falling edge from high level to low level, the low level timer is started and the high level timer is turned off, and the low level timer samples and outputs the second level; specifically, within any coding cycle, after the continuous high level ends, it is switched to a continuous low level, the low level timer is started, and the high level timer is turned off, and the low level timer samples and outputs the second level, and the sampling frequency of the low level timer is greater than 8 times / coding cycle, and the sampling frequency is preferably 30 times / coding cycle. The specific frequency can be adjusted according to the size of the coding cycle. When the coding cycle is longer, the sampling frequency can be 50 times / coding cycle; it should be noted that the sampling frequency of the low level timer should be the same as the sampling frequency of the high level timer to facilitate decoding.

[0047] S5: If the first level or the second level is less than L min If there is an interference wave greater than L in the first level or the second level, the duration of the interference wave is counted into the duration of the previous reverse level. max Specifically, during the sampling process of the high-level timer and the low-level timer, if a digital wave less than L min If there is an interference wave, the duration of the interference wave is counted as the duration of the previous reverse level, that is, in the high-level sampling process, when encountering a low-level interference wave, it is counted as a high level, and when encountering a higher-level interference wave, it is still counted as a high level, that is, no matter it is less than L min Low-level interference waves or higher-level interference waves will be captured without affecting the continuous high-level sampling results, thereby enhancing the anti-interference ability; and in the low-level sampling process, when encountering high-level interference waves, they are counted as low-level, and when encountering lower-level interference waves, they are also counted as low-level, that is, no matter it is less than L min Whether it is a high-level interference wave or a lower-level interference wave, it will be captured without affecting the continuous low-level sampling results, thereby enhancing the anti-interference ability; if a signal greater than L max The digital wave is considered invalid, and the next data packet containing the data synchronization header is received, that is, the corresponding data packet is greater than L max The interfering digital wave is considered invalid until a new data synchronization header signal arrives and is resampled.

[0048] S6: interpret the data packet of step S1 according to step S2-step S5. Specifically, the data packet of step S1 is converted into a ripple consisting of a continuous low-level data synchronization header and a number of digital waves by installing steps S2-step S5. The interference wave in the ripple has been captured, and a reliable digital wave is generated at the hardware bottom layer. Then, the ripple consisting of a continuous low-level data synchronization header and a number of digital waves is sent to the smart lock through the set communication protocol. The smart lock executes the instruction after decoding successfully.

[0049] According to this embodiment, during the sampling process of the high level timer and the low level timer, if a value less than L min The interference wave is counted as the duration of the previous reverse level, so that the interference wave in the continuous high level and the continuous low level can be captured to avoid interference, and the interference wave greater than L max The digital wave is considered invalid until a new data synchronization header signal arrives and is resampled, which determines the reliability of the digital communication of the smart lock from the hardware bottom level. Example 2

[0050] Ginseng Figure 3 As shown, this embodiment discloses a specific implementation of a digital communication system for a smart lock based on timer capture.

[0051] A digital communication system for smart locks based on timer capture, comprising a control center and several smart locks controlled by the control center, wherein the control center sends instructions to the several smart locks through a signal line, the instructions of the smart locks come from the bound control center, and the instructions contain AES128 encrypted data with the ID information of the control center and the ID information of the smart locks as seeds, so as to ensure the uniqueness of the source of the instructions; the data synchronization header is preferably a continuous low level and the duration of the data synchronization header is between L and 2L, such as 1.5L, so as to distinguish between digital waves with a coding period of L and invalid waves; the control center is provided with a first MCU controller, and the first MCU controller includes a high level timer and a low level timer; the smart lock is provided with a second MCU controller; the first MCU controller generates a control instruction and encapsulates the instruction into a data packet, the data packet consists of a data synchronization header and several bit data, each bit data sets a digital wave with a fixed coding period of L, and sets a minimum valid digital wave length of L min and the maximum effective digital wave length L max , where L min >50%L, such as L min =60%L,L max <200%L, such as L max =190%L, the digital wave consists of a high level and a low level; the digital wave starts with a continuous high level and ends with a low continuous level, and the digital wave consists of a continuous high level and a continuous low level, see Figure 2 The data synchronization header h shown, the continuous high level m of the first coding cycle, the continuous low level n of the first coding cycle, L=m+n; the high level timer is used to calculate the high level duration, and the low level timer is used to calculate the low level duration.

[0052] Specifically, when the digital wave changes from a low level to a high level at the rising edge, the high level timer is started and the low level timer is turned off, and the high level timer samples and outputs a first level; when the data synchronization header is a continuous low level with a duration between L and 2L, when it jumps to a high level, the high level timer is started and the low level timer is turned off, and the high level timer samples and outputs the first level; after the continuous low level of the previous coding cycle ends, it jumps to the high level of the subsequent coding cycle, and the high level timer is also started, and the low level timer is turned off, and the high level timer samples and outputs the first level. The sampling frequency of the high level timer is greater than 8 times / coding cycle, and the sampling frequency is preferably 30 times / coding cycle. The specific frequency can be adjusted according to the size of the coding cycle. When the coding cycle is longer, the sampling frequency can be 50 times / coding cycle.

[0053] When the digital wave changes from a high level to a low level at the falling edge, the low level timer is started and the high level timer is turned off. The low level timer samples and outputs the second level; within any coding cycle, after the continuous high level ends, it is switched to a continuous low level, the low level timer is started, and the high level timer is turned off. The low level timer samples and outputs the second level. The sampling frequency of the low level timer is greater than 8 times / coding cycle, and the sampling frequency is preferably 30 times / coding cycle. The specific frequency can be adjusted according to the size of the coding cycle. When the coding cycle is longer, the sampling frequency can be 50 times / coding cycle; it should be noted that the sampling frequency of the low level timer should be the same as the sampling frequency of the high level timer to facilitate decoding.

[0054] If the first level or the second level has a value less than L min If there is an interference wave, the duration of the interference wave will be counted into the duration of the previous reverse level; during the sampling process of the high level timer and the low level timer, if there is a time less than L min If there is an interference wave, the duration of the interference wave is counted as the duration of the previous reverse level, that is, in the high-level sampling process, when encountering a low-level interference wave, it is counted as a high level, and when encountering a higher-level interference wave, it is still counted as a high level, that is, no matter it is less than L min Low-level interference waves or higher-level interference waves will be captured without affecting the continuous high-level sampling results, thereby enhancing the anti-interference ability; and in the low-level sampling process, when encountering high-level interference waves, they are counted as low-level, and when encountering lower-level interference waves, they are also counted as low-level, that is, no matter it is less than L min Whether it is a high-level interference wave or a lower-level interference wave, it will be captured without affecting the continuous low-level sampling results, thereby enhancing the anti-interference ability; if a signal greater than L maxThe digital wave is considered invalid, and the next data packet containing the data synchronization header is received, that is, the corresponding data packet is greater than L max The interfering digital wave is considered invalid until a new data synchronization header signal arrives and is resampled.

[0055] It should be noted that, in this embodiment, the signal line is a multi-strand cable signal line, which is used to transmit control signals between the control center and the smart lock. When the signal line is used, the lock instructions are not connected to the Internet, which is more secure. The signal line length is 0 meters < ≤ 100 meters.

[0056] The smart lock digital communication system based on timer capture described in Example 2 executes the smart lock digital communication method based on timer capture described in Example 1. For the parts of Example 2 that are the same as Example 1, please refer to Example 1 and will not be repeated here.

Claims

1. A digital communication filtering method for smart locks based on timer capture, characterized in that: The following steps are involved: S1: Encapsulate the smart lock's command into a data packet, which consists of a data synchronization header and several bits of data; S2: Set a digital wave with a fixed coding period of L for each bit of data and set the minimum effective digital wave length L min and the maximum effective digital wave length L max , where L min >50%L,L max <200%L, the digital wave consists of a high level and a low level; S3: When the rising edge changes from low level to high level, the high level timer is started and the low level timer is closed, and the high level timer samples and outputs the first level; S4: At the falling edge from the high level to the low level, the low level timer is started and the high level timer is closed, and the low level timer samples and outputs the second level; S5: If the first level or the second level is less than L min If there is an interference wave, the duration of the interference wave is counted into the duration of the previous reverse level; If the first level or the second level has a value greater than L max The digital wave is considered invalid; S6: Decode the data packet of step S1 according to steps S2 to S5.

2. The digital communication filtering method for smart locks based on timer capture as claimed in claim 1, characterized in that: The data synchronization header is a continuous low level and the duration of the data synchronization header is between L and 2L.

3. The digital communication filtering method for smart locks based on timer capture as claimed in claim 1, characterized in that: The digital wave starts with a continuous high level and ends with a continuous low level.

4. The digital communication filtering method for smart locks based on timer capture as described in any one of claims 1 to 3, characterized in that: If the first level or the second level has a value greater than L max If the digital wave is not received, it is deemed invalid and the next data packet containing the data synchronization header is received.

5. The digital communication filtering method for smart locks based on timer capture as described in any one of claims 1 to 3, characterized in that: The sampling frequency of the high-level timer is greater than 8 times / encoding cycle.

6. The digital communication filtering method for smart locks based on timer capture as described in any one of claims 1 to 3, characterized in that: The sampling frequency of the low-level timer is greater than 8 times / encoding cycle.

7. Intelligent lock digital communication system based on timer capture, characterized in that: It includes a control center and several smart locks controlled by the control center, and the control center sends instructions to the several smart locks through a signal line; The control center is provided with a first MCU controller, wherein the first MCU controller includes a high level timer and a low level timer; The smart lock is provided with a second MCU controller; The first MCU controller generates a control instruction and encapsulates the instruction into a data packet, wherein the data packet consists of a data synchronization header and a plurality of bit data, each bit data sets a digital wave with a fixed coding period of L, and sets a minimum effective digital wave length of L min and the maximum effective digital wave length L max , where L min >50%L,L max <200%L, the digital wave consists of a high level and a low level; The high level timer is used to calculate the high level duration, and the low level timer is used to calculate the low level duration.

8. The intelligent lock digital communication system based on timer capture as claimed in claim 7, characterized in that: When the digital wave changes from a low level to a high level at a rising edge, a high level timer is started and a low level timer is closed, and the high level timer samples and outputs a first level; When the digital wave changes from a high level to a low level at a falling edge, the low level timer is started and the high level timer is turned off, and the low level timer samples and outputs a second level.

9. The intelligent lock digital communication system based on timer capture as claimed in claim 8, characterized in that: If the first level or the second level has a value less than L min If there is an interference wave, the duration of the interference wave is counted into the duration of the previous reverse level; If the first level or the second level has a value greater than L max If the digital wave is not received, it is deemed invalid and the next data packet containing the data synchronization header is received.

10. The intelligent lock digital communication system based on timer capture according to any one of claims 7 to 9, characterized in that: The data synchronization header is a continuous low level and the duration of the data synchronization header is between L and 2L; The digital wave starts with a continuous high level and ends with a low continuous level; The sampling frequency of the high level timer is greater than 8 times / coding cycle; The sampling frequency of the low-level timer is greater than 8 times / encoding cycle.

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