Electronic packaging and manufacturing method thereof

Abstract

An electronic package and its manufacturing method include embedding a heat dissipation bump in a coating layer to support an electronic component, and forming a circuit structure electrically connected to the heat dissipation bump on the coating layer, so that heat energy from the electronic component can be guided to the circuit structure by the heat dissipation bump and dissipated to the outside, thereby effectively ensuring the heat dissipation capability of the electronic package.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging technology, and in particular to an electronic packaging part with embedded components and a manufacturing method thereof. Background Art

[0002] The technologies currently used in the chip packaging field include chip scale packaging (CSP), direct chip attached packaging (DCA), double-side packaging or multi-chip module packaging (MCM).

[0003] Figure 1 FIG is a cross-sectional view of an existing semiconductor package 1. Figure 1 As shown, the semiconductor package 1 is a flip-chip package type, which includes a package substrate 10 having a core insulating layer 15, a semiconductor chip 12 disposed on the package substrate 10 via solder bumps 11, and an encapsulation layer 13 for encapsulating the semiconductor chip 12 to reflow the solder bumps 11 and secure the semiconductor chip 12. The package substrate 10 has a plurality of dielectric layers 100 on opposite sides of the core insulating layer 15 and a circuit layer 101 disposed on the dielectric layer 100. The core insulating layer 15 is a bismaleimide triazine (BT) layer, and the encapsulation layer 13 is formed of an epoxy molding compound (EMC).

[0004] However, in the conventional semiconductor package 1 , the plurality of semiconductor chips 12 are disposed on the surface of the dielectric layer 100 on one side of the package substrate 10 , making it difficult to reduce the thickness of the semiconductor package 1 , thereby failing to meet the thinning requirement.

[0005] Furthermore, if the core insulating layer 15 is removed from the package substrate 10 to reduce the thickness of the semiconductor package 1 , the package substrate 10 is likely to warp due to insufficient strength of the dielectric layer 100 .

[0006] In addition, the semiconductor chip 12 needs to be fixed on the package substrate 10 by reflowing the plurality of solder bumps 11. Therefore, when the reflow process is performed in a high temperature environment or other thermal cycle process, the package substrate 10 is prone to heat accumulation, resulting in uneven distribution of thermal stress, which may cause the package substrate 10 to warp.

[0007] Therefore, how to overcome the various problems of the above-mentioned existing methods has become a topic that needs to be solved urgently. Summary of the Invention

[0008] In view of the above-mentioned deficiencies in the prior art, the present invention provides an electronic package and a method for manufacturing the same, which can at least partially solve the problems in the prior art.

[0009] The electronic package of the present invention includes: a coating having a first surface and a second surface opposite to each other; a first circuit layer formed on the first surface of the coating; a heat dissipation bump embedded in the second surface of the coating; an electronic component embedded in the coating and disposed on the heat dissipation bump; and a circuit structure formed on the second surface of the coating, wherein the circuit structure includes at least one insulating layer formed on the coating and a second circuit layer formed on the insulating layer, so that the second circuit layer is electrically connected to the heat dissipation bump, allowing the electronic component to dissipate heat through the second circuit layer and the heat dissipation bump, and the insulating layer is formed of bismaleimide triazine (BT) or Ajinomoto build-up film (ABF).

[0010] The present invention also provides a method for manufacturing an electronic package, comprising: arranging a carrier substrate on opposite sides of a carrier, wherein the carrier substrate has at least one heat dissipation bump; arranging an electronic component on the heat dissipation bump; forming a coating layer on the carrier substrate to cover the heat dissipation bump and the electronic component, wherein the coating layer has a first surface and a second surface opposite to each other, so that the coating layer is bonded to the carrier substrate with its second surface; forming a first circuit layer on the first surface of the coating layer to form a packaging module; removing the carrier and the carrier substrate to obtain a plurality of the packaging modules, and exposing the second surface of the coating layer, wherein the packaging module retains The heat dissipation bump is retained so that the heat dissipation bump is exposed on the second surface of the coating layer; the packaging modules are respectively arranged on opposite sides of a support member, and each packaging module is pressed onto the support member with its first circuit layer so that the second surface of the coating layer faces outward; a circuit structure is formed on the second surface of the coating layer, wherein the circuit structure includes at least one insulating layer formed on the coating layer and a second circuit layer formed on the insulating layer, so that the second circuit layer is electrically connected to the heat dissipation bump, so that the electronic component dissipates heat through the second circuit layer and the heat dissipation bump, and the material forming the insulating layer is bismaleimide triazine (BT) or Ajinomoto build-up film (ABF); and the support member is removed.

[0011] In the aforementioned electronic package and its manufacturing method, the carrier substrate further comprises a plurality of conductive bumps, wherein the second surface of the cladding layer is embedded with the plurality of conductive bumps, so that the first circuit layer is electrically connected to the plurality of conductive bumps via a conductor. For example, the electronic component is electrically connected to the conductive bumps via a wire.

[0012] In the aforementioned electronic package and its manufacturing method, the electronic component is combined with the heat dissipation bump via an adhesive layer.

[0013] The aforementioned electronic package and its manufacturing method further include forming an insulating protection layer on the circuit structure, wherein the insulating protection layer exposes a portion of the surface of the second circuit layer, wherein the insulating protection layer has a filling material.

[0014] As can be seen from the above, the electronic package and its manufacturing method of the present invention mainly save the usable space on the first surface of the coating layer by embedding the electronic components in the coating layer, thereby facilitating the thinning of the electronic package. Therefore, compared with the prior art, the manufacturing method of the present invention can thin the electronic package to meet the needs of miniaturization.

[0015] Furthermore, by combining the electronic components with the adhesive layer, the solder bumps and reflow process used in conventional flip-chips can be replaced. This effectively reduces the risk of warping caused by high-temperature environments (or thermal cycles) when the electronic package meets miniaturization requirements. Furthermore, by using the carrier and support members to perform two symmetrical pressing operations, warping during the electronic package manufacturing process can be avoided.

[0016] In addition, by embedding the heat dissipation bump in the covering layer, the heat energy from the electronic component can be guided to the second circuit layer through the heat dissipation bump and dissipated to the outside world, thereby effectively ensuring the heat dissipation capacity of the electronic package. Therefore, when the electronic package is to meet the demand for miniaturization, the electronic package is suitable for the design of thinning the insulating layer and will not warp due to high temperature environment (or thermal cycle).

[0017] In addition, since the insulating protective layer has a filler to enhance its toughness, if the insulating layer needs to be thinned, the reinforced design of the insulating protective layer can serve as a support structure to prevent the electronic package from warping due to factors such as stress shrinkage or asymmetrical construction. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a cross-sectional schematic diagram of a conventional semiconductor package.

[0019] Figures 2A to 2H It is a cross-sectional schematic diagram of the method for manufacturing the electronic package of the present invention.

[0020] Figure 2H-1 for Figure 2H A cross-sectional schematic diagram of another embodiment of the present invention.

[0021] Figure 3 for Figure 2H Schematic cross-sectional view of other embodiments.

[0022] The description of the accompanying drawings is as follows:

[0023] 1Semiconductor package

[0024] 10 package substrate

[0025] 100 dielectric layer

[0026] 101 circuit layer

[0027] 11 solder bumps

[0028] 12 semiconductor chips

[0029] 13, 23 cladding layer

[0030] 15 core insulation layer

[0031] 2, 3 electronic packaging

[0032] 2a package module

[0033] 20 carrier substrate

[0034] 200 conductive bumps

[0035] 201 heat dissipation bump

[0036] 21 Adhesive layer

[0037] 22, 32 electronic components

[0038] 22a working surface

[0039] 22b non-active surface

[0040] 220 electrode pads

[0041] 23a first surface

[0042] 23b Second surface

[0043] 230, 231 blind holes

[0044] 24First circuit layer

[0045] 240, 241 Conductors

[0046] 25 line structure

[0047] 250 insulation layer

[0048] 251, 252 second circuit layer

[0049] 28 insulation protection layer

[0050] 280 openings

[0051] 29 conductive elements

[0052] 341 wire

[0053] 8 support parts

[0054] 80 tape

[0055] 9 bearing parts

[0056] 90 peeling layer

[0057] A crystal area DETAILED DESCRIPTION

[0058] The following describes the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0059] It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the conditions for the implementation of the present invention. Therefore, they have no substantial technical significance. Any modification of the structure, change in the proportional relationship or adjustment of the size should still fall within the scope of the technical content disclosed in the present invention without affecting the efficacy and purpose of the present invention. At the same time, the terms such as "on", "first", "second", "one" and so on quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0060] Figures 2A to 2H It is a cross-sectional schematic diagram of a method for manufacturing the electronic package 2 of the present invention.

[0061] like Figure 2A As shown, a carrier 9 is provided, with a carrier substrate 20 mounted on two opposite sides thereof. The carrier substrate 20 has a plurality of adjacent conductive bumps 200 and a die-stack region A. The die-stack region A has at least one heat dissipation bump 201 disposed between the conductive bumps 200. Next, an electronic component 22 is mounted on the heat dissipation bump 201 in the die-stack region A of the carrier substrate 20.

[0062] In this embodiment, the carrier 9 is a temporary detachable core carrier, which can be a plate having metal layers on opposite sides, such as a copper foil substrate, and a peeling layer 90 is formed on its metal surface, so that the carrier substrate 20 is formed on the peeling layer 90.

[0063] Furthermore, the carrier substrate 20, the heat dissipation bumps 201, and the conductive bumps 200 are formed of metal. For example, a copper plate is etched to integrally form the conductive bumps 200 and the heat dissipation bumps 201 on the carrier substrate 20. It should be understood that additional bumps may be added to the carrier substrate 20, such as by electroplating or bonding, without particular limitation.

[0064] Furthermore, the electronic component 22 is an active component, a passive component, or a combination thereof. The active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, or an inductor. For example, if the electronic component 22 is a semiconductor chip, it has an active surface 22 a and an inactive surface 22 b opposite to each other. The active surface 22 a has a plurality of electrode pads 220 , and the electronic component 22 is bonded to the heat dissipation bump 201 via an adhesive layer 21 at its inactive surface 22 b.

[0065] In addition, the adhesive layer 21 may be a heat dissipation adhesive material, such as silicon oxide (SiO 2 ) or metal adhesive, to facilitate heat transfer from the electronic component 22 to the heat dissipation bump 201 .

[0066] like Figure 2B As shown, a coating layer 23 is formed on the carrier substrate 20 to cover the conductive bumps 200, the heat dissipation bumps 201, the electronic components 22 and the adhesive layer 21. Next, a plurality of blind holes 230 are formed on the coating layer 23 to expose the conductive bumps 200.

[0067] In this embodiment, the cladding layer 23 has a first surface 23a and a second surface 23b opposite to each other, so that the cladding layer 23 is bonded to the carrier substrate 20 via its second surface 23b. A plurality of blind holes 230 are formed on the first surface 23a of the cladding layer 23 to expose the plurality of conductive bumps 200. For example, the blind holes 230 are formed by laser or other methods.

[0068] Furthermore, the electrode pads 220 may also be exposed on the first surface 23a of the cladding layer 23. For example, blind holes 231 may be formed at locations corresponding to the electrode pads 220 using a laser or other method, such that the blind holes 231 expose the electrode pads 220. Alternatively, a flattening process, such as grinding, may be used to make the electrode pads 220 flush with the first surface 23a of the cladding layer 23, thereby exposing the electrode pads 220.

[0069] In addition, the covering layer 23 is made of an insulating material, such as polyimide (PI), dry film, epoxy molding compound (EMC), or other packaging materials, and can be formed on the carrier substrate 20 by lamination or molding.

[0070] like Figure 2C As shown, conductors 240, 241 are formed in the multiple blind holes 230, 231, and a first circuit layer 24 is formed on the conductors 240, 241 and on the first surface 23a of the cladding layer 23 to form a packaging module 2a, so that the first circuit layer 24 is electrically connected to each of the conductive bumps 200 and each of the electrode pads 220 through the multiple conductors 240, 241.

[0071] In this embodiment, the conductors 240 , 241 and the first circuit layer 24 are manufactured simultaneously by a patterned electroplating process, so that the first circuit layer 24 and the plurality of conductors 240 , 241 are integrally formed.

[0072] like Figure 2D As shown, the carrier 9 and the packaging module 2 a are separated by a peeling layer 90 , and the carrier substrate 20 is removed by etching or other methods to obtain a plurality of packaging modules 2 a and expose the second surface 23 b of the encapsulation layer 23 .

[0073] In this embodiment, the package module 2 a retains the conductive bumps 200 and the heat dissipation bumps 201 , such that the conductive bumps 200 and the heat dissipation bumps 201 are exposed on the second surface 23 b of the cladding layer 23 .

[0074] like Figure 2E As shown, the plurality of packaging modules 2 a are symmetrically formed on opposite sides of a support member 8 by pressing, and the packaging modules 2 a are pressed onto the support member 8 with their first circuit layers 24 .

[0075] In this embodiment, the support member 8 has a tape 80 , so that the tape 80 covers the first circuit layer 24 , so that the first circuit layer 24 is embedded in the tape 80 , and the second surface 23 b of the covering layer 23 of the packaging module 2 a faces outward.

[0076] like Figure 2F As shown, a circuit structure 25 is formed on the second surface 23 b of the cladding layer 23 of each packaging module 2 a.

[0077] In this embodiment, the circuit structure 25 includes at least one insulating layer 250 formed on the cladding layer 23 and second circuit layers 251 and 252 formed on the insulating layer 250. The second circuit layers 251 and 252 electrically connect the conductive bumps 200 and the heat dissipation bumps 201. For example, the second circuit layers 251 and 252 are formed using a build-up process by electroplating metal (e.g., copper) or other methods. It should be understood that using the build-up process, multiple insulating layers can be added to the circuit structures 25 as needed to form multiple circuit layers.

[0078] Furthermore, the material forming the insulating layer 250 is Bismaleimidetriazine (BT) or Ajinomoto build-up film (ABF), which is different from the material forming the cladding layer 23. For example, if the insulating layer 250 is made of BT, its coefficient of thermal expansion (CTE) is 10-15 ppm / °C, while if the cladding layer 23 is made of EMC material, its CTE is 6-10 ppm / °C. Therefore, the insulating layer 250 is strong enough to prevent warping caused by uneven thermal stress distribution.

[0079] like Figure 2G As shown, the support member 8 and the tape 80 are removed to obtain a plurality of electronic packages 2 .

[0080] In this embodiment, before or after removing the support member 8 and the tape 80, an insulating protective layer 28 such as a solder mask can be formed on the outermost insulating layer 250 of the circuit structure 25 as required. Figure 2H As shown, portions of the surfaces of the second wiring layers 251 and 252 are exposed for bonding conductive elements 29, such as solder balls. For example, the CTE of the insulating protective layer 28 is less than 20 ppm / °C, and the insulating protective layer 28 contains a filler material such as aluminum oxide (Al2O3), aluminum hydroxide (Al(OH)3), or other polymers such as P-compound, enabling the insulating protective layer 28 to meet the fine line / fine pitch (L / S) wiring requirements of the circuit structure 25.

[0081] Furthermore, since the solder mask layer has a filler composition, it can strengthen the insulating protective layer 28 to enhance its toughness. Therefore, when the circuit structure 25 has only a single insulating layer 250, such as Figure 2H-1As shown, by supporting the insulating layer 250 with the insulating protection layer 28 , the electronic package 2 can be prevented from warping due to factors such as stress shrinkage or asymmetrical construction.

[0082] Therefore, if the insulating layer 250 needs to be thinned, the insulating protective layer 28 can prevent the electronic package 2 from warping, so that the insulating layer 250 can be as thin as possible. Therefore, the electronic package 2 can simultaneously meet the requirements of thinning and preventing warping.

[0083] In addition, the conductive element 29 is electrically connected to the conductive bump 200 via the second circuit layer 251 , while the second circuit layer 252 electrically connected to the heat dissipation bump 201 may not be combined with the conductive element 29 , such as at the opening 280 of the insulating protection layer 28 .

[0084] In addition, in other embodiments, Figure 3 In the electronic package 3 shown, the electronic component 32 can be electrically connected to the electrode pad 220 and the conductive bump 200 via a wire 341 using a wire bonding method, thereby omitting the process associated with the conductor 241. It should be understood that in other embodiments (not shown), the electronic component can also be electrically connected to the heat dissipation bump via a wire.

[0085] Therefore, the manufacturing method of the present invention mainly saves the use space on the first surface 23a of the coating layer 23 by embedding the electronic components 22, 32 in the coating layer 23, thereby facilitating the thinning of the electronic packages 2, 3. Therefore, compared with the prior art, the manufacturing method of the present invention can thin the electronic packages 2, 3 to meet the requirements of miniaturization.

[0086] Furthermore, by combining the electronic components 22, 32 with the adhesive layer 21, the solder bumps 11 and reflow process used in conventional flip-chip designs are replaced. Thus, when the electronic packages 2, 3 meet miniaturization requirements, the risk of warping caused by high-temperature environments (or thermal cycles) can be effectively reduced. Furthermore, by using the carrier 9 and support 8 to perform two symmetrical pressing operations, the warping problem during the production of the electronic packages 2, 3 can be further avoided.

[0087] In addition, by embedding the heat dissipation bump 201 in the coating layer 23, the heat dissipation path can be optimized to enhance the heat dissipation effect. Therefore, when the electronic package 2, 3 is to meet the demand for miniaturization, the electronic package 2, 3 is suitable for the design of thinning the insulating layer 250 without warping due to high temperature environment (or thermal cycle).

[0088] In addition, heat energy from the electronic component 22 can be guided to the opening 280 corresponding to the second circuit layer 252 by the heat dissipation bump 201 and dissipated to the outside, thereby effectively ensuring the heat dissipation capability of the electronic package 2 , 3 .

[0089] The present invention further provides an electronic package 2 , 3 , comprising: a covering layer 23 , a first circuit layer 24 , at least one heat dissipation bump 201 , at least one electronic component 22 , 32 , and a circuit structure 25 .

[0090] The coating layer 23 has a first surface 23 a and a second surface 23 b opposite to each other.

[0091] The first circuit layer 24 is formed on the first surface 23 a of the cladding layer 23 .

[0092] The heat dissipation bumps 201 are embedded in the second surface 23 b of the cladding layer 23 .

[0093] The electronic components 22 , 32 are embedded in the cladding layer 23 and disposed on the heat dissipation bump 201 .

[0094] The circuit structure 25 is formed on the second surface 23b of the cladding layer 23. The circuit structure 25 includes at least one insulating layer 250 formed on the cladding layer 23 and second circuit layers 251, 252 formed on the insulating layer 250. The second circuit layer 252 is electrically connected to the heat dissipation bump 201, so that the electronic components 22, 32 can dissipate heat through the second circuit layer 252 and the heat dissipation bump 201. The insulating layer 250 is formed of bismaleimide triazine (BT) or Ajinomoto build-up film (ABF).

[0095] In one embodiment, a plurality of conductive bumps 200 are embedded in the second surface 23b of the cladding layer 23, so that the first circuit layer 24 is electrically connected to the plurality of conductive bumps 200 via conductors 240. For example, the electronic component 32 is electrically connected to the conductive bumps 200 via wires 341.

[0096] In one embodiment, the electronic components 22 , 32 are bonded to the heat dissipation bump 201 via an adhesive layer 21 .

[0097] In one embodiment, the electronic package 2 , 3 further includes an insulating protective layer 28 formed on the circuit structure 25 and exposing a portion of the surface of the second circuit layers 251 , 252 , wherein the insulating protective layer 28 has a filling material.

[0098] In summary, the electronic package and its manufacturing method of the present invention saves the space on the first surface of the covering layer by embedding the electronic component in the covering layer, thereby facilitating the thinning of the electronic package. Therefore, the manufacturing method of the present invention can thin the electronic package to meet the requirements of miniaturization.

[0099] Furthermore, by combining the electronic components with the adhesive layer, the solder bumps and reflow process used in conventional flip-chips can be replaced. This effectively reduces the risk of warping caused by high-temperature environments (or thermal cycles) when the electronic package meets miniaturization requirements. Furthermore, by using the carrier and support members to perform two symmetrical pressing operations, warping during the electronic package manufacturing process can be avoided.

[0100] In addition, by embedding the heat dissipation bump in the coating layer, the heat dissipation path can be optimized to enhance the heat dissipation effect. Therefore, when the electronic package is to meet the demand for miniaturization, the electronic package is suitable for the design of thinning the insulation layer without warping due to high temperature environment (or thermal cycle).

[0101] In addition, heat energy from the electronic component can be guided to the opening corresponding to the second circuit layer by the heat dissipation bump and dissipated to the outside, thereby effectively ensuring the heat dissipation capability of the electronic package.

[0102] The above embodiments are intended only to illustrate the principles and effects of the present invention and are not intended to limit the present invention. Those skilled in the art may modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be as set forth in the claims.

Claims

1. A method for manufacturing an electronic package, comprising: A carrier substrate is respectively disposed on two opposite sides of a carrier, wherein the carrier substrate has at least one heat dissipation bump; Disposing an electronic component on the heat dissipation bump, wherein the electronic component is bonded to the heat dissipation bump via an adhesive layer; forming a coating layer on the carrier substrate to cover the heat dissipation bump and the electronic component, wherein the coating layer has a first surface and a second surface opposite to each other, so that the coating layer is bonded to the carrier substrate with its second surface; forming a first circuit layer on the first surface of the cladding layer to form a packaging module; Removing the carrier and the carrier substrate to obtain a plurality of the packaging modules and exposing the second surface of the covering layer, wherein the packaging modules retain the heat dissipation bumps so that the heat dissipation bumps are exposed on the second surface of the covering layer; The packaging modules are respectively arranged on opposite sides of a support member, and each packaging module is pressed onto the support member with its first circuit layer, so that the second surface of the covering layer faces outward; forming a circuit structure on the second surface of the cladding layer, wherein the circuit structure includes at least an insulating layer formed on the cladding layer and a second circuit layer formed on the insulating layer, wherein the second circuit layer is electrically connected to the heat dissipation bump, so that the electronic component dissipates heat through the second circuit layer and the heat dissipation bump, and the insulating layer is formed of a material of bis(maleic acid imide) / trinitrogen trap or ajinomoto build-up layer film; and Remove the support.

2. The method for manufacturing an electronic package according to claim 1, wherein: The carrier substrate also has a plurality of conductive bumps. The second surface of the cladding layer is embedded with the plurality of conductive bumps, so that the first circuit layer is electrically connected to the plurality of conductive bumps through a conductor.

3. The method for manufacturing an electronic package according to claim 2, wherein: The electronic component is electrically connected to the conductive bump via a wire.

4. The method for manufacturing an electronic package according to claim 1, wherein: The manufacturing method further comprises forming an insulating protection layer on the circuit structure, wherein the insulating protection layer exposes a portion of the surface of the second circuit layer, wherein the insulating protection layer has a filling material.

5. An electronic package manufactured by the method for manufacturing an electronic package according to any one of claims 1 to 4, comprising: a cladding layer having a first surface and a second surface opposite to each other; A first circuit layer is formed on the first surface of the cladding layer; a heat dissipation bump embedded in the second surface of the covering layer; an electronic component embedded in the coating layer and disposed on the heat dissipation bump, wherein the electronic component is bonded to the heat dissipation bump via an adhesive layer; and A circuit structure is formed on the second surface of the cladding layer, wherein the circuit structure includes at least one insulating layer formed on the cladding layer and a second circuit layer formed on the insulating layer, so that the second circuit layer is electrically connected to the heat dissipation bump, so that the electronic component dissipates heat through the second circuit layer and the heat dissipation bump, and the material forming the insulating layer is bis(maleic acid imide) / trinitrogen trap or Ajinomoto build-up layer film.

6. The electronic package according to claim 5, wherein: A plurality of conductive bumps are embedded in the second surface of the cladding layer, so that the first circuit layer is electrically connected to the plurality of conductive bumps via a conductor.

7. The electronic package according to claim 6, wherein: The electronic component is electrically connected to the conductive bump via a wire.

8. The electronic package according to claim 5, wherein: The electronic package further includes an insulating protection layer formed on the circuit structure and exposing a portion of the surface of the second circuit layer, wherein the insulating protection layer has a filling material.

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