Semiconductor device and method for forming the same
By forming the MIM capacitors of the groove inner wall on the semiconductor substrate and using the groove-shaped insulating layer, the short circuit problem and insufficient capacity of the MIM capacitor during the dry etching process is solved, and higher capacitance density and simplification are achieved The process flow reduces costs.
Patent Information
- Application Number
- CN202411117011.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-15
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2044-08-15
AI Technical Summary
Existing MIM capacitors are prone to short-circuit problems during dry etching, and the capacitance is small, which cannot meet the performance requirements of semiconductor devices. The multi-layer stacking structure of high dielectric layers increases process complexity and cost.
By forming a plurality of spaced grooves on the semiconductor substrate, forming a MIM capacitor on the inner wall of the groove, and covering the first dielectric layer, a multi-layer stacking structure with a groove-shaped structure as an insulating layer instead of a high dielectric layer, Use wet etching process to avoid short circuit problems and improve capacitance.
A MIM capacitor with a larger specific surface area is realized, the specific capacitance density per unit area is improved, the area occupied by MIM capacitors is reduced, the structure is simplified, the process cost is reduced, and the integration and capacitance are improved.
Smart Images
Figure CN118647260B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor device and a method for forming the same. Background Art
[0002] There are various capacitor structures in integrated circuit chips, such as MOS field effect transistor capacitors, PIP capacitors, variable junction capacitors, and metal-insulator-metal (MIM) capacitors and metal-oxide-metal (MOM) capacitors in the back-end interconnection. Currently, the capacitor structures commonly used in the interconnection structure are MIM capacitors and MOM capacitors, both of which have the performance of resisting external noise interference, especially MIM capacitors have better performance in resisting external interference.
[0003] MIM capacitors are placed as filters between the top metal layer of the semiconductor interconnect structure and the aluminum metal layer above it to protect the semiconductor device from external noise interference. Figure 1 As shown, a MIM capacitor is embedded in the dielectric layer between the top metal layer TM1 and the top metal layer TM2, and the MIM capacitor includes a bottom plate 1, a dielectric layer 3 and a top plate 2 from bottom to top, wherein the thickness of the top plate 2 is thicker than that of the bottom plate 1, for example, the thickness of the top plate 2 is twice that of the bottom plate 1, as shown in FIG. Figure 2 As shown, in area A, when the top plate 2 and the dielectric layer 3 are dry-etched, metal will accumulate on both sides of the dielectric layer 3, so that the top plate 2 and the bottom plate 1 are connected, causing a short circuit. At the same time, when the top plate is dry-etched, due to different pattern densities, the top plate 2 is not completely etched in some areas (area B), causing the contact holes connected to the bottom plate 1 to mistakenly connect to the top plate 2 when the contact holes are subsequently formed, causing a short circuit. As semiconductor processes become more and more advanced, the performance requirements for semiconductor devices are gradually increasing. Common MIM capacitors have a small capacitance and cannot meet the needs of semiconductor devices. Therefore, in order to obtain a larger capacitance, it is usually necessary to design the dielectric layer as a multilayer stacked structure containing a high dielectric layer (HK layer), and the high dielectric layer requires special deposition equipment and etching equipment, which increases the process complexity and process cost. Summary of the invention
[0004] One of the objectives of the present invention is to provide a semiconductor device that can increase the capacitance of a MIM capacitor.
[0005] Another object of the present invention is to provide a method for forming a semiconductor device, which can avoid the short circuit problem that occurs when the top plate is dry-etched.
[0006] The present invention provides a semiconductor device, comprising a semiconductor substrate, a first dielectric layer is arranged on the semiconductor substrate, the first dielectric layer comprises a first region, a plurality of grooves arranged at intervals are arranged in the first dielectric layer of the first region, a MIM capacitor is formed on the inner wall of the groove, the MIM capacitor also covers the first dielectric layer of the first region, a second dielectric layer is arranged on the first dielectric layer, the second dielectric layer covers the MIM capacitor and fills the groove.
[0007] Optionally, the semiconductor substrate includes an interconnect structure layer located on a base, the interconnect structure layer is provided with a first top metal layer on a side away from the base, and a second top metal layer is provided on the second dielectric layer.
[0008] Optionally, the MIM capacitor includes a first metal layer, an insulating layer and a second metal layer from bottom to top, the first metal layer covers the inner wall of the groove and the first dielectric layer of the first area, the insulating layer covers the first metal layer, and the second metal layer exposes part of the insulating layer at the edge of the first area.
[0009] Furthermore, the materials of the first metal layer and the second metal layer are both titanium nitride, and the material of the insulating layer is silicon oxide or silicon nitride.
[0010] Furthermore, the first dielectric layer and the second dielectric layer are both TEOS layers.
[0011] On the other hand, the present invention also provides a method for forming a semiconductor device, comprising the following steps:
[0012] A semiconductor substrate is provided, on which a first dielectric layer is formed, the first dielectric layer includes a first region, and an imaged first photoresist layer is formed on the first dielectric layer, the imaged first photoresist layer has a plurality of openings arranged at intervals in the first region;
[0013] At the opening, using the imaged first photoresist layer as a mask, etching the first dielectric layer and exposing the semiconductor substrate to form a groove;
[0014] forming a MIM capacitor on the inner wall of the groove, wherein the MIM capacitor also covers the first dielectric layer of the first region;
[0015] A second dielectric layer is formed on the first dielectric layer, and the second dielectric layer covers the MIM capacitor and fills the groove.
[0016] Optionally, the MIM capacitor includes, from bottom to top, a first metal layer, an insulating layer, and a second metal layer, and the method for forming the MIM capacitor is specifically as follows:
[0017] forming a first metal layer and an insulating layer in sequence on the inner wall of the groove by a deposition process, wherein the first metal layer also covers the first dielectric layer in the first region;
[0018] Using a mask technology, the insulating layer and the first metal layer are sequentially etched by a wet etching process to expose the first dielectric layer outside the first region;
[0019] forming a second metal layer on the insulating layer by a deposition process, wherein the second metal layer also covers the first dielectric layer outside the first region;
[0020] The second metal layer is etched by a wet etching process using a mask technology to expose the first dielectric layer outside the first metal layer and a portion of the insulating layer at the edge of the first region.
[0021] Furthermore, a first metal layer is formed on the inner wall of the groove by an ALD deposition process.
[0022] Furthermore, a second metal layer is formed on the insulating layer by an ALD deposition process.
[0023] Furthermore, the materials of the first metal layer and the second metal layer are both titanium nitride, and the material of the insulating layer is silicon oxide or silicon nitride.
[0024] Compared with the prior art, the present invention has the following unexpected technical effects:
[0025] The present invention provides a semiconductor device and a method for forming the same. The semiconductor device includes a semiconductor substrate, a first dielectric layer is arranged on the semiconductor substrate, the first dielectric layer includes a first region, a plurality of grooves are arranged at intervals in the first dielectric layer of the first region, a MIM capacitor is formed on the inner wall of the groove, the MIM capacitor also covers the first dielectric layer of the first region, a second dielectric layer is arranged on the first dielectric layer, the second dielectric layer covers the MIM capacitor and fills the groove. The present invention forms the MIM capacitor on the inner wall of the groove and the first dielectric layer of the first region. Compared with the planar MIM capacitor formed only on the surface of the first dielectric layer in the prior art, a MIM capacitor with a larger specific surface area can be obtained in the same region through the groove. If an insulating layer of the same material is used, a larger specific capacitance density per unit area can be obtained or the area occupied by the MIM capacitor can be reduced to match the device requirements, thereby improving the integration; if a single-layer dielectric layer with a groove-shaped structure is used as an insulating layer to replace the existing multi-layer stacked structure with a planar high dielectric layer as the insulating layer of the MIM capacitor, it can avoid the use of additional special equipment for deposition and etching of high dielectric materials, simplify the structure of the semiconductor device, reduce the process cost, and increase the capacitance. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 Schematic diagram of the structure of current semiconductor devices.
[0027] Figure 2 This is a schematic diagram of the structure of the current conductor device after etching the top plate of the MIM capacitor.
[0028] Figure 3 It is a schematic diagram of the structure after forming a patterned first photoresist layer according to an embodiment of the present invention.
[0029] Figure 4 FIG. 4 is a schematic diagram of the structure of an embodiment of the present invention after a groove is formed.
[0030] Figure 5 FIG. 4 is a schematic diagram of the structure of an embodiment of the present invention after depositing an insulating layer.
[0031] Figure 6 It is a schematic diagram of the structure after forming an imaged second photoresist layer according to an embodiment of the present invention.
[0032] Figure 7 It is a schematic diagram of the structure after etching the insulating layer according to an embodiment of the present invention.
[0033] Figure 8 FIG. 4 is a schematic diagram of the structure of an embodiment of the present invention after depositing the second metal layer.
[0034] Fig. 9 It is a schematic diagram of the structure after forming a patterned third photoresist layer according to an embodiment of the present invention.
[0035] Fig.10 It is a schematic diagram of the structure after etching the second metal layer according to an embodiment of the present invention.
[0036] Fig.11 FIG. 4 is a schematic diagram of the structure after forming a capping layer according to an embodiment of the present invention.
[0037] Fig.12 A schematic structural diagram of a semiconductor device provided by an embodiment of the present invention.
[0038] Description of reference numerals:
[0039] Figure 1-Figure 2 middle:
[0040] 1- bottom plate; 2- top plate; 3- dielectric layer;
[0041] Figure 3-Figure 12 middle:
[0042] 100-substrate; 110-interconnection structure layer; 111-first top metal layer; 120-first etch stop layer; 130-bottom dielectric layer; 140-second etch stop layer; 150-first dielectric layer; 151-groove; 210-first metal layer; 220-insulating layer; 230-second metal layer; 240-cap layer; 310-first photoresist layer; 320-second photoresist layer; 330-third photoresist layer; 410-second dielectric layer; 421-first conductive pillar; 422-second conductive pillar; 430-second top metal layer. DETAILED DESCRIPTION
[0043] A semiconductor device and a method for forming the same of the present invention will be described in further detail below. The present invention will be described in more detail below with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown, and it should be understood that those skilled in the art may modify the present invention described herein and still achieve the beneficial effects of the present invention. Therefore, the following description should be understood as being broadly known to those skilled in the art and not as a limitation of the present invention.
[0044] For the sake of clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would clutter the invention with unnecessary detail. It should be recognized that in the development of any actual embodiment, a large number of implementation details must be made to achieve the developer's specific goals, such as changing from one embodiment to another according to the limitations of the relevant system or the relevant business. In addition, it should be recognized that such development work may be complex and time-consuming, but it is just a routine task for those skilled in the art.
[0045] In order to make the purpose and features of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are further described below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and use inaccurate ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0046] like Fig.12 As shown, this embodiment provides a semiconductor device, including a semiconductor substrate, on which a first dielectric layer 150 is arranged, the first dielectric layer 150 includes a first region, a plurality of grooves 151 arranged at intervals are arranged in the first dielectric layer 150 in the first region, a MIM capacitor is formed on the inner wall of the groove 151, and the MIM capacitor also covers the first dielectric layer 150 in the first region, a second dielectric layer 410 is arranged on the first dielectric layer 150, and the second dielectric layer 410 covers the MIM capacitor and fills the groove 151.
[0047] In this embodiment, the MIM capacitor is formed on the inner wall of the groove 151 in the first region and on the first dielectric layer 150. Compared with the planar MIM capacitor formed only on the surface of the first dielectric layer 150 in the prior art, a MIM capacitor with a larger specific surface area can be obtained in the same region through the groove 151. If the insulating layer 220 made of the same material is used, a larger specific capacitance density per unit area can be obtained or the area occupied by the MIM capacitor can be reduced to match the corresponding device performance, thereby improving the integration level. If a single-layer dielectric layer with a groove-shaped structure is used as the insulating layer 220 to replace the existing planar multi-layer stacked structure containing a high dielectric layer as the insulating layer 220 of the MIM capacitor, the use of additional dedicated equipment for deposition and etching of high dielectric materials can be avoided, the structure of the semiconductor device is simplified, the process cost is reduced, and the capacitance can be increased.
[0048] In detail, the semiconductor substrate includes a base 100 and an interconnection structure layer 110, wherein the interconnection structure layer 110 is located on the base 100, and the interconnection structure layer 110 includes a plurality of bottom metal layers, a first top metal and an interlayer dielectric layer spaced apart along a thickness direction, all of the bottom metal layers are embedded in the interlayer dielectric layer, and the first top metal layer 111 is located on the interlayer dielectric layer.
[0049] The first top metal layer 111 is provided with a first etch stop layer 120, a bottom dielectric layer 130, a second etch stop layer 140 and a first dielectric layer 150 in sequence. The first etch stop layer 120 covers the first top metal layer 111, and the bottom dielectric layer 130 is used to isolate the semiconductor substrate and the MIM capacitor. In order to achieve a better isolation effect between the semiconductor substrate and the MIM capacitor and reduce parasitic capacitance, the material of the bottom dielectric layer 130 is a low-K material, an ultra-low-K material or an oxide. In this embodiment, the material of the bottom dielectric layer 130 is silicon oxide.
[0050] The bottom dielectric layer 130 covers the surface of the first etch stop layer 120. The material of the first etch stop layer 120 is a material having a greater etching selectivity than the bottom dielectric layer 130, such as silicon nitride.
[0051] The second etch stop layer 140 is used as an etch stop layer when forming the groove 151 , and its material selection ratio is greater than that of the first dielectric layer 150 , such as silicon nitride.
[0052] The first dielectric layer 150 includes a first region, and the first region is used to form a MIM capacitor. A groove 151 with a preset line width and a preset interval is provided in the first dielectric layer 150 to adjust the area of the subsequent formation of the MIM capacitor (i.e., the total area of the MIM capacitor on the inner wall of the groove 151 and the MIM capacitor on the first dielectric layer 150). In the first region, the groove 151 passes through the first dielectric layer 150 and exposes the second etch stop layer 140. The material of the first dielectric layer 150 can be an oxide layer, such as a TEOS layer.
[0053] The MIM capacitor is arranged on the inner wall of the groove 151 and covers the first dielectric layer 150 in the first area. The MIM capacitor includes a first metal layer 210, an insulating layer 220 and a second metal layer 230 from bottom to top, wherein the first metal layer 210 covers the inner wall (side wall and bottom wall) of the groove 151 and the surface of the first dielectric layer 150 in the first area, the insulating layer 220 covers the first metal layer 210, and the second metal layer 230 covers the insulating layer 220 and exposes a part of the edge of the insulating layer 220. The materials of the first metal layer 210 and the second metal layer 230 are, for example, titanium nitride. In this embodiment, the material of the insulating layer 220 can be silicon oxide, silicon nitride, etc. In this way, under the premise of achieving the same capacitance, there is no need to use a multilayer stacked structure containing a high dielectric layer (HK layer) as the insulating layer 220, so there is no need to use special deposition equipment and etching equipment to form the insulating layer 220, thereby reducing process complexity and process cost. In addition, the use of the groove 151 can increase the unit capacitance density of the MIM capacitor in the same area (the area occupied on the plane perpendicular to the thickness direction).
[0054] The second metal layer 230 is covered with an oxide layer, which can prevent the second metal layer 230 from being oxidized, and the first oxide layer is provided with a cap layer 240, which also covers the insulating layer 220 and the first dielectric layer 150 outside the oxide layer. The oxide layer can be a TEOS layer, and the material of the cap layer 240 is silicon oxynitride.
[0055] A second dielectric layer 410 is disposed on the first dielectric layer 150, and the second dielectric layer 410 covers the cap layer 240 and fills the groove 151. A second top metal layer 430 is disposed on the second dielectric layer 410, and the second top metal layer 430 may be a connection layer for external devices.
[0056] A first conductive column 421 is arranged between the first metal layer 210 and the second top metal layer 430. The first conductive column 421 is arranged at the edge of the first metal layer 210 and is located outside the second metal layer 230. The first conductive column 421 passes through the second dielectric layer 410, the cap layer 240 and the insulating layer 220, and the two ends contact the first metal layer 210 and the second top metal layer 430 respectively.
[0057] A second conductive column 422 is disposed between the second metal layer 230 and the second top metal layer 430 . The second conductive column 422 is disposed above the second metal layer 230 and passes through the second dielectric layer 410 and the cap layer 240 , and contacts the second metal layer 230 and the second top metal layer 430 at both ends.
[0058] A third conductive column is disposed between the first top metal layer 111 and the second top metal layer 430, and the third conductive column is disposed outside the MIM capacitor and passes through the second dielectric layer 410, the cap layer 240, the first dielectric layer 150, the second etch stop layer 140, the bottom dielectric layer 130 and the first etch stop layer 120, and the two ends are respectively in contact with the first top metal layer 111 and the second top metal layer 430. The material of the second dielectric layer 410 and the material of the first dielectric layer 150 may be the same.
[0059] This embodiment also provides a method for forming a semiconductor device, comprising the following steps:
[0060] Step S1: providing a semiconductor substrate, on which a first dielectric layer 150 is formed, the first dielectric layer 150 including a first region, and forming an imaged first photoresist layer 310 on the first dielectric layer 150, the imaged first photoresist layer 310 having a plurality of openings spaced apart in the first region;
[0061] Step S2: At the opening, using the patterned first photoresist layer 310 as a mask, etching the first dielectric layer 150 and exposing the semiconductor substrate to form a groove 151;
[0062] Step S3: forming a MIM capacitor on the inner wall of the groove 151, wherein the MIM capacitor also covers the first dielectric layer 150 in the first region;
[0063] Step S4 : forming a second dielectric layer 410 on the first dielectric layer 150 , wherein the second dielectric layer 410 covers the MIM capacitor and fills the groove 151 .
[0064] The following combination Figure 3-Figure 12A method for forming a semiconductor device provided in this embodiment is described in detail.
[0065] like Figure 3 As shown, step S1 is first performed to provide a semiconductor substrate, and a first dielectric layer 150 is formed on the semiconductor substrate, wherein the first dielectric layer 150 includes a first region, and an imaged first photoresist layer 310 is formed on the first dielectric layer 150, wherein the imaged first photoresist layer 310 has a plurality of openings spaced apart in the first region.
[0066] The specific steps of this step are:
[0067] First, a semiconductor substrate is provided, wherein the semiconductor substrate includes a base 100 and an interconnection structure layer 110, wherein the interconnection structure layer 110 is located on the base 100, and the interconnection structure layer 110 includes a plurality of bottom metal layers, a first top metal and an interlayer dielectric layer spaced apart along a thickness direction, wherein all the bottom metal layers are embedded in the interlayer dielectric layer, and the first top metal layer 111 is located on the interlayer dielectric layer.
[0068] Next, a first etch stop layer 120 and a bottom dielectric layer 130 are sequentially formed on the first top metal layer 111. The first etch stop layer 120 covers the first top metal layer 111, and the bottom dielectric layer 130 is subsequently used to isolate the semiconductor substrate and the MIM capacitor. In order to achieve a better isolation effect between the semiconductor substrate and the MIM capacitor and reduce parasitic capacitance, the material of the bottom dielectric layer 130 is a low-K material, an ultra-low-K material or an oxide, and the formation process is a chemical vapor deposition process. In this embodiment, the bottom dielectric layer 130 is formed by a chemical vapor deposition process, and its material is silicon oxide.
[0069] The bottom dielectric layer 130 covers the surface of the first etch stop layer 120. The first etch stop layer 120 is made of a material having a higher etching rate than the bottom dielectric layer 130 (under the same process conditions), such as silicon nitride.
[0070] Next, a second etch stop layer 140 and a first dielectric layer 150 are sequentially formed on the bottom dielectric layer 130. The first dielectric layer 150 includes a first region, and the first region is used to form a MIM capacitor. The first dielectric layer 150 is a TEOS layer. The second etch stop layer 140 covers the bottom dielectric layer 130 and serves as an etch stop layer for forming the groove 151. The material of the second etch stop layer 140 is a material having a greater etching rate than the first dielectric layer 150 (under the same process conditions), such as silicon nitride.
[0071] Next, a patterned first photoresist layer 310 is formed on the first dielectric layer 150 , and the patterned first photoresist layer 310 has a plurality of openings arranged at intervals in the first region.
[0072] like Figure 4 As shown, step S2 is then performed, at the opening, the first dielectric layer 150 is etched using the patterned first photoresist layer 310 as a mask, and the semiconductor substrate is exposed to form a groove 151. In detail, at the opening, the first dielectric layer 150 is etched by a wet etching process using the patterned first photoresist layer 310 as a mask to form a groove 151, and the groove 151 exposes the second etch stop layer 140.
[0073] Next, the first photoresist layer 310 is removed.
[0074] like Figure 5-Figure 11 As shown, step S3 is then performed to form a MIM capacitor on the inner wall of the groove 151, and the MIM capacitor also covers the first dielectric layer 150 in the first area.
[0075] This step specifically includes:
[0076] like Figure 5 As shown, first, a first metal layer 210 is sequentially formed on the inner wall of the groove 151 by a deposition process. The first metal layer 210 can be deposited by any number of well-known deposition techniques such as PVD (physical vapor deposition), CVD (chemical vapor deposition), or ALD (atomic layer deposition). Preferably, the present embodiment adopts ALD deposition to form the first metal layer 210, so as to form a better step coverage in the groove 151. The material of the first metal layer 210 can be titanium nitride.
[0077] Please continue reading Figure 5 Then, an insulating layer 220 is formed on the first metal layer 210 by a deposition process. The material of the insulating layer 220 can be silicon oxide, silicon nitride, etc., and the deposition process of the insulating layer 220 can be obtained by a conventional deposition process, such as CVD. Compared with the prior art that uses a multi-layer stacked structure containing a high dielectric layer as the insulating layer 220 of the MIM capacitor, this embodiment uses a single layer of silicon oxide as the insulating layer 220. On the basis of not reducing the capacitance of the MIM capacitor or even increasing the capacitance, the area of the first dielectric layer 150 occupied by the capacitor is not increased, the structure of the MIM capacitor is simplified, and no special deposition equipment and etching equipment are required, thereby reducing the process complexity and process cost.
[0078] like Figure 6As shown, next, a patterned second photoresist layer 320 is formed on the insulating layer 220 , and the patterned second photoresist layer 320 covers the first region and exposes the insulating layer 220 outside the first region.
[0079] like Figure 7 As shown, the insulating layer 220 and the first metal layer 210 are sequentially etched by a wet etching process using the imaged second photoresist layer 320 as a mask to expose the first dielectric layer 150 outside the first region. Since the load effect of the wet etching process is smaller than that of the dry etching process, this step avoids the load effect, and the isotropic etching of the wet etching avoids the longitudinal over-etching defect at the sidewall of the MIM capacitor, thereby improving the performance and reliability of the MIM capacitor.
[0080] Next, the second photoresist layer 320 is removed.
[0081] like Figure 8 As shown, a second metal layer 230 and an oxide layer are sequentially deposited on the insulating layer 220, and the second metal layer 230 also covers the first dielectric layer 150 outside the insulating layer 220. The second metal layer 230 can be deposited by any number of well-known deposition techniques such as PVD (physical vapor deposition), CVD (chemical vapor deposition), or ALD (atomic layer deposition). Preferably, in this embodiment, ALD deposition is used to form the second metal layer 230 to form a better step coverage in the groove 151. The material of the second metal layer 230 can be titanium nitride.
[0082] like Fig. 9 As shown, then, a patterned third photoresist layer 330 is formed on the oxide layer, and the patterned third photoresist layer 330 covers most of the first region and exposes the oxide layer at the edge of the first region.
[0083] like Fig.10 As shown, then, the oxide layer and the second metal layer 230 are sequentially etched by a wet etching process using the imaged third photoresist layer 330 mask to expose the first dielectric layer 150 outside the first metal layer 210 and the insulating layer 220 at the edge of the first region. Since the load effect of the wet etching process is smaller than that of the dry etching process, the etching effect brought by the etching process in this step is smaller, which avoids the metal accumulation on both sides of the insulating layer 220 caused by etching, thereby avoiding the occurrence of the short circuit problem, and also solves the problem of incomplete etching of the second metal layer 230 caused by different pattern densities. The isotropic etching of the wet etching avoids the longitudinal over-etching defect at the sidewall of the MIM capacitor, thereby improving the performance and reliability of the MIM capacitor.
[0084] Next, the third photoresist layer 330 is removed.
[0085] like Fig.11 As shown, then, a capping layer 240 is formed on the second metal layer 230, and the capping layer 240 also covers the exposed first dielectric layer 150 and the insulating layer 220. The capping layer 240 can improve thermal stability and protect the second metal layer 230 as a diffusion barrier layer. The material of the capping layer 240 is silicon oxynitride.
[0086] like Fig.12 As shown, step S4 is then performed to form a second dielectric layer 410 on the first dielectric layer 150 , wherein the second dielectric layer 410 covers the MIM capacitor and fills the groove 151 .
[0087] In detail, first, a second dielectric layer 410 is formed on the first dielectric layer 150 through a deposition process, and the second dielectric layer 410 covers the cap layer 240 and fills the groove 151 .
[0088] Next, a first contact hole, a second contact hole and a third contact hole are formed, wherein the first contact hole is located at the edge of the first metal layer 210 and outside the second metal layer 230, and the first contact hole passes through the second dielectric layer 410, the cap layer 240 and the insulating layer 220, and exposes the first metal layer 210; the second contact hole is located above the second metal layer 230, passes through the second dielectric layer 410 and the cap layer 240, and exposes the second metal layer 230; the third contact hole is located outside the MIM capacitor, passes through the second dielectric layer 410, the cap layer 240, the first dielectric layer 150, the second etch stop layer 140, the bottom dielectric layer 130 and the first etch stop layer 120, and exposes the first top metal layer 111.
[0089] Next, the first contact hole, the second contact hole and the third contact hole are filled to form a first conductive column 421 in the first contact hole, a second conductive column 422 in the second contact hole, a third conductive column in the third contact hole, and a second top metal layer 430 is formed on the second dielectric layer 410.
[0090] In summary, the present invention provides a semiconductor device and a method for forming the same, wherein the semiconductor device comprises a semiconductor substrate, a first dielectric layer is arranged on the semiconductor substrate, the first dielectric layer comprises a first region, a plurality of grooves are arranged at intervals in the first dielectric layer of the first region, a MIM capacitor is formed on the inner wall of the groove, the MIM capacitor also covers the first dielectric layer of the first region, a second dielectric layer is arranged on the first dielectric layer, the second dielectric layer covers the MIM capacitor and fills the groove. The present invention forms the MIM capacitor on the inner wall of the groove and the first dielectric layer of the first region, and compared with the planar MIM capacitor formed only on the surface of the first dielectric layer in the prior art, a MIM capacitor with a larger specific surface area can be obtained through the groove in the same region, and if an insulating layer of the same material is used, a larger specific capacitance density per unit area can be obtained or the area occupied by the MIM capacitor can be reduced to match the device requirements, thereby improving the integration; if a single-layer dielectric layer with a groove-shaped structure is used as an insulating layer to replace the existing multi-layer stacked structure with a planar high dielectric layer as the insulating layer of the MIM capacitor, it can avoid the use of additional special equipment for deposition and etching of high dielectric materials, simplify the structure of the semiconductor device, reduce the process cost, and increase the capacitance.
[0091] In addition, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.
[0092] It is to be understood that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.
Claims
1. A method for forming a semiconductor device, characterized in that: The following steps are involved: A semiconductor substrate is provided, on which a first dielectric layer is formed, the first dielectric layer includes a first region, and an imaged first photoresist layer is formed on the first dielectric layer, the imaged first photoresist layer has a plurality of openings arranged at intervals in the first region; At the opening, using the imaged first photoresist layer as a mask, etching the first dielectric layer and exposing the semiconductor substrate to form a groove; A MIM capacitor is formed on the inner wall of the groove, wherein the MIM capacitor also covers the first dielectric layer of the first region, wherein the MIM capacitor includes a first metal layer, an insulating layer, and a second metal layer in sequence from bottom to top; A second dielectric layer is formed on the first dielectric layer, wherein the second dielectric layer covers the MIM capacitor and fills the groove; The method of forming the MIM capacitor is specifically as follows: forming a first metal layer and an insulating layer in sequence on the inner wall of the groove by a deposition process, wherein the first metal layer also covers the first dielectric layer in the first region; Using a mask technology, the insulating layer and the first metal layer are sequentially etched by a wet etching process to expose the first dielectric layer outside the first region; forming a second metal layer on the insulating layer by a deposition process, wherein the second metal layer also covers the first dielectric layer outside the first region, the sidewall of the insulating layer and the sidewall of the first metal layer; Using mask technology, the first dielectric layer located outside the first region, the side wall of the insulating layer and the second metal layer on the side wall of the first metal layer are etched through a wet etching process to expose the first dielectric layer outside the first metal layer and a portion of the insulating layer at the edge of the first region.
2. The method for forming a semiconductor device according to claim 1, wherein: A first metal layer is formed on the inner wall of the groove by an ALD deposition process.
3. The method for forming a semiconductor device according to claim 1, wherein: A second metal layer is formed on the insulating layer by an ALD deposition process.
4. The method for forming a semiconductor device according to claim 1, wherein: The materials of the first metal layer and the second metal layer are both titanium nitride, and the material of the insulating layer is silicon oxide or silicon nitride.
5. A semiconductor device, manufactured by the method for forming a semiconductor device according to claim 1, characterized in that: It includes a semiconductor substrate, a first dielectric layer is arranged on the semiconductor substrate, the first dielectric layer includes a first area, a plurality of grooves arranged at intervals are arranged in the first dielectric layer of the first area, a MIM capacitor is formed on the inner wall of the groove, the MIM capacitor also covers the first dielectric layer of the first area, a second dielectric layer is arranged on the first dielectric layer, the second dielectric layer covers the MIM capacitor and fills the groove.
6. The semiconductor device according to claim 5, characterized in that The semiconductor substrate comprises an interconnection structure layer located on a base, wherein a first top metal layer is arranged on a side of the interconnection structure layer away from the base, and a second top metal layer is arranged on the second dielectric layer.
7. The semiconductor device according to claim 5, characterized in that The MIM capacitor includes, from bottom to top, a first metal layer, an insulating layer, and a second metal layer, wherein the first metal layer covers the inner wall of the groove and the first dielectric layer of the first region, the insulating layer covers the first metal layer, and the second metal layer exposes a portion of the insulating layer at the edge of the first region.
8. The semiconductor device according to claim 7, wherein: The materials of the first metal layer and the second metal layer are both titanium nitride, and the material of the insulating layer is silicon oxide or silicon nitride.
9. The semiconductor device according to claim 7, wherein: The first dielectric layer and the second dielectric layer are both TEOS layers.