A control system and method for a universal load driving chip

Abstract

The present invention discloses a control system and method for a universal load driver chip, relates to the field of control, and is suitable for driving and controlling a variety of loads. The system includes a load, a register address space table, a state vector table, an abnormal protection unit, a driver unit, and an algorithm control engine. The register address space table provides configurable register parameters. The state vector table provides a control vector for a data path. The abnormal protection unit monitors the operating state parameters of the load in real time, and generates an abnormal protection signal when the operating state parameters are abnormal. The driver unit is used to generate a drive signal to drive the load to achieve different working states. The algorithm control engine controls the driver unit to generate a corresponding drive signal according to the control vector, the register parameter, and the abnormal protection signal to achieve driving and controlling the load. The register parameter can change the circuit configuration, thereby improving the flexibility of control and driving.

Description

Technical Field

[0001] The present invention relates to the field of control, and in particular to a control system and method for a universal load driving chip. Background Art

[0002] There are two main solutions for implementing load drive controllers used in application control fields such as motors, power supplies and inverters: software and hardware.

[0003] The development of software solutions can be done with the help of high-level language programming, and the algorithm development and design can be repeatedly modified and iterated. However, the performance indicators of the load are overly dependent on the host microcontroller, and the real-time performance is poor. The hardware solution can solidify the control algorithm in hardware. Compared with the software solution, it has obvious advantages in terms of performance, power consumption, integration, real-time performance and reliability, but the design implementation is closely tied to the actual application, and the algorithm flexibility is low. Summary of the invention

[0004] The present invention provides a control system and method for a universal load driving chip to improve the flexibility of control and driving.

[0005] According to one aspect of the present invention, a control system of a universal load driver chip is provided, comprising: a load, a register address space table, a state vector table, an abnormal protection unit, a driver unit and an algorithm control engine;

[0006] The register address space table is used to provide configurable register parameters;

[0007] The state vector table is used to provide a control vector for the data path;

[0008] The abnormality protection unit is connected to the load, and is used to monitor the operating state parameters of the load in real time, and generate an abnormality protection signal when the operating state parameters are abnormal;

[0009] The driving unit is connected to the load and is used to generate a driving signal to drive the load to achieve different working states;

[0010] The algorithm control engine is connected to the exception protection unit, the register address space table and the state vector table respectively, and is used to control the drive unit to generate the corresponding drive signal according to the control vector, the register parameter and the exception protection signal.

[0011] Optionally, the control system of the universal load driver chip is controlled by means of microinstruction codes, wherein the space of the microinstruction codes includes a basic function domain, a test function domain and an extended function domain.

[0012] Optionally, the algorithm control engine includes at least two layers of state machines, each basic stage in the upper layer state machine corresponds to a lower layer state machine, the lower layer state machine includes multiple sub-stages, and the algorithm control engine is also used to selectively execute each of the basic stages in sequence according to the control vector.

[0013] Optionally, the operating state of the load includes multiple operating actions; the algorithm control engine includes two layers of state machines, the top-level state machine includes the basic stages that correspond one-to-one to the operating states of the load and are arranged in a preset order, wherein the preset order is pre-evaluated and determined based on the actual operating goals of the load and the actual operating process to achieve the actual operating goals; the bottom-level state machine includes the sub-stages that correspond one-to-one to each operating action of the load in the corresponding operating state.

[0014] Optionally, the algorithm control engine is further configured to skip the invalid basic phase when the control vector indicates that the basic phase is invalid.

[0015] Optionally, the load includes at least one of a motor, a power supply and an inverter.

[0016] According to another aspect of the present invention, a control method for a universal load driver chip is provided, which is implemented by using any control system of the universal load driver chip described in the first aspect, and the control method for the universal load driver chip includes:

[0017] The abnormal protection unit monitors the operating state parameters of the load in real time, and generates an abnormal protection signal when the operating state parameters are abnormal;

[0018] The algorithm control engine controls the driving unit to generate the corresponding driving signal according to the control vector, register parameters and the abnormal protection signal, so as to drive the load to achieve different working states, wherein the control vector is provided by a state vector table, and the register parameters are divided by a register address space table.

[0019] Optionally, the algorithm control engine includes at least two layers of state machines, each basic stage in the upper layer state machine corresponds to a lower layer state machine, the lower layer state machine includes multiple sub-stages, and the algorithm control engine is also used to selectively execute each of the basic stages in sequence according to the control vector.

[0020] Optionally, the algorithm control engine is further configured to skip the invalid basic phase when the control vector indicates that the basic phase is invalid.

[0021] The control system and method of the universal load driver chip provided in the embodiment of the present invention are applied to the driving and control of various loads such as motors, power supplies and inverters. The control system of the universal load driver chip includes a load, a register address space table, a state vector table, an abnormal protection unit, a drive unit and an algorithm control engine. The register address space table provides configurable register parameters. The state vector table provides a control vector for the data path. The abnormal protection unit is connected to the load, and the abnormal protection unit monitors the operating state parameters of the load in real time, and generates an abnormal protection signal when the operating state parameters are abnormal. The drive unit is connected to the load and is used to generate a drive signal to drive the load to achieve different working states. The algorithm control engine controls the drive unit to generate a corresponding drive signal according to the control vector, register parameters and abnormal protection signal to achieve driving and control of the load. The register parameters can change the circuit configuration, thereby improving the flexibility of control and driving.

[0022] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 A schematic diagram of the composition of a control system of a universal load driver chip provided by an embodiment of the present invention;

[0025] Figure 2 A schematic diagram of the spatial division of a microinstruction code provided by an embodiment of the present invention;

[0026] Figure 3 A schematic diagram of an implementation of a control driving method in an algorithm control engine provided by an embodiment of the present invention;

[0027] Figure 4 A schematic flow chart of a control method for a universal load driver chip provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0030] As described in the background technology, hardware solutions are mostly dedicated integrated circuit solutions, which can solidify the control algorithm into hardware. Compared with software solutions, they have obvious advantages in terms of performance, power consumption, integration, real-time and reliability. However, the design and implementation of traditional dedicated integrated circuit solutions are closely tied to actual applications, with low algorithm flexibility and high design complexity.

[0031] Based on this, the inventor has proposed a control system and method for a universal load driver chip after research, which is applied to load driver chips such as motors, power supplies and inverters. The control system of the universal load driver chip is a dedicated integrated circuit, which adopts a microinstruction code dedicated to the universal load driver chip. This is a coarse-grained instruction set implementation method similar to the instructions of a fast instruction set computer (also known as a reduced instruction set computer or RISC). The entire instruction space can be divided into three parts according to the function: basic function domain, test function domain and extended function domain. Each microinstruction is an abstraction of the working state of the load, and more complex control functions can be realized through the combination of microinstructions. The microinstruction code has the format consistency of the instruction set encoding in the fast instruction set computer, and also has the richness of the functional expression content of the complex instruction set, taking into account the performance and flexibility of the load, and has good scalability, and also avoids the workload of complex compiler or firmware development and design. In addition, the operation control of the load is also realized by the control method of a multi-layer state machine according to the complexity of the load control. Taking the motor as an example, the general load driver chip can adopt a two-layer state machine. The first-layer state machine extracts independent basic stages according to the actual working state of the motor. For example, the basic stages can be the start-up state stage, the acceleration state stage, the uniform speed state stage, the stop state stage and the transition state stage, etc. A basic data path is formed by a pipeline-like mode between each stage. The sub-stages in the second-layer state machine are the specific implementations of the actual operation details and actions of each basic stage. For example, the sub-stages can be the forward excitation sub-stage, the reverse excitation sub-stage and the freewheeling sub-stage, etc. The second-layer state machine shields the details of the underlying implementation of the first-layer state machine, and the first-layer state machine can realize different functional operations at a higher level by wrapping the second-layer state machine. Each basic stage can be executed according to the mode selection of the corresponding control bit of the state vector table. For the basic stage without actual effective operation, it can be directly skipped during operation, and only one additional system clock cycle is occupied. Combined with the configurable characteristics of the register address space table parameters, the flexibility of the control scheme is greatly improved. The above is the main point of the invention of the present invention, which is briefly described here.

[0032] An embodiment of the present invention provides a control system of a universal load driver chip, which is applied to driving and controlling loads such as motors, power supplies and inverters. Figure 1 A schematic diagram of a control system of a universal load driver chip provided by an embodiment of the present invention, referring to Figure 1The control system 100 of the universal load driver chip includes a load, a register address space table 101, a state vector table 102, an exception protection unit 103, a driver unit 104, and an algorithm control engine 105. The register address space table 101 is used to provide configurable register parameters. The state vector table 102 is used to provide a control vector for a data path. The exception protection unit 103 is connected to the load, and the exception protection unit 103 is used to monitor the operating state parameters of the load in real time, and generate an exception protection signal when the operating state parameters are abnormal. The driver unit 104 is connected to the load and is used to generate a drive signal to drive the load to achieve different working states. The algorithm control engine 105 is respectively connected to the exception protection unit 103, the register address space table 101, and the state vector table 102, and the algorithm control engine 105 is used to control the driver unit 104 to generate a corresponding drive signal according to the control vector, the register parameter, and the exception protection signal.

[0033] Specifically, the control system 100 of the universal load driver chip is applied to drive and control the load, wherein the load may include at least one of a motor, a power supply, an inverter, etc. The register address space table 101 specifies the division and specification of register parameters in the system, wherein the configurable register parameters refer to data that can be edited and written to the register. For example, in the motor drive control scenario, the configurable register parameters may include parameters such as carrier frequency, dead time, PID parameters, and monitoring frequency.

[0034] The state vector table 102 refers to a circuit component that can store and / or generate control vectors of a data path, and can provide the algorithm control engine 105 with the execution direction of its algorithm by providing the control vector to the algorithm control engine 105. The state vector in the state vector table 102 is essentially a coarse-grained microinstruction code that controls the drive control process and operating state of the load. The state vector can indicate the execution direction and execution content of the algorithm in the algorithm control engine 105. For example, the state vector can indicate whether the algorithm control engine 105 executes the second basic stage in sequence after executing the first basic stage, or skips the second basic stage and directly executes the third basic stage, or adopts other execution methods.

[0035] The abnormal protection unit 103 is a circuit unit for monitoring the load for abnormal protection according to the operating state parameters of the load. Exemplarily, the abnormal protection unit 103 may include sensors corresponding to a plurality of operating state parameters and a data processing center for the state parameters. The abnormal protection unit 103 may monitor a plurality of operating state parameters of the load in real time and make abnormal protection judgments. When the operating state parameters are not within the normal range, the abnormal protection unit 103 determines that the state judgment result of the load is abnormal, generates an abnormal protection signal corresponding to the abnormal parameter and feeds it back to the algorithm control engine 105 to instruct the algorithm control engine 105 to control the output of the drive unit 104 to the load, thereby achieving protection of the load. Exemplarily, the abnormal protection unit 103 may determine that the motor is overcurrent according to the monitored phase current data. In the case of overcurrent, the abnormal protection unit 103 generates an overcurrent abnormal protection signal and feeds it back to the algorithm control engine 105. The algorithm control engine 105 may suspend the original control process of the load after receiving the abnormal protection signal, and preferentially adjust the output control of the drive unit according to the abnormal protection signal, thereby achieving overcurrent abnormal protection of the load. When the operating state parameters are all within the normal range, the abnormal protection unit 103 determines that the state judgment result of the load is normal. For example, when the load is a motor, the operating state parameters may include motor phase current and other state parameters related to motor safety.

[0036] The drive unit 104 refers to an intermediate circuit between the load and the algorithm control engine 105, and can generate a corresponding drive signal to drive the load to achieve a corresponding action according to the control signal sent by the algorithm control engine 105. The type of the drive unit 104 corresponds to the type of the load. For example, when the load is a motor, the drive unit 104 may include a drive circuit of the motor, and the switch device in the control circuit of the algorithm control engine 105 can realize the control of the motor state.

[0037] The algorithm control engine 105 is the control hub of the control system 100 of the universal load driver chip. The algorithm control engine 105 is connected to the register address space table 101 and the state vector table 102 respectively, and can execute the drive control algorithm according to the control vector and the register parameter to generate a control signal to control the drive unit 104 to generate a corresponding drive signal, wherein the state vector indicates the process execution direction of the drive control algorithm, and the register parameter provides register parameter support for the process execution. Exemplarily, the drive control algorithm in the algorithm control engine 105 can be implemented using a finite state machine paradigm, and each stage in the state machine is set according to the actual operating state of the load. For example, the state machine can be set to multiple layers, and two layers are taken as an example here. The first layer extracts each basic stage according to the operating state of the load, and each basic stage is connected in a pipeline-like mode to form a basic data path chain list. The second layer sets sub-stages representing each action according to the specific implementation actions of the load in each operating state, wherein the sub-stage represents the specific description and implementation of the action.

[0038] The control system of the universal load driver chip provided in this embodiment includes a load, a register address space table, a state vector table, an abnormal protection unit, a drive unit and an algorithm control engine. The register address space table is used to provide configurable register parameters. The state vector table is used to provide a control vector of a data path. The abnormal protection unit is connected to the load, and the abnormal protection unit is used to monitor the operating state parameters of the load in real time, and generate an abnormal protection signal when the operating state parameters are abnormal. The drive unit is connected to the load and is used to generate a drive signal to drive the load to achieve different working states. The algorithm control engine is connected to the abnormal protection unit, the register address space table and the state vector table respectively, and the algorithm control engine is used to control the drive unit to generate a corresponding drive signal according to the control vector, the register parameter and the abnormal protection signal, so as to realize the drive and control of the load. The algorithm control engine performs drive control according to the configurable register parameter and the control vector. The system is generally applicable to the drive and control scenarios of various different loads such as motors, power supplies and inverters, and the scope of application of the universal load driver chip is broadened. The register parameter can be changed to adapt to the control requirements of the load, and the flexibility of control and drive is improved.

[0039] Optionally, Figure 2 A schematic diagram of the spatial division of a microinstruction code provided by an embodiment of the present invention, based on the above embodiment, combined with Figure 1 and Figure 2 The control system 100 of the universal load driving chip adopts a microinstruction code control method, wherein the space of the microinstruction code includes a basic function domain, a test function domain and an extended function domain.

[0040] Specifically, similar to the principles of reduced instruction sets and complex instruction sets, microinstruction codes are internal customized instructions of the algorithm control engine 105 in the control system 100 of the general load driver chip. This microinstruction code draws on the consistency of the reduced instruction set in the encoding format. On the basis of the reduced instruction set, the entire microinstruction code space is divided into three functional domains. The basic functional domain is the basic drive control instruction of the load. The test functional domain is the control instruction related to the load test requirements. The extended functional domain is the drive control instruction reserved for the extended function.

[0041] The control system of the universal load driver chip provided in this embodiment adopts microinstruction code for control in the control system of the universal load driver chip. The space of the microinstruction code includes a basic function domain, a test function domain and an extended function domain, which realizes the reservation of instruction encoding space for test functions and extended functions, facilitates the testing and function expansion of the universal load driver chip, and improves the scalability of the control system.

[0042] Optionally, Figure 3 A schematic diagram of an implementation of a control driving method in an algorithm control engine provided by an embodiment of the present invention, wherein the figure only exemplarily shows a two-layer state machine and only exemplarily shows a sub-stage in a lower-layer state machine included in a basic stage in an upper-layer state machine. Figure 3 The dotted line indicates that the lower state machine on the right is a specific embodiment of the corresponding basic stage in the upper state machine, and it cannot be understood that the lower state machine exists independently of the upper state machine. Figure 1 and Figure 3 The algorithm control engine 105 includes at least two layers of state machines. Each basic stage 301 in the upper state machine includes a lower state machine, and the lower state machine includes at least one sub-stage 302. The algorithm control engine 105 is also used to selectively execute each basic stage 301 in sequence according to the control vector.

[0043] Specifically, each basic stage in the upper state machine can be set in one-to-one correspondence with the operating state of the load to form a basic data path. Each operating state of the load will also include (or be split into) multiple stage states or multiple operating actions, so a sub-stage corresponding to the stage state or operating action can be set in the lower state machine to realize the action details of control and drive. Exemplarily, the motor start-up can be split into a forward excitation process, a reverse excitation process, and a freewheeling process, etc. Then, the lower state machine corresponding to the basic stage of the motor start-up state includes sub-stages corresponding to each process.

[0044] The algorithm control engine 105 includes two layers of state machines. The top-level state machine includes basic stages that correspond one-to-one to the operating states of the load and are arranged in a preset order, wherein the preset order is pre-evaluated and determined based on the actual operating goals of the load and the actual operating process to achieve the actual operating goals; the bottom-level state machine includes sub-stages that correspond one-to-one to each operating action of the load in the corresponding operating state. It should be noted here that when there are only two layers of state machines in the algorithm control engine, the sub-stages included in the lower-level state machine are called states.

[0045] In addition, in addition to the bottom state machine, the execution order of each stage in each layer state machine can be determined according to the control vector. The algorithm control engine 105 can skip the invalid basic stage when the control vector indicates that a basic stage is invalid. The algorithm control engine 105 can also skip the invalid sub-stage during the execution of the sub-stage included in a basic stage if the control vector indicates that a sub-stage is invalid.

[0046] The first advantage of setting up a multi-layer state machine is that it realizes the separation of abstract behavior and specific implementation. The bottom state machine shields the bottom implementation details from the top state machine. When the control vector indicates that a certain stage is invalid, the invalid stage is skipped. The top state machine can flexibly implement different high-order functional operations at a coarser granularity by wrapping the bottom state machine in a combined manner. The second advantage is that the implementation scheme of the two-layer state machine avoids the drastic modification of the circuit when adding or deleting the load operation state in the later stage due to the tight coupling between the states of the traditional state machine. By introducing the state vector table 102, each sub-stage selects the execution mode according to the validity of the control bit corresponding to the data path control vector, and the execution of each stage is carried out according to the state vector table 102. For the stage that has no actual effective operation or the early stage of development function occupancy, it can be skipped according to the control vector, and only an additional system clock cycle of time overhead is generated during the operation, which is usually negligible relative to the effective calculation time of the load.

[0047] The algorithm control engine of the control system of the universal load driver chip provided in this embodiment is provided with a multi-layer state machine. Each basic stage in the upper state machine corresponds to a lower state machine. The lower state machine includes at least one sub-stage. The algorithm control engine is also used to selectively execute each basic stage in sequence according to the control vector. The multi-layer state machine is used to realize the separation of coarse-grained state control and specific action implementation, taking into account stability and flexibility. While meeting the requirements of performance, power consumption, integration, real-time and reliability indicators, it also takes into account the actual needs of the subsequent joint debugging and function expansion of dedicated integrated circuits, and also avoids the complicated compilation-related work.

[0048] An embodiment of the present invention further provides a control method for a universal load driver chip, which is implemented by the control system of any of the aforementioned universal load driver chips. Figure 4 A flow chart of a control method for a universal load driver chip provided by an embodiment of the present invention, referring to Figure 4 , the control method of the general load driver chip includes:

[0049] S401 . The abnormality protection unit monitors the operating state parameters of the load, and generates an abnormality protection signal when the operating state parameters are abnormal.

[0050] S402: The algorithm control engine controls the driving unit to generate a corresponding driving signal according to the control vector, register parameters and abnormal protection signal, so as to drive the load to achieve different working states.

[0051] The control vector is provided by a state vector table, and the register parameter is provided by a register address space table. The algorithm control engine includes at least two layers of state machines, each basic stage in the upper state machine corresponds to a lower state machine, and the lower state machine includes multiple sub-stages. The algorithm control engine is also used to selectively execute each basic stage in sequence according to the control vector. The algorithm control engine is also used to skip the invalid basic stage when the control vector indicates that the basic stage is invalid.

[0052] The control system and method of the universal load driver chip provided by the present invention are applied to various loads such as motors, power supplies and inverters. The control system of the universal load driver chip includes a load, a register address space table, a state vector table, an abnormal protection unit, a drive unit and an algorithm control engine. The register address space table provides configurable register parameters. The state vector table provides a control vector of a data path. The abnormal protection unit is connected to the load, and the abnormal protection unit monitors the operating state parameters of the load in real time, and generates an abnormal protection signal when the operating state parameters are abnormal. The drive unit is connected to the load and is used to generate a drive signal to drive the load to achieve different working states. The algorithm control engine controls the drive unit to generate a corresponding drive signal according to the control vector, register parameters and abnormal protection signal, thereby realizing the drive and control of various loads such as motors, power supplies and inverters, broadening the scope of application of the universal load chip, and the register parameters can change the circuit configuration, thereby improving the flexibility of control and drive.

[0053] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0054] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A control system for a universal load driver chip, characterized in that: include: Load, register address space table, state vector table, exception protection unit, drive unit and algorithm control engine; The register address space table is used to provide configurable register parameters; The state vector table is used to provide a control vector for a data path, wherein the state vector is a coarse-grained microinstruction code that controls the drive control process and operating state of the load; The abnormality protection unit is connected to the load, and is used to monitor the operating state parameters of the load in real time, and generate an abnormality protection signal when the operating state parameters are abnormal; The driving unit is connected to the load and is used to generate a driving signal to drive the load to achieve different working states; The algorithm control engine is connected to the exception protection unit, the register address space table and the state vector table respectively, and is used to control the drive unit to generate the corresponding drive signal according to the control vector, the register parameter and the exception protection signal.

2. The control system of the universal load driver chip according to claim 1, characterized in that: The control system of the universal load driving chip adopts microinstruction code to perform control, wherein the space of the microinstruction code includes a basic function domain, a test function domain and an extended function domain.

3. The control system of the universal load driver chip according to claim 1, characterized in that: The algorithm control engine includes at least two layers of state machines, each basic stage in the upper layer state machine corresponds to a lower layer state machine, and the lower layer state machine includes multiple sub-stages. The algorithm control engine is also used to selectively execute each of the basic stages in sequence according to the control vector.

4. The control system of the universal load driver chip according to claim 3, characterized in that: The operating state of the load includes multiple operating actions; the algorithm control engine includes two layers of state machines, the top-level state machine includes the basic stages that correspond one-to-one to the operating states of the load and are arranged in a preset order, wherein the preset order is pre-evaluated and determined based on the actual operating goals of the load and the actual operating process to achieve the actual operating goals; the bottom-level state machine includes the sub-stages that correspond one-to-one to each operating action of the load in the corresponding operating state.

5. The control system of the universal load driver chip according to claim 3, characterized in that: The algorithm control engine is further configured to skip the invalid basic phase if the control vector indicates that the basic phase is invalid.

6. The control system of the universal load driver chip according to claim 1, characterized in that: The load includes at least one of a motor, a power supply, and an inverter.

7. A control method for a universal load driver chip, characterized in that: The control system of the universal load driver chip according to any one of claims 1 to 6 is used for implementation, and the control method of the universal load driver chip includes: The abnormal protection unit monitors the operating state parameters of the load in real time, and generates an abnormal protection signal when the operating state parameters are abnormal; The algorithm control engine controls the driving unit to generate the corresponding driving signal according to the control vector, register parameters and the abnormal protection signal, so as to drive the load to achieve different working states, wherein the control vector is provided by a state vector table, and the register parameters are divided by a register address space table.

8. The control method of the universal load driver chip according to claim 7, characterized in that: The algorithm control engine includes at least two layers of state machines, each basic stage in the upper layer state machine corresponds to a lower layer state machine, and the lower layer state machine includes multiple sub-stages. The algorithm control engine is also used to selectively execute each of the basic stages in sequence according to the control vector.

9. The control method of the universal load driver chip according to claim 8, characterized in that: The algorithm control engine is further configured to skip the invalid basic phase if the control vector indicates that the basic phase is invalid.

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