Cache method, device, electronic device and readable storage medium

Abstract

A cache method, device, electronic device and readable storage medium relate to the field of computer technology. The cache method is applied to a consistency base node, the consistency base node is connected to a master node and a slave node respectively through an interconnection network, the consistency base node includes a final cache and a state holding register, the final cache includes a local tag and a data storage device, and the cache method includes: receiving multiple requests sent by one or more master nodes; determining a target request according to the multiple requests, the target request includes a target address; querying the cache line state corresponding to the target address in the local tag and the state holding register according to the target address, and determining a hit result according to the cache line state; determining a cache transaction according to the target request and the hit result, and sending a request for the cache transaction to an execution module so that the execution module executes the cache transaction, and the execution module is located in the consistency base node, the master node and / or the slave node.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a cache method, device, electronic device and readable storage medium. Background Art

[0002] The physical limitations of single-core processor performance have prompted the integration of multiple processing cores into a single chip to become the mainstream trend of modern processor design. Multi-core processors have higher computing power and energy efficiency, and can meet the growing demand for parallel computing. However, as the number of cores increases, communication and data sharing between cores become complicated, and the on-chip interconnect network provides a more efficient data transmission and communication mechanism. Summary of the invention

[0003] The embodiments of the present application provide a method, device, electronic device and computer-readable storage medium for processing a cache request to solve the problems in the related art.

[0004] In a first aspect, an embodiment of the present application provides a caching method, which is applied to a consistency base node, wherein the consistency base node is connected to a master node and a slave node respectively through an interconnection network, wherein the consistency base node includes a final level cache and a state holding register, wherein the final level cache includes a local tag and a data storage device, and wherein the caching method includes:

[0005] Receiving multiple requests sent by one or more of the master nodes;

[0006] Determine a target request according to the multiple requests, the target request including a target address;

[0007] According to the target address, query the cache line state corresponding to the target address in the local tag and the state holding register, and determine the hit result according to the cache line state, wherein the local tag includes: the correspondence between the cache line and the address stored in the data memory, and the state information of the cache line stored in the data memory, and the state holding register includes: the correspondence between the cache line and the address stored in the master node, and the state information of the cache line stored in the master node;

[0008] According to the target request and the hit result, a cache transaction is determined, and a request for the cache transaction is sent to an execution module so that the execution module executes the cache transaction. The execution module is located in the consistency base node, the master node and / or the slave node.

[0009] Optionally, the multiple requests include a first request and a second request, and the step of determining the target request according to the multiple requests includes:

[0010] When the address carried by the first request is the same as the address carried by the second request, and the first request is received earlier than the second request, the first request is first determined as the target request, and after the cache transaction corresponding to the first request is executed, the second request is determined as a new target request.

[0011] Optionally, the step of determining a target request according to the multiple requests includes:

[0012] According to the priority information carried by the multiple requests, a request with a higher priority is determined as the target request.

[0013] Optionally, the multiple requests include a first read request, a second read request, and a write request, the first read request is received earlier than the second read request, the second read request is received earlier than the write request, the cache line requested to be read by the first read request, the cache line requested to be read by the second read request, and the cache line requested to be written by the write request are the same cache line, and after the step of determining that the second read request is the target request, the step further includes:

[0014] A retry flag is added to the second read request, where the retry flag is used to indicate that the cache transaction corresponding to the second read request is executed again when a preset condition is met, where the preset condition includes that the cache transaction corresponding to the write request is executed completely.

[0015] Optionally, the target request is a read request, and the step of determining a cache transaction according to the target request and the hit result, and sending the request of the cache transaction to an execution module includes:

[0016] If the hit result indicates that the local tag hits, it is determined that the cache transaction is to read the cache line corresponding to the target address from the data memory, and the execution module is the data memory. If the cache transaction needs to obtain a unique state cache line, the execution module also includes the remaining master nodes that have the address cache line;

[0017] If the hit result indicates that the local tag misses and the state holding register hits, determining that the cache transaction is to read the cache line corresponding to the target address from the target master node, the execution module is the target master node, and the state of the cache line corresponding to the target address in the target master node is valid data or dirty data;

[0018] If the hit result indicates that both the local tag and the state holding register are misses, it is determined that the cache transaction is to read the cache line corresponding to the target address from the slave node, and the execution module is the slave node.

[0019] Optionally, the state holding register includes a monitoring filter and a monitoring filter eviction queue, and after the step of determining the hit result according to the buffer line state, further includes:

[0020] If the hit result indicates that the snoop filter misses and the snoop filter is full, the cache line information in the snoop filter is replaced, and the replaced cache line information is written into the snoop filter eviction queue.

[0021] Optionally, after the step of determining the hit result according to the buffer row state, the method further includes:

[0022] If the hit result indicates that the monitoring filter evicts the queue, a monitoring request is multicasted to a plurality of the master nodes.

[0023] In a second aspect, an embodiment of the present application provides a cache device, which is applied to a consistency base node, wherein the consistency base node is connected to a master node and a slave node respectively through an interconnection network, wherein the consistency base node includes a final level cache and a state holding register, wherein the final level cache includes a local tag and a data storage device, and wherein the cache device includes:

[0024] a link interface configured to receive a plurality of requests sent by one or more of the master nodes;

[0025] a miss status holding register configured to determine a target request based on the plurality of requests, the target request including a target address;

[0026] A cache pipeline, configured to query the cache line state corresponding to the target address in the local tag and the state holding register according to the target address, and determine a hit result according to the cache line state, wherein the local tag includes: a correspondence between a cache line and an address stored in the data memory, and state information of the cache line stored in the data memory, and the state holding register includes: a correspondence between a cache line and an address stored in a master node, and state information of the cache line stored in the master node;

[0027] The cache pipeline is also configured to determine a cache transaction based on the target request and the hit result, and send a request for the cache transaction to an execution module so that the execution module executes the cache transaction. The execution module is located in the consistency base node, the master node and / or the slave node.

[0028] Optionally, the miss status holding register is a register stack including multiple storage items, the storage items correspond one-to-one to the requests, and the storage items include: control bits of the multiple requests, the master node ID sending the request, priority information of the request, and address information carried by the request.

[0029] Optionally, the consistency base node further includes:

[0030] A data buffer is connected between the link interface and the data storage device. The data buffer is a register stack including a plurality of buffer items. The buffer items correspond one-to-one to the storage items. The buffer items include: buffer data and byte enable. The byte enable is used to indicate whether each byte in the buffer data is valid.

[0031] Optionally, the cache device further includes:

[0032] An atomic operation unit for performing atomic operations, wherein the atomic operation unit is located in the consistency base node, is arranged close to the data buffer in the consistency base node, and is directly connected to the data buffer; or the atomic operation unit is located in the slave node or the master node.

[0033] In a third aspect, an embodiment of the present application further provides an electronic device, including a processor;

[0034] a memory for storing instructions executable by the processor;

[0035] The processor is configured to execute the instructions to implement the method of the first aspect.

[0036] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, which, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute the method of the first aspect.

[0037] In an embodiment of the present application, the consistency base node receives the request sent by the master node and pipelines the process of processing the request, supporting cache consistency on the hardware, thereby providing higher efficiency and performance, reducing the difficulty of software development, and facilitating the realization of a high-performance consistency on-chip network.

[0038] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0040] Figure 1 A scenario architecture diagram of a cache device provided in an embodiment of the present application is shown;

[0041] Figure 2 An architecture diagram of a consistency base node provided in an embodiment of the present application is shown;

[0042] Figure 3 A flowchart of a caching method provided by an embodiment of the present application is shown;

[0043] Figure 4 A flowchart showing a specific example of the caching method provided in an embodiment of the present application is shown;

[0044] Figure 5 A block diagram of a cache device provided by an embodiment of the present application is shown;

[0045] Figure 6 A block diagram of an electronic device provided in an embodiment of the present application is shown;

[0046] Figure 7 A block diagram of an electronic device provided by another embodiment of the present application is shown. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0048] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally a class, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three kinds of relationships can exist, for example, A and / or B can be represented: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the front and back associated objects are a kind of "or" relationship. In the embodiment of the present application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0049] How to efficiently ensure cache consistency and memory consistency in multi-core processor systems is also a key and difficult point in modern processor design. The on-chip interconnect network architecture of some multi-core processors does not implement cache consistency in hardware, which requires cache consistency to be implemented through software. However, implementing cache consistency through software will greatly increase the difficulty of software development and affect software performance and stability.

[0050] Reference Figure 1 FIG. 1 shows an architecture diagram of a cache device provided in an embodiment of the present application. Figure 1 As shown, the cache device includes a consistency base node HN-F (such as Figure 1 HN-F0 and HN-F1 shown), master node RN-F (such as Figure 1 As shown in FIG. 15 , the consistency base node HN-F, the master node RN-F and the slave node SN-F are connected to each other to form an interconnection network. The consistency base node HN-F is connected to the master node RN-F and the slave node SN-F through the interconnection network, and the master node RN-F is also connected to the slave node SN-F.

[0051] For example, Figure 1 As shown, the master node RN-F is provided with a processor core (such as Figure 1 RV-Core) and the first-level cache (such as Figure 1 L11 and L1D shown in the figure), a secondary cache can also be set in the master node RN-F. The master node RN-F can be, for example, a fully consistent requesting node, responsible for generating protocol transactions, which include read and write operations on the interconnected network. The cache in the master node RN-F allows the generation of all transactions defined by the CHI protocol and supports all listening requests.

[0052] Exemplarily, the slave node SN-F is provided with a main memory or a memory (such as Figure 1 DDR shown).

[0053] Exemplarily, a final level cache is provided in the consistency base node HN-F, and the final level cache is, for example, a third level cache. The consistency base node HN-F is used to receive requests from the master node RN-F and process cache consistency issues. The consistency base node HN-F can, for example, record the cache line status of the consistency base node HN-F itself and the cache line status of the master node RN-F, and ensure cache consistency by sending a listener to the master node RN-F.

[0054] Among them, the last level cache is the last level cache in the cache hierarchy structure located between the processor and the main memory. It is used to store frequently accessed but large data blocks to provide faster access speed and reduce the frequency of main memory access.

[0055] Cache consistency refers to the state in which when multiple processors or cores have cached copies of the same piece of data in a multi-processor system, these copies remain consistent. When a processor modifies the data in the cache, the corresponding cache copies of other processors need to be updated or invalidated to ensure that all processors see the latest data.

[0056] Reference Figure 2 FIG. 2 shows an architecture diagram of a consistency base node HN-F provided in an embodiment of the present application. Figure 2 As shown, the consistency base node HN-F includes a link interface, a miss status holding register (MSHR), a cache pipeline and a data memory, and the cache pipeline includes a local tag and a status holding register. Among them, the local tag and the data memory constitute the last level cache, and the status holding register includes a snoop filter and a snoop filter eviction queue BIQ / SEQ.

[0057] The snoop filter is used to store the status information of the cache line in each master node RN-F, and it decides whether to send a snoop request to the corresponding master node RN-F according to the status information. The snoop filter can effectively reduce the number of snoop messages sent and alleviate network congestion.

[0058] The miss status holding register MSHR is a register used to track and process cache miss events.

[0059] Figure 2The link interface shown is an interface that includes the consistency base node HN-F and the external interaction, which can realize the sending and receiving of Flit (CHI protocol message) based on the CHI protocol channel specification. The link interface includes the following channels: RXREQ, RXRSP, RXDAT, TXREQ, TXRSP, TXSNP, TXDAT. The main functions of the link interface are the network layer packet grouping and link layer flow control functions specified by the protocol. The link interface can also arbitrate multiple message sending requests according to the priority carried in the message sending request, and select the message sending request with a higher priority for sending. The link interface can also unpack the data packets received by the RX class channel.

[0060] The link interface is independently set as a module for packaging or unpacking each request and response data packet, so that different interfaces can be designed according to different interconnection protocols, thereby improving compatibility.

[0061] For example, a data packet may be composed of one or more Flits, and all Flits of the same data packet pass through the interconnection network along the same path. Among them, a flow control unit (Flit) is the smallest flow control unit.

[0062] Exemplarily, the cache pipeline is responsible for updating the data status in the last-level cache and the state holding register. The cache pipeline is a multi-stage non-blocking pipeline that accepts a request from the miss state holding register MSHR in each cycle and returns a request result to the miss state holding register MSHR. The cache pipeline only accepts a small amount of message fields and control bits it needs from the miss state holding register MSHR, and returns the cache status and the number and target of the monitored messages to be sent to the miss state holding register MSHR. The cache pipeline connects the ports of all other memories (such as the monitor filter eviction queue BIQ / SEQ, the monitor filter, and the LRU memory, etc.) except the data memory, and is responsible for the reading and writing of these memories and the calculation of the new state.

[0063] Reference Figure 3 The flowchart of a cache method provided by an embodiment of the present application is shown. The cache method is applied to the consistency base node HN-F, and the consistency base node HN-F is the execution subject of the cache method. Figure 3 As shown, the caching method includes:

[0064] Step 301: Receive multiple requests sent by one or more master nodes RN-F.

[0065] Exemplarily, the link interface is used to perform step 301 .

[0066] Among them, one or more master nodes RN-F act as request nodes for sending requests, and the requests may include, for example, read requests, write requests, atomic requests, and update requests.

[0067] Step 302: Determine a target request according to multiple requests, where the target request includes a target address.

[0068] Exemplarily, the miss status holding register MSHR is used to execute step 302. The miss status holding register MSHR can modify the control bit inside the miss status holding register MSHR according to multiple requests, and then determine the target request according to the control bit.

[0069] The miss status holding register MSHR serves as the control center of the consistency base node HN-F. It receives information such as messages from the link interface, requests from the monitoring filter eviction queue BIQ / SEQ, and results returned by the cache pipeline, and modifies its internal control bits according to the received information. The miss status holding register MSHR determines the target request only according to the state of its internal control bits. The target request includes, for example, at least one of the following: a request to read the last-level cache, a request to read the status holding register, a request to update the last-level cache, a request to update the status holding register, and a request to send a message outward.

[0070] Step 303: According to the target address, query the cache line status corresponding to the target address in the local tag and the status holding register, and determine the hit result according to the buffer line status, wherein the local tag includes: the correspondence between the buffer line and the address stored in the data memory, and the status information of the buffer line stored in the data memory, and the status holding register includes: the correspondence between the buffer line and the address stored in the main node RN-F, and the status information of the buffer line stored in the main node RN-F.

[0071] The status information includes, for example, whether the data is valid, whether the data is invalid, whether the data cache line is unique or shared, and whether the data is dirty. Dirty data means that the data has been modified and is inconsistent with the memory data.

[0072] Exemplarily, when the cache line state corresponding to the target address in the local tag is data valid or data dirty, the local tag is determined to be a hit; when the cache line state corresponding to the target address in the state holding register is data valid or data dirty, the state holding register is determined to be a hit.

[0073] Step 304: Determine the cache transaction based on the target request and the hit result, and send the cache transaction request to the execution module so that the execution module executes the cache transaction. The execution module is located in the consistency base node HN-F, the master node RN-F and / or the slave node SN-F.

[0074] Exemplarily, a cache pipeline is used to perform steps 303 and 304 .

[0075] In the cache method provided by the present application, the consistency base node receives the request sent by the master node and pipelines the process of processing the request, thereby increasing the operating frequency and frequency and improving performance. In addition, the present application supports the implementation of cache consistency on hardware, thereby providing higher efficiency and performance, reducing the difficulty of software development, and facilitating the implementation of high-performance consistency on-chip networks.

[0076] Among them, the on-chip network is a network topology structure used to connect various functional modules or processing units inside the chip to achieve data transmission and communication, also known as the on-chip interconnection network.

[0077] Exemplarily, the consistency base node HN-F can be implemented based on the AMBA CHI protocol. The consistency base node HN-F can implement the PoC and PoS functions specified by the CHI protocol, support various CHI protocol transactions, and receive request messages through the RXREQ channel. Each received request message corresponds to a transaction. A single transaction may include multiple responses, listeners, and data messages. The consistency base node HN-F cooperates with the master node RN-F and the slave node SN-F to complete the entire transaction process. The consistency base node HN-F chooses to complete a certain behavior at a certain time based on its internal state and the received message.

[0078] The Point of Coherence (PoC) is the point where all agents that can access memory are guaranteed to see the same copy of the memory location. In a typical architecture based on a CHI system, it is located at the HN-F in the interconnect. The Point of Serialization (PoS) is a location in the interconnect network that determines the order of requests between different agents.

[0079] Exemplarily, the miss status holding register MSHR is a register stack including multiple storage items, and the storage items correspond one-to-one with the requests and the replacement transactions brought by the requests. The storage items include: control bits of multiple requests, the master node ID that sends the request, the priority information of the request, and the address information carried by the request. This structure enables the miss status holding register MSHR to process multiple transactions at the same time. That is, the miss status holding register MSHR can save and track the status information of each request.

[0080] Since multiple request transactions can exist simultaneously, in order to implement PoC and PoS functions, illustratively, the multiple requests include a first request and a second request, and step 302 may specifically include: when the address carried by the first request is the same as the address carried by the second request, and the receiving time point of the first request is earlier than the receiving time point of the second request, first determine the first request as the target request, and after the cache transaction corresponding to the first request is executed, determine the second request as the new target request.

[0081] That is, for multiple request transactions carrying the same address, the miss status holding register MSHR adopts the following conflict handling mechanism: that is, the subsequent transaction with the same address is dormant until the previous transaction has been completed. In this way, the miss status holding register MSHR can improve the overall performance by adopting a non-blocking cache operation mode.

[0082] Since the link interface can only complete one transaction corresponding operation per cycle to the external channel and cache pipeline, the miss status holding register MSHR needs to have an arbitration function. In order to implement the arbitration function, step 302 may specifically include: determining a request with a higher priority as a target request according to the priority information carried by the multiple requests.

[0083] Since there is a certain interval between reading and writing to the data storage, there may be another read request after a cache line is read and before it is written, and the latter read request may want to modify the same cache line as the previous read request. In order to avoid the latter read request reading outdated information, illustratively, the multiple requests include a first read request, a second read request, and a write request, the first read request is received earlier than the second read request, the second read request is received earlier than the write request, and the cache line requested to be read by the first read request, the cache line requested to be read by the second read request, and the cache line requested to be written by the write request are the same cache line. That is, the second read request is located after the first read request and before the write request.

[0084] Exemplarily, after the step of determining that the second read request is the target request, it also includes: adding a retry mark for the second read request, the retry mark is used to indicate that the cache transaction corresponding to the second read request is executed when a preset condition is met, and the preset condition includes that the cache transaction corresponding to the write request is executed.

[0085] In this way, the cache pipeline ensures that the updates of cache line status and snoop filters are atomic through the Hazard mechanism.

[0086] Exemplarily, the target request is a read request, such as Figure 4 As shown, step 304 may specifically include:

[0087] Step 401: If the hit result indicates a local tag hit, the cache transaction is determined to be reading a cache line corresponding to a target address from a data memory, and the execution module is the data memory. If the cache transaction needs to obtain a unique state cache line, the execution module also includes other master nodes that own the address cache line.

[0088] In step 401, if the local tag hits, it can be considered that the cache line corresponding to the target address exists in the data memory in the consistency base node HN-F, so a read task can be sent to the data memory.

[0089] Step 402: If the hit result indicates that the local tag misses and the status holding register hits, it is determined that the cache transaction is to read the cache line corresponding to the target address from the target master node RN-F, the execution module is the target master node RN-F (such as the cache in the target master node RN-F), and the status of the cache line corresponding to the target address in the target master node RN-F is valid data or dirty data.

[0090] In this way, non-target master nodes can be filtered out through the state holding register, and the state of the cache line corresponding to the target address in the non-target master node RN-F is invalid data. There is no need to send the cache transaction to all master nodes, which can effectively reduce the number of monitoring messages sent, reduce network load, improve efficiency and overall system performance, and save power consumption.

[0091] In step 402, if the local tag misses and the status holding register hits, it can be considered that the cache line corresponding to the target address does not exist in the consistency base node HN-F, but exists in the target master node RN-F, so a read task can be sent to the cache in the target master node RN-F.

[0092] Step 403: If the hit result indicates that both the local tag and the status holding register are not hit, it is determined that the cache transaction is to read the cache line corresponding to the target address from the slave node SN-F, and the execution module is the slave node SN-F (such as the memory in the slave node SN-F).

[0093] In step 403, if both the local tag and the status holding register do not hit, it can be considered that the cache line corresponding to the target address does not exist in the consistency base node HN-F and the master node RN-F, so a read task can be sent to the memory in the slave node SN-F.

[0094] Exemplarily, after step 303, the following may be included: if the hit result indicates that the snoop filter does not hit and the snoop filter is full, the cache line information in the snoop filter is replaced, and the replaced cache line information is written into the snoop filter eviction queue BIQ / SEQ.

[0095] Exemplarily, the consistency base node HN-F may also include an LRU memory, which records the access history information of different cache ways and is used to determine the replaced way or cache line information. Accordingly, the cache pipeline may determine which cache line information in the snoop filter to replace based on the access history information of different cache ways stored in the LRU memory.

[0096] Exemplarily, after step 303, the following may be included: if the hit result indicates that the monitoring filter evicts the queue BIQ / SEQ, a monitoring request is multicast to multiple master nodes RN-F.

[0097] Since the monitoring filter eviction queue BIQ / SEQ is used to store the replaced items in the monitoring filter (i.e. the replaced items or cache line information), and the cache lines corresponding to the replaced items need to be invalidated, and the sending and transmission of the monitoring request to invalidate these cache lines takes time, the monitoring filter eviction queue BIQ / SEQ is used to temporarily store these replaced items during this period of time. If there happens to be another read / write request to access the cache line corresponding to the address of the replaced item during this period of time, a result indicating that the monitoring filter eviction queue BIQ / SEQ hits will be generated. At this time, the consistency base node HN-F can multicast the monitoring request to multiple master nodes RN-F, so as to avoid missing any master node RN-F that still caches the cache line of the address.

[0098] Exemplarily, one or more of the local tag, data memory, snoop filter, snoop filter eviction queue BIQ / SEQ, and LRU memory all use static random access memory, and the internal storage unit of the static random access memory is constructed using a trigger, so there is no need to refresh the data periodically, the speed is fast, but the cost is also high, and it is suitable for applications such as cache and registers. In this way, the static random access memory is used to store data, tags, status information, historical information, etc., which can take into account both read and write speed and resource consumption.

[0099] Among them, the static random access memory is a single-port memory, and its read and write operations are completed in one clock cycle. That is, if a read request enters the static random access memory at time T0, the read data is available at time T1; if a write request and write data enter the static random access memory at time T0, the write data can be read at time T1.

[0100] For example, Figure 2 As shown, the cache pipeline also includes: an Sx1 module, which is, for example, an arbitrator. The arbitrator receives transactions such as requests from the miss status holding register MSHR and results returned by the cache pipeline, and arbitrates these transactions, for example, giving priority to executing the results returned by the cache pipeline.

[0101] For example, Figure 2 As shown, the cache pipeline also includes: an Sx2 module, which is used to read the address and status information of the cache line from the local tag and status holding register.

[0102] For example, Figure 2 As shown, the cache pipeline also includes: an Sx3 module, which is used to compare the target address and the address of the cache line in the local tag and the state holding register, and determine the required hit result according to the comparison result. The Sx3 module is also used to replace the state information in the local tag when the local tag is full and there is a miss, and replace the state information in the state holding register when the state holding register is full and there is a miss.

[0103] For example, Figure 2 As shown, the cache pipeline also includes: an Sx4 module, which determines a cache transaction based on a hit result. The cache transaction includes, for example, reading a cache line corresponding to a target address from a data memory, reading a cache line corresponding to a target address from a target master node RN-F, reading a cache line corresponding to a target address from a slave node SN-F, writing a cache line to a data memory, updating a local tag, updating a monitoring filter, etc.

[0104] For example, Figure 2 As shown, the cache pipeline also includes: an Sx5 module for sending cache transactions to an execution module, wherein the execution module is, for example, a data storage device of a consistency base node, a cache in a target master node, or a memory in a slave node.

[0105] Reference Figure 5 A block diagram of a cache device provided in an embodiment of the present application is shown, the cache device is applied to a consistency base node HN-F, and the cache device includes:

[0106] The link interface 501 is configured to receive multiple requests sent by one or more master nodes RN-F.

[0107] The miss status holding register MSHR is configured to determine a target request according to the plurality of requests, wherein the target request includes a target address.

[0108] The cache pipeline 503 is configured to query the cache line status corresponding to the target address in the local tag and the status holding register according to the target address, and determine the hit result according to the buffer line status, wherein the local tag includes: the correspondence between the buffer line and the address stored in the data memory, and the status information of the buffer line stored in the data memory, and the status holding register includes: the correspondence between the buffer line and the address stored in the main node RN-F, and the status information of the buffer line stored in the main node RN-F.

[0109] The cache pipeline is also configured to determine the cache transaction based on the target request and the hit result, and send the cache transaction request to the execution module so that the execution module executes the cache transaction. The execution module is located in the consistency base node HN-F, the master node RN-F and / or the slave node SN-F.

[0110] Exemplarily, the miss status holding register MSHR is a register stack including multiple storage items, and the storage items correspond one-to-one with the requests and the replacement transactions brought by the requests. The storage items include: control bits of multiple requests, the master node ID that sends the request, the priority information of the request, and the address information carried by the request. This structure enables the miss status holding register MSHR to process multiple transactions at the same time. That is, the miss status holding register MSHR can save and track the status information of each request.

[0111] Exemplarily, the consistency base node HN-F also includes: a data buffer, connected between the link interface and the data storage device, the data buffer is a register stack including multiple buffer items, the buffer items correspond one-to-one to the storage items, and the buffer items include: buffer data and byte enable (the same meaning as BE in the protocol), the byte enable is used to indicate whether each byte in the buffer data is valid.

[0112] The data buffer is used to buffer data. When data is read from the data memory or arrives from the RXDAT channel of the link interface, it will be written into the data buffer first; when data needs to be written into the data memory or sent by the TXDAT channel of the link interface, it will be read from the data buffer.

[0113] By using the register file as the storage structure of the data buffer, the read and write latency can be further reduced, and dirty data blocks evicted from the cache can be temporarily stored.

[0114] Exemplarily, the cache device further includes: an atomic operation unit, configured to perform atomic operations.

[0115] In some examples, such as Figure 2 As shown, the atomic operation unit is located in the consistency base node HN-F, is set close to the data buffer in the consistency base node HN-F, and is directly connected to the data buffer. This facilitates data transmission, speeds up the reading and writing of operands, and can improve overall performance.

[0116] By setting the atomic operation unit to support atomic operations, the consistency base node and the on-chip network can achieve memory consistency more efficiently. Implementing atomic operations in the on-chip network can make it have higher performance and compatibility.

[0117] Atomic operation means that during the execution of an operation involving multiple data values, the loading of the original value, the execution of the operation, and the storage of the updated value are completed atomically. That is, during the entire operation, no other device can access the memory location.

[0118] The last level cache in the consistency base node HN-F can be used to read and write the required data during the atomic operation.

[0119] Memory consistency means that in a multi-processor system, different processors or cores should follow certain rules when accessing shared memory to ensure that the memory state seen by all processors is consistent. The memory consistency model defines the visibility and order of memory operations when a program is executed on different processors.

[0120] In some other examples, the atomic operation unit may also be located in the slave node SN-F. For example, the atomic operation unit may also be placed at the slave node SN-F (SN) based on the AMBA CHI protocol.

[0121] In some other examples, the atomic operation unit may also be located in the master node RN-F. For example, in other protocols, the atomic operation unit may also be placed in the master node RN-F including the processor core.

[0122] Exemplarily, the multiple requests include a first request and a second request, and the miss status holding register MSHR is further configured to: when the address carried by the first request is the same as the address carried by the second request, and the receiving time point of the first request is earlier than the receiving time point of the second request, first determine the first request as the target request, and after the cache transaction corresponding to the first request is executed, determine the second request as the new target request.

[0123] Exemplarily, the miss status holding register MSHR is also configured as follows: the miss status holding register MSHR modifies the control bit inside the miss status holding register MSHR according to multiple requests; and determines the target request according to the control bit, and the target request includes at least one of the following: a request to read the last-level cache, a request to read the status holding register, a request to update the last-level cache, a request to update the status holding register, and a request to send a message to the outside.

[0124] Exemplarily, the miss status holding register MSHR is further configured to: determine a request with a higher priority as a target request according to priority information carried by the multiple requests.

[0125] Exemplarily, the multiple requests include a first read request, a second read request, and a write request, the first read request is received earlier than the second read request, the second read request is received earlier than the write request, and the cache line requested to be read by the first read request, the cache line requested to be read by the second read request, and the cache line requested to be written by the write request are the same cache line. Accordingly, the miss status holding register MSHR is further configured as:

[0126] After determining that the second read request is the target request, a retry flag is added to the second read request, the retry flag is used to indicate that the cache transaction corresponding to the second read request is executed again when a preset condition is met, the preset condition including that the cache transaction corresponding to the write request is executed.

[0127] Exemplarily, the target request is a read request, and the cache pipeline 503 is specifically configured as follows:

[0128] If the hit result indicates a local tag hit, it is determined that the cache transaction is to read the cache line corresponding to the target address from the data memory, and the execution module is the data memory. If the cache transaction needs to obtain a unique state cache line, the execution module also includes the remaining master nodes that own the address cache line;

[0129] If the hit result indicates that the local tag misses and the state holding register hits, it is determined that the cache transaction is to read the cache line corresponding to the target address from the target master node, the execution module is the target master node, and the state of the cache line corresponding to the target address in the target master node is valid data or dirty data;

[0130] If the hit result indicates that both the local tag and the state holding register are not hit, then the cache transaction is determined to be reading a cache line corresponding to the target address from the slave node, and the execution module is the slave node.

[0131] Exemplarily, the state holding register includes a snoop filter and a snoop filter eviction queue BIQ / SEQ, and after the buffer pipeline performs the step of determining the hit result according to the buffer line state, it is further configured as follows:

[0132] If the hit result indicates that the snoop filter misses and the snoop filter is full, the cache line information in the snoop filter is replaced, and the replaced cache line information is written into the snoop filter eviction queue BIQ / SEQ.

[0133] Exemplarily, after executing the step of determining a hit result according to the buffer row status, the buffer pipeline is further configured to: if the hit result indicates that the monitoring filter evicts the queue BIQ / SEQ hit, then multicast a monitoring request to multiple master nodes RN-F.

[0134] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0135] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0136] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0137] An embodiment of the present application provides a cache request processing device, including a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors to include methods for performing one or more of the above-mentioned embodiments.

[0138] Figure 6 800 is a block diagram of an electronic device 800 shown in the present application. For example, the electronic device 800 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0139] Reference Figure 6 , the electronic device 800 may include one or more of the following components: a processing component 802 , a memory 804 , a power component 806 , a multimedia component 808 , an audio component 810 , an input / output (I / O) interface 812 , a sensor component 814 , and a communication component 816 .

[0140] The processing component 802 generally controls the overall operation of the electronic device 800, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to complete all or part of the steps of the above method. In addition, the processing component 802 may include one or more modules to facilitate the interaction between the processing component 802 and other components. For example, the processing component 802 may include a multimedia module to facilitate the interaction between the multimedia component 808 and the processing component 802.

[0141] The memory 804 is configured to store various types of data to support operations on the device 800. Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phone book data, messages, images, videos, etc. The memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0142] The power supply component 806 provides power to the various components of the electronic device 800. The power supply component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 800.

[0143] The multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front camera and / or a rear camera. When the device 800 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and the rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0144] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC), and when the electronic device 800 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 804 or sent via the communication component 816. In some embodiments, the audio component 810 also includes a speaker for outputting audio signals.

[0145] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: home button, volume button, start button, and lock button.

[0146] The sensor assembly 814 includes one or more sensors for providing various aspects of status assessment for the electronic device 800. For example, the sensor assembly 814 can detect the open / closed state of the device 800, the relative positioning of components, such as the display and keypad of the electronic device 800, and the sensor assembly 814 can also detect the position change of the electronic device 800 or a component of the electronic device 800, the presence or absence of contact between the user and the electronic device 800, the orientation or acceleration / deceleration of the electronic device 800, and the temperature change of the electronic device 800. The sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 814 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0147] The communication component 816 is configured to facilitate wired or wireless communication between the electronic device 800 and other devices. The electronic device 800 can access a wireless network based on a communication standard, such as WiFi, a carrier network (such as 2G, 3G, 4G or 5G), or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0148] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above methods.

[0149] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 804 including instructions, and the instructions can be executed by a processor 820 of an electronic device 800 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0150] Figure 71 is a block diagram of an electronic device 1900 shown in the present application. For example, the electronic device 1900 may be provided as a server.

[0151] Reference Figure 7 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0152] The electronic device 1900 may also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output (I / O) interface 1958. The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™ or the like.

[0153] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0154] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A caching method, characterized in that: Applied to a consistency base node, the consistency base node is connected to a master node and a slave node respectively through an interconnection network, the consistency base node includes a final level cache and a state holding register, the final level cache includes a local tag and a data memory, and the cache method includes: Receiving multiple requests sent by one or more of the master nodes; Determine a target request according to the multiple requests, the target request including a target address; According to the target address, query the cache line state corresponding to the target address in the local tag and the state holding register, and determine the hit result according to the cache line state, wherein the local tag includes: the correspondence between the cache line and the address stored in the data memory, and the state information of the cache line stored in the data memory, and the state holding register includes: the correspondence between the cache line and the address stored in the master node, and the state information of the cache line stored in the master node; Determine a cache transaction according to the target request and the hit result, and send the request of the cache transaction to an execution module so that the execution module executes the cache transaction, the execution module is located in the consistency base node, the master node and / or the slave node, the consistency base node is an HN-F node that complies with the CHI protocol, the master node is an RN-F node that complies with the CHI protocol, and the slave node is an SN-F node that complies with the CHI protocol; The state holding register includes a snoop filter and a snoop filter eviction queue, and after the step of determining a hit result according to the cache line state, further includes: If the hit result indicates that the snoop filter misses and the snoop filter is full, the cache line information in the snoop filter is replaced, and the replaced cache line information is written into the snoop filter eviction queue.

2. The caching method according to claim 1, characterized in that: The multiple requests include a first request and a second request, and the step of determining a target request according to the multiple requests includes: When the address carried by the first request is the same as the address carried by the second request, and the first request is received earlier than the second request, the first request is first determined as the target request, and after the cache transaction corresponding to the first request is executed, the second request is determined as a new target request.

3. The caching method according to claim 1, characterized in that: The step of determining the target request according to the multiple requests comprises: According to the priority information carried by the multiple requests, a request with a higher priority is determined as the target request.

4. The caching method according to claim 1, characterized in that: The multiple requests include a first read request, a second read request, and a write request, the first read request is received earlier than the second read request, the second read request is received earlier than the write request, the cache line requested to be read by the first read request, the cache line requested to be read by the second read request, and the cache line requested to be written by the write request are the same cache line, and after the step of determining that the second read request is the target request, the step further includes: A retry flag is added to the second read request, where the retry flag is used to indicate that the cache transaction corresponding to the second read request is executed again when a preset condition is met, where the preset condition includes that the cache transaction corresponding to the write request is executed completely.

5. The caching method according to any one of claims 1 to 4, characterized in that: The target request is a read request, and the step of determining a cache transaction according to the target request and the hit result, and sending the request of the cache transaction to an execution module includes: If the hit result indicates that the local tag hits, it is determined that the cache transaction is to read the cache line corresponding to the target address from the data memory, and the execution module is the data memory. If the cache transaction needs to obtain a unique state cache line, the execution module also includes the remaining master nodes that have the address cache line; If the hit result indicates that the local tag misses and the state holding register hits, determining that the cache transaction is to read the cache line corresponding to the target address from the target master node, the execution module is the target master node, and the state of the cache line corresponding to the target address in the target master node is valid data or dirty data; If the hit result indicates that both the local tag and the state holding register are misses, it is determined that the cache transaction is to read the cache line corresponding to the target address from the slave node, and the execution module is the slave node.

6. The caching method according to claim 5, characterized in that: After the step of determining the hit result according to the cache line state, the method further includes: If the hit result indicates that the monitoring filter evicts the queue, a monitoring request is multicasted to a plurality of the master nodes.

7. A cache device, characterized in that: Applied to a consistency base node, the consistency base node is connected to a master node and a slave node respectively through an interconnection network, the consistency base node includes a final level cache and a state holding register, the final level cache includes a local tag and a data storage device, and the cache device includes: a link interface configured to receive a plurality of requests sent by one or more of the master nodes; a miss status holding register configured to determine a target request based on the plurality of requests, the target request including a target address; A cache pipeline, configured to query the cache line state corresponding to the target address in the local tag and the state holding register according to the target address, and determine a hit result according to the cache line state, wherein the local tag includes: a correspondence between a cache line and an address stored in the data memory, and state information of the cache line stored in the data memory, and the state holding register includes: a correspondence between a cache line and an address stored in a master node, and state information of the cache line stored in the master node; The cache pipeline is further configured to determine a cache transaction according to the target request and the hit result, and send a request for the cache transaction to an execution module so that the execution module executes the cache transaction, the execution module is located in the consistency base node, the master node and / or the slave node, the consistency base node is an HN-F node that complies with the CHI protocol, the master node is an RN-F node that complies with the CHI protocol, and the slave node is an SN-F node that complies with the CHI protocol; The state holding register includes a snoop filter and a snoop filter eviction queue BIQ / SEQ. After the buffer pipeline performs the step of determining the hit result according to the buffer line state, it is also configured as follows: If the hit result indicates that the snoop filter does not hit, and the snoop filter is full, the cache line information in the snoop filter is replaced, and the replaced cache line information is written into the snoop filter eviction queue.

8. The cache device according to claim 7, characterized in that: The miss status holding register is a register stack including multiple storage items, each of which corresponds to the request one by one, and includes: control bits of the multiple requests, the master node ID that sends the request, priority information of the request, and address information carried by the request.

9. The cache device according to claim 8, characterized in that: The consistency base node also includes: A data buffer is connected between the link interface and the data storage device. The data buffer is a register stack including a plurality of buffer items. The buffer items correspond one-to-one to the storage items. The buffer items include: buffer data and byte enable. The byte enable is used to indicate whether each byte in the buffer data is valid.

10. The cache device according to claim 9, characterized in that: The cache device also includes: An atomic operation unit for performing atomic operations, wherein the atomic operation unit is located in the consistency base node, is arranged close to the data buffer in the consistency base node, and is directly connected to the data buffer; or the atomic operation unit is located in the slave node or the master node.

11. An electronic device, characterized in that: include: processor; a memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the cache method according to any one of claims 1 to 6.

12. A computer-readable storage medium, characterized in that: When the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the cache method as claimed in any one of claims 1 to 6.

Images