Deep source super junction MOSFET device and preparation method and chip thereof

Abstract

The present application belongs to the technical field of power devices, and provides a deep source super junction MOSFET device and a preparation method and chip thereof. By setting a convex N-type drift layer, a first gate polysilicon layer and a second gate polysilicon layer are formed on both sides of the N-type drift layer, the gate area is reduced, the gate charge is reduced, and the source layer with an inverted mountain-shaped structure is used to control the opening of the third P-type base region between the first gate polysilicon layer and the second gate polysilicon layer, thereby increasing the current conduction channel. The thickness of the insulating dielectric layer can also be controlled so that its conduction voltage is lower than the conduction voltage drop of the body diode, thereby reducing the hole injection of the P-type source. Moreover, the presence of the N-type source increases the electron concentration, improves the forward conduction current, and does not affect the forward conduction characteristics of the device. At the same time, the lifetime of minority holes is reduced, thereby further improving the reverse recovery of the device.

Description

Technical Field

[0001] The present application belongs to the technical field of power devices, and in particular, relates to a deep-source superjunction MOSFET device and a preparation method and chip thereof. Background Art

[0002] In recent years, Super Junction Metal-Oxide-Semiconductor Field-Effect Transistor (SJMOSFET) has gradually replaced the traditional Vertical Double-diffused Metal-Oxide-Semiconductor (VDMOS) in many application fields due to its excellent performance such as high voltage resistance and low internal resistance. However, during the reverse conduction process, the P-type source will inject a large number of minority holes into the drift region, affecting the reverse recovery process of the super junction MOSFET device. Summary of the invention

[0003] In order to solve the above technical problems, the embodiments of the present application provide a deep source super junction MOSFET device and a preparation method and chip thereof, which can improve the reverse recovery process of the super junction MOSFET device.

[0004] A first aspect of an embodiment of the present application provides a deep source super junction MOSFET device, the deep source super junction MOSFET device comprising:

[0005] N-type substrate;

[0006] A first P column, an N-type drift layer and a second P column are formed on the N-type substrate; wherein the first P column and the second P column are respectively located on both sides of the N-type drift layer, and the N-type drift layer is a convex structure;

[0007] A first P-type base region and a second P-type base region, wherein the first P-type base region is formed on the first P column and a first horizontal portion of the N-type drift layer, and the second P-type base region is formed on the second P column and a second horizontal portion of the N-type drift layer, and the first P-type base region and the second P-type base region are L-shaped structures;

[0008] A first P-type source region and a first N-type source region are formed on a horizontal portion of the first P-type base region;

[0009] A second P-type source region and a second N-type source region are formed on a horizontal portion of the second P-type base region;

[0010] a first gate dielectric layer and a first gate polysilicon layer, wherein the first gate dielectric layer is located on a vertical portion of the first P-type base region, a partial region of the third horizontal portion of the N-type drift layer, and a partial region of the first N-type source region, and the first gate dielectric layer wraps the first gate polysilicon layer;

[0011] a second gate dielectric layer and a second gate polysilicon layer, wherein the second gate dielectric layer is located on a vertical portion of the second P-type base region, a partial region of the N-type drift layer, and a partial region of the second N-type source region, and the second gate dielectric layer wraps the second gate polysilicon layer;

[0012] a third P-type base region, formed on the N-type drift layer and located between the first gate dielectric layer and the second gate dielectric layer;

[0013] a third N-type source region, formed on the third P-type base region and located between the first gate dielectric layer and the second gate dielectric layer;

[0014] a source layer having an inverted chevron-shaped structure, wherein the source layer contacts the first P-type source region, the first N-type source region, the second P-type source region, and the second N-type source region, and a middle convex portion of the inverted chevron-shaped structure of the source layer is embedded in the third P-type base region and the third N-type source region, and the source layer embedded in the third P-type base region and the third N-type source region is isolated from the third P-type base region and the third N-type source region by an insulating dielectric layer;

[0015] The drain layer is formed on the back side of the N-type substrate.

[0016] In some embodiments, the deep source super junction MOSFET device further comprises:

[0017] A first N-type heavily doped region is formed between the N-type drift layer and the first gate dielectric layer, and the first N-type heavily doped region is in contact with a vertical portion of the first P-type base region and the first gate dielectric layer.

[0018] In some embodiments, the deep source super junction MOSFET device further comprises:

[0019] A second N-type heavily doped region is formed between the N-type drift layer and the second gate dielectric layer, and the second N-type heavily doped region is in contact with a vertical portion of the second P-type base region and the second gate dielectric layer.

[0020] In some embodiments, a first Schottky metal layer is disposed between the source layer and the first P-type source region.

[0021] In some embodiments, a second Schottky metal layer is disposed between the source layer and the second P-type source region.

[0022] In some embodiments, the thickness of the insulating dielectric layer is a preset thickness; wherein, when the thickness of the insulating dielectric layer is the preset thickness, the on-voltage of the deep source super junction MOSFET device is less than the body diode on-voltage of the deep source super junction MOSFET device.

[0023] A second aspect of the embodiment of the present application further provides a method for preparing a deep source super junction MOSFET device, the preparation method comprising:

[0024] Epitaxially growing silicon material on an N-type substrate and implanting N-type doping ions to form an N-type drift layer;

[0025] Implanting P-type doping ions into the two side regions of the N-type drift layer to form a first P column and a second P column;

[0026] Forming a first P-type base region and a second P-type base region on the first P-column, the N-type drift layer and the second P-column, and making the N-type drift layer present a convex structure, wherein the first P-type base region is located on the first horizontal portion of the first P-column and the N-type drift layer, and the second P-type base region is formed on the second P-column and the second horizontal portion of the N-type drift layer;

[0027] Sequentially implanting N-type doping ions and P-type doping ions into the first P-type base region and the second P-type base region to form a first P-type source region, a first N-type source region, a second P-type source region, and a second N-type source region, so that the first P-type base region and the second P-type base region are L-shaped structures; wherein the first P-type source region and the first N-type source region are located on a horizontal portion of the first P-type base region, and the second P-type source region and the second N-type source region are located on a horizontal portion of the second P-type base region;

[0028] Epitaxially growing silicon material on the N-type drift layer and implanting N-type doping ions to form an N-type layer, and sequentially implanting P-type doping ions and N-type doping ions into the central region of the N-type layer to form a third P-type base region and a third N-type source region; wherein the third N-type source region is formed on the third P-type base region;

[0029] The N-type layers on both sides of the third P-type base region and the third N-type source region are respectively subjected to trench etching and oxide layer deposition to form a first gate dielectric layer, a first gate polysilicon layer, a second gate dielectric layer, and a second gate polysilicon layer; wherein the first gate dielectric layer and the first gate polysilicon layer are located on the vertical portion of the first P-type base region, a partial region of the third horizontal portion of the N-type drift layer, and a partial region of the first N-type source region, and the first gate dielectric layer wraps the first gate polysilicon layer; the second gate dielectric layer and the second gate polysilicon layer are located on the vertical portion of the second P-type base region, a partial region of the N-type drift layer, and a partial region of the second N-type source region, and the second gate dielectric layer wraps the second gate polysilicon layer;

[0030] Etching the third P-type base region and the third N-type source region to form deep grooves, and forming an insulating dielectric layer in the deep grooves;

[0031] Depositing source metal material to form a source layer with an inverted chevron-shaped structure; the source layer is in contact with the first P-type source region, the first N-type source region, the second P-type source region, and the second N-type source region, and the middle convex portion of the inverted chevron-shaped structure of the source layer is embedded in an insulating dielectric layer with a concave chevron-shaped structure, so that the middle convex portion of the inverted chevron-shaped structure of the source layer is isolated from the third P-type base region and the third N-type source region by the insulating dielectric layer;

[0032] A drain layer is formed on the back side of the N-type substrate.

[0033] In some embodiments, the preparation method further comprises:

[0034] A first N-type heavily doped region and a second N-type heavily doped region are formed on both sides of the third horizontal portion of the N-type drift layer; the first N-type heavily doped region contacts the vertical portion of the first P-type base region and the first gate dielectric layer, and the second N-type heavily doped region contacts the vertical portion of the second P-type base region and the second gate dielectric layer.

[0035] In some embodiments, the preparation method further comprises:

[0036] The thickness of the insulating dielectric layer is set to a preset thickness; wherein, when the thickness of the insulating dielectric layer is the preset thickness, the on-voltage of the deep source super junction MOSFET device is less than the body diode on-voltage of the deep source super junction MOSFET device.

[0037] A third aspect of the embodiments of the present application further provides a chip, comprising the deep source super junction MOSFET device as described in any of the above embodiments.

[0038] The beneficial effects of the embodiments of the present application are as follows: by providing an N-type drift layer with a convex structure, a first gate polysilicon layer and a second gate polysilicon layer are formed on both sides of the N-type drift layer, the gate area is reduced, the gate charge is reduced, and the source layer with an inverted mountain-shaped structure is used to control the opening of the third P-type base region between the first gate polysilicon layer and the second gate polysilicon layer, thereby increasing the current conduction channel, and by providing the middle convex portion of the inverted mountain-shaped structure of the source layer embedded in the third P-type base region and the third N-type source region, and the source layer embedded in the third P-type base region and the third N-type source region is isolated from the third P-type base region and the third N-type source region by an insulating dielectric layer, thereby achieving the control of the thickness of the insulating dielectric layer so that its on-voltage is lower than the on-voltage drop of the body diode, reducing the hole injection into the first P-type source region and the second P-type source region, and improving the reverse recovery of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a first structural schematic diagram of a deep source super junction MOSFET device provided in an embodiment of the present application;

[0040] Figure 2 is a second structural schematic diagram of a deep source super junction MOSFET device provided in an embodiment of the present application;

[0041] Figure 3 is a third structural schematic diagram of a deep source super junction MOSFET device provided in an embodiment of the present application;

[0042] Figure 4 It is a comparison diagram of forward conduction current simulation results of a deep source super junction MOSFET device provided by an embodiment of the present application and a conventional super junction MOSFET device;

[0043] Figure 5 is a comparison chart of breakdown voltage simulation results of a deep source super junction MOSFET device provided by an embodiment of the present application and a conventional super junction MOSFET device;

[0044] Figure 6 It is a comparison diagram of reverse recovery speed simulation results of a deep source super junction MOSFET device provided by an embodiment of the present application and a conventional super junction MOSFET device;

[0045] Figure 7 It is a schematic flow chart of a method for preparing a deep source super junction MOSFET device provided in an embodiment of the present application;

[0046] Figure 8 is a schematic diagram of forming an N-type drift region on an N-type substrate layer provided by an embodiment of the present application;

[0047] Fig. 9 is a schematic diagram of forming a first P column and a second P column provided in an embodiment of the present application;

[0048] Fig.10 It is a schematic diagram of forming a first P-type base region, a second P-type base region, a first P-type source region, a second P-type source region, a first N-type source region, and a second N-type source region provided by an embodiment of the present application;

[0049] Fig.11 It is a schematic diagram of forming an N-type layer, a third P-type source region, and a third N-type source region provided by an embodiment of the present application;

[0050] Fig.12 is a schematic diagram of forming a first gate dielectric layer, a first gate polysilicon layer, a second gate dielectric layer, and a second gate polysilicon layer provided in an embodiment of the present application;

[0051] Fig.13 It is a schematic diagram of forming an insulating dielectric layer provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0053] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0054] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0055] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means one or more, unless otherwise clearly and specifically defined.

[0056] Deep source super junction MOSFET devices (Super Junction Metal-Oxide-Semiconductor Field-Effect Transistor, SJMOSFET) are gradually replacing traditional vertical double diffused metal-oxide semiconductor field effect transistors (Vertical Double-diffused Metal-Oxide-Semiconductor, VDMOS) in many application fields due to their excellent performance such as high voltage resistance and low internal resistance. However, during the reverse conduction process, the P-type source will inject a large number of minority holes into the drift region, affecting the reverse recovery process of the super junction MOSFET device.

[0057] In order to solve the above technical problems, the present application embodiment provides a deep source super junction MOSFET device, see Figure 1 As shown, the deep source super junction MOSFET device includes an N-type substrate 110, a first P-column 121, an N-type drift layer 120, a second P-column 122, a first P-type base region 130, a second P-type base region 131, a first P-type source region 132, a first N-type source region 133, a second P-type source region 134, a second N-type source region 135, a first gate dielectric layer 151, a first gate polysilicon layer 152, a second gate dielectric layer 153, a second gate polysilicon layer 154, a third P-type base region 141, a third N-type source region 142, a source layer 161 and a drain layer 162.

[0058] In the present application embodiment, Figure 1 As shown, a first P-column 121, an N-type drift layer 120 and a second P-column 122 are formed on an N-type substrate 110, and the first P-column 121 and the second P-column 122 are respectively located on both sides of the N-type drift layer 120, and the N-type drift layer 120 is a convex structure; a first P-type base region 130 and a second P-type base region 131, the first P-type base region 130 is formed on the first P-column 121 and the first horizontal portion of the N-type drift layer, the second P-type base region 131 is formed on the second P-column 122 and the second horizontal portion of the N-type drift layer, and the first P-type base region 130 and the second P-type base region 131 are L-shaped structures.

[0059] In the present application embodiment, Figure 1As shown, the first P-type source region 132 and the first N-type source region 133 are formed on the horizontal portion of the first P-type base region 130; the second P-type source region 134 and the second N-type source region 135 are formed on the horizontal portion of the second P-type base region 131; the first gate dielectric layer 151 and the first gate polysilicon layer 152 are located on the vertical portion of the first P-type base region 130, a partial area of ​​the third horizontal portion of the N-type drift layer 120, and a partial area of ​​the first N-type source region 133, and the first gate dielectric layer 151 wraps the first gate polysilicon layer 152; the second gate dielectric layer 153 and the second gate polysilicon layer 154 are located on the vertical portion of the second P-type base region 131, a partial area of ​​the N-type drift layer 120, and a partial area of ​​the second N-type source region 135, and the second gate dielectric layer 153 wraps the second gate polysilicon layer 154.

[0060] In the present application embodiment, Figure 1 As shown, the third P-type base region 141 is formed on the N-type drift layer 120 and is located between the first gate dielectric layer 151 and the second gate dielectric layer 153 ; the third N-type source region 142 is formed on the third P-type base region 141 and is located between the first gate dielectric layer 151 and the second gate dielectric layer 153 .

[0061] In the present application embodiment, Figure 1 As shown, the source layer 161 is in an inverted mountain-shaped structure, and the source layer 161 is in contact with the first P-type source region 132, the first N-type source region 133, the second P-type source region 134, and the second N-type source region 135, and the middle protrusion of the inverted mountain-shaped structure of the source layer 161 is embedded in the third P-type base region 141 and the third N-type source region 142, and the source layer 161 embedded in the third P-type base region 141 and the third N-type source region 142 is isolated from the third P-type base region 141 and the third N-type source region 142 by the insulating dielectric layer 160; the drain layer 162 is formed on the back side of the N-type substrate 110.

[0062] In the embodiment of the present application, in the first aspect, a first gate dielectric layer 151 and a first gate polysilicon layer 152 are arranged on the vertical portion of the first P-type base region 130, and on a partial area of ​​the third horizontal portion of the N-type drift layer 120 and a partial area of ​​the first N-type source region 133, and a second gate dielectric layer 153 and a second gate polysilicon layer 154 are arranged on the vertical portion of the second P-type base region 131, and on the third horizontal portion of the N-type drift layer 120 and a partial area of ​​the second N-type source region 135, so as to reduce the gate area, and the reduction in the gate area will reduce the channel length to a certain extent, so as to reduce the gate charge, thereby improving the reverse recovery and switching speed of the deep source super junction MOSFET device; in the second aspect, a source layer 161 with an inverted mountain-shaped structure is arranged, and the source voltage is used to control the first P-type The base region 130 and the second P-type base region 131 are opened to increase the current conduction channel and compensate for the adverse effect of the forward conduction characteristics of the deep source super junction MOSFET device caused by the reduction of the gate area; on the third aspect, the present application also sets the middle protrusion of the inverted mountain-shaped structure of the source layer 161 to be embedded in the third P-type base region 141 and the third N-type source region 142, and the source layer 161 embedded in the third P-type base region 141 and the third N-type source region 142 is isolated from the third P-type base region 141 and the third N-type source region 142 by an insulating dielectric layer, thereby achieving the turn-on voltage of the deep source super junction MOSFET device lower than the turn-on voltage of the body diode by controlling the thickness of the insulating dielectric layer, reducing the hole injection of the first P-type source region 132 and the second P-type source region 134, and improving the reverse recovery of the device.

[0063] In some embodiments, in combination Figure 2 As shown, the deep source super junction MOSFET device may also include: a first N-type heavily doped region 171, the first N-type heavily doped region 171 is formed between the N-type drift layer 120 and the first gate dielectric layer 151, and the first N-type heavily doped region 171 is in contact with the vertical portion of the first P-type base region 130 and the first gate dielectric layer 151.

[0064] In this embodiment, the presence of the first N-type heavily doped region 171 increases the electron concentration and improves the forward conduction current without affecting the forward conduction characteristics of the device. At the same time, it reduces the lifetime of minority holes in the device, further improving the reverse recovery characteristics of the device.

[0065] In some embodiments, in combination Figure 2 As shown, the deep source super junction MOSFET device can also include a second N-type heavily doped region 172, which is formed between the N-type drift layer 120 and the second gate dielectric layer 153, and the second N-type heavily doped region 172 is in contact with the vertical portion of the second P-type base region 131 and the second gate dielectric layer 153.

[0066] In this embodiment, the presence of the second N-type heavily doped region 172 increases the electron concentration and improves the forward conduction current without affecting the forward conduction characteristics of the device. At the same time, it reduces the lifetime of minority holes in the device, further improving the reverse recovery characteristics of the device.

[0067] As shown in Table 1, Figure 4 , Figure 5 , Figure 6 As shown, in the embodiment of the present application, by setting a first N-type heavily doped region 171 (N+) between the first gate dielectric layer 151 and the N-type drift layer 120, and setting a second N-type heavily doped region 172 (N+) between the second gate dielectric layer 153 and the N-type drift layer 120, the electron concentration of the device can be increased, thereby improving the forward conduction current of the device without affecting its forward conduction characteristics, and at the same time reducing the lifetime of minority holes, further improving the reverse recovery of the device.

[0068] Among them, the V （BR）DSS is the drain-source breakdown voltage, R DS(ON) is the on-resistance, I D is the source-drain saturation current, V th is the threshold voltage, t rr is the body diode reverse recovery time, Q rr is the body diode reverse recovery charge, I RRM Reverse recovery current, V GS is the turn-on voltage, I DS is the drain current, VDD is the power supply voltage, and di / dt is the current.

[0069] Figure 4 Curve 1 in FIG. 1 is a forward conduction current variation curve of a deep source super junction MOSFET device provided in an embodiment of the present application, and curve 2 is a forward conduction current variation curve of a conventional super junction MOSFET device; Figure 4 The horizontal axis is the drain voltage Vd, and the vertical axis is the saturation current Id of the super junction device when it is forward-conducted.

[0070] Figure 5 Curve 3 in the figure is the breakdown voltage curve of the deep source super junction MOSFET device provided in the embodiment of the present application, and curve 4 is the breakdown voltage curve of the traditional super junction MOSFET device; Vds is the voltage between the drain and the source, and Ids is the current between the drain and the source.

[0071] Figure 6Curve 5 in the figure is the reverse recovery change curve of the deep source super junction MOSFET device provided in the embodiment of the present application without the first N-type heavily doped region 171 and the second N-type heavily doped region 172, Curve 6 is the reverse recovery change curve of the deep source super junction MOSFET device provided in the embodiment of the present application with the first N-type heavily doped region 171 and the second N-type heavily doped region 172, Curve 7 is the reverse recovery change curve of the traditional super junction MOSFET device, the horizontal axis is time, and the vertical axis is current.

[0072] In the embodiment of the present application, a convex N-type drift layer 120 is provided, and a first gate polysilicon layer 152 and a second gate polysilicon layer 154 are formed on both sides of the N-type drift layer 120 to reduce the gate area and gate charge, and a source layer 161 with an inverted mountain-shaped structure is used to control the opening of the third P-type base region 141 between the first gate polysilicon layer 152 and the second gate polysilicon layer 154 to increase the current conduction channel, and the thickness of the insulating dielectric layer can be controlled so that its conduction voltage is lower than the conduction voltage drop of the body diode, thereby reducing the hole injection of the P-type source. Moreover, the presence of the N-type source increases the electron concentration and improves the forward conduction current, which will not affect the forward conduction characteristics of the device. At the same time, it also reduces the lifetime of minority holes, further improving the reverse recovery of the device.

[0073] Table 1:

[0074]

[0075] In some embodiments, the first N-type heavily doped region 171 and the second N-type heavily doped region 172 may be provided separately or simultaneously.

[0076] In some embodiments, in combination Figure 2 As shown, the first N-type heavily doped region 171 and the second N-type heavily doped region 172 are formed on both sides of the third horizontal portion of the N-type drift layer 120 .

[0077] In some embodiments, see Figure 3 As shown, a first Schottky metal layer 181 may be further provided between the source layer 161 and the first P-type source region 132 .

[0078] In some embodiments, see Figure 3 As shown, a second Schottky metal layer 182 is further disposed between the source layer 161 and the second P-type source region 134 .

[0079] In this embodiment, by forming a Schottky contact between the first P-type source region 132 and the first Schottky metal layer 181, and forming a Schottky contact between the second P-type source region 134 and the second Schottky metal layer 182, during reverse recovery of the device, only the first N-type source region 133 and the second N-type source region 135 enter the raised portion of the N-type drift layer 120, and the first N-type heavily doped region 171 and the second N-type heavily doped region 172 are superimposed to reduce the injection of minority carriers, thereby achieving the purpose of further reducing hole injection and improving the reverse recovery of the device.

[0080] In one embodiment, the thickness of the insulating medium layer is a preset thickness.

[0081] In the embodiment of the present application, when the thickness of the insulating dielectric layer is a preset thickness, the on-voltage of the deep source super junction MOSFET device is less than the body diode on-voltage of the deep source super junction MOSFET device.

[0082] In the embodiment of the present application, the thickness of the insulating dielectric layer is controlled so that the on-voltage of the deep source super junction MOSFET device is lower than the on-voltage of the body diode, thereby reducing hole injection into the first P-type source region 132 and the second P-type source region 134 .

[0083] In one embodiment, the width of the first gate dielectric layer 151 is smaller than the width of the horizontal portion of the first P-type base region 130 ; and the width of the second gate dielectric layer 153 is smaller than the width of the horizontal portion of the second P-type base region 131 .

[0084] In the embodiment of the present application, the width of the first gate dielectric layer 151 is set to be smaller than the width of the horizontal portion of the first P-type base region 130; the width of the second gate dielectric layer 153 is set to be smaller than the width of the horizontal portion of the second P-type base region 131, so as to reduce the gate area and the gate charge, thereby improving the reverse recovery and switching speed of the deep source super junction MOSFET device.

[0085] In one embodiment, the thickness of the first gate dielectric layer 151 is smaller than the thickness of the vertical portion of the first P-type base region 130 ; the thickness of the second gate dielectric layer 153 is smaller than the thickness of the vertical portion of the second P-type base region 131 .

[0086] In the embodiment of the present application, the thickness of the first gate dielectric layer 151 is set to be smaller than the thickness of the vertical portion of the first P-type base region 130; the thickness of the second gate dielectric layer 153 is set to be smaller than the thickness of the vertical portion of the second P-type base region 131, so as to reduce the gate area and the gate charge, thereby improving the reverse recovery and switching speed of the deep source super junction MOSFET device.

[0087] See also Figure 7As shown, this embodiment also provides a method for preparing a deep source super junction MOSFET device, and the preparation method includes steps S100 to S900.

[0088] In step S100 , a silicon material is epitaxially grown on an N-type substrate 110 and N-type dopant ions are implanted to form an N-type drift layer 120 .

[0089] In this embodiment, combined with Figure 8 As shown, a silicon material can be epitaxially grown on a silicon substrate, and N-type doping ions can be implanted into the epitaxial silicon material to form an N-type substrate 110, and then an N-type drift layer 120 can be epitaxially grown on the front side of the N-type substrate 110. The N-type doping ion concentration of the N-type drift layer 120 is lower than the doping ion concentration of the N-type substrate 110.

[0090] In one embodiment, the doping concentration of the N-type substrate 110 layer is at least 100 times the doping concentration of the N-type epitaxial layer.

[0091] In one embodiment, the N-type doping ion concentration of the N-type substrate 110 may be 1e20 cm-3, and the N-type doping ion concentration of the N-type drift layer 120 may be 1e15 cm-3-1e17 cm-3. The thickness of the N-type substrate 110 may be 3 um-10 um. The thickness of the N-type drift layer 120 may be 20 um-60 um.

[0092] In step S200 , P-type doping ions are implanted into two side regions of the N-type drift layer 120 to form a first P column 121 and a second P column 122 .

[0093] In this embodiment, combined with Fig. 9 As shown, by injecting P-type doping ions on both sides of the N-type drift layer 120 , a first P column 121 and a second P column 122 that penetrate into the N-type substrate 110 can be formed, and the N-type drift layer 120 is located between the first P column 121 and the second P column 122 .

[0094] In one embodiment, the first P column 121 and the second P column 122 have the same width, and the sum of the widths of the first P column 121 and the second P column 122 may be less than or equal to the width of the N-type drift layer 120 .

[0095] In step S300, a first P-type base region 130 and a second P-type base region 131 are formed on the first P-column 121, the N-type drift layer 120, and the second P-column 122, and the N-type drift layer 120 is made to have a convex structure. The first P-type base region 130 is located on the first horizontal portion of the first P-column 121 and the N-type drift layer, and the second P-type base region 131 is formed on the second P-column 122 and the second horizontal portion of the N-type drift layer.

[0096] In step S400, N-type dopant ions and P-type dopant ions are sequentially implanted into the first P-type base region 130 and the second P-type base region 131 to form a first P-type source region 132, a first N-type source region 133, a second P-type source region 134, and a second N-type source region 135, so that the first P-type base region 130 and the second P-type base region 131 are L-shaped structures.

[0097] In this embodiment, combined with Fig.10 As shown, the first P-type source region 132 and the first N-type source region 133 are located on the horizontal portion of the first P-type base region 130 , and the second P-type source region 134 and the second N-type source region 135 are located on the horizontal portion of the second P-type base region 131 .

[0098] In step S500 , silicon material is epitaxially grown on the N-type drift layer 120 and N-type dopant ions are implanted to form an N-type layer. P-type dopant ions and N-type dopant ions are implanted in sequence in the central region of the N-type layer to form a third P-type base region 141 and a third N-type source region 142 .

[0099] In this embodiment, combined with Fig.11 As shown, the third N-type source region 142 is formed on the third P-type base region 141 in a stacked manner.

[0100] In one embodiment, the width of the third N-type source region 142 is the same as the width of the third P-type base region 141 . The thickness of the third N-type source region 142 is the same as the thickness of the third P-type base region 141 .

[0101] In one embodiment, the ion doping concentration of the N-type layer is the same as the ion doping concentration of the N-type drift layer 120. In addition, the total thickness of the third N-type source region 142 and the third P-type base region 141 is less than the thickness of the N-type layer.

[0102] In one embodiment, the thickness of the N-type layer may be less than the thickness of the first P-type base region 130 .

[0103] In step S600 , the N-type layers on both sides of the third P-type base region 141 and the third N-type source region 142 are respectively trench etched and an oxide layer is deposited to form a first gate dielectric layer 151 , a first gate polysilicon layer 152 , a second gate dielectric layer 153 and a second gate polysilicon layer 154 .

[0104] In this embodiment, combined with Fig.12As shown, the first gate dielectric layer 151 and the first gate polysilicon layer 152 are located on the vertical portion of the first P-type base region 130, a partial area of ​​the third horizontal portion of the N-type drift layer 120, and a partial area of ​​the first N-type source region 133, and the first gate dielectric layer 151 wraps the first gate polysilicon layer 152; the second gate dielectric layer 153 and the second gate polysilicon layer 154 are located on the vertical portion of the second P-type base region 131, a partial area of ​​the N-type drift layer 120, and a partial area of ​​the second N-type source region 135, and the second gate dielectric layer 153 wraps the second gate polysilicon layer 154.

[0105] In step S700 , the third P-type base region 141 and the third N-type source region 142 are etched to form deep trenches, and an insulating dielectric layer is formed in the deep trenches.

[0106] In one embodiment, in combination Fig.13 As shown, an insulating dielectric material such as silicon oxide or silicon nitride may be epitaxially grown at a predetermined depth in the middle of the third P-type base region 141 and the third N-type source region 142 to form an insulating dielectric layer.

[0107] In one embodiment, the predetermined depth is less than or equal to the total thickness of the third P-type base region 141 and the third N-type source region 142 .

[0108] In step S800, source metal material is deposited to form a source layer 161 in an inverted V-shaped structure; the source layer 161 is in contact with the first P-type source region 132, the first N-type source region 133, the second P-type source region 134, and the second N-type source region 135, and the middle protruding portion of the inverted V-shaped structure of the source layer 161 is embedded in the insulating dielectric layer in a concave V-shaped structure.

[0109] In this embodiment, combined with Figure 1 As shown, the middle protrusion of the inverted chevron structure of the source layer 161 is isolated from the third P-type base region 141 and the third N-type source region 142 by an insulating dielectric layer; and the middle protrusion of the inverted chevron structure of the source layer 161 contacts the insulating dielectric layer.

[0110] In step S900 , a drain layer 162 is formed on the back surface of the N-type substrate 110 .

[0111] In the embodiment of the present application, in the first aspect, a first gate dielectric layer 151 and a first gate polysilicon layer 152 are arranged on the vertical portion of the first P-type base region 130, and on a partial area of ​​the third horizontal portion of the N-type drift layer 120 and a partial area of ​​the first N-type source region 133, and a second gate dielectric layer 153 and a second gate polysilicon layer 154 are arranged on the vertical portion of the second P-type base region 131, and on the third horizontal portion of the N-type drift layer 120 and a partial area of ​​the second N-type source region 135, so as to reduce the gate area, and the reduction in the gate area will reduce the channel length to a certain extent, so as to reduce the gate charge, thereby improving the reverse recovery and switching speed of the deep source super junction MOSFET device; in the second aspect, a source layer 161 with an inverted mountain-shaped structure is arranged, and the source voltage is used to control the first P-type base Region 130 and the second P-type base region 131 are opened to increase the current conduction channel and compensate for the adverse effect of the forward conduction characteristics of the deep source super junction MOSFET device caused by the reduction of the gate area; on the third aspect, the present application also arranges the middle convex portion of the inverted mountain-shaped structure of the source layer 161 to be embedded in the third P-type base region 141 and the third N-type source region 142, and the source layer 161 embedded in the third P-type base region 141 and the third N-type source region 142 is isolated from the third P-type base region 141 and the third N-type source region 142 by an insulating dielectric layer, thereby achieving the turn-on voltage of the deep source super junction MOSFET device lower than the turn-on voltage of the body diode by controlling the thickness of the insulating dielectric layer, reducing the hole injection of the first P-type source region 132 and the second P-type source region 134, and improving the reverse recovery of the device.

[0112] In one embodiment, before the above step S400, a first N-type heavily doped region 171 and a second N-type heavily doped region 172 may be formed on both sides of the third horizontal portion of the N-type drift layer 120. Then, silicon material is epitaxially grown on the first P column 121, the N-type drift layer 120, and the second P column 122, and N-type doping ions are implanted to form a new N-type drift layer 120, and P-type doping ions are implanted on both sides of the new N-type drift layer 120 to form a first P-type base region 130 and a second P-type base region 131, and the new N-type drift layer 120 is made to have a convex structure, the first P-type base region 130 is located on the first P column 121 and the first horizontal portion of the N-type drift layer, and the second P-type base region 131 is formed on the second P column 122 and the second horizontal portion of the N-type drift layer.

[0113] In this embodiment, the first N-type heavily doped region 171 contacts the vertical portion of the first P-type base region 130 and the first gate dielectric layer 151 , and the second N-type heavily doped region 172 contacts the vertical portion of the second P-type base region 131 and the second gate dielectric layer 153 .

[0114] In this embodiment, the first N-type heavily doped region 171123 and the second N-type heavily doped region 172124 have the same thickness and the same width.

[0115] In some embodiments, see Figure 3 As shown, a first Schottky metal layer 181 may be further provided between the source layer 161 and the first P-type source region 132 .

[0116] In some embodiments, see Figure 3 As shown, a second Schottky metal layer 182 is further disposed between the source layer 161 and the second P-type source region 134 .

[0117] In this embodiment, by forming a Schottky contact between the first P-type source region 132 and the first Schottky metal layer 181, and forming a Schottky contact between the second P-type source region 134 and the second Schottky metal layer 182, during reverse recovery of the device, only the first N-type source region 133 and the second N-type source region 135 enter the raised portion of the N-type drift layer 120, and the first N-type heavily doped region 171 and the second N-type heavily doped region 172 are superimposed to reduce the injection of minority carriers, thereby achieving the purpose of further reducing hole injection and improving the reverse recovery of the device.

[0118] In one embodiment, the preparation method further includes: setting the thickness of the insulating dielectric layer to a preset thickness.

[0119] In this embodiment, when the thickness of the insulating dielectric layer is a preset thickness, the on-voltage of the deep source super junction MOSFET device is less than the on-voltage of the body diode of the deep source super junction MOSFET device.

[0120] In the embodiment of the present application, the thickness of the insulating dielectric layer is controlled so that the on-voltage of the deep source super junction MOSFET device is lower than the on-voltage of the body diode, thereby reducing hole injection into the first P-type source region 132 and the second P-type source region 134 .

[0121] An embodiment of the present application also provides a chip, comprising a deep source super junction MOSFET device as in any of the above embodiments.

[0122] In this embodiment, the chip includes a chip substrate, on which one or more deep source super junction MOSFET devices are arranged. The deep source super junction MOSFET device can be prepared by the preparation method in any of the above embodiments, or the deep source super junction MOSFET device in any of the above embodiments can be arranged on the chip substrate.

[0123] In a specific application embodiment, other related semiconductor devices and deep source super junction MOSFET devices can also be integrated on the chip substrate to form an integrated circuit.

[0124] In a specific application embodiment, the chip may be a switch chip or a driver chip.

[0125] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned doping regions and devices is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different doping regions and devices as needed, that is, the internal structure of the device is divided into different doping regions to complete all or part of the functions described above. The doping regions and devices in the embodiments can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0126] In addition, the specific names of the doping regions and devices are only for the convenience of distinguishing each other and are not used to limit the scope of protection of the present application.

[0127] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0128] In addition, each doping region in each embodiment of the present application may be integrated into one unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0129] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A deep source super junction MOSFET device, characterized in that: include: N-type substrate; A first P column, an N-type drift layer and a second P column are formed on the N-type substrate; wherein the first P column and the second P column are respectively located on both sides of the N-type drift layer, and the N-type drift layer is a convex structure; A first P-type base region and a second P-type base region, wherein the first P-type base region is formed on the first P column and a first horizontal portion of the N-type drift layer, and the second P-type base region is formed on the second P column and a second horizontal portion of the N-type drift layer, and the first P-type base region and the second P-type base region are L-shaped structures; A first P-type source region and a first N-type source region are formed on a horizontal portion of the first P-type base region; A second P-type source region and a second N-type source region are formed on a horizontal portion of the second P-type base region; a first gate dielectric layer and a first gate polysilicon layer, wherein the first gate dielectric layer is located on a vertical portion of the first P-type base region, a partial region of the third horizontal portion of the N-type drift layer, and a partial region of the first N-type source region, and the first gate dielectric layer wraps the first gate polysilicon layer; a second gate dielectric layer and a second gate polysilicon layer, wherein the second gate dielectric layer is located on a vertical portion of the second P-type base region, a partial region of the N-type drift layer, and a partial region of the second N-type source region, and the second gate dielectric layer wraps the second gate polysilicon layer; a third P-type base region, formed on the N-type drift layer and located between the first gate dielectric layer and the second gate dielectric layer; a third N-type source region, formed on the third P-type base region and located between the first gate dielectric layer and the second gate dielectric layer; a source layer having an inverted chevron-shaped structure, wherein the source layer contacts the first P-type source region, the first N-type source region, the second P-type source region, and the second N-type source region, and a middle convex portion of the inverted chevron-shaped structure of the source layer is embedded in the third P-type base region and the third N-type source region, and the source layer embedded in the third P-type base region and the third N-type source region is isolated from the third P-type base region and the third N-type source region by an insulating dielectric layer; A drain layer, formed on the back side of the N-type substrate; The source layer embedded in the third P-type base region and the third N-type source region is isolated from the third P-type base region and the third N-type source region by an insulating dielectric layer; the source layer of the inverted mountain-shaped structure controls the opening of the third P-type base region between the first gate polysilicon layer and the second gate polysilicon layer, increases the current conduction channel, and controls the thickness of the insulating dielectric layer so that the on-voltage of the deep source super junction MOSFET device is less than the body diode on-voltage of the deep source super junction MOSFET device.

2. The deep source super junction MOSFET device according to claim 1, characterized in that: The deep source super junction MOSFET device also includes: A first N-type heavily doped region is formed between the N-type drift layer and the first gate dielectric layer, and the first N-type heavily doped region is in contact with a vertical portion of the first P-type base region and the first gate dielectric layer.

3. The deep source super junction MOSFET device according to claim 1, characterized in that: The deep source super junction MOSFET device also includes: A second N-type heavily doped region is formed between the N-type drift layer and the second gate dielectric layer, and the second N-type heavily doped region is in contact with a vertical portion of the second P-type base region and the second gate dielectric layer.

4. The deep source super junction MOSFET device according to any one of claims 1 to 3, characterized in that: A first Schottky metal layer is provided between the source layer and the first P-type source region.

5. The deep source super junction MOSFET device according to any one of claims 1 to 3, characterized in that: A second Schottky metal layer is provided between the source layer and the second P-type source region.

6. The deep source super junction MOSFET device according to any one of claims 1 to 3, characterized in that: The thickness of the insulating dielectric layer is a preset thickness; wherein, when the thickness of the insulating dielectric layer is the preset thickness, the on-voltage of the deep source super junction MOSFET device is less than the on-voltage of the body diode of the deep source super junction MOSFET device.

7. A method for preparing a deep source super junction MOSFET device, characterized in that: The preparation method comprises: Epitaxially growing silicon material on an N-type substrate and implanting N-type doping ions to form an N-type drift layer; Implanting P-type doping ions into the two side regions of the N-type drift layer to form a first P column and a second P column; Forming a first P-type base region and a second P-type base region on the first P-column, the N-type drift layer and the second P-column, and making the N-type drift layer present a convex structure, wherein the first P-type base region is located on the first horizontal portion of the first P-column and the N-type drift layer, and the second P-type base region is formed on the second P-column and the second horizontal portion of the N-type drift layer; Sequentially implanting N-type doping ions and P-type doping ions into the first P-type base region and the second P-type base region to form a first P-type source region, a first N-type source region, a second P-type source region, and a second N-type source region, so that the first P-type base region and the second P-type base region are L-shaped structures; wherein the first P-type source region and the first N-type source region are located on a horizontal portion of the first P-type base region, and the second P-type source region and the second N-type source region are located on a horizontal portion of the second P-type base region; Epitaxially growing silicon material on the N-type drift layer and implanting N-type doping ions to form an N-type layer, and sequentially implanting P-type doping ions and N-type doping ions into the central region of the N-type layer to form a third P-type base region and a third N-type source region; wherein the third N-type source region is formed on the third P-type base region; The N-type layers on both sides of the third P-type base region and the third N-type source region are respectively subjected to trench etching and oxide layer deposition to form a first gate dielectric layer, a first gate polysilicon layer, a second gate dielectric layer, and a second gate polysilicon layer; wherein the first gate dielectric layer and the first gate polysilicon layer are located on the vertical portion of the first P-type base region, a partial region of the third horizontal portion of the N-type drift layer, and a partial region of the first N-type source region, and the first gate dielectric layer wraps the first gate polysilicon layer; the second gate dielectric layer and the second gate polysilicon layer are located on the vertical portion of the second P-type base region, a partial region of the N-type drift layer, and a partial region of the second N-type source region, and the second gate dielectric layer wraps the second gate polysilicon layer; The third P-type base region and the third N-type source region are etched to form deep grooves, and an insulating dielectric layer is formed in the deep grooves; the insulating dielectric layer is in a concave shape; Depositing source metal material to form a source layer with an inverted chevron-shaped structure; the source layer is in contact with the first P-type source region, the first N-type source region, the second P-type source region, and the second N-type source region, and the middle convex portion of the inverted chevron-shaped structure of the source layer is embedded in an insulating dielectric layer with a concave chevron-shaped structure, so that the middle convex portion of the inverted chevron-shaped structure of the source layer is isolated from the third P-type base region and the third N-type source region by the insulating dielectric layer; A drain layer is formed on the back side of the N-type substrate; the source layer embedded in the third P-type base region and the third N-type source region is isolated from the third P-type base region and the third N-type source region by an insulating dielectric layer; the source layer of the inverted mountain-shaped structure controls the opening of the third P-type base region between the first gate polysilicon layer and the second gate polysilicon layer, increases the current conduction channel, and controls the thickness of the insulating dielectric layer so that the on-voltage of the deep source super junction MOSFET device is less than the on-voltage of the body diode of the deep source super junction MOSFET device.

8. The preparation method according to claim 7, characterized in that: The preparation method further comprises: A first N-type heavily doped region and a second N-type heavily doped region are formed on both sides of the third horizontal portion of the N-type drift layer; the first N-type heavily doped region contacts the vertical portion of the first P-type base region and the first gate dielectric layer, and the second N-type heavily doped region contacts the vertical portion of the second P-type base region and the second gate dielectric layer.

9. The preparation method according to claim 7, characterized in that: The preparation method further comprises: The thickness of the insulating dielectric layer is set to a preset thickness; wherein, when the thickness of the insulating dielectric layer is the preset thickness, the on-voltage of the deep source super junction MOSFET device is less than the body diode on-voltage of the deep source super junction MOSFET device.

10. A chip, characterized in that: Comprising a deep source super junction MOSFET device as described in any one of claims 1-6.

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