Method and device for implementing real-time simulation of hardware logic using FPGA

Abstract

The embodiment of the present application provides a method and device for implementing real-time simulation of hardware logic in FPGA, the method comprising: encapsulating an algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, and defining the input and output ports and parameter interfaces of the algorithm model in the algorithm IP core; performing comprehensive layout and routing on the top-level design file through a preset design tool of the programmable array logic device, generating a corresponding bit stream file that can be directly run on the programmable array logic device, and downloading the bit stream file to a target hardware platform to start running; the present application can effectively improve simulation efficiency and accuracy.

Description

Technical Field

[0001] The present application relates to the field of simulation experiments, and in particular to a method and device for implementing real-time simulation of hardware logic using an FPGA. Background Art

[0002] In the current electronic design automation (EDA) field, field programmable gate arrays (FPGAs) are widely used in various high-performance computing and real-time processing scenarios due to their high flexibility and reconfigurability. However, with the increasing complexity of algorithms and application requirements, the real-time simulation of FPGA hardware logic has become a technical challenge. Although existing technologies have made some progress in the real-time simulation of FPGA hardware logic, there are still many challenges and shortcomings in terms of simulation efficiency, accuracy, reusability and development cycle.

[0003] First, existing FPGA hardware logic simulation methods usually rely on manually writing hardware description language (HDL) code, such as Verilog or VHDL. This method not only has a long development cycle, but also requires high professional knowledge from developers. Developers need to have a detailed understanding of the FPGA's hardware architecture and design process in order to write efficient and accurate simulation code. For complex algorithm models, the process of manually writing HDL code is not only cumbersome, but also prone to errors, resulting in deviations between simulation results and actual operating results.

[0004] Secondly, existing simulation methods are insufficient in terms of the encapsulation and reusability of algorithm models. Many algorithm models have similar logical structures in different application scenarios, but because existing simulation methods lack effective modularization and encapsulation mechanisms, developers need to write and debug simulation codes separately for each specific application scenario. This not only increases the development workload, but also is not conducive to the reuse and maintenance of algorithm models. Especially in the face of rapidly changing application requirements, the lack of modular and reusable simulation methods seriously affects the flexibility and adaptability of FPGA design.

[0005] In terms of hardware resource management and mapping, existing technologies also have significant deficiencies. The allocation and management of FPGA hardware resources is the key to achieving efficient simulation, but existing methods usually rely on manual configuration and optimization by developers. This manual configuration is not only inefficient, but also difficult to ensure optimal resource utilization. Especially when faced with complex algorithm models and diverse hardware resources, how to effectively map and manage resources is a problem that is difficult to solve with existing simulation methods. In addition, errors and non-optimized configurations during manual configuration may lead to reduced simulation performance and even affect the accuracy of simulation results.

[0006] In terms of the generation and operation of simulation results, the existing technology mainly relies on static design and offline simulation. This traditional method can meet the simulation requirements of simple algorithm models to a certain extent, but for complex algorithm models with high real-time requirements, static design and offline simulation are obviously difficult to meet the requirements. Real-time simulation not only requires that the algorithm model can run efficiently on the FPGA, but also requires that the simulation results can be fed back and adjusted in a timely manner. The shortcomings of the existing methods in this regard lead to unsatisfactory real-time simulation results and are difficult to meet the needs of practical applications.

[0007] In addition, existing FPGA simulation tools and platforms are also insufficient in terms of integration and ease of use. Although some EDA tools provide basic FPGA simulation functions, in actual use, the integration and ease of use of these tools still need to be improved. Developers need to switch between different tools and manually adjust and optimize the simulation process, which increases the complexity and workload of development. Especially when faced with multiple heterogeneous platforms and complex algorithm models, the lack of effective integration and automated simulation tools has seriously affected the efficiency and effectiveness of FPGA simulation.

[0008] In summary, the existing FPGA hardware logic real-time simulation methods still have many shortcomings and challenges in terms of algorithm model encapsulation, hardware resource management, simulation result generation and tool integration. Summary of the invention

[0009] In response to the problems in the prior art, the present application provides a method and device for implementing real-time simulation of hardware logic using FPGA, which can effectively improve the simulation efficiency and accuracy.

[0010] In order to solve at least one of the above problems, the present application provides the following technical solutions:

[0011] In a first aspect, the present application provides a method for implementing hardware logic real-time simulation using an FPGA, comprising:

[0012] Encapsulating the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, and defining the input and output ports and parameter interface of the algorithm model in the algorithm IP core;

[0013] Acquire the hardware resource description information of the programmable array logic device, establish a mapping relationship between the input / output port and the parameter interface and the hardware resource description information of the programmable array logic device using a model-driven method based on the input / output port and the parameter interface of the algorithm IP core and the hardware resource description information of the programmable array logic device, and dynamically generate an engineering configurable top-level design file of the programmable array logic device according to the established mapping relationship;

[0014] The top-level design file is comprehensively laid out and routed through the preset design tool of the programmable array logic device, a corresponding bit stream file that can be directly run on the programmable array logic device is generated, and the bit stream file is downloaded to the target hardware platform to start running.

[0015] Furthermore, the method of packaging the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device includes:

[0016] Constructing an algorithm model to be simulated by using a preset modeling tool, wherein the algorithm model includes elements required for the simulation;

[0017] The algorithm IP core is obtained by generating the implementation code of the algorithm IP core and defining the input and output port interfaces of the algorithm IP core through a preset programmable array logic device design tool.

[0018] Furthermore, the input and output ports and parameter interfaces of the algorithm model are defined in the algorithm IP core, including:

[0019] Defining at least one of the port name, port direction, port data type and port bit width of the algorithm model in the algorithm IP core;

[0020] At least one of a parameter name, a parameter data type, and a parameter initial value of the algorithm model is defined in the algorithm IP core.

[0021] Furthermore, the input / output ports and parameter interfaces of the algorithm IP core and the hardware resource description information of the programmable array logic device are used to establish a mapping relationship between the input / output ports and parameter interfaces and the hardware resource description information using a model-driven method, including:

[0022] Extracting detailed information of the input and output ports and parameter interfaces from the description file of the constructed algorithm IP core, and acquiring resource description information of the target programmable array logic device hardware platform;

[0023] A model-driven approach is adopted to establish automatic mapping between the input / output ports and parameter interfaces and the hardware resources, wherein the input / output ports and parameter interfaces of the input / output port type are mapped to corresponding hardware physical channels.

[0024] Furthermore, the dynamically generating the engineering configurable top-level design file of the programmable array logic device according to the established mapping relationship includes:

[0025] Generate a configurable description of a corresponding programmable array logic device project according to a mapping relationship between the input and output ports and the parameter interface and the hardware resources;

[0026] The corresponding configurable top-level design file is obtained through a preset design tool of the programmable array logic device.

[0027] Furthermore, the top-level design file is subjected to comprehensive layout and routing by a preset design tool of the programmable array logic device to generate a corresponding bitstream file that can be directly run on the programmable array logic device, including:

[0028] Importing the top-level design file of the programmable array logic device into a preset design tool and converting it into a corresponding logic netlist;

[0029] The layout and routing process operation is performed through the logic netlist to obtain a corresponding bit stream file.

[0030] Further, downloading the bitstream file to the target hardware platform to start running includes:

[0031] Transmitting the bitstream file to a hardware platform of a corresponding target programmable array logic device;

[0032] The execution of the bitstream file is started on a hardware platform of the target programmable array logic device.

[0033] In a second aspect, the present application provides a device for implementing hardware logic real-time simulation using an FPGA, comprising:

[0034] A package definition module, used to package the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, and define the input and output ports and parameter interfaces of the algorithm model in the algorithm IP core;

[0035] A file design model is used to obtain the hardware resource description information of the programmable array logic device, and based on the input and output ports and parameter interfaces of the algorithm IP core and the hardware resource description information of the programmable array logic device, a mapping relationship between the input and output ports and parameter interfaces and the hardware resource description information is established by a model-driven method, and an engineering configurable top-level design file of the programmable array logic device is dynamically generated according to the established mapping relationship;

[0036] The simulation test module is used to perform comprehensive layout and routing of the top-level design file through the preset design tool of the programmable array logic device, generate a corresponding bit stream file that can be directly run on the programmable array logic device, and download the bit stream file to the target hardware platform to start running.

[0037] In a third aspect, the present application provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method for implementing hardware logic real-time simulation using an FPGA when executing the program.

[0038] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method for implementing hardware logic real-time simulation using an FPGA.

[0039] In a fifth aspect, the present application provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the method for implementing real-time simulation of hardware logic using FPGA.

[0040] It can be seen from the above technical scheme that the present application provides a method and device for implementing real-time simulation of hardware logic using FPGA, by encapsulating the algorithm model to be simulated into a reusable algorithm IP core of a programmable array logic device, and defining the input and output ports and parameter interfaces of the algorithm model in the algorithm IP core; performing comprehensive layout and routing on the top-level design file through the preset design tool of the programmable array logic device, generating a corresponding bitstream file that can be directly run on the programmable array logic device, and downloading the bitstream file to the target hardware platform to start running, thereby effectively improving the simulation efficiency and accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0042] Figure 1 This is one of the flow charts of the method for implementing hardware logic real-time simulation by FPGA in the embodiment of the present application;

[0043] Figure 2 The second flowchart of the method for implementing hardware logic real-time simulation by FPGA in the embodiment of the present application;

[0044] Figure 3 The third flowchart of the method for implementing hardware logic real-time simulation by FPGA in the embodiment of the present application;

[0045] Figure 4 The fourth flowchart of the method for implementing hardware logic real-time simulation by FPGA in the embodiment of the present application;

[0046] Figure 5 The fifth flowchart of the method for implementing hardware logic real-time simulation by FPGA in the embodiment of the present application;

[0047] Figure 6 The sixth flowchart of the method for implementing hardware logic real-time simulation by FPGA in the embodiment of the present application;

[0048] Figure 7 FIG7 is a flow chart of a method for implementing hardware logic real-time simulation by FPGA in an embodiment of the present application;

[0049] Figure 8 A structural diagram of a device for implementing real-time simulation of hardware logic using an FPGA in an embodiment of the present application;

[0050] Fig. 9 It is a schematic diagram of the structure of an electronic device in an embodiment of the present application.

[0051] Reference numerals:

[0052] Electronic device 9600, central processing unit 9100, memory 9140, communication module 9110, input unit 9120, audio processor 9130, display 9160, power supply 9170, buffer memory 9141, application / function storage unit 9142, data storage unit 9143, driver program storage unit 9144, antenna 9111, speaker 9131, microphone 9132. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0054] The acquisition, storage, use, and processing of data in the technical solution of this application comply with the relevant provisions of national laws and regulations.

[0055] In view of the problems existing in the prior art, the present application provides a method and device for implementing real-time simulation of hardware logic in FPGA, which encapsulates the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, and defines the input and output ports and parameter interfaces of the algorithm model in the algorithm IP core; uses the preset design tool of the programmable array logic device to perform comprehensive layout and routing on the top-level design file, generates a corresponding bitstream file that can be directly run on the programmable array logic device, and downloads the bitstream file to the target hardware platform to start running, thereby effectively improving the simulation efficiency and accuracy.

[0056] In order to effectively improve the simulation efficiency and accuracy, the present application provides an embodiment of a method for implementing hardware logic real-time simulation on an FPGA. Figure 1 The method for implementing hardware logic real-time simulation on FPGA specifically includes the following contents:

[0057] Step S101: encapsulating the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, and defining the input and output ports and parameter interface of the algorithm model in the algorithm IP core;

[0058] Optionally, in this embodiment, in step S101, the system encapsulates the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device (FPGA), and defines the input and output ports and parameter interfaces of the algorithm model in the algorithm IP core. The specific technical process of implementation includes the following steps: First, the system analyzes the algorithm model to be simulated to determine its core functions and key parameters. Then, the system converts the algorithm model into hardware description code using a hardware description language (such as VHDL or Verilog). In this process, the system maps each logical part of the algorithm to the programmable logic unit of the FPGA, thereby realizing the hardware of the algorithm. Then, the system creates an IP core for the hardware description code, which is a reusable hardware module that contains all the functions and interfaces of the algorithm model. When creating the IP core, the system defines the input and output ports and parameter interfaces of the algorithm model so that it can be called and configured in different application scenarios.

[0059] In terms of technical principles, step S101 utilizes the programmable characteristics of FPGA and directly maps the algorithm model to the hardware circuit through the hardware description language. FPGA has the advantages of high parallel computing power and low latency. Hardwareizing complex algorithm models can significantly improve computing speed and efficiency. The creation of IP cores allows algorithm models to be reused in different FPGA designs, reducing the workload of repeated development and improving development efficiency and system flexibility. By defining input and output ports and parameter interfaces, the system can be easily integrated with other hardware modules to achieve flexible system design.

[0060] In terms of the technical problems solved, step S101 mainly solves how to efficiently map complex algorithm models to FPGAs, and how to achieve the reusability and configurability of algorithm models. Traditional software simulation methods often have problems with slow calculation speed and poor real-time performance when facing complex algorithms. By hardwareizing the algorithm model, not only can the calculation speed be improved, but the parallel computing capabilities of FPGA can also be utilized to significantly improve the performance of the system. In addition, by creating an IP core, the algorithm model can be reused in different designs, reducing development time and cost, and improving the flexibility and maintainability of the system.

[0061] In terms of the technical effects achieved, through step S101, the system can efficiently encapsulate complex algorithm models into FPGA algorithm IP cores to achieve high-performance hardware simulation. The created IP core is highly reusable and configurable, and can be called and configured in different designs, which improves the development efficiency and flexibility of the system. By defining input and output ports and parameter interfaces, the system can be easily integrated with other hardware modules to achieve flexible system design and efficient hardware simulation.

[0062] For example, suppose a team is developing a high-performance digital signal processing (DSP) system and needs to perform real-time simulation of complex signal processing algorithms. Traditional software simulation methods often have problems with slow computing speed and poor real-time performance when processing large-scale data. Through step S101, the team can encapsulate these complex signal processing algorithms into FPGA algorithm IP cores. First, the team will analyze the signal processing algorithm to determine its core functions and key parameters. Then, the algorithm model is converted into hardware description code using a hardware description language, and each logical part is mapped to the programmable logic unit of the FPGA. Next, the team creates an IP core for the hardware description code and defines the input and output ports and parameter interfaces. The created IP core can be reused in different DSP system designs, reducing the workload of repeated development and improving development efficiency and system flexibility. By hardwareizing the algorithm model, the team can significantly improve the computing speed and efficiency of the system and achieve high-performance real-time signal processing.

[0063] In another example, a research team is developing an intelligent transportation system and needs to simulate and optimize a complex traffic flow algorithm. Through step S101, the team can encapsulate the traffic flow algorithm into an algorithm IP core for the FPGA. First, the team will analyze the traffic flow algorithm to determine its core functions and key parameters. Then, the algorithm model is converted into hardware description code using a hardware description language, and each logical part is mapped to the programmable logic unit of the FPGA. Next, the team creates an IP core for the hardware description code and defines input and output ports and parameter interfaces. The created IP core can be reused in different intelligent transportation system designs, reducing the workload of repeated development and improving development efficiency and system flexibility. By hardwareizing the algorithm model, the team can significantly improve the computing speed and efficiency of the system and achieve high-performance real-time traffic flow simulation and optimization. Through these steps, the system not only improves the accuracy and real-time performance of the simulation, but also provides strong support for the development and optimization of intelligent transportation systems.

[0064] Step S102: Acquire the hardware resource description information of the programmable array logic device, establish a mapping relationship between the input / output port and parameter interface and the hardware resource description information based on the input / output port and parameter interface of the algorithm IP core and the hardware resource description information of the programmable array logic device by using a model-driven method, and dynamically generate an engineering configurable top-level design file of the programmable array logic device according to the established mapping relationship;

[0065] Optionally, in this embodiment, in step S102, the system obtains the hardware resource description information of the programmable array logic device (FPGA), and based on the input and output ports and parameter interfaces of the algorithm IP core and the hardware resource description information, uses a model-driven method to establish a mapping relationship between these interfaces and the hardware resource description information, and then dynamically generates an engineering configurable top-level design file of the FPGA according to the established mapping relationship. The specific implementation of the technical process can be divided into the following links: First, the system extracts hardware resource description information from the hardware resource management module of the FPGA, which usually includes logic units, storage units, I / O ports, clock resources, etc. Then, the system uses a model-driven method to map these ports and interfaces with the specific hardware resources of the FPGA according to the input and output ports and parameter interfaces of the algorithm IP core. The model-driven method can efficiently convert the design requirements of the software level into hardware implementation by defining the relationship between the abstract model and the specific implementation model. After establishing the mapping relationship, the system dynamically generates a top-level design file based on these relationships, which defines the overall design structure and configuration of the FPGA to ensure that each module can be correctly connected and work.

[0066] In terms of technical principles, step S102 relies on the model-driven engineering (MDE) method, which is a method for system design and development through models. It uses the abstract ability of the model to enable designers to design the system at a high level and then automatically generate specific implementations. In this way, the system can efficiently convert the design requirements of the algorithm IP core into the hardware implementation of the FPGA to ensure the consistency and accuracy of the design. The establishment of the mapping relationship is the key. By matching the abstract design requirements with the specific hardware resources, the system can automatically generate a hardware configuration file that meets the design requirements.

[0067] In terms of the technical problems to be solved, step S102 mainly solves the problem of how to efficiently and accurately match and configure the design requirements of the algorithm IP core with specific hardware resources in a complex FPGA design. FPGA has a high degree of flexibility and programmability, but this also increases the complexity of the design. The traditional manual configuration method is not only time-consuming and labor-intensive, but also prone to errors. By introducing a model-driven approach, the system can automatically design and configure, reducing human errors and improving design efficiency and accuracy. In addition, by dynamically generating top-level design files, the system can quickly adapt to different design requirements and hardware resource changes, improving the flexibility and adaptability of the system.

[0068] In terms of the technical effects achieved, through step S102, the system can efficiently establish the mapping relationship between the algorithm IP core and the FPGA hardware resources, and automatically generate the top-level design file. This not only improves the efficiency of design and configuration, but also ensures the accuracy and consistency of the design. Through the automated design process, the system can quickly adapt to different design requirements and hardware resource changes, improving the flexibility and adaptability of the system. The top-level design file finally generated defines the overall design structure and configuration of the FPGA, ensuring that each module can be correctly connected and work, laying the foundation for subsequent hardware implementation.

[0069] For example, suppose a team is developing a high-performance image processing system and needs to implement a complex image processing algorithm on an FPGA. In step S101, the team has encapsulated the image processing algorithm into an algorithm IP core of the FPGA and defined the input and output ports and parameter interfaces. In step S102, the team first extracts hardware resource description information from the hardware resource management module of the FPGA, including logic units, storage units, I / O ports, clock resources, etc. Next, the team uses a model-driven approach to map these ports and interfaces to the specific hardware resources of the FPGA based on the input and output ports and parameter interfaces of the image processing algorithm IP core. For example, the system may need to map the image input port to the I / O port of the FPGA, map the algorithm operation unit to the logic unit, and map the intermediate data storage unit to the storage unit of the FPGA. By establishing these mapping relationships, the system can ensure the correct implementation and efficient operation of the image processing algorithm on the FPGA. Finally, based on the established mapping relationships, the system dynamically generates the engineering configurable top-level design file of the FPGA, defining the overall design structure and configuration of the FPGA. Through these steps, the team not only improved the efficiency of design and configuration, but also ensured the accuracy and consistency of the design, providing strong support for the high-performance implementation of the image processing system.

[0070] In another example, a research team is developing a real-time data processing system for autonomous driving, which requires hardware acceleration of complex sensor data processing algorithms. In step S101, the team has encapsulated the sensor data processing algorithm into an algorithm IP core of the FPGA and defined the input and output ports and parameter interfaces. In step S102, the team first extracts hardware resource description information from the hardware resource management module of the FPGA, including logic units, storage units, I / O ports, clock resources, etc. Next, the team uses a model-driven approach to map these ports and interfaces to the specific hardware resources of the FPGA based on the input and output ports and parameter interfaces of the sensor data processing algorithm IP core. For example, the system may need to map the sensor input port to the I / O port of the FPGA, map the data processing unit to the logic unit, and map the intermediate data storage unit to the storage unit of the FPGA. By establishing these mapping relationships, the system can ensure the correct implementation and efficient operation of the sensor data processing algorithm on the FPGA. Finally, based on the established mapping relationships, the system dynamically generates the engineering configurable top-level design file of the FPGA, defining the overall design structure and configuration of the FPGA. Through these steps, the team not only improved the efficiency of design and configuration, but also ensured the accuracy and consistency of the design, providing strong support for real-time data processing of the autonomous driving system.

[0071] Step S103: Perform comprehensive layout and routing on the top-level design file through the preset design tool of the programmable array logic device, generate a corresponding bitstream file that can be directly run on the programmable array logic device, and download the bitstream file to the target hardware platform to start running.

[0072] Optionally, in this embodiment, in step S103, the top-level design file is integrated and laid out by the preset design tool of the programmable array logic device (FPGA), and a corresponding bitstream file that can be directly run on the FPGA is generated, and the bitstream file is downloaded to the target hardware platform to start running. The specific technical process of implementation includes the following steps: First, the system uses the design tool provided by the FPGA manufacturer (such as Xilinx's Vivado or Intel's Quartus) to import the previously generated top-level design file. These design files define the logical structure and connection relationship inside the FPGA. The design tool will synthesize the top-level design file, and the synthesis process is to convert the high-level hardware description language (HDL) code into basic logic units and connections that the FPGA can understand. Next, the system performs layout and routing. This step specifically allocates and connects the logic units on the physical resources of the FPGA to ensure the optimization of signal transmission and the satisfaction of timing requirements. After the synthesis and layout and routing are completed, the design tool generates a bitstream file, which is a binary file that can be directly run on the FPGA and contains all the information required to configure the FPGA. Finally, the system downloads the bitstream file to the FPGA on the target hardware platform and starts running.

[0073] In terms of technical principles, step S103 utilizes the synthesis, layout and routing functions of the FPGA design tool. Synthesis is the conversion of abstract HDL code into specific logic circuits, and layout and routing is the specific placement and connection of these logic circuits on the physical resources of the FPGA. FPGA design tools use complex algorithms and optimization techniques to ensure that the generated circuits achieve the best performance, power consumption and resource utilization. The bitstream file is the configuration file of the FPGA, which contains all the configuration information that needs to be downloaded to the FPGA. By downloading the bitstream file to the FPGA, the FPGA can work according to the designer's intention and realize specific functions.

[0074] In terms of the technical problems to be solved, step S103 mainly solves the problem of how to convert the abstract design file into a specific configuration file that can be run on FPGA. The flexibility and powerful parallel computing capabilities of FPGA make it an ideal choice for complex systems, but this also increases the complexity of the design. By using FPGA design tools, the system can automatically perform design synthesis and layout and routing, reducing the workload and error rate of manual design. In addition, the generation and downloading process of the bitstream file enables designers to quickly deploy the design to the hardware platform for verification and operation, shortening the development cycle.

[0075] In terms of the technical effects achieved, through step S103, the system can efficiently convert the top-level design file into a bitstream file that can be directly run on the FPGA, and download it to the target hardware platform to start running. This process not only improves the efficiency of design and verification, but also ensures the accuracy and consistency of the design. By using FPGA design tools, the system can automatically perform synthesis and layout and routing to optimize the performance, power consumption and resource utilization of the design. The generated bitstream file can be directly downloaded to the FPGA, so that it works according to the designer's intention and quickly realizes specific functions.

[0076] For example, suppose a team is developing a system for real-time image processing. In steps S101 and S102, the team has packaged the image processing algorithm into an algorithm IP core for the FPGA and generated a top-level design file. In step S103, the team uses Xilinx's Vivado design tool to import the top-level design file. First, the design tool synthesizes the design file and converts the HDL code into basic logic units and connections. Next, the tool performs layout and routing, specifically assigns these logic units to the physical resources of the FPGA, and optimizes them to meet timing requirements. After synthesis and layout and routing are completed, the tool generates a bitstream file, which contains all the configuration information of the FPGA. Finally, the team downloads the bitstream file to the FPGA on the target hardware platform and starts the image processing system. Through these steps, the team not only speeds up the development process, but also ensures efficient operation and performance optimization of the system.

[0077] In another example, a research team is developing a sensor data fusion system for driverless cars. In steps S101 and S102, the team has packaged the data fusion algorithm into an algorithm IP core for the FPGA and generated a top-level design file. In step S103, the team uses Intel's Quartus design tool to import the top-level design file. The design tool first performs synthesis to convert the HDL code into basic logic units and connections. Then, the tool performs layout and routing, specifically assigns the logic units to the physical resources of the FPGA, and optimizes to meet the timing and performance requirements of the system. After synthesis and layout and routing are completed, the tool generates a bitstream file, which contains all the configuration information of the FPGA. Finally, the team downloads the bitstream file to the FPGA on the hardware platform of the driverless car and starts the data fusion system. Through these steps, the team not only improves the efficiency of design and verification, but also ensures the real-time performance and accuracy of the system, providing a guarantee for the safe operation of the driverless car.

[0078] In summary, step S103 uses FPGA design tools to synthesize and place and route the top-level design file, generate a bitstream file, and download it to the target hardware platform to start running. This process not only improves the efficiency of design and verification, but also ensures the efficient operation and performance optimization of the system, providing strong support for the development and deployment of complex systems.

[0079] From the above description, it can be seen that the method for implementing real-time simulation of hardware logic using FPGA provided in the embodiment of the present application can encapsulate the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, and define the input and output ports and parameter interfaces of the algorithm model in the algorithm IP core; perform comprehensive layout and routing on the top-level design file through the preset design tool of the programmable array logic device, generate a corresponding bitstream file that can be directly run on the programmable array logic device, and download the bitstream file to the target hardware platform to start running, thereby effectively improving the simulation efficiency and accuracy.

[0080] In one embodiment of the method for implementing hardware logic real-time simulation on FPGA of the present application, see Figure 2 , and can also include the following:

[0081] Step S201: constructing an algorithm model to be simulated by using a preset modeling tool, wherein the algorithm model includes elements required for the simulation;

[0082] Step S202: Generate the implementation code of the algorithm IP core and define the input and output port interfaces of the algorithm IP core by using a preset programmable array logic device design tool to obtain the algorithm IP core.

[0083] Optionally, in this embodiment, in step S201, the algorithm model to be simulated is constructed by a preset modeling tool. This algorithm model contains all the elements required for simulation to ensure that the behavior of the actual system can be accurately simulated in subsequent steps. The specific technical process of implementation includes the following steps: First, select appropriate modeling tools, which are usually designed for specific fields, such as MATLAB / Simulink for control systems and signal processing, SystemC for system-level design, etc. Then, according to the algorithm to be simulated, use the modeling tool to build the algorithm model. This process may involve disassembling the various parts of the algorithm into basic operation units, logic units and control units, and connecting these units according to the process of the algorithm. The model needs to contain all the elements required for simulation, such as input and output interfaces, parameter settings, timing control, etc. After completing the modeling, a preliminary simulation verification is usually performed to ensure the correctness and completeness of the model.

[0084] In terms of technical principles, step S201 utilizes the graphical modeling and simulation functions of modeling tools. These tools make the modeling of complex algorithms more intuitive and convenient by providing rich library functions and modules. Through the graphical interface, designers can intuitively build and adjust models, reducing the workload and error rate of coding. The simulation function allows designers to verify and debug the algorithm at the model level to ensure the correctness and performance of the model. This model-based design method improves design efficiency and accuracy, laying a solid foundation for subsequent hardware implementation.

[0085] In terms of the technical problems solved, step S201 mainly solves the problem of how to effectively build and verify the algorithm model in the early stage of design. In the design of complex systems, direct hardware implementation and verification are costly and risky. By using modeling tools, designers can verify the algorithm at an early stage and discover and solve potential problems. This not only reduces design risks, but also reduces development costs and cycles. In addition, through modeling and simulation, designers can better understand the behavior and performance of the algorithm, providing important reference and guidance for subsequent hardware implementation.

[0086] In terms of the technical effects achieved, through step S201, the system can efficiently build and verify the algorithm model, improving the efficiency of design and verification. By using modeling tools, designers can quickly build and adjust the model, perform simulation and debugging, and ensure the correctness and performance of the model. By fully verifying in the early stages of the design, the system can reduce problems in subsequent hardware implementation and improve the reliability and quality of the overall design.

[0087] For example, suppose a team is developing a filtering algorithm for image processing. In step S201, the team chooses to use MATLAB / Simulink as the modeling tool. First, the team uses the basic operation units and signal processing modules in Simulink to build a model of the filtering algorithm based on the design requirements of the filtering algorithm. The model contains input and output interfaces for receiving and outputting image data, a parameter setting module for adjusting the parameters of the filter, and a timing control module for controlling the execution of the filtering process. After completing the modeling, the team conducts preliminary simulation verification by importing test image data and observing the output results after filtering to ensure the correctness and performance of the model.

[0088] In step S202, the implementation code of the algorithm IP core is generated by a preset programmable array logic device (FPGA) design tool, and the input and output port interfaces of the algorithm IP core are defined to obtain the algorithm IP core. The specific implementation technical process includes the following steps: First, select a suitable FPGA design tool, such as Xilinx's Vivado or Intel's Quartus. These tools usually provide a rich design library and automated design process, which facilitates designers to generate efficient hardware implementation code. Then, the system uses the FPGA design tool to generate the implementation code of the algorithm IP core based on the algorithm model constructed in step S201. This process may include converting various parts of the algorithm into hardware description language (HDL) code, such as VHDL or Verilog. The generated implementation code needs to define the input and output port interfaces of the algorithm IP core to ensure that it can be correctly connected and exchange data with other modules. After the code generation is completed, a preliminary functional verification is usually performed to ensure that the generated code can correctly implement the functions of the algorithm.

[0089] In terms of technical principles, step S202 utilizes the code generation and interface definition functions of FPGA design tools. These tools make the hardware implementation of complex algorithms more efficient and reliable by providing automated design processes and optimization techniques. By converting the algorithm model into HDL code, the system can utilize the hardware resources of FPGA to achieve efficient parallel computing and real-time processing. The definition of the input and output port interface ensures that the algorithm IP core can correctly connect and communicate with other modules to achieve the overall function of the system.

[0090] In terms of the technical problems to be solved, step S202 mainly solves the problem of how to convert the abstract algorithm model into a specific hardware implementation code. The design and implementation process of FPGA is complicated, and the traditional manual coding method is not only time-consuming and labor-intensive, but also prone to errors. By using FPGA design tools, the system can automatically generate code and define interfaces, improving design efficiency and accuracy. In addition, through preliminary functional verification, the system can discover and solve potential problems at an early stage, reducing subsequent debugging and modification work.

[0091] In terms of the technical effects achieved, through step S202, the system can efficiently generate the implementation code of the algorithm IP core and define the input and output port interfaces. By using FPGA design tools, the system can automatically perform code generation and interface definition, thereby improving design efficiency and accuracy. The generated algorithm IP core can not only efficiently utilize the hardware resources of FPGA to achieve high-performance parallel computing and real-time processing, but also can correctly connect and communicate with other modules to achieve the overall function of the system.

[0092] For example, suppose a team is developing a filtering algorithm IP core for real-time image processing. In step S202, the team chooses to use Xilinx's Vivado design tool. First, the team uses Vivado to generate the HDL code of the filtering algorithm based on the filtering algorithm model built in step S201. The generated code defines the operation unit and control logic of the filtering algorithm, and includes input and output port interfaces for receiving and outputting image data. After completing the code generation, the team conducts preliminary functional verification by importing test image data and observing the output results after filtering to ensure that the generated code can correctly implement the function of the filtering algorithm.

[0093] In summary, through steps S201 and S202, the system can efficiently build and verify the algorithm model and generate the implementation code and interface definition of the algorithm IP core. This process not only improves the efficiency of design and verification, but also ensures the efficient operation and performance optimization of the system, providing strong support for the development and deployment of complex systems.

[0094] In one embodiment of the method for implementing hardware logic real-time simulation on FPGA of the present application, see Figure 3 , and can also include the following:

[0095] Step S301: defining at least one of the port name, port direction, port data type and port bit width of the algorithm model in the algorithm IP core;

[0096] Step S302: defining at least one of a parameter name, a parameter data type and a parameter initial value of the algorithm model in the algorithm IP core.

[0097] Optionally, in this embodiment, in step S301, the system needs to define at least one of the port name, port direction, port data type and port bit width of the algorithm model in the algorithm IP core. The purpose of this step is to clarify the interface specification of the algorithm IP core to ensure that it can correctly communicate and exchange data with other modules. The specific technical process of implementation includes the following steps: First, the system determines the port information that needs to be defined in the IP core according to the requirements of the algorithm model. The port name is used to identify the function of each port, the port direction (input or output) is used to indicate the direction of the data flow, the port data type (such as integer, floating point, etc.) is used to define the data type processed by the port, and the port bit width is used to specify the number of bits of the data. Then, the designer adds corresponding port definitions to the algorithm IP core in the FPGA design tool based on this information. Usually, this process can be completed through a graphical interface or by directly editing the hardware description language (HDL) code. After completing the port definition, the system needs to perform preliminary verification to ensure that the port definition is correct and consistent with the design requirements.

[0098] In terms of technical principles, step S301 utilizes the interface definition function of FPGA design tools. These tools provide a convenient way to define and manage the port information of the IP core. Through a graphical interface or HDL code, designers can intuitively add and configure ports. The definition of port name, direction, data type, and bit width ensures that the interface specification of the IP core is clear and can correctly exchange data with other modules. This modular design method improves the maintainability and scalability of the system design, and facilitates subsequent debugging and optimization.

[0099] In terms of the technical problems solved, step S301 mainly solves the interface definition problem between the algorithm IP core and the external system. In complex system design, data exchange and communication between different modules are crucial. By clearly defining the port information of the IP core, the system can ensure the consistency and correctness of the interfaces between modules, avoiding design errors and communication failures caused by interface mismatch. In addition, by using FPGA design tools, the port definition process becomes more intuitive and efficient, reducing the workload and error rate of manual coding.

[0100] In terms of the technical effects achieved, through step S301, the system can clarify the interface specifications of the algorithm IP core to ensure that it can correctly communicate and exchange data with other modules. By using FPGA design tools, designers can easily define and manage the port information of the IP core, improving design efficiency and accuracy. Clear interface definitions not only facilitate system debugging and optimization, but also improve the maintainability and scalability of system design, facilitating subsequent development and upgrades.

[0101] For example, suppose a team is developing an algorithm IP core for signal processing. In step S301, the team chooses to use Intel's Quartus design tool. First, based on the requirements of the signal processing algorithm, the team determines the port information that needs to be defined in the IP core, including input signal ports, output signal ports, and control signal ports. The input signal port is used to receive external signal data, the output signal port is used to output processed signal data, and the control signal port is used to receive control commands. Next, the team adds the corresponding port definition to the algorithm IP core through the graphical interface in Quartus, specifying the port name, direction, data type, and bit width. After completing the port definition, the team performs preliminary verification to ensure that the port definition is correct and consistent with the design requirements.

[0102] In step S302, the system needs to define at least one of the parameter name, parameter data type and parameter initial value of the algorithm model in the algorithm IP core. The purpose of this step is to clarify the parameter configuration of the algorithm IP core to ensure that it can correctly execute the algorithm according to the design requirements. The specific technical process of implementation includes the following steps: First, the system determines the parameter information that needs to be defined in the IP core according to the requirements of the algorithm model. The parameter name is used to identify the function of each parameter, the parameter data type (such as integer, floating point number, etc.) is used to define the data type of the parameter, and the parameter initial value is used to set the default value of the parameter. Then, the designer adds corresponding parameter definitions to the algorithm IP core based on this information in the FPGA design tool. Usually, this process can be completed through a graphical interface or by directly editing the HDL code. After completing the parameter definition, the system needs to perform preliminary verification to ensure that the parameter definition is correct and consistent with the design requirements.

[0103] In terms of technical principles, step S302 utilizes the parameter configuration function of FPGA design tools. These tools provide a convenient way to define and manage the parameter information of the IP core. Through a graphical interface or HDL code, designers can intuitively add and configure parameters. The definition of parameter name, data type, and initial value ensures that the parameter configuration of the IP core is clear and the algorithm can be correctly executed according to the design requirements. This modular design method improves the flexibility and configurability of the system design, and facilitates subsequent debugging and optimization.

[0104] In terms of the technical problems solved, step S302 mainly solves the parameter configuration problem of the algorithm IP core. In complex system design, the execution of the algorithm usually depends on the configuration of multiple parameters. By clearly defining the parameter information of the IP core, the system can ensure that the execution of the algorithm meets the design requirements and avoid algorithm failure and performance degradation due to parameter configuration errors. In addition, by using FPGA design tools, the parameter definition process becomes more intuitive and efficient, reducing the workload and error rate of manual coding.

[0105] In terms of the technical effects achieved, through step S302, the system can clearly define the parameter configuration of the algorithm IP core to ensure that it can correctly execute the algorithm according to the design requirements. By using FPGA design tools, designers can easily define and manage the parameter information of the IP core, improving design efficiency and accuracy. Clear parameter configuration not only facilitates system debugging and optimization, but also improves the flexibility and configurability of system design, facilitating subsequent development and upgrades.

[0106] For example, suppose a team is developing a filtering algorithm IP core for image processing. In step S302, the team chooses to use Xilinx's Vivado design tool. First, based on the requirements of the filtering algorithm, the team determines the parameter information that needs to be defined in the IP core, including the type of filter, the order of the filter, and the coefficients of the filter. The type of filter is used to select different filtering algorithms, the order of the filter is used to set the order of the filter, and the coefficients of the filter are used to set the specific parameters of the filter. Next, the team adds the corresponding parameter definition to the algorithm IP core through the graphical interface in Vivado, specifying the parameter name, data type, and initial value. After completing the parameter definition, the team performs preliminary verification to ensure that the parameter definition is correct and consistent with the design requirements.

[0107] In short, through steps S301 and S302, the system can clarify the interface specifications and parameter configuration of the algorithm IP core, ensure that it can correctly communicate and exchange data with other modules, and correctly execute the algorithm according to the design requirements. This process not only improves the efficiency of design and verification, but also ensures the efficient operation and performance optimization of the system, providing strong support for the development and deployment of complex systems.

[0108] In one embodiment of the method for implementing hardware logic real-time simulation on FPGA of the present application, see Figure 4 , and can also include the following:

[0109] Step S401: extracting detailed information of the input and output ports and parameter interfaces from the description file of the constructed algorithm IP core, and acquiring resource description information of the target programmable array logic device hardware platform;

[0110] Step S402: using a model-driven approach to establish automatic mapping between the input / output ports and parameter interfaces and the hardware resources, wherein the input / output ports and parameter interfaces of the input / output port type are mapped to corresponding hardware physical channels.

[0111] Optionally, in this embodiment, in step S401, the system first needs to extract detailed information of input and output ports and parameter interfaces from the description file of the constructed algorithm IP core, and obtain resource description information of the target programmable logic device hardware platform. The specific technical process of implementation includes the following steps: First, the system extracts detailed information of each input and output port and parameter interface by parsing the description file of the algorithm IP core. This information usually includes port name, direction, data type, bit width, parameter name, parameter type and initial value, etc. Next, the system needs to obtain resource description information of the target hardware platform, which includes available resources of the hardware platform, such as logic units, storage units, I / O ports, etc.

[0112] In terms of technical principles, step S401 utilizes the relevant technologies of description file parsing and hardware resource management. Description files usually adopt standardized formats (such as XML, JSON, etc.) to facilitate automatic parsing by the program. By parsing the description file, the system can extract the detailed interface information and parameter information of the algorithm IP core. At the same time, the resource description information of the hardware platform is usually obtained through the development tools or API interfaces provided by the manufacturer to ensure that the system can accurately understand the resource distribution and availability of the hardware platform.

[0113] In terms of the technical problems solved, step S401 mainly solves the information docking problem between the algorithm IP core and the hardware platform. In complex hardware design, the interface and parameter configuration of the algorithm IP core need to match the resource situation of the specific hardware platform. By extracting detailed information from the description file and obtaining the resource description of the hardware platform, the system can ensure that the design of the algorithm IP core conforms to the actual situation of the hardware platform, avoiding design failures or performance problems caused by resource mismatch. In addition, through automated description file parsing and resource acquisition, the complexity and error rate of manual operations are reduced, and the design efficiency and accuracy are improved.

[0114] In terms of the technical effects achieved, through step S401, the system can accurately extract the detailed interface information and parameter information of the algorithm IP core, and obtain the resource description information of the target hardware platform. This process ensures the design matching between the algorithm IP core and the hardware platform, and improves the correctness and reliability of the system design. Clear interface and resource information not only facilitates subsequent mapping and optimization, but also provides a basis for efficient operation and performance optimization of the system.

[0115] For example, suppose a team is developing an algorithm IP core for audio processing. In step S401, the team first extracts detailed information about each input and output port and parameter interface by parsing the description file of the IP core, including audio input port, audio output port, control signal port, and filter parameters. Then, the team uses the development tools provided by the manufacturer to obtain resource description information of the target FPGA hardware platform, including available logic units, storage units, and I / O ports. Through this step, the team can fully understand the interface requirements of the algorithm IP core and the resource situation of the hardware platform, laying the foundation for subsequent mapping and optimization.

[0116] In step S402, the system uses a model-driven method to establish automatic mapping between input and output ports and parameter interfaces and hardware resources. The specific technical process includes the following steps: First, the system establishes a mapping relationship between input and output ports and parameter interfaces and hardware resources based on the detailed interface information and hardware resource description information extracted in step S401. The model-driven method usually maps the input and output ports and parameter interfaces of the algorithm IP core to the corresponding hardware physical channels by defining a set of mapping rules. These mapping rules can be determined based on factors such as resource distribution, performance requirements and design constraints of the hardware platform. Then, the system automatically generates corresponding hardware configuration files or HDL codes based on these mapping rules to complete the mapping of input and output ports and parameter interfaces.

[0117] In terms of technical principles, step S402 utilizes model-driven design (MDD) and automated mapping technology. The model-driven design method realizes the automatic conversion between high-level design and low-level implementation by defining a set of abstract models and mapping rules. By mapping the interface information and hardware resource description information of the algorithm IP core to the specific hardware physical channel, the system can ensure the correct implementation of the design on the hardware platform. Automated mapping technology realizes the automatic application of mapping rules and the automation of the mapping process in a programmatic way, reducing the complexity and error rate of manual operations.

[0118] In terms of the technical problems solved, step S402 mainly solves the problem of automatic mapping between the algorithm IP core interface and the hardware resources. In complex hardware design, manual mapping of interfaces and resources is not only time-consuming and labor-intensive, but also prone to errors. By adopting the model-driven method and automated mapping technology, the system can quickly and accurately complete the mapping process to ensure that the design meets the actual situation and performance requirements of the hardware platform. In addition, the automated mapping technology also improves the flexibility and scalability of the design, facilitating subsequent optimization and adjustment.

[0119] In terms of the technical effects achieved, through step S402, the system can quickly and accurately establish the mapping relationship between the input and output ports and parameter interfaces and the hardware resources, ensuring the correct implementation of the algorithm IP core on the hardware platform. Through the model-driven approach and automated mapping technology, the design process becomes more efficient and reliable, reducing the complexity and error rate of manual operations. The clear mapping relationship not only facilitates the debugging and optimization of the system, but also improves the flexibility and scalability of the design, facilitating subsequent development and upgrades.

[0120] For example, suppose a team is developing an algorithm IP core for image processing. In step S402, the team first defines a set of mapping rules based on the detailed interface information and hardware resource description information extracted in step S401 to map the image input port, image output port, control signal port, and filter parameters of the algorithm IP core to the corresponding physical channels on the FPGA hardware platform. Then, the team uses the automated mapping tool to automatically generate the corresponding hardware configuration files or HDL codes based on these mapping rules to complete the mapping of input and output ports and parameter interfaces. Through this step, the team can ensure the correct implementation of the algorithm IP core on the hardware platform, which provides a guarantee for the efficient operation and performance optimization of the system.

[0121] In short, through steps S401 and S402, the system can accurately extract and map the interface and parameter information of the algorithm IP core to specific hardware resources, ensuring that the design meets the actual situation and performance requirements of the hardware platform. This process not only improves the design efficiency and reliability, but also provides strong support for the efficient operation and performance optimization of the system, laying a solid foundation for the development and deployment of complex systems.

[0122] In one embodiment of the method for implementing hardware logic real-time simulation on FPGA of the present application, see Figure 5 , and can also include the following:

[0123] Step S501: generating a configurable description of a corresponding programmable array logic device project according to a mapping relationship between the input and output ports and the parameter interface and the hardware resources;

[0124] Step S502: Obtain a corresponding configurable top-level design file through a preset design tool of a programmable array logic device.

[0125] Optionally, in this embodiment, in step S501, the system generates a configurable description of the corresponding programmable array logic device project based on the mapping relationship between the input and output ports and parameter interfaces and the hardware resources. The specific technical process of implementation includes the following steps: First, the system obtains the mapping relationship between the input and output ports and parameter interfaces and the hardware resources established in the previous steps. These mapping relationships describe in detail how each interface is mapped to the specific location on the hardware resources. Then, the system uses these mapping relationships to generate a configurable description file for the programmable array logic device project. This description file is usually recorded in a standard format (such as HDL, VHDL, Verilog, etc.) and contains the configuration details of all ports and parameters. The description file must not only accurately define the mapping relationship between the interface and the resources, but also include timing constraints, performance requirements and other hardware configuration parameters to ensure that the entire design can run normally on the target hardware platform.

[0126] In terms of technical principles, step S501 utilizes hardware description language (HDL) and automated generation technology. Hardware description language is a special language used to describe digital logic circuits and systems, which can accurately describe the structure, behavior and connection of the circuit. Automated generation technology converts the mapping relationship between input and output ports and parameter interfaces into configuration description files of programmable array logic devices through a programmatic method. These files usually include multi-level design information, from top-level modules to bottom-level units, to ensure the integrity and consistency of the entire design.

[0127] In terms of the technical problems solved, step S501 mainly solves the conversion problem between the algorithm IP core design and the actual configuration of the hardware platform. Manually converting complex mapping relationships into hardware configuration description files is not only time-consuming and labor-intensive, but also prone to errors. Through automated generation technology, the system can quickly and accurately generate configuration description files to ensure that the design matches the actual resource configuration of the hardware platform, avoiding design failures or performance problems caused by configuration errors. In addition, automated generation technology also improves the flexibility and scalability of the design, facilitating subsequent optimization and adjustment.

[0128] In terms of the technical effects achieved, through step S501, the system can generate an accurate and complete configurable description file to ensure the correct implementation of the algorithm IP core on the hardware platform. This process not only improves the design efficiency and reliability, but also provides a basis for the efficient operation and performance optimization of the system. A clear configuration description file not only facilitates the debugging and verification of the system, but also provides strong support for subsequent hardware configuration and resource management.

[0129] For example, suppose a team is developing an algorithm IP core for video processing. In step S501, the team first obtains the mapping relationship between the input and output ports and parameter interfaces established in the previous step and the hardware resources. These relationships describe in detail how the video input port, video output port, control signal port, and filter parameters are mapped to specific locations on the FPGA hardware platform. Then, the team uses automated generation tools to generate configurable description files for the programmable array logic device project based on these mapping relationships. These files contain the configuration details of all ports and parameters to ensure that the design can run normally on the target hardware platform.

[0130] In step S502, the system obtains the corresponding configurable top-level design file through the preset design tool of the programmable array logic device. The specific technical process of implementation includes the following steps: First, the system imports the configurable description file generated in step S501 into the preset design tool of the programmable array logic device. These design tools are usually provided by hardware platform manufacturers and have powerful design, simulation and verification functions. Then, the system uses these tools to generate the corresponding configurable top-level design file based on the description file. The top-level design file is the core of the entire design and contains the connection relationship, timing constraints and performance requirements of all modules and units. These files must not only ensure the correct implementation of the design on the hardware platform, but also meet specific performance and functional requirements.

[0131] In terms of technical principles, step S502 utilizes hardware design tools and automated configuration technology. Hardware design tools are special software used to design, simulate and verify digital logic circuits, providing comprehensive design functions and powerful simulation capabilities. Automated configuration technology converts configurable description files into top-level design files through a programmatic method to ensure the correctness and consistency of the design. These files usually include the overall structure of the design, the connection relationship of the modules and the timing constraints to ensure that the design can meet the performance and functional requirements of the hardware platform.

[0132] In terms of the technical problems solved, step S502 mainly solves the conversion problem between the configurable description file and the top-level design file. Manually converting complex description files into top-level design files is not only time-consuming and labor-intensive, but also prone to errors. Through automated configuration technology, the system can quickly and accurately generate top-level design files to ensure that the design matches the actual configuration of the hardware platform and avoid design failures or performance problems caused by configuration errors. In addition, automated configuration technology also improves the flexibility and scalability of the design, facilitating subsequent optimization and adjustment.

[0133] In terms of the technical effects achieved, through step S502, the system can generate an accurate, complete and configurable top-level design file to ensure the correct implementation of the algorithm IP core on the hardware platform. This process not only improves the design efficiency and reliability, but also provides a basis for the efficient operation and performance optimization of the system. Clear top-level design files not only facilitate system debugging and verification, but also provide strong support for subsequent hardware configuration and resource management.

[0134] For example, suppose a team is developing an algorithm IP core for image recognition. In step S502, the team first imports the configurable description file generated in step S501 into the preset design tools of the FPGA hardware platform. These tools provide comprehensive design functions and powerful simulation capabilities, and can generate corresponding configurable top-level design files based on the description files. Then, the team uses these tools to generate top-level design files based on the description files to ensure that the design can run normally on the hardware platform and meet specific performance and functional requirements.

[0135] In summary, through steps S501 and S502, the system can accurately generate and configure the hardware description file of the algorithm IP core, ensuring that the design meets the actual resource configuration and performance requirements of the hardware platform. This process not only improves the design efficiency and reliability, but also provides strong support for the efficient operation and performance optimization of the system, laying a solid foundation for the development and deployment of complex systems.

[0136] In one embodiment of the method for implementing hardware logic real-time simulation on FPGA of the present application, see Figure 6 , and can also include the following:

[0137] Step S601: importing the top-level design file of the programmable array logic device into a preset design tool and converting it into a corresponding logic netlist;

[0138] Step S602: Performing a layout and routing process operation through the logic netlist to obtain a corresponding bitstream file.

[0139] Optionally, in this embodiment, in step S601, the system first imports the top-level design file of the programmable array logic device into a preset design tool and converts it into a corresponding logic netlist. The specific technical process of implementation includes the following steps: First, the designer uses the hardware development environment to load the top-level design file into the preset design tool. The preset design tool is usually provided by the FPGA manufacturer and has powerful design and conversion functions. After loading the top-level design file, the tool will parse the file and generate a corresponding logic netlist based on the description in the design file. The logic netlist is an intermediate representation that describes in detail the basic units such as each logic gate, trigger, register, etc. in the design and their connection relationships. The process of generating the logic netlist needs to ensure that all logic units and connection relationships in the design are accurately reflected so that subsequent layout and routing operations can proceed smoothly.

[0140] In terms of technical principles, step S601 utilizes hardware description language parsing and logic synthesis technology. Hardware description language parsing technology extracts the logic units and connection relationships in the design by parsing the syntax and semantics of the top-level design file. Logic synthesis technology ensures the correct implementation of the design on the hardware platform by converting these logic units and connection relationships into a logic netlist that the FPGA can understand. During this process, the preset design tool usually performs a variety of optimization operations, such as logic optimization, timing optimization, etc., to improve the performance and resource utilization of the design.

[0141] In terms of the technical problems solved, step S601 mainly solves the conversion problem between the top-level design file and the logic netlist. The top-level design file usually describes the structure and behavior of the design at a high level of abstraction, while the logic netlist is a low-level concrete representation that directly corresponds to the hardware implementation. Converting a high-level design into a low-level logic netlist is a complex process, and it is necessary to ensure that all logic units and connection relationships in the design can be correctly mapped to the hardware platform. Through automated parsing and synthesis technology, the system can quickly and accurately complete this conversion process, avoiding the complexity and error rate of manual operations.

[0142] In terms of the technical effects achieved, through step S601, the system can generate an accurate and complete logic netlist to ensure the correct implementation of the top-level design file on the hardware platform. The logic netlist not only describes in detail the various logic units and connection relationships in the design, but also provides a basis for subsequent layout and routing operations. Through automated parsing and synthesis technology, the design efficiency and reliability are improved, ensuring that the design can meet the performance and resource requirements of the hardware platform.

[0143] For example, suppose a team is developing an algorithm IP core for signal processing. In step S601, the team imports the top-level design file into the preset design tool of the FPGA hardware platform. The tool first parses the top-level design file to extract the logic units and connection relationships in the design. Then, the tool uses logic synthesis technology to convert these logic units and connection relationships into a logic netlist. The logic netlist describes in detail the various modules of the signal processing algorithm and their connection relationships, laying the foundation for subsequent layout and routing operations.

[0144] In step S602, the system performs layout and routing process operations through the logic netlist to obtain the corresponding bitstream file. The specific technical process includes the following steps: First, the designer uses the layout and routing function in the preset design tool to layout and route the logic netlist. Layout and routing is a key step in FPGA design, which determines the specific location and connection method of the logic unit on the hardware resources. The layout and routing operation needs to consider many factors, such as timing constraints, resource distribution, power consumption optimization, etc., to ensure that the design can run efficiently on the hardware platform. After completing the layout and routing, the tool will generate the corresponding bitstream file. The bitstream file is the final file of the FPGA configuration, which contains the location and connection information of all logic units and can be directly used for FPGA configuration and programming.

[0145] In terms of technical principles, step S602 utilizes the layout and routing algorithm and bitstream generation technology. The layout and routing algorithm optimizes and adjusts the logic netlist, allocates the logic units to the hardware resources, and ensures that the timing and performance requirements of the design are met. The bitstream generation technology converts the layout and routing results into a bitstream file that the FPGA can recognize, ensuring that the design can be correctly loaded onto the hardware platform for operation. The entire process usually combines multiple optimization techniques, such as timing analysis, power optimization, etc., to improve the overall performance and resource utilization of the design.

[0146] In terms of the technical problems solved, step S602 mainly solves the problem of converting the logic netlist to the bitstream file. The logic netlist is the intermediate representation of the design, while the bitstream file is the final file of the FPGA configuration. Converting a complex logic netlist into an efficient bitstream file is a complex process, which requires ensuring the correct implementation and efficient operation of the design on the hardware platform. Through automated placement and routing algorithms and bitstream generation technology, the system can quickly and accurately complete this conversion process, avoiding the complexity and error rate of manual operations.

[0147] In terms of the technical effects achieved, through step S602, the system can generate an accurate and optimized bitstream file to ensure the correct implementation and efficient operation of the design on the FPGA hardware platform. The bitstream file not only contains all the logic units and connection information of the design, but also undergoes a variety of optimization operations to ensure that the design can meet the requirements of timing, performance, power consumption, etc. Through automated placement and routing and bitstream generation technology, the design efficiency and reliability are improved, providing a basis for the efficient operation and performance optimization of the system.

[0148] For example, suppose a team is developing an algorithm IP core for encryption and decryption. In step S602, the team first uses the layout and routing function in the preset design tool to layout and route the logic netlist. The tool optimizes and adjusts the logic units according to the timing constraints and resource distribution to ensure that the design can run efficiently. After completing the layout and routing, the tool generates the corresponding bitstream file. The bitstream file contains the location and connection information of all the logic units of the encryption and decryption algorithm, which can be directly used for the configuration and programming of the FPGA to ensure the correct implementation and efficient operation of the algorithm on the hardware platform.

[0149] In summary, through steps S601 and S602, the system can accurately generate and configure the logic netlist and bitstream file of the algorithm IP core, ensuring that the design meets the actual resource configuration and performance requirements of the hardware platform. This process not only improves design efficiency and reliability, but also provides strong support for the efficient operation and performance optimization of the system, laying a solid foundation for the development and deployment of complex systems.

[0150] In one embodiment of the method for implementing hardware logic real-time simulation on FPGA of the present application, see Figure 7 , and can also include the following:

[0151] Step S701: transmitting the bitstream file to a hardware platform of a corresponding target programmable array logic device;

[0152] Step S702: Start the execution of the bitstream file on the hardware platform of the target programmable array logic device.

[0153] Optionally, in this embodiment, in step S701, the system first transfers the generated bitstream file to the hardware platform of the corresponding target programmable array logic device (FPGA). The specific technical process of implementation includes the following steps: First, the designer stores the bitstream file on a computer or server, ready to be transferred to the FPGA hardware platform. During the transmission process, the system usually connects to the FPGA hardware platform through a dedicated programming interface or communication protocol (such as JTAG, USB, Ethernet, etc.). These interfaces and protocols ensure that the bitstream file can be reliably and quickly transferred to the hardware platform. After the transmission is completed, the system verifies whether the bitstream file is correctly loaded into the configuration memory of the FPGA to ensure the integrity and correctness of the file.

[0154] In terms of technical principles, step S701 utilizes data transmission and verification technology. Data transmission technology ensures that the bitstream file can be transmitted efficiently and reliably through a dedicated interface or communication protocol between the computer and the FPGA hardware platform. Verification technology verifies the bitstream file to ensure that the file is not damaged or lost during the transmission process. During this process, the system usually performs multiple verification operations, such as CRC verification and data comparison, to ensure the integrity and correctness of the bitstream file.

[0155] In terms of the technical problems solved, step S701 mainly solves the problem of transmitting the bitstream file from the design environment to the hardware platform. The bitstream file is the final file of the FPGA configuration, which contains all the logic units and connection information. Reliably transmitting the bitstream file to the hardware platform is a key step in the FPGA configuration process, and it is necessary to ensure that the file is not damaged or lost during the transmission process. Through a dedicated transmission interface and verification technology, the system can quickly and accurately complete this transmission process to ensure that the bitstream file is correctly loaded into the configuration memory of the FPGA.

[0156] In terms of the technical effects achieved, through step S701, the system can reliably transfer the bitstream file to the FPGA hardware platform to ensure the integrity and correctness of the file. The correct loading of the bitstream file provides a basis for the configuration and programming of the FPGA, ensuring that the design can be correctly implemented and run on the hardware platform. Through efficient and reliable transmission and verification technology, the efficiency and reliability of the configuration process are improved, providing strong support for the efficient operation and performance optimization of the system.

[0157] For example, suppose a team is developing an algorithm IP core for data encryption. In step S701, the team stores the generated bitstream file on the computer and prepares to transfer it to the FPGA hardware platform. The team connects the computer to the FPGA hardware platform through the JTAG interface and uses a dedicated programming tool to transfer the bitstream file to the FPGA's configuration memory. During the transmission process, the system will perform a CRC check to ensure that the bitstream file is not damaged or lost. After the transmission is completed, the system will verify whether the bitstream file is correctly loaded into the FPGA's configuration memory to ensure the integrity and correctness of the file.

[0158] In step S702, the system starts the execution of the bitstream file on the hardware platform of the target programmable array logic device. The specific technical process includes the following steps: First, the designer starts the loading process of the bitstream file through the control interface or programming tool of the FPGA. During the loading process, the FPGA will write the configuration data in the bitstream file into its internal configuration memory. The data in the configuration memory determines the specific implementation of the internal logic units and connection relationships of the FPGA. After the loading is completed, the FPGA will initialize its internal logic units according to the configuration data and prepare to execute the logic functions in the design. Finally, the system will start the operation of the FPGA, execute the logic design in the bitstream file, and complete the various functions and operations in the design.

[0159] In terms of technical principles, step S702 utilizes FPGA configuration and initialization technology. FPGA configuration technology determines the internal logic units and connection relationships of the FPGA by writing the configuration data in the bitstream file into the configuration memory of the FPGA. Initialization technology initializes the internal logic units of the FPGA according to the configuration data to prepare to execute the logical functions in the design. During this process, the system usually performs a variety of initialization and verification operations, such as configuration verification, timing initialization, etc., to ensure that the FPGA can correctly load and execute the logic design in the bitstream file.

[0160] In terms of the technical problems solved, step S702 mainly solves the problem of loading and executing the bitstream file on the FPGA hardware platform. The bitstream file contains all the logical units and connection information in the design. Correctly loading and executing the bitstream file is a key step in the FPGA configuration process. Through automated configuration and initialization technology, the system can quickly and accurately complete this loading and execution process, ensuring that the design can be correctly implemented and run on the hardware platform.

[0161] In terms of the technical effects achieved, through step S702, the system can correctly load and execute the bitstream file on the FPGA hardware platform, ensuring that the design can run efficiently on the hardware platform. The correct loading and execution of the bitstream file provides a basis for the function realization and performance optimization of the FPGA, ensuring that the design can meet the performance and resource requirements of the hardware platform. Through efficient and reliable configuration and initialization technology, the efficiency and reliability of the configuration process are improved, providing strong support for the efficient operation and performance optimization of the system.

[0162] For example, suppose a team is developing an algorithm IP core for image processing. In step S702, the team starts the loading process of the bitstream file through the control interface of the FPGA. The FPGA writes the configuration data in the bitstream file into its internal configuration memory and initializes its internal logic units according to the configuration data. After loading and initialization, the system starts the operation of the FPGA, executes the logic design in the bitstream file, and completes the various functions and operations of the image processing algorithm. Through this process, the team can ensure the correct implementation and efficient operation of the image processing algorithm on the FPGA hardware platform.

[0163] In summary, through steps S701 and S702, the system can accurately transmit and execute the bitstream file of the algorithm IP core, ensuring that the design meets the actual resource configuration and performance requirements of the hardware platform. This process not only improves the efficiency and reliability of the configuration process, but also provides strong support for the efficient operation and performance optimization of the system, laying a solid foundation for the development and deployment of complex systems.

[0164] In order to effectively improve the simulation efficiency and accuracy, the present application provides an embodiment of an FPGA device for implementing all or part of the method for implementing hardware logic real-time simulation on an FPGA, see Figure 8 The device for implementing hardware logic real-time simulation by FPGA specifically includes the following contents:

[0165] A package definition module 10 is used to package the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, and define the input and output ports and parameter interface of the algorithm model in the algorithm IP core;

[0166] The file design model 20 is used to obtain the hardware resource description information of the programmable array logic device, establish a mapping relationship between the input and output ports and parameter interfaces and the hardware resource description information of the programmable array logic device using a model-driven method based on the input and output ports and parameter interfaces of the algorithm IP core and the hardware resource description information of the programmable array logic device, and dynamically generate an engineering configurable top-level design file of the programmable array logic device according to the established mapping relationship;

[0167] The simulation test module 30 is used to perform comprehensive layout and routing on the top-level design file through the preset design tool of the programmable array logic device, generate a corresponding bit stream file that can be directly run on the programmable array logic device, and download the bit stream file to the target hardware platform to start running.

[0168] From the above description, it can be seen that the device for implementing real-time simulation of hardware logic using FPGA provided in the embodiment of the present application can encapsulate the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, and define the input and output ports and parameter interfaces of the algorithm model in the algorithm IP core; perform comprehensive layout and routing on the top-level design file through the preset design tool of the programmable array logic device, generate a corresponding bitstream file that can be directly run on the programmable array logic device, and download the bitstream file to the target hardware platform to start running, thereby effectively improving the simulation efficiency and accuracy.

[0169] From the hardware level, in order to effectively improve the simulation efficiency and accuracy, the present application provides an embodiment of an electronic device for implementing all or part of the content of the method for implementing hardware logic real-time simulation using FPGA, and the electronic device specifically includes the following content:

[0170] Processor, memory, communication interface and bus; wherein the processor, memory and communication interface communicate with each other through the bus; the communication interface is used to realize information transmission between the device for implementing hardware logic real-time simulation by FPGA and related equipment such as core business system, user terminal and related database; the logic controller can be a desktop computer, tablet computer and mobile terminal, etc., but the present embodiment is not limited thereto. In the present embodiment, the logic controller can be implemented with reference to the embodiment of the method for implementing hardware logic real-time simulation by FPGA and the embodiment of the device for implementing hardware logic real-time simulation by FPGA in the embodiment, and the contents thereof are incorporated herein, and the repeated parts are not repeated.

[0171] It is understandable that the user terminal may include a smart phone, a tablet electronic device, a network set-top box, a portable computer, a desktop computer, a personal digital assistant (PDA), a vehicle-mounted device, a smart wearable device, etc. Among them, the smart wearable device may include smart glasses, a smart watch, a smart bracelet, etc.

[0172] In practical applications, part of the method for implementing hardware logic real-time simulation by FPGA can be executed on the electronic device side as described above, or all operations can be completed in the client device. The selection can be made based on the processing capability of the client device and the limitations of the user's usage scenario. This application does not limit this. If all operations are completed in the client device, the client device may also include a processor.

[0173] The client device may have a communication module (i.e., a communication unit) that can communicate with a remote server to achieve data transmission with the server. The server may include a server on the task scheduling center side, and other implementation scenarios may also include a server on an intermediate platform, such as a server on a third-party server platform that has a communication link with the task scheduling center server. The server may include a single computer device, or a server cluster consisting of multiple servers, or a server structure of a distributed device.

[0174] Fig. 9 FIG. 9 is a schematic block diagram of the system structure of the electronic device 9600 according to an embodiment of the present application. Fig. 9 As shown, the electronic device 9600 may include a central processor 9100 and a memory 9140; the memory 9140 is coupled to the central processor 9100. It is worth noting that Fig. 9 is exemplary; other types of structures may also be used to supplement or replace this structure to implement telecommunication functions or other functions.

[0175] In one embodiment, the method function of implementing hardware logic real-time simulation by FPGA can be integrated into the central processing unit 9100. The central processing unit 9100 can be configured to perform the following control:

[0176] Step S101: encapsulating the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, and defining the input and output ports and parameter interface of the algorithm model in the algorithm IP core;

[0177] Step S102: Acquire the hardware resource description information of the programmable array logic device, establish a mapping relationship between the input / output port and parameter interface and the hardware resource description information based on the input / output port and parameter interface of the algorithm IP core and the hardware resource description information of the programmable array logic device by using a model-driven method, and dynamically generate an engineering configurable top-level design file of the programmable array logic device according to the established mapping relationship;

[0178] Step S103: Perform comprehensive layout and routing on the top-level design file through the preset design tool of the programmable array logic device, generate a corresponding bitstream file that can be directly run on the programmable array logic device, and download the bitstream file to the target hardware platform to start running.

[0179] From the above description, it can be seen that the electronic device provided in the embodiment of the present application encapsulates the algorithm model to be simulated into a reusable algorithm IP core of a programmable array logic device, and defines the input and output ports and parameter interfaces of the algorithm model in the algorithm IP core; uses the preset design tool of the programmable array logic device to comprehensively layout and route the top-level design file, generates a corresponding bitstream file that can be directly run on the programmable array logic device, and downloads the bitstream file to the target hardware platform to start running, thereby effectively improving the simulation efficiency and accuracy.

[0180] In another embodiment, the device for implementing hardware logic real-time simulation by FPGA can be configured separately from the central processing unit 9100. For example, the device for implementing hardware logic real-time simulation by FPGA can be configured as a chip connected to the central processing unit 9100, and the method function of implementing hardware logic real-time simulation by FPGA can be realized through the control of the central processing unit.

[0181] like Fig. 9 As shown, the electronic device 9600 may also include: a communication module 9110, an input unit 9120, an audio processor 9130, a display 9160, and a power supply 9170. It is worth noting that the electronic device 9600 does not necessarily have to include Fig. 9 In addition, the electronic device 9600 may also include Fig. 9 For components not shown, reference may be made to the prior art.

[0182] like Fig. 9 As shown, the central processing unit 9100 is sometimes also referred to as a controller or an operation control, and may include a microprocessor or other processor device and / or logic device, which receives input and controls the operation of various components of the electronic device 9600.

[0183] The memory 9140 may be, for example, one or more of a cache, a flash memory, a hard drive, a removable medium, a volatile memory, a non-volatile memory or other suitable devices. The above-mentioned information related to the failure may be stored, and a program for executing the relevant information may also be stored. The CPU 9100 may execute the program stored in the memory 9140 to implement information storage or processing, etc.

[0184] The input unit 9120 provides input to the central processing unit 9100. The input unit 9120 is, for example, a key or a touch input device. The power supply 9170 is used to provide power to the electronic device 9600. The display 9160 is used to display display objects such as images and texts. The display may be, for example, an LCD display, but is not limited thereto.

[0185] The memory 9140 may be a solid-state memory, such as a read-only memory (ROM), a random access memory (RAM), a SIM card, etc. It may also be a memory that saves information even when the power is off, can be selectively erased, and is provided with more data, examples of which are sometimes referred to as EPROMs, etc. The memory 9140 may also be some other type of device. The memory 9140 includes a buffer memory 9141 (sometimes referred to as a buffer). The memory 9140 may include an application / function storage unit 9142, which is used to store application programs and function programs or processes for executing the operation of the electronic device 9600 through the central processor 9100.

[0186] The memory 9140 may also include a data storage unit 9143 for storing data, such as contacts, digital data, pictures, sounds, and / or any other data used by the electronic device. The driver storage unit 9144 of the memory 9140 may include various drivers for communication functions of the electronic device and / or for executing other functions of the electronic device (such as messaging applications, address book applications, etc.).

[0187] The communication module 9110 is a transmitter / receiver that sends and receives signals via the antenna 9111. The communication module 9110 (transmitter / receiver) is coupled to the central processor 9100 to provide input signals and receive output signals, which may be the same as the case of a conventional mobile communication terminal.

[0188] Based on different communication technologies, multiple communication modules 9110 may be provided in the same electronic device, such as a cellular network module, a Bluetooth module and / or a wireless LAN module. The communication module 9110 (transmitter / receiver) is also coupled to a speaker 9131 and a microphone 9132 via an audio processor 9130 to provide an audio output via the speaker 9131 and receive an audio input from the microphone 9132, thereby realizing a common telecommunication function. The audio processor 9130 may include any suitable buffer, decoder, amplifier, etc. In addition, the audio processor 9130 is also coupled to the central processor 9100, so that recording can be performed on the local machine through the microphone 9132, and the sound stored on the local machine can be played through the speaker 9131.

[0189] The embodiments of the present application also provide a computer-readable storage medium capable of implementing all the steps in the method for implementing real-time hardware logic simulation by an FPGA of a server or client in the above embodiments. The computer-readable storage medium stores a computer program. When the computer program is executed by a processor, all the steps in the method for implementing real-time hardware logic simulation by an FPGA of a server or client in the above embodiments are implemented. For example, when the processor executes the computer program, the following steps are implemented:

[0190] Step S101: encapsulating the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, and defining the input and output ports and parameter interface of the algorithm model in the algorithm IP core;

[0191] Step S102: Acquire the hardware resource description information of the programmable array logic device, establish a mapping relationship between the input / output port and parameter interface and the hardware resource description information based on the input / output port and parameter interface of the algorithm IP core and the hardware resource description information of the programmable array logic device by using a model-driven method, and dynamically generate an engineering configurable top-level design file of the programmable array logic device according to the established mapping relationship;

[0192] Step S103: Perform comprehensive layout and routing on the top-level design file through the preset design tool of the programmable array logic device, generate a corresponding bitstream file that can be directly run on the programmable array logic device, and download the bitstream file to the target hardware platform to start running.

[0193] From the above description, it can be seen that the computer-readable storage medium provided in the embodiment of the present application can effectively improve the simulation efficiency and accuracy by encapsulating the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, and defining the input and output ports and parameter interfaces of the algorithm model in the algorithm IP core; performing comprehensive layout and routing on the top-level design file through the preset design tool of the programmable array logic device, generating a corresponding bitstream file that can be directly run on the programmable array logic device, and downloading the bitstream file to the target hardware platform to start running.

[0194] The embodiments of the present application also provide a computer program product capable of implementing all the steps of the method for implementing hardware logic real-time simulation on an FPGA in the above embodiment, where the execution subject is a server or a client. When the computer program / instruction is executed by a processor, the steps of the method for implementing hardware logic real-time simulation on an FPGA are implemented. For example, the computer program / instruction implements the following steps:

[0195] Step S101: encapsulating the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, and defining the input and output ports and parameter interface of the algorithm model in the algorithm IP core;

[0196] Step S102: Acquire the hardware resource description information of the programmable array logic device, establish a mapping relationship between the input / output port and parameter interface and the hardware resource description information based on the input / output port and parameter interface of the algorithm IP core and the hardware resource description information of the programmable array logic device by using a model-driven method, and dynamically generate an engineering configurable top-level design file of the programmable array logic device according to the established mapping relationship;

[0197] Step S103: Perform comprehensive layout and routing on the top-level design file through the preset design tool of the programmable array logic device, generate a corresponding bitstream file that can be directly run on the programmable array logic device, and download the bitstream file to the target hardware platform to start running.

[0198] From the above description, it can be seen that the computer program product provided in the embodiment of the present application encapsulates the algorithm model to be simulated into a reusable algorithm IP core of a programmable array logic device, and defines the input and output ports and parameter interfaces of the algorithm model in the algorithm IP core; uses the preset design tool of the programmable array logic device to perform comprehensive layout and routing on the top-level design file, generates a corresponding bitstream file that can be directly run on the programmable array logic device, and downloads the bitstream file to the target hardware platform to start running, thereby effectively improving the simulation efficiency and accuracy.

[0199] It should be understood by those skilled in the art that embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0200] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (apparatus), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0201] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0202] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0203] The present invention uses specific embodiments to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for implementing hardware logic real-time simulation using FPGA, characterized in that: The method comprises: Encapsulating the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, and defining the input and output ports and parameter interface of the algorithm model in the algorithm IP core; Acquire the hardware resource description information of the programmable array logic device, establish a mapping relationship between the input / output port and the parameter interface and the hardware resource description information of the programmable array logic device using a model-driven method based on the input / output port and the parameter interface of the algorithm IP core and the hardware resource description information of the programmable array logic device, and dynamically generate an engineering configurable top-level design file of the programmable array logic device according to the established mapping relationship; The top-level design file is comprehensively laid out and routed through the preset design tool of the programmable array logic device, a corresponding bit stream file that can be directly run on the programmable array logic device is generated, and the bit stream file is downloaded to the target hardware platform to start running.

2. The method for implementing hardware logic real-time simulation using FPGA according to claim 1, characterized in that: The method of packaging the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device includes: Constructing an algorithm model to be simulated by using a preset modeling tool, wherein the algorithm model includes elements required for the simulation; The algorithm IP core is obtained by generating the implementation code of the algorithm IP core and defining the input and output port interfaces of the algorithm IP core through a preset programmable array logic device design tool.

3. The method for implementing hardware logic real-time simulation using FPGA according to claim 1, characterized in that: The input and output ports and parameter interfaces of the algorithm model are defined in the algorithm IP core, including: Defining at least one of the port name, port direction, port data type and port bit width of the algorithm model in the algorithm IP core; At least one of a parameter name, a parameter data type, and a parameter initial value of the algorithm model is defined in the algorithm IP core.

4. The method for implementing hardware logic real-time simulation using FPGA according to claim 1, characterized in that: The input / output ports and parameter interfaces based on the algorithm IP core and the hardware resource description information of the programmable array logic device are used to establish a mapping relationship between the input / output ports and parameter interfaces and the hardware resource description information using a model-driven method, including: Extracting detailed information of the input and output ports and parameter interfaces from the description file of the constructed algorithm IP core, and acquiring resource description information of the target programmable array logic device hardware platform; A model-driven approach is adopted to establish automatic mapping between the input / output ports and parameter interfaces and the hardware resources, wherein the input / output ports and parameter interfaces of the input / output port type are mapped to corresponding hardware physical channels.

5. The method for implementing hardware logic real-time simulation using FPGA according to claim 1, characterized in that: The dynamically generating the engineering configurable top-level design file of the programmable array logic device according to the established mapping relationship includes: Generate a configurable description of a corresponding programmable array logic device project according to a mapping relationship between the input and output ports and the parameter interface and the hardware resources; The corresponding configurable top-level design file is obtained through a preset design tool of the programmable array logic device.

6. The method for implementing hardware logic real-time simulation using FPGA according to claim 1, characterized in that: The method of performing comprehensive layout and routing on the top-level design file by using a preset design tool of the programmable array logic device to generate a corresponding bitstream file that can be directly run on the programmable array logic device includes: Importing the top-level design file of the programmable array logic device into a preset design tool and converting it into a corresponding logic netlist; The layout and routing process operation is performed through the logic netlist to obtain a corresponding bit stream file.

7. The method for implementing hardware logic real-time simulation using FPGA according to claim 1, characterized in that: The step of downloading the bitstream file to the target hardware platform and starting the operation includes: Transmitting the bitstream file to a hardware platform of a corresponding target programmable array logic device; The execution of the bitstream file is started on a hardware platform of the target programmable array logic device.

8. A device for implementing real-time simulation of hardware logic using FPGA, characterized in that: The device comprises: A package definition module, used to package the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, and define the input and output ports and parameter interfaces of the algorithm model in the algorithm IP core; A file design model is used to obtain the hardware resource description information of the programmable array logic device, and based on the input and output ports and parameter interfaces of the algorithm IP core and the hardware resource description information of the programmable array logic device, a mapping relationship between the input and output ports and parameter interfaces and the hardware resource description information is established by a model-driven method, and an engineering configurable top-level design file of the programmable array logic device is dynamically generated according to the established mapping relationship; The simulation test module is used to perform comprehensive layout and routing of the top-level design file through the preset design tool of the programmable array logic device, generate a corresponding bit stream file that can be directly run on the programmable array logic device, and download the bit stream file to the target hardware platform to start running.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps of the method for implementing hardware logic real-time simulation on FPGA as described in any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for implementing hardware logic real-time simulation on FPGA as described in any one of claims 1 to 7 are implemented.

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