Method of controlling a power factor correction circuit

Abstract

The application provides a control method of a power factor correction circuit, which comprises the following steps: outputting a first synchronization signal to a second controller by a first controller; adjusting a second PWM signal group based on the first synchronization signal to obtain a new second PWM signal group by the second controller, so that the new second PWM signal group and the first PWM signal group are staggered by a preset angle in phase; and outputting a first PWM signal group by the first controller to drive a first power factor correction module, and outputting the new second PWM signal group by the second controller to drive a second power factor correction module. The control method of the power factor correction circuit provided by the application can avoid RCD misoperation and ensure normal operation of the system.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic device control, and in particular to a control method of a power factor correction circuit. BACKGROUND

[0002] In the prior art, PFC (Power Factor Correction) technology is usually used in AC / DC converters to reduce the influence of harmonic currents generated by power electronic devices on the power grid.

[0003] At present, the application scheme of dual-channel PFC control mainly uses two PFC modules in parallel, and the two PFC modules are independently controlled. However, since the dual-channel PFC control system is not synchronized, the driving signals of the two PFC modules are not synchronized, which cannot effectively suppress high-frequency leakage current. Moreover, the leakage current of the dual-channel PFC module of the vehicle charger is superimposed on the ground during the charging process, which easily causes the leakage current to exceed the standard requirement and causes the RCD (Residual Current Device) to malfunction, thereby affecting the normal operation of the vehicle charger. SUMMARY

[0004] In order to solve the problem that the leakage current of the two PFC modules in the existing dual-channel PFC system is superimposed on the ground, easily exceeds the standard requirement, causes the RCD to malfunction, and thereby affects the normal operation of the vehicle charger, the present application provides a control method of a power factor correction circuit.

[0005] To achieve the above-mentioned purpose, the present application provides a control method of a power factor correction circuit, the power factor correction circuit comprising a first power factor correction module, a second power factor correction module, a first controller for generating a first PWM signal group to drive the first power factor correction module, and a second controller for generating a second PWM signal group to drive the second power factor correction module, the AC port of the first power factor correction module and the AC port of the second power factor correction module being electrically connected to the output port of an AC power supply. The control method comprises: outputting a first synchronization signal from the first controller to the second controller; adjusting the second PWM signal group based on the first synchronization signal to obtain a new second PWM signal group by the second controller, so that the new second PWM signal group and the first PWM signal group are offset by a preset angle in phase; and outputting the first PWM signal group from the first controller to drive the first power factor correction module, and outputting the new second PWM signal group from the second controller to drive the second power factor correction module.

[0006] The control method of the power factor correction circuit provided in the application comprises the following steps: outputting a first synchronization signal to a second controller by a first controller; and adjusting a second PWM signal group based on the first synchronization signal by the second controller to obtain a new second PWM signal group, so that the new second PWM signal group and the first PWM signal group are staggered by a preset angle in phase, the first leakage current of the first power factor correction module and the second leakage current of the second power factor correction module are staggered by a preset angle, the amplitude of the leakage current Ie is reduced, and the RCD is prevented from malfunctioning, so that the power factor correction circuit can work normally.

[0007] Optionally, the first PWM signal group and the second PWM signal group each comprise a plurality of PWM sub-signals. The adjusting of the second PWM signal group by the second controller based on the first synchronization signal to obtain a new second PWM signal group, so that the new second PWM signal group and the first PWM signal group are staggered by a preset angle in phase, comprises the following steps: capturing the first synchronization signal by the second controller; determining whether the first synchronization signal is normal by the second controller; if it is determined that the first synchronization signal is normal, calculating a first phase difference between the first synchronization signal and a preset PWM sub-signal in the second PWM signal group by the second controller; adjusting at least the phase of each PWM sub-signal in the second PWM signal group according to the first phase difference by the second controller to obtain a new second PWM signal group, so that the new second PWM signal group and the first PWM signal group are staggered by a preset angle in phase; and if it is determined that the first synchronization signal is abnormal, feeding back a first synchronization abnormal signal to the first controller by the second controller.

[0008] Optionally, the determining of whether the first synchronization signal is normal by the second controller comprises the following steps: counting the first synchronization signal by a counter of the second controller to obtain a first count record; identifying the period of the first synchronization signal according to the first count record by the second controller; determining whether the period of the first synchronization signal is an integer multiple of a first preset period by the second controller; if the period of the first synchronization signal is an integer multiple of the first preset period, determining that the first synchronization signal is normal; and if the period of the first synchronization signal is not an integer multiple of the first preset period, determining that the first synchronization signal is abnormal.

[0009] Optionally, the calculating, by the second controller, of the first phase difference between the first synchronization signal and the preset PWM sub-signal in the second PWM signal group comprises: counting, by a counter of the second controller, the preset PWM sub-signal in the second PWM signal group to obtain a second count record; and calculating, by the second controller, the first phase difference between the first synchronization signal and the preset PWM sub-signal in the second PWM signal group according to the first count record and the second count record.

[0010] Optionally, after the feeding back, by the second controller, of the first synchronization abnormal signal to the first controller, the control method further comprises: outputting, by the second controller, a second synchronization signal to the first controller; stopping, by the first controller, outputting the first synchronization signal in response to the first synchronization abnormal signal, and adjusting the first PWM signal group based on the second synchronization signal to obtain a new first PWM signal group, so that the new first PWM signal group and the second PWM signal group are staggered by a preset angle in phase; and outputting, by the first controller, the new first PWM signal group to drive the first power factor correction module, and outputting, by the second controller, the second PWM signal group to drive the second power factor correction module.

[0011] Optionally, the stopping, by the first controller, of outputting the first synchronization signal in response to the first synchronization abnormal signal, and the adjusting, by the first controller, of the first PWM signal group based on the second synchronization signal to obtain a new first PWM signal group so that the new first PWM signal group and the second PWM signal group are staggered by a preset angle in phase, comprises: stopping, by the first controller, outputting the first synchronization signal in response to the first synchronization abnormal signal; capturing, by the first controller, the second synchronization signal; determining, by the first controller, whether the second synchronization signal is normal; if it is determined that the second synchronization signal is normal, calculating, by the first controller, a second phase difference between the second synchronization signal and a preset PWM sub-signal in the first PWM signal group; adjusting, by the first controller, each PWM sub-signal in the first PWM signal group at least in phase according to the second phase difference to obtain a new first PWM signal group, so that the new first PWM signal group and the second PWM signal group are staggered by a preset angle in phase; and if it is determined that the second synchronization signal is abnormal, feeding back, by the first controller, a second synchronization abnormal signal to the second controller, and starting synchronization failure protection.

[0012] Optionally, the determining, by the first controller, whether the second synchronization signal is normal, comprises: counting, by a counter of the first controller, the second synchronization signal to obtain a third counting record; identifying, by the first controller, a period of the second synchronization signal according to the third counting record; determining, by the first controller, whether the period of the second synchronization signal is an integer multiple of a second preset period; if the period of the second synchronization signal is an integer multiple of the second preset period, determining that the second synchronization signal is normal; and if the period of the second synchronization signal is not an integer multiple of the second preset period, determining that the second synchronization signal is abnormal.

[0013] Optionally, the calculating, by the first controller, the second phase difference between the second synchronization signal and a preset PWM sub-signal in the first PWM signal group, comprises: counting, by a counter of the first controller, the preset sub-signal in the first PWM signal group to obtain a fourth counting record; and calculating, by the first controller, the second phase difference between the second synchronization signal and the preset PWM sub-signal in the first PWM signal group according to the third counting record and the fourth counting record.

[0014] Optionally, the control method of the power factor correction circuit further comprises: stopping, by the second controller, outputting the second synchronization signal in response to the second synchronization abnormal signal, and starting synchronization failure protection.

[0015] Optionally, the preset angle is 180 degrees.

[0016] Additional aspects and advantages of the application will be made apparent by the following description. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a structural schematic diagram of a power factor correction circuit provided by an embodiment of the application.

[0018] Figure 2 is Figure 1 is a leakage current loop schematic diagram of the power factor correction circuit shown in

[0019] Figure 3 is a first flowchart of a control method of a power factor correction circuit provided by an embodiment of the application.

[0020] Figure 4 is Figure 3 is a refinement flowchart of step 620 in

[0021] Figure 5 is Figure 4 is a refinement flowchart of step 622 in

[0022] Figure 6 is Figure 4 a detailed flow chart of step 623 in

[0023] Figure 7 is a second flow chart of the control method of the power factor correction circuit provided by the embodiments of the present application.

[0024] Figure 8 is Figure 7 a detailed flow chart of step 627 in

[0025] Figure 9 is Figure 8 a detailed flow chart of step 6273 in

[0026] Figure 10 is Figure 8 a detailed flow chart of step 6274 in

[0027] Figure 11 is Figure 1 a frequency spectrum diagram of the leakage current Ie generated by the power factor correction circuit shown in

[0028] Figure 12 is Figure 1 a frequency spectrum diagram of the leakage current Ie generated by the power factor correction circuit shown in

[0029] The following is a description of the reference signs:

[0030] power factor correction circuit 100

[0031] first power factor correction module 110

[0032] second power factor correction module 120

[0033] isolation circuit 130

[0034] first controller 111

[0035] second controller 121

[0036] AC port 1101, 1201

[0037] switching tube P11-P16, P21-P26

[0038] AC power supply AC

[0039] capacitor C11-C16, C1i, C2i, YC3, YC4

[0040] inductor L11, L12

[0041] Positive terminal 101

[0042] Negative terminal 102

[0043] First synchronization signal Syn1

[0044] Second synchronization signal Syn2

[0045] PWM sub-signals PWM11-PWM16, PWM21-PWM26

[0046] The following detailed description will describe the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0048] In the description of the present application, it should be noted that the terms "first", "second" and the like are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0049] As Figure 1 As shown in the figure, the present application provides a power factor correction circuit 100, which comprises a first power factor correction module 110, a second power factor correction module 120, a first controller 111 and a second controller 121. Wherein, the AC port 1101 of the first power factor correction module 110 and the AC port 1201 of the second power factor correction module 120 are electrically connected with the output port of the AC power supply AC, the DC port of the first power factor correction module 110 is electrically connected with the capacitor C1i, and the DC port of the second power factor correction module 120 is electrically connected with the capacitor C2i, that is, the first power factor correction module 110 and the second power factor correction module 120 are used in parallel, constituting a double PFC.

[0050] Further, the first power factor correction module 110 and the second power factor correction module 120 each include a first bridge arm, a second bridge arm and a third bridge arm. Taking the first power factor correction module 110 as an example, the first ends of the three bridge arms are commonly connected to the positive terminal 101, and the second ends of the three bridge arms are commonly connected to the negative terminal 102, and the positive terminal 101 and the negative terminal 102 are electrically connected to the positive terminal and the negative terminal of the capacitor C1i. Each bridge arm includes two switch tubes electrically connected in series, and each switch tube has a capacitor connected in parallel across the two ends thereof. Specifically, the first bridge arm includes switch tube P11 and switch tube P12 electrically connected in series, the two ends of switch tube P11 are connected in parallel with capacitor C11, and the two ends of switch tube P12 are connected in parallel with capacitor C12; the second bridge arm includes switch tube P13 and switch tube P14 electrically connected in series, the two ends of switch tube P13 are connected in parallel with capacitor C13, and the two ends of switch tube P14 are connected in parallel with capacitor C14; and the third bridge arm includes switch tube P15 and switch tube P16 electrically connected in series, the two ends of switch tube P15 are connected in parallel with capacitor C15, and the two ends of switch tube P16 are connected in parallel with capacitor C16. The first end of the AC port 1101 is electrically connected to the midpoint of the first bridge arm, i.e. the connection point between switch tube P11 and switch tube P12, through inductor L11, and is also electrically connected to the midpoint of the second bridge arm, i.e. the connection point between switch tube P13 and switch tube P14, through inductor L12, and the second end of the AC port 1101 is electrically connected to the midpoint of the third bridge arm, i.e. the connection point between switch tube P15 and switch tube P16. The circuit structure of the second power factor correction module 120 is the same as that of the first power factor correction module 110, and will not be described here.

[0051] Further, the first controller 111 is electrically connected to the control terminals of switch tubes P11-P16 in the first power factor correction module 110, and the first controller 111 is configured to generate a first PWM signal group, i.e. PWM sub-signals PWM11-PWM16, and output the PWM sub-signals PWM11-PWM16 to switch tubes P11-P16 respectively, so as to control the switching states of switch tubes P11-P16, thereby driving the first power factor correction module 110 to work. The second controller 121 is electrically connected to the control terminals of switch tubes P21-P26 in the second power factor correction module 120, and the second controller 121 is configured to generate a second PWM signal group, i.e. PWM sub-signals PWM21-PWM26, and output the PWM sub-signals PWM21-PWM26 to switch tubes P21-P26 respectively, so as to control the switching states of switch tubes P21-P26, thereby driving the second power factor correction module 120 to work.

[0052] Exemplarily, the first controller 111 and the second controller 121 can be implemented in at least one of a hardware form of a Digital Signal Processor (DSP), a Field-Programmable Gate Array (FPGA), and a Programmable Logic Array (PLA).

[0053] As shown in Figure 2 In actual working process, due to the existence of the parasitic capacitances of the power factor correction circuit 100, leakage current is generated to the ground. Specifically, the first power factor correction module 110 has a parasitic capacitance YC3, generating a first leakage current to the ground, and the second power factor correction module 120 has a parasitic capacitance YC4, generating a second leakage current to the ground. The first leakage current and the second leakage current are combined into the leakage current Ie flowing into the common ground. Due to the superposition of the first leakage current and the second leakage current, the leakage current Ie is likely to exceed the standard requirement, causing the RCD to malfunction, thereby affecting the normal working of the on-board charger.

[0054] Referring back to Figure 1 The provided power factor correction circuit 100 further includes an isolation circuit 130, and the first controller 111 and the second controller 121 are electrically connected to the isolation circuit 130 and communicate through the isolation circuit 130. For example, the first controller 111 outputs a first synchronization signal Syn1 to the second controller 121 through the isolation circuit 130, or the second controller 121 outputs a second synchronization signal Syn2 to the first controller 111 through the isolation circuit 130. Exemplarily, the isolation circuit 130 is an optical coupling isolation circuit, which is used to electrically isolate the first controller 111 and the second controller 121 to avoid mutual interference therebetween.

[0055] Referring to Figure 3 To solve the problem that the superposition of the leakage currents generated by the first power factor correction module and the second power factor correction module in the existing power factor correction circuit easily causes the leakage current Ie to exceed the standard requirement, causing the RCD to malfunction, thereby affecting the normal working of the on-board charger, the present application provides a control method of a power factor correction circuit, which is applied to the above-mentioned power factor correction circuit 100. Specifically, the control method includes the following steps:

[0056] In step 610, the first controller 111 outputs a first synchronization signal Syn1 to the second controller 121.

[0057] At step 620, the second controller 121 adjusts the second PWM signal group based on the first synchronization signal Syn1 to obtain a new second PWM signal group, so that the new second PWM signal group and the first PWM signal group are staggered by a preset angle in phase.

[0058] At step 630, the first controller 111 outputs the first PWM signal group to drive the first power factor correction module 110, and the second controller 121 outputs the new second PWM signal group to drive the second power factor correction module 120.

[0059] The control method of the power factor correction circuit provided in the present application can make the first leakage current of the first power factor correction module 110 and the second leakage current of the second power factor correction module 120 staggered by a preset angle, so as to reduce the amplitude of the leakage current Ie, and further avoid the RCD misoperation, and can ensure the normal operation of the power factor correction circuit 100.

[0060] The control method of the power factor correction circuit provided in the present application can improve the leakage current Ie of the power factor correction circuit 100 without additional design of a hardware filter, and can save the hardware cost. When the control method is applied to a vehicle charger provided with the power factor correction circuit 100, the design cost of the system can be reduced and the stability of the system can be improved.

[0061] It should be noted that in the embodiments of the present application, the first synchronization signal Syn1 is formed by the first controller 111 based on a preset PWM sub-signal in the first PWM signal group. Specifically, the first synchronization signal Syn1 is staggered by a preset angle with the preset PWM sub-signal in the first PWM signal group. For example, the preset PWM sub-signal can be PWM11, and the first synchronization signal Syn1 is staggered by a preset angle with PWM11. The new second PWM signal group and the first PWM signal group are staggered by a preset angle in phase, which means that each PWM sub-signal in the new second PWM signal group and the corresponding PWM sub-signal in the first PWM signal group are staggered by a preset angle. Specifically, PWM11 and the new PWM21, PWM12 and the new PWM22, PWM13 and the new PWM23, PWM14 and the new PWM24, PWM15 and the new PWM25, and PWM16 and the new PWM26 are all staggered by a preset angle.

[0062] It can be understood that when the new second PWM signal group and the first PWM signal group are staggered by a preset angle in phase, the first leakage current generated by the first power factor correction module 110 and the second leakage current generated by the second power factor correction module 120 are also staggered by a preset angle, and the amplitude of the leakage current Ie formed by the confluence of the first leakage current and the second leakage current is necessarily smaller than the algebraic sum of the two, and the greater the value of the preset angle, the smaller the amplitude of the leakage current Ie, preferably, the preset angle is 180 degrees, the first leakage current and the second leakage current just counteract each other, the amplitude of the leakage current Ie is the smallest, and the working reliability of the power factor correction circuit 100 is the highest.

[0063] Further, please refer to Figure 4 , the step 620 specifically includes the following steps:

[0064] Step 621, capturing the first synchronization signal Syn1 by the second controller 121.

[0065] Step 622, determining whether the first synchronization signal Syn1 is normal by the second controller 121. If it is determined that the first synchronization signal Syn1 is normal, step 623 is executed. If it is determined that the first synchronization signal Syn1 is abnormal, step 625 is executed.

[0066] Step 623, calculating the first phase difference between the first synchronization signal Syn1 and a preset PWM sub-signal in the second PWM signal group by the second controller 121.

[0067] Step 624, at least phase adjusting each PWM sub-signal in the second PWM signal group according to the first phase difference by the second controller 121, to obtain a new second PWM signal group, so that the new second PWM signal group and the first PWM signal group are staggered by a preset angle in phase.

[0068] Step 625, feeding back a first synchronization abnormal signal to the first controller 111 by the second controller 121.

[0069] Optionally, when phase adjusting each PWM sub-signal in the second PWM signal group, frequency adjustment can also be performed, so that the new second PWM signal group and the first PWM signal group remain synchronized in frequency and are staggered by a preset angle in phase. After obtaining the new second PWM signal group, the period register of the second PWM signal group can also be updated, that is, the frequency and phase angle of the new second PWM signal group are stored.

[0070] It should be noted that the first synchronization signal Syn1 may become abnormal during transmission due to interference or a malfunction of the isolation circuit 130. In this embodiment, the state of the first synchronization signal Syn1 is determined before adjusting the second PWM signal group to ensure the accuracy of synchronization. Furthermore, engineers can troubleshoot based on the first synchronization anomaly signal fed back by the first controller 111, which can improve troubleshooting efficiency.

[0071] Further, please refer to Figure 5 Step 622 specifically includes the following steps:

[0072] Step 6221: The first synchronization signal Syn1 is counted by the counter of the second controller 121 to obtain the first count record.

[0073] Step 6222: The second controller 121 identifies the period of the first synchronization signal Syn1 based on the first counting record.

[0074] Step 6223: The second controller 121 determines whether the period of the first synchronization signal Syn1 is an integer multiple of the first preset period. If the period of the first synchronization signal Syn1 is an integer multiple of the first preset period, then step 6224 is executed. If the period of the first synchronization signal Syn1 is not an integer multiple of the first preset period, then step 6225 is executed.

[0075] Step 6224: Determine that the first synchronization signal Syn1 is normal.

[0076] Step 6225: Determine that the first synchronization signal Syn1 is abnormal.

[0077] Specifically, the counter of the second controller 121 can identify the period of the first synchronization signal Syn1 based on the rising or falling edge of the first synchronization signal Syn1, and count the first synchronization signal Syn1 to obtain the first count record. For example, if the time corresponding to the first rising edge in the nth period of the first synchronization signal Syn1 is 0.04ms, then the counting time corresponding to the nth period is 0.04ms; if the time corresponding to the first rising edge in the (n+1)th period is 0.05ms, then the counting time corresponding to the (n+1)th period is 0.05ms. Therefore, the period of the first synchronization signal Syn1 is 0.01ms.

[0078] It should be noted that in the embodiment, the first preset period is a period of a preset PWM sub-signal in the first PWM signal group, for example, a period of the PWM sub-signal PWM11. The period of the first synchronization signal Syn1 generated by the first controller 111 is an integer multiple of the period of the preset PWM sub-signal in the first PWM signal group, so that whether the first synchronization signal Syn1 is normal can be determined by identifying the period of the received first synchronization signal Syn1 through the second controller 121, and the judgment principle is simple.

[0079] Further, referring to Figure 6 , the step 623 specifically includes the following steps:

[0080] Step 6231, counting the preset PWM sub-signal in the second PWM signal group through the counter of the second controller 121 to obtain a second counting record.

[0081] Step 6232, calculating the first phase difference between the first synchronization signal Syn1 and the preset PWM sub-signal in the second PWM signal group through the second controller 121 according to the first counting record and the second counting record.

[0082] Exemplarily, the counting moment corresponding to the nth period of the first synchronization signal Syn1 is 0.04 ms, the period of the first synchronization signal Syn1 is 0.01 ms, and the counting moment corresponding to the nth period of the preset PWM sub-signal in the second PWM signal group is 0.041 ms, so the preset PWM sub-signal in the second PWM signal group and the first synchronization signal Syn1 are different by 0.001 ms, that is, the first phase difference is-36 degrees, wherein "+" in the first phase difference represents leading, and "-" represents lagging.

[0083] Since the first controller 111 has made the first synchronization signal Syn1 and the preset PWM sub-signal in the first PWM signal group stagger by a preset angle when generating the first synchronization signal Syn1, it is only necessary to keep the new second PWM signal group and the first synchronization signal Syn1 in synchronization, that is, the new second PWM signal group and the first PWM signal group can be ensured to stagger by a preset angle. Exemplarily, the preset PWM sub-signal in the second PWM signal group leads the first synchronization signal Syn1 by 30 degrees, at this time, the phase angle of each PWM sub-signal (including PWM sub-signals PWM21-PWM26) in the second PWM signal group is adjusted to lag by 30 degrees, that is, the new second PWM signal group is obtained.

[0084] Optionally, referring to Figure 7The embodiment of the present application provides another control method of the power factor correction circuit, and the control method is applied to the power factor correction circuit 100. Specifically, the control method comprises the following steps.

[0085] In step 610, the first controller 111 outputs a first synchronization signal Syn1 to the second controller 121.

[0086] In step 621, the second controller 121 captures the first synchronization signal Syn1.

[0087] In step 622, the second controller 121 determines whether the first synchronization signal Syn1 is normal. If it is determined that the first synchronization signal Syn1 is normal, step 623 is performed. If it is determined that the first synchronization signal Syn1 is abnormal, step 625 is performed.

[0088] In step 623, the second controller 121 calculates a first phase difference between the first synchronization signal Syn1 and a preset PWM sub-signal in the second PWM signal group.

[0089] In step 624, the second controller 121 adjusts at least the phase of each PWM sub-signal in the second PWM signal group according to the first phase difference, so as to obtain a new second PWM signal group, so that the new second PWM signal group and the first PWM signal group are staggered by a preset angle in phase.

[0090] In step 630, the first controller 111 outputs the first PWM signal group to drive the first power factor correction module 110, and the second controller 121 outputs the new second PWM signal group to drive the second power factor correction module 120.

[0091] In step 625, the second controller 121 feeds back a first synchronization abnormal signal to the first controller 111.

[0092] In step 626, the second controller 121 outputs a second synchronization signal Syn2 to the first controller 111.

[0093] In step 627, the first controller 111 stops outputting the first synchronization signal Syn1 in response to the first synchronization abnormal signal, and adjusts the first PWM signal group based on the second synchronization signal Syn2 to obtain a new first PWM signal group, so that the new first PWM signal group and the second PWM signal group are staggered by a preset angle in phase.

[0094] Step 628, outputting the new first PWM signal group by the first controller 111 to drive the first power factor correction module 110, and outputting the second PWM signal group by the second controller 121 to drive the second power factor correction module 120.

[0095] In the embodiment of the present application, the second synchronization signal Syn2 is formed by the second controller 121 based on a preset PWM sub-signal in the second PWM signal group, specifically, the second synchronization signal Syn2 is offset by a preset angle from the preset PWM sub-signal in the second PWM signal group. For example, the preset PWM sub-signal is PWM21, then the second synchronization signal Syn2 is offset by a preset angle from PWM21. The new first PWM signal group and the second PWM signal group are offset by a preset angle in phase, which means that each PWM sub-signal in the new first PWM signal group and the corresponding PWM sub-signal in the second PWM signal group are offset by a preset angle, specifically, new PWM11 and PWM21 are offset by a preset angle, new PWM12 and PWM22 are offset by a preset angle, new PWM13 and PWM23 are offset by a preset angle, new PWM14 and PWM24 are offset by a preset angle, new PWM15 and PWM25 are offset by a preset angle, and new PWM16 and PWM26 are offset by a preset angle.

[0096] It should be noted that in the present application, the first controller 111 is the master and the second controller 121 is the slave, the first controller 111 outputs the first synchronization signal Syn1 as the synchronization source for the second controller 121 to perform signal synchronization operation. In the embodiment, the second controller 121 switches to the master after determining that the first synchronization signal Syn1 is abnormal, that is, the second controller 121 outputs the first synchronization abnormal signal and the second synchronization signal Syn2 as the synchronization source. The first controller 111 switches to the slave in response to the first synchronization abnormal signal, receives the second synchronization signal Syn2, and adjusts the first PWM signal group based on the second synchronization signal Syn2 to obtain a new first PWM signal group, so that the new first PWM signal group and the second PWM signal group are offset by a preset angle in phase, that is, the first controller 111 performs signal synchronization operation, so that in the case that the second controller 121 cannot synchronize, the first controller 111 serves as a backup synchronization operation executor, that is, dual-channel synchronization is adopted, and after detecting that single-channel synchronization fails, the backup synchronization loop is switched to, so that the stability of the power factor correction circuit 100 can be further improved.

[0097] Further, referring to Figure 8 , the step 627 specifically includes the following steps:

[0098] Step 6271, stopping outputting the first synchronization signal Syn1 by the first controller 111 in response to the first synchronization abnormal signal.

[0099] Step 6272, capturing the second synchronization signal Syn2 by the first controller 111.

[0100] Step 6273, determining whether the second synchronization signal Syn2 is normal by the first controller 111. If it is determined that the second synchronization signal Syn2 is normal, step 6274 is performed. If it is determined that the second synchronization signal Syn2 is abnormal, step 6276 is performed.

[0101] Step 6274, calculating a second phase difference between the second synchronization signal Syn2 and a preset PWM sub-signal in the first PWM signal group by the first controller 111.

[0102] Step 6275, performing at least phase adjustment on each PWM sub-signal in the first PWM signal group according to the second phase difference by the first controller 111 to obtain a new first PWM signal group, so that the new first PWM signal group and the second PWM signal group are staggered by a preset angle in phase.

[0103] Step 6276, feeding back a second synchronization abnormal signal to the second controller 121 and starting synchronization failure protection by the first controller 111.

[0104] Step 6277, stopping outputting the second synchronization signal Syn2 by the second controller 121 in response to the second synchronization abnormal signal and starting synchronization failure protection.

[0105] Thus, after the first controller 111 and the second controller 121 switch master and slave, if the first controller 111 still cannot complete signal synchronization operation, it can be determined that the power factor correction circuit 100 has a synchronization fault. In this embodiment, while bidirectional synchronization switching control is performed, synchronization failure fast detection is also performed, which can further improve the stability of the power factor correction circuit 100.

[0106] Further, referring to Figure 9 , the step 6273 specifically includes the following steps:

[0107] Step 62731, counting the second synchronization signal Syn2 by a counter of the first controller 111 to obtain a third count record.

[0108] Step 62732, identifying the period of the second synchronization signal Syn2 by the first controller 111 according to the third count record.

[0109] Step 62733, judging whether the period of the second synchronization signal Syn2 is an integer multiple of a second preset period by the first controller 111. If the period of the second synchronization signal Syn2 is an integer multiple of the second preset period, step 62734 is performed. If the period of the second synchronization signal Syn2 is not an integer multiple of the second preset period, step 62735 is performed.

[0110] Step 62734, determining that the second synchronization signal Syn2 is normal.

[0111] Step 62735, determining that the second synchronization signal Syn2 is abnormal.

[0112] It should be noted that in the embodiment, the second preset period is the period of a preset PWM sub-signal in the second PWM signal group, for example, the period of the PWM sub-signal PWM21. The period of the second synchronization signal Syn2 generated by the second controller 121 is an integer multiple of the period of the preset PWM sub-signal in the second PWM signal group, so that the period of the received second synchronization signal Syn2 can be identified by the first controller 111 to determine whether the second synchronization signal Syn2 is normal, and the judgment principle is simple.

[0113] Further, referring to Figure 10 , the step 6274 specifically includes the following steps:

[0114] Step 62741, counting the preset sub-signal in the first PWM signal group by the counter of the first controller 111 to obtain a fourth count record.

[0115] Step 62742, calculating the second phase difference between the second synchronization signal Syn2 and the preset PWM sub-signal in the first PWM signal group by the first controller 111 according to the third count record and the fourth count record.

[0116] Since the second controller 121 has let the second synchronization signal Syn2 be offset by a preset angle from the preset PWM sub-signal in the second PWM signal group when generating the second synchronization signal Syn2, it is only required to keep the new first PWM signal group synchronized with the second synchronization signal Syn2, that is, the preset angle between the new first PWM signal group and the second PWM signal group can be ensured. Exemplarily, the preset PWM sub-signal in the first PWM signal group lags 30 degrees relative to the second synchronization signal Syn2, at this time, the phase angle of each PWM sub-signal (including PWM sub-signals PWM11-PWM16) in the first PWM signal group is adjusted by 30 degrees in advance, that is, the new first PWM signal group is obtained.

[0117] Please refer to Figures 11-12 , Figure 11 The frequency spectrum diagram of the leakage current Ie generated by the power factor correction circuit 100 when the control method provided in the present application is not used, Figure 12 The frequency spectrum diagram of the leakage current Ie generated by the power factor correction circuit 100 when the control method provided in the present application is used (wherein the preset angle is 180 degrees). As shown in Figure 11 When the control method provided in the present application is not used, the component with a frequency of 36KHz in the leakage current Ie generated by the power factor correction circuit 100 is close to 600mA. As shown in Figure 12 In comparison, when the control method provided in the present application is used, the component with a frequency of 36KHz in the leakage current Ie generated by the power factor correction circuit 100 is less than 10mA, and the component with a frequency of 72KHz is less than 70mA. According to the experimental results, it can be known that the amplitude of the leakage current Ie generated by the power factor correction circuit 100 is greatly reduced after the control method provided in the present application is used, so that the vehicle-mounted charger can meet the high-frequency and low-frequency leakage standards, thereby the phenomenon of RCD misoperation can be avoided, and the work is more stable.

[0118] Although the embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, replacements and variations can be made to the embodiments without departing from the principles and purposes of the present application, and the scope of the present application is defined by the claims and their equivalents.

Claims

1. A control method of a power factor correction circuit, the power factor correction circuit comprising a first power factor correction module, a second power factor correction module, a first controller for generating a first set of PWM signals to drive the first power factor correction module, and a second controller for generating a second set of PWM signals to drive the second power factor correction module, an AC port of the first power factor correction module and an AC port of the second power factor correction module are electrically connected with an output port of an AC power source, characterized in that, The first power factor correction module and the second power factor correction module each comprise a first inductor, a second inductor, a first bridge arm, a second bridge arm and a third bridge arm, each bridge arm comprising two switch tubes connected in series, wherein the first ends of the first bridge arm, the second bridge arm and the third bridge arm are connected to the positive terminal, the second ends of the first bridge arm, the second bridge arm and the third bridge arm are connected to the negative terminal, the first end of the AC port is connected to the midpoint of the first bridge arm through the first inductor, the first end of the AC port is also connected to the midpoint of the second bridge arm through the second inductor, and the second end of the AC port is connected to the midpoint of the third bridge arm; the first PWM signal group is used to control the switching state of the switch tubes in the first power factor correction module, the second PWM signal group is used to control the switching state of the switch tubes in the second power factor correction module, and the control method comprises: outputting, by the first controller, a first synchronization signal to the second controller; adjusting, by the second controller, the second PWM signal group based on the first synchronization signal to obtain a new second PWM signal group, so that the new second PWM signal group and the first PWM signal group are offset by a preset angle in phase; and outputting, by the first controller, the first PWM signal group to drive the first power factor correction module, and outputting, by the second controller, the new second PWM signal group to drive the second power factor correction module.

2. The control method of the power factor correction circuit according to claim 1, characterized by, The first PWM signal group and the second PWM signal group each comprise a plurality of PWM sub-signals; The adjusting, by the second controller, the second PWM signal group based on the first synchronization signal to obtain a new second PWM signal group, so that the new second PWM signal group and the first PWM signal group are offset by a preset angle in phase, comprises: capturing, by the second controller, the first synchronization signal; determining, by the second controller, whether the first synchronization signal is normal; if it is determined that the first synchronization signal is normal, calculating, by the second controller, a first phase difference between the first synchronization signal and a preset PWM sub-signal in the second PWM signal group; adjusting, by the second controller, each PWM sub-signal in the second PWM signal group at least in phase according to the first phase difference, to obtain a new second PWM signal group, so that the new second PWM signal group and the first PWM signal group are offset by a preset angle in phase; and if it is determined that the first synchronization signal is abnormal, feeding back, by the second controller, a first synchronization abnormal signal to the first controller.

3. The control method of the power factor correction circuit according to claim 2, characterized by, The determining, by the second controller, whether the first synchronization signal is normal, comprises: counting, by a counter of the second controller, the first synchronization signal to obtain a first count record; identifying, by the second controller, a period of the first synchronization signal according to the first count record; determining, by the second controller, whether the period of the first synchronization signal is an integer multiple of a first preset period. If the period of the first synchronization signal is an integer multiple of the first preset period, it is determined that the first synchronization signal is normal; and If the period of the first synchronization signal is not an integer multiple of the first preset period, it is determined that the first synchronization signal is abnormal.

4. The control method of the power factor correction circuit according to claim 3, characterized by, The first phase difference between the first synchronization signal and a preset PWM sub-signal in the second PWM signal group is calculated by the second controller, including: The preset PWM sub-signal in the second PWM signal group is counted by a counter of the second controller to obtain a second counting record; and The first phase difference between the first synchronization signal and the preset PWM sub-signal in the second PWM signal group is calculated by the second controller according to the first counting record and the second counting record.

5. The control method of the power factor correction circuit according to claim 2, wherein, After the first synchronization abnormal signal is fed back to the first controller by the second controller, the control method further includes: The second synchronization signal is output by the second controller to the first controller; The first synchronization signal is stopped from being output by the first controller in response to the first synchronization abnormal signal, and the first PWM signal group is adjusted based on the second synchronization signal to obtain a new first PWM signal group, so that the new first PWM signal group and the second PWM signal group are staggered by a preset angle in phase; and The new first PWM signal group is output by the first controller to drive the first power factor correction module, and the second PWM signal group is output by the second controller to drive the second power factor correction module.

6. The control method of the power factor correction circuit according to claim 5, wherein, The first synchronization signal is stopped from being output by the first controller in response to the first synchronization abnormal signal, and the first PWM signal group is adjusted based on the second synchronization signal to obtain a new first PWM signal group, so that the new first PWM signal group and the second PWM signal group are staggered by a preset angle in phase, including: The first synchronization signal is stopped from being output by the first controller in response to the first synchronization abnormal signal; The second synchronization signal is captured by the first controller; It is determined by the first controller whether the second synchronization signal is normal; If it is determined that the second synchronization signal is normal, a second phase difference between the second synchronization signal and a preset PWM sub-signal in the first PWM signal group is calculated by the first controller; At least phase adjustment is performed on each PWM sub-signal in the first PWM signal group by the first controller according to the second phase difference, to obtain a new first PWM signal group, so that the new first PWM signal group and the second PWM signal group are staggered by a preset angle in phase; and If it is determined that the second synchronization signal is abnormal, a second synchronization abnormal signal is fed back to the second controller by the first controller, and synchronization failure protection is started.

7. The control method of the power factor correction circuit according to claim 6, wherein, The determination by the first controller whether the second synchronization signal is normal includes: The second synchronization signal is counted by a counter of the first controller to obtain a third counting record; The second synchronization signal is counted by a counter of the first controller to obtain a third counting record; identifying, by the first controller, a period of the second synchronization signal according to the third count record; determining, by the first controller, whether the period of the second synchronization signal is an integer multiple of a second preset period; if the period of the second synchronization signal is an integer multiple of the second preset period, determining that the second synchronization signal is normal; and if the period of the second synchronization signal is not an integer multiple of the second preset period, determining that the second synchronization signal is abnormal.

8. The control method of the power factor correction circuit according to claim 7, characterized by, The calculating, by the first controller, of the second phase difference between the second synchronization signal and a preset PWM sub-signal in the first PWM signal group comprises: counting, by a counter of the first controller, the preset sub-signal in the first PWM signal group to obtain a fourth count record; and calculating, by the first controller, the second phase difference between the second synchronization signal and the preset PWM sub-signal in the first PWM signal group according to the third count record and the fourth count record.

9. The control method of the power factor correction circuit according to claim 6, wherein, The control method of the power factor correction circuit further comprises: stopping, by the second controller, outputting the second synchronization signal in response to the second synchronization abnormal signal, and starting synchronization failure protection.

10. The control method of the power factor correction circuit according to claim 1, wherein, The preset angle is 180 degrees.

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