Bit operation instruction calculation circuit, chip, processor and electronic device

Abstract

An embodiment of the present application provides a bit operation instruction calculation circuit, chip, processor and electronic device. The bit operation instruction calculation circuit includes a bit reversal module, which is used to arrange the source operands in the instruction to be calculated of the first instruction type in reverse order to obtain an intermediate operand; or, use the source operands in the instruction to be calculated of the second instruction type as the intermediate operand; wherein the first instruction type is used to perform calculations based on the valid bit with the highest bit weight in the source operand, and the second instruction type is used to perform calculations based on the valid bit with the lowest bit weight in the source operand; the calculation module is used to calculate the index value result of the valid bit with the lowest bit weight in the intermediate operand, and determine the target operand corresponding to the instruction to be calculated based on the instruction to be calculated, the source operand and the index value result. This solution reduces the occupied area of the chip.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of integrated circuit technology, and specifically to bit operation instruction calculation circuits, chips, processors and electronic devices. Background Art

[0002] Bit manipulation instructions operate on binary bits and are used to find, count, or locate specific bits in a binary number. Typical bit manipulation instructions include LZCNT (Leading Zero Count), TZCNT (Trailing Zero Count), BSF (Bit Scan Forward), and BSR (Bit Scan Reverse).

[0003] In order to realize the calculation of bit operation instructions, a relatively large area on the chip is usually required to arrange the corresponding circuit structure for hardware support. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a bit operation instruction calculation circuit, a chip, a processor, and an electronic device to reduce the occupied area of the chip.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present application provides a bit operation instruction calculation circuit, comprising:

[0007] a bit reversal module, configured to reverse the order of source operands in a to-be-calculated instruction of a first instruction type to obtain an intermediate operand; or to use source operands in a to-be-calculated instruction of a second instruction type as intermediate operands; wherein the first instruction type is configured to perform calculations based on the most weighted significant bits in the source operands, and the second instruction type is configured to perform calculations based on the least weighted significant bits in the source operands;

[0008] A calculation module is used to calculate the index value result of the valid bit with the lowest bit weight in the intermediate operand, and determine the target operand corresponding to the instruction to be calculated based on the instruction to be calculated, the source operand and the index value result.

[0009] Optionally, the bit operation instruction calculation circuit further includes a source operand register, and the width of the source operand register is the maximum number of bits of the source operand supported by the hardware or the host system;

[0010] The source operand includes a plurality of data segments having a preset size, where the preset size is determined based on a size of a minimum computing unit supported by hardware or a host system.

[0011] Optionally, the bit reversal module includes a plurality of bit reversal units, each of which is used to arrange the data of the corresponding data segment in reverse order or in forward order and output the data, with one bit reversal unit corresponding to one data segment;

[0012] Different bit reversal units are connected to different interfaces in the source operand register, and different interfaces correspond to different bits of the source operand.

[0013] Optionally, the calculation module includes an encoding unit and a summing unit, wherein the encoding unit is used to encode the intermediate operand into a hot unique code that only retains the valid bits with the lowest bit weight, and the summing unit is used to determine the corresponding index value result based on the hot unique code.

[0014] Optionally, there are multiple encoding units, wherein one encoding unit corresponds to one bit reversal unit, and the encoding unit is connected to the corresponding bit reversal unit.

[0015] Optionally, for the calculation of the bit backward scan BSR, the index value determined in the summing unit is the reverse index value; for the calculation of other instructions, the index value determined by the summing unit is the index value; the sum of the reverse index value and the index value is n-1, where n is the number of bits of the data segment.

[0016] Optionally, there are multiple summing units, wherein one summing unit corresponds to one encoding unit, and the summing unit is connected to the corresponding encoding unit.

[0017] Optionally, the computing module further includes a zero detection unit, configured to determine whether the source operand is all “0”;

[0018] There are multiple zero detection units, one zero detection unit corresponds to one data segment, and different zero detection units are used to read data in different data segments in the source operand register.

[0019] Optionally, the bit reversal unit includes a preset number of selectors for selecting the normal sequence data or the reverse sequence data of the data segment and outputting the encoding unit of the calculation module;

[0020] The encoding unit includes a preset number of encoders, each of which includes a bitwise OR circuit, a bitwise NOT circuit, and a logic AND gate connected in sequence; wherein the bitwise NOT circuit is connected to an input end of the logic AND gate, wherein the other input end of the logic AND gate is used to input an intermediate operand, and the output end of the logic AND gate is connected to the summing unit to output a hot single-hot code that only retains the valid bit with the lowest bit weight;

[0021] The summing unit includes a preset number of selectors and a summing selector connected to each of the selectors. The input end of the selector inputs the index value and reverse index value in the hot unique code data segment, as well as the calculated instruction type, and is used to select the reverse index value in the hot unique code data segment to output to the summing selector when the BSR instruction is executed, and to select the index value in the hot unique code data segment to output to the summing selector when other instructions are executed; the input end of the summing selector inputs the hot unique code data segment to select the index data input into the summing selector after multiplexing as the index value result based on the valid bits in the hot unique code data segment, and the index data is the index value or the reverse index value.

[0022] Optionally, the calculation module further includes a slice zero reordering unit, a slice selection unit, and a sum selection unit;

[0023] Among them, the slice zero reordering unit is used to sort the detection results of the zero detection unit based on the slice weights of the data segments in the source operands, the slice selection unit is used to select the non-all "0" data segments with the lowest slice weights based on the sorting results output by the slice zero reordering unit, and the sum selection unit is used to determine the index value result of the source operand corresponding to the selection result based on the selection result of the slice selection unit.

[0024] Optionally, the sum selection unit includes two multiplexers, wherein one multiplexer is used to select one of the index value results corresponding to the multiple data segments as a first result value based on the result of the slice selection unit, and the other multiplexer is used to select one of the multiple second candidate results as a second result value based on the result of the slice selection unit, and combine the first result value and the second result value into a comprehensive result value as the index value result;

[0025] The second candidate result is an index value to be merged corresponding to data segments with different slice weights.

[0026] Optionally, the calculation module further includes an all-zero detection unit connected to the zero detection unit, and the all-zero detection unit is used to determine that the source operand is all "0" based on the detection result of the zero detection unit.

[0027] Optionally, the calculation module also includes a result selection unit, which is used to output the index value result, the source operand or the number of bits of the source operand as the target operand based on the operation type of the instruction and the detection result of the all-zero detection unit.

[0028] Optionally, the bit operation instruction calculation circuit further includes: an instruction confirmation module, used to confirm the instruction type of the instruction to be calculated, wherein the instruction type includes the first instruction type and the second instruction type.

[0029] Optionally, leading zero count LZCNT and bit backward scan BSR are used as the first instruction type; trailing zero count TZCNT and bit forward scan BSF are used as the second instruction type.

[0030] In a second aspect, an embodiment of the present application provides a chip comprising the bit operation instruction calculation circuit as described in the first aspect.

[0031] In a third aspect, an embodiment of the present application provides a processor, which includes the bit operation instruction calculation circuit described in the first aspect.

[0032] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes the chip described in the second aspect, or the processor described in the third aspect.

[0033] In view of this, an embodiment of the present application provides a bit operation instruction calculation circuit, a chip, a processor and an electronic device, wherein the bit operation instruction calculation circuit includes: a bit reversal module, used to arrange the source operands in the instruction to be calculated of the first instruction type in reverse order to obtain an intermediate operand; or, to use the source operands in the instruction to be calculated of the second instruction type as intermediate operands; wherein the first instruction type is used to perform calculations based on the valid bit with the highest bit weight in the source operand, and the second instruction type is used to perform calculations based on the valid bit with the lowest bit weight in the source operand; a calculation module, used to calculate the index value result of the valid bit with the lowest bit weight in the intermediate operand, and determine the target operand corresponding to the instruction to be calculated based on the instruction to be calculated, the source operand and the index value result.

[0034] It can be seen that the bit operation instruction calculation circuit provided in the embodiment of the present application can be used for the first instruction type based on the effective bit with the highest bit weight in the source operand for calculation, and the slice bit reversal module obtains the intermediate operand based on the reverse arrangement of the source operand; for the second instruction type based on the effective bit with the lowest bit weight in the source operand for calculation, the slice bit reversal module uses the source operand as the intermediate operand, so as to change the numerical arrangement direction and not change the numerical arrangement order, and then, the calculation module calculates the index value result of the effective bit with the lowest bit weight in the intermediate operand based on the instruction type, and uses the index value result as the bit operation result value. It can be understood that based on the existence of index value 0 (that is, bit 0) in binary data, the index value of the effective bit with the lowest bit weight in an intermediate operand is also the number of "0"s after the effective bit. Therefore, with LZCNT as the first instruction type and TZCNT and BSF as the second instruction type, the bit operation instruction calculation circuit described in this application can at least simultaneously realize the calculation of these three instructions, so there is no need to set up three dedicated circuits on the chip at the same time, reducing the chip area occupied.

[0035] Furthermore, the embodiments of the present application avoid setting up too many circuits on the chip, thereby eliminating the need to provide corresponding power consumption to maintain the various dedicated circuits, thereby reducing power consumption losses of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0037] Figure 1 A schematic diagram of an optional architecture of a bit operation instruction calculation circuit provided in an embodiment of the present application.

[0038] Figure 2 This is an optional circuit structure diagram of some modules in a bit operation instruction calculation circuit provided in an embodiment of the present application.

[0039] Figure 3 A circuit structure diagram of a zero detection unit provided in an embodiment of the present application.

[0040] Figure 4 A circuit structure diagram of a slice zero reordering unit provided in an embodiment of the present application.

[0041] Figure 5 A circuit structure diagram of a chip selection unit provided in an embodiment of the present application.

[0042] Figure 6 This is a circuit structure diagram of an all-zero detection unit provided in an embodiment of the present application.

[0043] Figure 7 A circuit structure diagram of a summation selection unit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0045] In the fields of data compression, cryptographic calculation, and image processing, a large number of bit manipulation instructions are often required to perform searches, counts, or locations of specific bits in binary numbers. Taking LZCNT, TZCNT, BSF, and BSR as examples, the functions of these four bit manipulation instructions are as follows:

[0046] LZCNT: Calculates the number of leading zeros, starting from the highest bit weight to the lowest bit weight (i.e., from left to right), and calculates the number of "0s" before the highest significant bit weight (i.e., the bit with a value of "1") in the source operand, that is, the number of "0s" before the first "1" appears from left to right in the source operand, and writes them to the destination operand; if the source operand is all "0" (i.e., all bits of the source operand are "0"), then the number of bits of the source operand (i.e., the width) is written to the destination operand; taking the 8-bit binary value 00100010 as an example, the 0th to 7th bits of the value from the right and left are respectively, among which the first value on the left is the 7th bit, which can be understood as the bit with the highest bit weight, and the first value on the right is the 0th bit, which can be understood as the bit with the lowest bit weight. The LZCNT calculation result of this value is 2, that is, there are 2 0s before the first 1 appears from left to right.

[0047] TZCNT: Calculates the trailing 0s, starting from the lowest bit weight to the highest bit weight (i.e., from right to left), and calculates the number of "0s" before the lowest significant bit weight (i.e., the bit with a value of "1") in the source operand, that is, the number of "0s" before the first "1" from right to left in the source operand, and writes them to the destination operand; if the source operand is all "0" (i.e., all bits of the source operand are "0"), then the number of bits of the source operand (i.e., the width) is written to the destination operand; still taking the 8-bit binary value 00100010 as an example, the TZCNT calculation result of this value is 1, that is, there is a 0 before the first 1 from right to left.

[0048] BSF: Bit forward scan, from the bit with the lowest bit weight to the bit with the highest bit weight (that is, from right to left), calculate the index value of the valid bit with the lowest bit weight (that is, the bit with the value "1") in the source operand (that is, the Xth bit of the value), that is, the index value of the first bit set to "1" from right to left in the source operand, and write the index value of the bit to the destination operand; if the source operand is all "0" (that is, all bits of the source operand are "0"), the source operand is written to the destination operand; still taking the 8-bit binary value 00100010 as an example, the BSF calculation result of this value is 1, that is, the index value of the first 1 from right to left is 1, that is, the position where the first 1 appears is the 1st bit of the value.

[0049] BSR: Backward bit scan, from the bit with the highest bit weight to the bit with the lowest bit weight (i.e. from left to right), calculate the index value of the valid bit with the highest bit weight (i.e. the bit with the value "1") in the source operand (i.e. the Xth bit of the value), that is, the index value of the first bit set to "1" from left to right in the source operand, and write the index value of the bit to the destination operand; if the source operand is all "0" (i.e. all bits of the source operand are "0"), then write the source operand to the destination operand; still taking the 8-bit binary value 00100010 as an example, the BSR calculation result of the value is 5, that is, the index value of the first 1 from left to right is 5, that is, the position where the first 1 appears is the 5th bit of the value (counting from bit 0).

[0050] Based on the background technology, it is known that in order to realize the calculation of bit operation instructions, it is usually necessary to occupy a large area on the chip to arrange the corresponding circuit structure for hardware support.

[0051] This is because different bit operation instructions usually need to be implemented based on different circuit structures, and for multiple bit operation instructions, multiple different circuit structures need to be provided accordingly, so the multiple different circuit structures need to be arranged in hardware, and on the chip, it is manifested as occupying a larger area to implement the corresponding bit operation instructions.

[0052] In response to the above problems, the inventors of the present application believe that, for bit operation instructions that calculate the valid bits with the highest or lowest bit weight of the source operand, it is possible to consider finding the commonalities and differences of the above bit operation instructions, and using these commonalities and differences to design a bit operation instruction calculation circuit so that the circuit can simultaneously realize the calculation of multiple bit operation instructions, thereby eliminating the need to set up multiple dedicated circuits on the chip at the same time, thereby reducing the chip area occupied.

[0053] In view of this, an embodiment of the present application provides a bit operation instruction calculation circuit, chip, processor and electronic device, wherein the bit operation instruction calculation circuit includes a bit reversal module for arranging the source operands in the instruction to be calculated of the first instruction type in reverse order to obtain an intermediate operand; or, using the source operands in the instruction to be calculated of the second instruction type as intermediate operands; wherein the first instruction type is used to perform calculations based on the valid bit with the highest bit weight in the source operand, and the second instruction type is used to perform calculations based on the valid bit with the lowest bit weight in the source operand; a calculation module is used to calculate the index value result of the valid bit with the lowest bit weight in the intermediate operand, and determine the target operand corresponding to the instruction to be calculated based on the instruction to be calculated, the source operand and the index value result.

[0054] It can be seen that the bit operation instruction calculation circuit provided in the embodiment of the present application can be used for the first instruction type based on the effective bit with the highest bit weight in the source operand for calculation, and the slice bit reversal module obtains the intermediate operand based on the reverse arrangement of the source operand; for the second instruction type based on the effective bit with the lowest bit weight in the source operand for calculation, the slice bit reversal module uses the source operand as the intermediate operand, so as to change the numerical arrangement direction and not change the numerical arrangement order, and then, the calculation module calculates the index value result of the effective bit with the lowest bit weight in the intermediate operand based on the instruction type, and uses the index value result as the bit operation result value. It can be understood that based on the existence of index value 0 (that is, bit 0) in binary data, the index value of the effective bit with the lowest bit weight in an intermediate operand is also the number of "0"s after the effective bit. Therefore, with LZCNT as the first instruction type and TZCNT and BSF as the second instruction type, the bit operation instruction calculation circuit described in this application can at least simultaneously realize the calculation of these three instructions, so there is no need to set up three dedicated circuits on the chip at the same time, reducing the chip area occupied.

[0055] Furthermore, the embodiments of the present application avoid setting up too many circuits on the chip, thereby eliminating the need to provide corresponding power consumption to maintain the various dedicated circuits, thereby reducing power consumption losses of the device.

[0056] It should be noted that, below, the bit operation instruction calculation circuit in the embodiment of the present application is first described. Figure 1 The following is a schematic diagram of an optional architecture of a bit operation instruction calculation circuit provided in an embodiment of the present application, wherein the bit operation instruction calculation circuit includes:

[0057] A bit reversal module is configured to reverse the order of source operands in a to-be-calculated instruction of a first instruction type to obtain an intermediate operand; or to use source operands in a to-be-calculated instruction of a second instruction type as intermediate operands. The first instruction type is configured to perform calculations based on the most weighted significant bits in the source operands, while the second instruction type is configured to perform calculations based on the least weighted significant bits in the source operands.

[0058] The inventors have discovered that, for bit manipulation instructions that perform calculations on the most or least weighted significant bit of a source operand, the instruction types of the instructions to be calculated can be distinguished based on these characteristics, thereby performing different calculations based on the difference in instruction types. Instructions for performing calculations based on the most weighted significant bit of the source operand are defined as a first instruction type, while instructions for performing calculations based on the most weighted significant bit of the source operand are defined as a second instruction type.

[0059] Among them, in order to confirm the specific instruction type, the embodiment of the present application further includes an instruction confirmation module for confirming the instruction type of the instruction to be calculated, wherein the instruction type includes a first instruction type for calculating based on the valid bit with the highest weight in the source operand and a second instruction type for calculating based on the valid bit with the lowest weight in the source operand.

[0060] Specifically, the instruction to be calculated is an instruction to be executed, which is used to calculate a target operand based on a source operand. The instruction content of the instruction to be calculated may include a specific operation type, a corresponding source operand, etc., wherein the instruction type of the instruction to be calculated can be determined based on the operation type of the instruction.

[0061] Since LZCNT is an instruction for calculating the valid bit with the highest bit weight of the source operand, LZCNT can be used as the first instruction type. Since TZCNT and BSF are instructions for calculating the valid bit with the lowest bit weight of the source operand, TZCNT and BSF can be used as the second instruction type.

[0062] In a further example, considering that BSR is essentially an instruction that performs calculations on the valid bits with the highest bit weight of the source operand, it differs from other instructions only in the calculation of the index value result. Therefore, BSR can also be used as the first instruction type.

[0063] In a specific example, the instruction confirmation module can determine a specific operation type (such as LZCNT, TZCNT, BSF, BSR, etc.) based on the instruction encoding, and determine the corresponding instruction type based on the specific operation type. The specific operation type determination logic can, for example, determine whether the instruction encoding is LZCNT, determine whether the instruction encoding is TZCNT, determine whether the instruction encoding is BSF, and determine whether the instruction encoding is BSR, thereby obtaining a judgment logic branch with a judgment result of "yes", thereby determining the specific operation type.

[0064] In a further example, the instruction confirmation module may further confirm the source operand of the instruction to be calculated and the number of bits corresponding to the source operand, wherein the source operand is used as the basis for instruction calculation, and the number of bits of the source operand is used to participate in the subsequent calculation process of the instruction to be calculated.

[0065] In an optional implementation, based on the consideration of reducing the difficulty of calculation and simplifying the circuit structure, the source operand can be divided into multiple data segments with a preset size, so that corresponding calculations are performed on the basis of the divided data segments in the subsequent process. Wherein, the preset size can be recorded as, and the preset size can be determined based on the size of the minimum computing unit supported in the hardware or host system. The preset size can be an integer multiple of the minimum computing unit, for example, 1 times, 2 times, 4 times, etc., and the preset size is preferably the minimum computing unit (i.e., 1 times the minimum computing unit). At the same time, the preset size should also be divisible by the number of bits of the source operand. Taking the minimum computing unit as 16 bits as an example, the preset size can also be 16 bits.

[0066] Accordingly, a 16-bit source operand can be divided into one 16-bit data segment; a 32-bit source operand can be divided into two 16-bit data segments; and a 64-bit source operand can be divided into four 16-bit data segments. In subsequent calculation processes, calculations on the source operand can be performed based on these data segments.

[0067] In a specific example, the source operand can be stored in a source operand register, and the data can be read based on different bit ranges to achieve segmentation of the source operand. For example, data from bits 0 to 15 are read as the first data segment, data from bits 16 to 31 are read as the second data segment, and so on, to achieve reading of the source operand. The width of the source operand register can be the maximum number of bits of the source operand supported by the hardware or host system, for example, 64 bits, so that it can adapt to source operands of all bits below the maximum number of bits. For example, when the source operand register is 64 bits, it can simultaneously adapt to 64-bit, 32-bit or 16-bit source operation data, thereby making the structure more adaptable.

[0068] The bit reversal module performs different calculations on data of different instruction types to convert source operands into intermediate operands that conform to subsequent preset calculation modes. In a specific implementation, the bit reversal module can perform corresponding control based on the instruction type, thereby implementing different calculation processes. In a specific example, the bit reversal module is connected to the instruction confirmation module, so that corresponding control is performed based on the instruction type determined by the instruction confirmation module.

[0069] Among them, for the first instruction type that performs calculation based on the most weighted significant bit in the source operand, the most weighted significant bit in the source operand is converted to the least weighted significant bit by arranging the source operands in the instruction to be calculated of the first instruction type in reverse order. It is understandable that this conversion does not change the order of the arrangement of the values in the source operands while changing the direction of the arrangement of the values, so that the obtained intermediate operands conform to the subsequent preset calculation mode and do not change the specific calculation results.

[0070] Taking the binary number 00100010 as an example, if the data is used as the source operand, the source operand is arranged in reverse order, that is, the data on the left and the data on the right are swapped in sequence, and the resulting value is 01000100. It can be understood that for the LZCNT and BSF instructions, the calculation is based on the most significant bit of the source operand. Still taking 00100010 as an example, the most significant bit of the source operand is enclosed in square brackets and represented as: 00[1]00010, and after the data is arranged in reverse order, the intermediate operation data 01000[1]00 is obtained. The calculation basis in the data is transformed into the least significant bit of the source operand, that is, the "1" enclosed in square brackets on the right, and the corresponding result can be determined based on the number of 0s at the end.

[0071] The second instruction type that calculates the valid bit with the lowest bit weight in the source operand itself conforms to the subsequent preset calculation mode, so that the value of the source operand can be directly used as the intermediate operand, and then the corresponding calculation result can be calculated based on the intermediate operand.

[0072] In a specific example, in an example where the source operand is divided into multiple data segments, the bit reversal module may include multiple bit reversal units, wherein one bit reversal unit corresponds to one data segment, and is used to reverse (i.e., arrange in reverse order) or directly output the data of the corresponding data segment.

[0073] It can be understood that different bit reversal units are used to read data in different data segments in the source operand register. Accordingly, different bit reversal units are connected to different interfaces in the source operand register, wherein different interfaces correspond to different bits of the source operand. For example, the interface of the data segment of bits 0 to 15 can be connected to a bit reversal unit (which can be called a slice 0 bit reversal unit), the interface of the data segment of bits 16 to 31 can be connected to another bit reversal unit (which can be called a slice 1 bit reversal unit), the interface of the data segment of bits 32 to 47 can be connected to another bit reversal unit (which can be called a slice 2 bit reversal unit), and the interface of the data segment of bits 48 to 63 can be connected to another bit reversal unit (which can be called a slice 3 bit reversal unit).

[0074] Furthermore, the bit operation instruction calculation circuit also includes a calculation module for calculating the index value result of the valid bit with the lowest bit weight in the intermediate operand, and determining the target operand corresponding to the instruction to be calculated based on the instruction to be calculated, the source operand and the index value result.

[0075] Based on the aforementioned processing of the source operand, the source operand has been converted into an intermediate operand that conforms to the preset calculation mode. Therefore, the calculation module can first perform the corresponding calculation based on the intermediate operation data to obtain the index value result. It can be understood that the bit used for calculation in the intermediate operand has been adjusted to the significant bit with the lowest bit weight. Accordingly, the calculation module can calculate the index value result of the significant bit with the lowest bit weight in the intermediate operand.

[0076] Given the presence of index 0 (i.e., bit 0) in binary data, the index value of the least weighted significant bit in an intermediate operand is also the number of zeros following that significant bit. Therefore, the bit manipulation instruction calculation circuit described in this application can simultaneously calculate the results of LZCNT, TZCNT, and BSF. Furthermore, in the example of adjusting the index value result, the BSR result can also be calculated simultaneously.

[0077] In a specific example, the index value result of the valid bit with the lowest bit weight in the intermediate operand is calculated by encoding the intermediate operand into a hot unique code that only retains the valid bit with the lowest bit weight, and then determining the corresponding index value result based on the hot unique code.

[0078] Specifically, the calculation module may include an encoding unit and a summing unit, wherein the encoding unit is used to encode the intermediate operand into a hot unique code that only retains the valid bits with the lowest bit weight, and the summing unit is used to determine the corresponding index value result based on the hot unique code.

[0079] Specifically, the encoding method of the encoding unit is to search for the first valid bit (i.e., the bit with a value of "1") from the end (i.e., the right side) of the middle operand, and after finding it, set all other 1 bits to 0, thereby obtaining a hot single code. Taking 00100010 as an example, after finding the first "1" on the right side, all other bits are cleared to 0, resulting in 00000010; taking the bit-reversed value 01000100 of 001000010 as an example, after finding the first "1" on the right side, all other bits are cleared to 0, resulting in 00000100.

[0080] In the example where the source operand is divided into multiple data segments, there may be multiple encoding units, wherein one encoding unit corresponds to one bit reversal unit, and is configured to encode the intermediate operand output by the corresponding bit reversal unit. Accordingly, the encoding unit is connected to the corresponding bit reversal unit.

[0081] In the summing unit, the determined index value result may be an index value. Specifically, the index value is calculated by selecting an index value corresponding to the hot unique code data. Taking the hot unique code 00000010 corresponding to 00100010 as an example, the index value 3'b001 (i.e., 1 represented by 3 bits in binary) can be obtained based on the hot unique code. Taking the hot unique code 00000100 corresponding to the bit-reversed value 01000100 of 00100010 as an example, the index value 3'b010 (i.e., 2 represented by 3 bits in binary) can be obtained based on the hot unique code.

[0082] In a further example, for the calculation of the BSR, the index value result determined in the summing unit can also be a reverse index value. The reverse index value of the summing unit is calculated specifically by selecting a reverse index value corresponding to the hot unique code data. Taking the hot unique code 00000010 corresponding to 00100010 as an example, a reverse index value 3'b110 (i.e., 6 represented by 3 bits of binary) can be obtained based on the hot unique code; taking the hot unique code 00000100 corresponding to the bit-reversed value 01000100 of 00100010 as an example, a reverse index value 3'b101 (i.e., 5 represented by 3 bits of binary) can be obtained based on the hot unique code.

[0083] In the example where the source operand is divided into multiple data segments, there may be multiple summing units, wherein one summing unit corresponds to one encoding unit and is configured to calculate the hot unique code output by the corresponding encoding unit. Accordingly, the summing unit is connected to the corresponding encoding unit.

[0084] After calculating the index value result of the effective bit with the lowest bit weight in the intermediate operand, the calculation module further determines the target operand corresponding to the instruction to be calculated based on the instruction to be calculated, the source operand and the index value result.

[0085] It is understood that when the source operand is not all "0" (i.e., there are valid bits in the source operand), the destination operand can be determined based on the index value result; when the source operand is all "0" (i.e., the data on each bit in the source operand is "0"), the destination operand varies based on the instruction to be calculated. Specifically, for LZCNT and TZCNT, the destination operand corresponding to an all-0 source operand is the number of bits (i.e., width) of the source operand; for BSF and BSR, the destination operand corresponding to an all-0 source operand is the source operand.

[0086] Therefore, while the calculation module calculates the corresponding index value result, it can also simultaneously detect the source operand to determine whether the source operand is all "0". Accordingly, the calculation module can further include a zero detection unit for determining whether the source operand is all "0". In a specific example, if the source operand is all "0", it can output 1, otherwise it outputs 0.

[0087] In the example where the source operand is divided into multiple data segments, each of the multiple data segments can be tested to determine whether the corresponding data segment is all zeros. Specifically, there can be multiple zero detection units, where one zero detection unit corresponds to each data segment, and is used to determine whether the corresponding data segment is all zeros. Therefore, based on the results of all zero detection units, it can be determined whether the source operand is all zeros. Specifically, if the data segment is all zeros, a 1 can be output; otherwise, a 0 can be output.

[0088] In a specific example, the zero detection unit can be connected to a source operand register. Different zero detection units are used to read data in different data segments in the source operand register, and accordingly, different zero detection units are connected to different interfaces in the source operand register, wherein different interfaces correspond to different bits of the source operand. For example, the interface of the 0th to 15th bit data segment can be connected to a zero detection unit (which can be called a slice 0 zero detection unit), the interface of the 16th to 31st bit data segment can be connected to another zero detection unit (which can be called a slice 1 zero detection unit), the interface of the 32nd to 47th bit data segment can be connected to another zero detection unit (which can be called a slice 2 zero detection unit), and the interface of the 48th to 63rd bit data segment can be connected to another zero detection unit (which can be called a slice 3 zero detection unit).

[0089] It should be noted that in the embodiment of the present application, the detection of whether the data segment is all "0" is not only used to determine whether the source operand is all "0", but also can be used to combine the index value results of each data segment into the index value result of the source operand.

[0090] Specifically, the index value corresponding to the source operand can be determined by searching for a data segment that is not all zeros and based on the weight of the data segment in the source operand. The weight of the data segment in the source operand is used as the slice weight, and the index value corresponding to the source operand can be the sum of the index value corresponding to the non-all zero data segment with the lowest slice weight and the number of bits of the all-zero data segment with a slice weight lower than that data segment.

[0091] Specifically, the slice weight of the data segment is determined based on the operation type of the instruction.

[0092] For TZCNT and BSF instructions, the greater the weight of the data in the data segment in the source operand, the greater the corresponding slice weight. Taking the data segment of bits 0 to 15 of the source operand corresponding to the slice 0 zero detection unit and the data segment of bits 48 to 63 of the source operand corresponding to the slice 3 zero detection unit as examples, the data in the data segment of bits 0 to 15 corresponding to the slice 0 zero detection unit has the lowest corresponding weight in the source operand, so the slice weight of this data segment is the lowest, and the corresponding slice weight can be recorded as L0. The data in the data segment of bits 48 to 63 corresponding to the slice 3 zero detection unit has the highest corresponding weight in the source operand, so the slice weight of this data segment is the highest, and the corresponding slice weight can be recorded as L3.

[0093] For the LZCNT instruction, the greater the weight of the data in the data segment in the source operand, the smaller the corresponding slice weight. Taking the data segment of bits 0 to 15 of the source operand corresponding to the slice 0 zero detection unit and the data segment of bits 48 to 63 of the source operand corresponding to the slice 3 zero detection unit as examples, the data in the data segment of bits 0 to 15 corresponding to the slice 0 zero detection unit has the lowest corresponding weight in the source operand, and the slice weight of this data segment is the highest, and the corresponding slice weight can be recorded as L3. The data in the data segment of bits 48 to 63 corresponding to the slice 3 zero detection unit has the highest corresponding weight in the source operand, and the slice weight of this data segment is the lowest, and the corresponding slice weight can be recorded as L0.

[0094] For the BSR instruction in the optional example, the greater the weight of the data in the data segment in the source operand, the greater the corresponding slice weight. Taking the data segment of bits 0 to 15 of the source operand corresponding to the slice 0 zero detection unit and the data segment of bits 48 to 63 of the source operand corresponding to the slice 3 zero detection unit as examples, the data in the data segment of bits 0 to 15 corresponding to the slice 0 zero detection unit has the lowest corresponding weight in the source operand, and the slice weight of this data segment is the lowest, and the corresponding slice weight can be recorded as L0. The data in the data segment of bits 48 to 63 corresponding to the slice 3 zero detection unit has the highest corresponding weight in the source operand, and the slice weight of this data segment is the highest, and the corresponding slice weight can be recorded as L3.

[0095] Specifically, for the example of configuring a 64-bit source operand register, the slice weights corresponding to each data segment are shown in Table 1:

[0096] Table 1: Slice weights corresponding to each data segment in source operands of different bit sizes

[0097]

[0098] Correspondingly, after determining the index value results corresponding to each data segment, the index value results of the source operand can also be determined based on the slice weight of the data segment, so that when the source operand is not all "0", the index value results of the source operand are output as the target operand.

[0099] Specifically, the calculation module may further include a slice zero reordering unit, a slice selection unit, and a sum selection unit, wherein the slice zero reordering unit is used to sort the detection results based on the slice weights of the data segments in the source operand, thereby describing the slice weights of different data segments and the corresponding detection results in the data order. The slice selection unit selects the non-all-0 data segment with the lowest slice weight based on the sorting result output by the slice zero reordering unit. The sum selection unit is used to determine the index value result of the source operand corresponding to the selection result based on the selection result of the slice selection unit.

[0100] Furthermore, an all-zero detection unit connected to the zero detection unit may be provided to determine that the source operand is all zeros based on a detection result of the zero detection unit. Furthermore, the calculation module may further include a result selection unit to output the index value result, the source operand, or the number of bits of the source operand as the destination operand based on the instruction operation type and the detection result of the all-zero detection unit.

[0101] It is understood that each module in the bit operation instruction calculation circuit described in the embodiments of the present application, including the instruction confirmation module, the bit reversal module, the calculation module, etc., can be implemented based on hardware logic, that is, based on actual hardware circuits and the signal control implementation of the hardware circuits. Accordingly, each module can be designed as a specific hardware circuit structure. Below, the specific circuit structure examples of some modules in the bit operation instruction calculation circuit are described.

[0102] refer to Figure 2 The optional circuit structure diagram of some modules in a bit operation instruction calculation circuit provided by an embodiment of the present application is shown. The bit reversal unit includes a preset number of selectors for selecting the positive sequence data or the reverse sequence data of the data segment and outputting it to the calculation module. Figure 2 In the example, the preset number is specifically output to the encoding unit of the computing module. The preset number is determined based on the number of bits in the data segment. Specifically, when the data segment is 16 bits, the preset number is 16. The selector is controlled based on the instruction type determined by the instruction confirmation module to select the reverse data in the data segment for output when the instruction type is the first instruction type, and select the original data in the data segment for output when the instruction type is the second instruction type. For a 16-bit data segment, the specific instruction execution logic of the bit reversal unit is:

[0103] RevB[n]=BSR / LZCNT? RawB[15-n]:RawB[n],0<=n<=15

[0104] Take the input data segments as RawB[0]~RawB[c-1] and the output data as the intermediate data segment RevB[0]~RevB[c-1] as an example, where c is the number of bits in the data segment, RawB[0] is the data with the lowest bit weight in the data segment, and RawB[c-1] is the data with the highest bit weight in the data segment. Specifically, based on the control of the selector, one data is selected from RawB[0] and RawB[c-1] as RevB[0] (RawB[c-1] is selected in the first instruction type, and RawB[0] is selected in the second instruction type), and one data is selected from RawB[1] and RawB[c-2] as RevB[1] (RawB[c-2] is selected in the first instruction type, and RawB[1] is selected in the second instruction type), and so on. The output data RevB[0]~RevB[c-1] is used as the 0th to c-1th bits of the intermediate operand. In Figure 2 In the example, c is 16.

[0105] For further reference, Figure 2 The encoding unit includes a preset number of encoders, the preset number being determined based on the number of bits in the data segment. Specifically, when the data segment is 16 bits, the preset number is 16. The encoder includes a bitwise OR circuit and a bitwise NOT circuit connected in sequence, and a logic AND gate, wherein the bitwise NOT circuit is connected to one input of the logic AND gate, wherein the other input of the logic AND gate is used to input an intermediate operand, and the output of the logic AND gate is connected to a summing unit. The encoding unit can perform calculations based on the intermediate operands to obtain a single-hot code that retains only the significant bits with the lowest bit weight.

[0106] For a 16-bit intermediate data segment, the specific instruction execution logic of the encoding unit is:

[0107] EncB[n]=RevB[n]&(~|RevB[n-1:0]),1<=n<=15;

[0108] EncB[0]=RevB[0]

[0109] Take the input intermediate data segments as RevB[0]~RevB[c-1] and the output hot unique code data segments as EncB[0]~EncB[c-1] as an example, where c is the number of bits in the intermediate data segment, RevB[0] is the data with the lowest bit weight in the intermediate data segment, and RevB[c-1] is the data with the highest bit weight in the intermediate data segment. Specifically, based on the bitwise OR and bitwise NOT operations of RevB[n-1:0], it is used to determine whether there is "1" in the n:0 bit of the intermediate data segment. If so, the calculation result is "0", and if not, the calculation result is "1". Based on the AND operation of this result and RevB[n], the data corresponding to the nth bit in EncB is determined. Figure 2 In the example, c is 16.

[0110] refer to Figure 2 The summation unit includes a preset number of selectors and a summation selector respectively connected to the selectors. The preset number is determined based on the number of bits of the data segment. Specifically, when the data segment is 16 bits, the preset number is 16. The selector is controlled based on the operation type of the instruction. Specifically, the input end of the selector inputs the index value and the reverse index value in the hot unique code data segment, as well as the calculated instruction type, so as to select the reverse index value in the hot unique code data segment to be output to the summation selector when the BSR instruction is executed, and select the index value in the hot unique code data segment to be output to the summation selector when other instructions are executed. The input end of the summation selector inputs the hot unique code data segment to select the index data input into the summation selector after multiplexing as the index value result based on the valid bits in the hot unique code data segment. The index data is the index value or the reverse index value.

[0111] Here, the input hot unique code data segment is EncB[c-1:0], and the output data is the index value result SliceSumPre[r-1:0] as an example, where c is the number of bits of the hot unique code data segment and r is the number of bits of the index value result. Specifically, based on the control of the selector, one data is selected from the index value r'd0 and the reverse index value r'd(c-1) as MUX_1[0] (the BSR instruction selects r'd(c-1), and the non-BSR instruction selects r'd0), and one data is selected from r'd1 and r'd(c-2) as MUX_1[1] (the BSR instruction selects r'd(c-2), and the non-BSR instruction selects r'd1), and so on. The output data is SliceSumPre[r-1:0] as the index value result. For different data segments, the output data can be further recorded as SliceSumPre[k-1:0][r-1:0], where k is the number of segments into which the source data segment is divided. exist Figure 2 In the example, c is 16 and r is 4.

[0112] In the example of a 16-bit data segment, the index value is 4'b0000 to 4'b1111, that is, 4-bit binary data representation. In a specific example, the index value result can be recorded as SliceSumPre[3:0].

[0113] Among them, for the slice 0 bit inversion unit of the data segment from 0 to 15 bits, the corresponding index value result can be recorded as SliceSumPre[0][3:0]; for the slice 1 bit inversion unit of the data segment from 16 to 31 bits, the corresponding index value result can be recorded as SliceSumPre[1][3:0]; for the slice 2 bit inversion unit of the data segment from 32 to 47 bits, the corresponding index value result can be recorded as SliceSumPre[2][3:0]; for the slice 3 bit inversion unit of the data segment from 48 to 63 bits, the corresponding index value result can be recorded as SliceSumPre[3][3:0].

[0114] refer to Figure 3 The circuit structure of a zero detection unit is shown. The zero detection unit includes s NOR circuits and a logical AND circuit, where s is determined based on the number of bits c in the data segment and the number p of input interfaces of the NOR circuit, where one input interface is used to input one bit of data. Specifically, s = c / p. For example, when the number of input interfaces of the NOR circuit is 4 and the data segment is 16 bits, s is 4. The NOR circuit is used to perform calculations based on the input data. When all the input data are "0", the output data is "1"; when there is a "1" in the input data, the output data is "0". The logical AND circuit is used to determine whether the data segment is all "0" based on the data output by the NOR circuit. If so, the data output by the s NOR circuits are all "1", and the detection result is output as "1". If not, the data output by the s NOR circuits contains a "0", and the detection result is output as "0". The detection result can be recorded as PreSliceZero[m], where m is a natural number.

[0115] exist Figure 3 In FIG, the NOR circuit is NOR4 with 4 input interfaces, and the logical AND circuit is AND4 with 4 input interfaces.

[0116] For further reference, Figure 4 The circuit structure of a slice zero reordering unit is shown. The slice zero reordering unit includes a reordering circuit to perform sorting based on input detection results and preset slice weight values. The reordering circuit inputs the detection results PreSliceZero[m] of each data segment and outputs the sorted detection results, which can be denoted as SliceZero[m].

[0117] For further reference, Figure 5The circuit structure diagram of a slice selection unit is shown, and the slice selection unit includes multiple slice selectors, wherein the slice selector for the detection result SliceZero[0] with the lowest slice weight includes a logic NOT gate, the input of which is SliceZero[0] after the logic NOT operation, and the output of the slice 0 selection result SelSliceL0; the slice selector for other detection results SliceZero[m] includes two connected logic AND gates, the input of one logic AND gate is SliceZero[m-1:0], the output result is input to the other logic AND gate, and after the corresponding "AND" calculation is performed with SliceZero[m] after the logic NOT operation, the slice m selection result SelSliceLm is output.

[0118] For the 4-bit sorted detection result, the specific instruction execution logic of the chip selection unit is:

[0119] SliceSelL[m]=~SliceZero[m]&(&SliceZero[m-1:0])1<=m<=3

[0120] SliceSelL[0]=~SliceZero[0]

[0121] For further reference, Figure 6 1 shows a circuit structure diagram of an all-zero detection unit, wherein the all-zero detection unit includes a logic AND circuit, wherein the input is SliceZero[m-1:0] and the output is SliceZero; specifically, the logic AND circuit can be AND4 with 4 input interfaces.

[0122] For further reference, Figure 7 A circuit structure diagram of a summation selection unit is shown, wherein the summation selection unit includes two multiplexers, wherein one multiplexer is used to select a first result value from index value results corresponding to multiple data segments based on the result of the chip selection unit, and the other multiplexer is used to select a second result value from multiple second alternative results based on the result of the chip selection unit, and merge the first result value and the second result value into a comprehensive result value as the index value result.

[0123] In a specific example, the input of a multiplexer is the index value result SliceSumPre[k-1:0][r-1:0] of multiple data segments, and the reordering circuit sorts the data segments based on the slice weights to obtain the reordering result value SliceSum[k-1:0][r-1:0], where, taking the slice weight L0 as an example, the reordering result value corresponding to the data segment is SliceSum[0][r-1:0]; then, the non-zero result with the lowest slice weight is selected by the multiplexer and output as the first result value Sum[r-1:0] (r-1 is 3 as an example in the figure), and the second alternative result input by another multiplexer is the index value Sum[r+x:r] to be merged corresponding to the data segments with different slice weights. Taking slice weight L0 as an example, the index value of this data segment is the index value of the source operand, and the corresponding index value to be merged is 0; for the data segment of slice weight L1, its corresponding position in the source operand makes it possible to add the number of bits n of the data segment of slice weight L0 in addition to its own index value, so the index value to be merged is n; for the data segment of slice weight L2, its corresponding position in the source operand makes it possible to add the number of bits 2n of the data segment of slice weight L0 and the data segment of slice weight L1 in addition to its own index value, so the index value to be merged is 2n, and so on.

[0124] Taking n as 16 as an example, the first result value is 3 bits, recorded as Sum[3:0], the index value to be merged is 2 bits, recorded as Sum[5:4], and the index value to be merged of the data segment with slice weight L0 is 2'b00, wherein 00 represents the 4th to 5th bits of the binary comprehensive result value. Accordingly, 00 here indicates that the index value to be merged is 0; the index value to be merged of the data segment with slice weight L1 is 2'b01, wherein 01 represents the 4th to 5th bits of the binary comprehensive result value based on the 01, and accordingly, 01 here is binary 01000, indicating that the index value to be merged is 16; the index value to be merged of the data segment with slice weight L2 is 2'b10, wherein 10 represents the 4th to 5th bits of the binary comprehensive result value based on the 10, and accordingly, 10 here is binary 10000, indicating that the index value to be merged is 32, and so on.

[0125] Since both the first result value and the second result value are represented in binary form, in the specific process of merging the first result value and the second result value, a comprehensive result value can be obtained based on the numerical merging of the first result value and the second result value. Still using the above example, Sum[3:0] and Sum[5:4] are merged to form 5-bit binary data as the comprehensive result value. For example, if Sum[3:0] is 010 and Sum[5:4] is 01, the comprehensive result value is 01010.

[0126] It can be understood that the bit operation instruction calculation circuit described in the embodiment of the present application can at least simultaneously realize the calculation of the three instructions, so there is no need to set up three dedicated circuits on the chip at the same time, reducing the chip area occupied.

[0127] An embodiment of the present application further provides a chip, which may include the above-mentioned bit operation instruction calculation circuit.

[0128] An embodiment of the present application also provides a processor, which may include the above-mentioned bit operation instruction calculation circuit.

[0129] An embodiment of the present application also provides an electronic device, which may include the above-mentioned chip, or the above-mentioned processor.

[0130] The above describes multiple embodiment schemes provided by the embodiments of the present application. The various optional methods introduced in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment schemes, which can all be considered as embodiment schemes disclosed and open in the embodiments of the present application.

[0131] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims.

Claims

1. A bit operation instruction calculation circuit, characterized in that: include: A bit reversal module, configured to reverse the order of source operands in the to-be-calculated instruction of the first instruction type to obtain intermediate operands; Alternatively, a source operand in a to-be-calculated instruction of a second instruction type is used as an intermediate operand; wherein the first instruction type is used to perform calculation based on a significant bit with the highest weight in the source operand, and the second instruction type is used to perform calculation based on a significant bit with the lowest weight in the source operand; a calculation module, configured to calculate an index value result of a significant bit with the lowest bit weight in the intermediate operand, and determine a target operand corresponding to the instruction to be calculated based on the instruction to be calculated, the source operand, and the index value result; The calculation module includes a result selection unit for outputting the index value result, the source operand or the number of bits of the source operand as the target operand based on the operation type of the instruction and the detection result of the all-zero detection unit.

2. A bit operation instruction calculation circuit according to claim 1, characterized in that: The bit operation instruction calculation circuit further includes a source operand register, wherein the width of the source operand register is the maximum number of bits of the source operand supported by the hardware or the host system; The source operand includes a plurality of data segments having a preset size, where the preset size is determined based on a size of a minimum computing unit supported by hardware or a host system.

3. A bit operation instruction calculation circuit according to claim 2, characterized in that: The bit reversal module includes a plurality of bit reversal units, each of which is used to arrange the data of the corresponding data segment in reverse order or in forward order and output the data, with one bit reversal unit corresponding to one data segment; Different bit reversal units are connected to different interfaces in the source operand register, and different interfaces correspond to different bits of the source operand.

4. A bit operation instruction calculation circuit according to claim 3, characterized in that: The calculation module also includes an encoding unit and a summing unit, wherein the encoding unit is used to encode the intermediate operand into a hot unique code that only retains the valid bits with the lowest bit weight, and the summing unit is used to determine the corresponding index value result based on the hot unique code.

5. A bit operation instruction calculation circuit according to claim 4, characterized in that: There are multiple encoding units, wherein one encoding unit corresponds to one bit reversal unit, and the encoding unit is connected to the corresponding bit reversal unit.

6. A bit operation instruction calculation circuit according to claim 4, characterized in that: For the calculation of the bit backward scan BSR, the index value determined in the summing unit is the reverse index value; for the calculation of other instructions, the index value determined by the summing unit is the index value; the sum of the reverse index value and the index value is n-1, where n is the number of bits of the data segment.

7. The bit operation instruction calculation circuit according to claim 4, characterized in that: There are multiple summing units, wherein one summing unit corresponds to one encoding unit, and the summing unit is connected to the corresponding encoding unit.

8. The bit operation instruction calculation circuit according to claim 4, characterized in that: The bit reversal unit includes a preset number of selectors for selecting the normal sequence data or reverse sequence data of the data segment and outputting the encoding unit of the calculation module; The encoding unit includes a preset number of encoders, each of which includes a bitwise OR circuit, a bitwise NOT circuit, and a logic AND gate connected in sequence; wherein the bitwise NOT circuit is connected to an input end of the logic AND gate, wherein the other input end of the logic AND gate is used to input an intermediate operand, and the output end of the logic AND gate is connected to the summing unit to output a hot single-hot code that only retains the valid bit with the lowest bit weight; The summing unit includes a preset number of selectors and a summing selector connected to each of the selectors. The input end of the selector inputs the index value and reverse index value in the hot unique code data segment, as well as the calculated instruction type, and is used to select the reverse index value in the hot unique code data segment to output to the summing selector when the BSR instruction is executed, and to select the index value in the hot unique code data segment to output to the summing selector when other instructions are executed; the input end of the summing selector inputs the hot unique code data segment to select the index data input into the summing selector after multiplexing as the index value result based on the valid bits in the hot unique code data segment, and the index data is the index value or the reverse index value.

9. The bit operation instruction calculation circuit according to claim 4, characterized in that: The computing module further includes a zero detection unit, the zero detection unit being configured to determine whether the source operand is all “0”; There are multiple zero detection units, one zero detection unit corresponds to one data segment, and different zero detection units are used to read data in different data segments in the source operand register.

10. The bit operation instruction calculation circuit according to claim 9, characterized in that: The calculation module further includes a slice zero reordering unit, a slice selection unit, and a sum selection unit; The slice zero reordering unit is used to sort the detection results of the zero detection unit based on the slice weights of the data segments in the source operands; the slice selection unit is used to select the non-all-"0" data segment with the lowest slice weight based on the sorting result output by the slice zero reordering unit; and the sum selection unit is used to determine the index value result of the source operand corresponding to the selection result based on the selection result of the slice selection unit.

11. The bit operation instruction calculation circuit according to claim 10, characterized in that: The sum selection unit includes two multiplexers, wherein one multiplexer is used to select one of the index value results corresponding to the multiple data segments as a first result value based on the result of the slice selection unit, and the other multiplexer is used to select one of the multiple second candidate results as a second result value based on the result of the slice selection unit, and combine the first result value and the second result value into a comprehensive result value as the index value result; The second candidate result is an index value to be merged corresponding to data segments with different slice weights.

12. The bit operation instruction calculation circuit according to claim 9, characterized in that: The calculation module further includes an all-zero detection unit connected to the zero detection unit, and the all-zero detection unit is used to determine that the source operand is all "0" based on a detection result of the zero detection unit.

13. The bit operation instruction calculation circuit according to claim 1, characterized in that: Also includes: The instruction confirmation module is used to confirm the instruction type of the instruction to be calculated, wherein the instruction type includes the first instruction type and the second instruction type.

14. The bit operation instruction calculation circuit according to claim 1, characterized in that: Leading zero count LZCNT and bit backward scan BSR are used as the first instruction type; trailing zero count TZCNT and bit forward scan BSF are used as the second instruction type.

15. A chip, characterized in that: The method comprises the bit operation instruction calculation circuit according to any one of claims 1 to 14.

16. A processor, characterized in that: The processor includes the bit operation instruction calculation circuit according to any one of claims 1 to 14.

17. An electronic device, characterized in that: The electronic device includes the chip according to claim 15 or the processor according to claim 16.

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