Method for forming metal interconnect structure and metal interconnect structure

Abstract

The present invention provides a method for forming a metal interconnection structure and a metal interconnection structure, and specifically relates to the field of semiconductor technology. The formation method comprises: providing a substrate, the substrate comprising a first interlayer dielectric layer and a conductive layer formed in the first interlayer dielectric layer; forming a through hole on the first interlayer dielectric layer, wherein a portion of the conductive layer is exposed at the bottom of the through hole; sequentially forming a diffusion barrier layer and a seed layer on the inner wall of the through hole and the first interlayer dielectric layer on both sides of the through hole; forming an interconnection metal line on the seed layer, the interconnection metal line comprising a first interconnection metal line and a second interconnection metal line, the first interconnection metal line is filled in the through hole, the second interconnection metal line is located on the first interlayer dielectric layer and connected to the first interconnection metal line; forming a self-aligned alloy region on the top wall and side wall of the second interconnection metal line; and forming a second interlayer dielectric layer on the self-aligned alloy region. The method can improve the resistance of the interconnection metal to electromigration and improve the diffusion problem of the interconnection metal.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a metal interconnection structure and a metal interconnection structure. Background Art

[0002] Interconnect technology is the process of manufacturing metal interconnect structures in the back end of line (BEOL) of semiconductor manufacturing to wire semiconductor devices to form the circuits required by semiconductor devices. With the development of semiconductor manufacturing technology, the area of ​​semiconductor chips is getting smaller and smaller, and at the same time, the number of semiconductor devices on a semiconductor chip is increasing. In order to reduce the interconnection resistance, metals with low resistivity are usually used as interconnection materials, such as aluminum, copper, tungsten, etc. However, these metal interconnection materials also generally have the problem of metal diffusion, especially when copper is used as an interconnection material, the diffusion is more serious. In the semiconductor manufacturing process, the metal ions in the metal interconnection structure diffuse into the surrounding dielectric layer, which will cause the insulation performance of the dielectric layer to decrease and the circuit to short-circuit, thereby affecting the reliability and life of the semiconductor device. Summary of the invention

[0003] In view of the above shortcomings of the prior art, the present invention provides a method for forming a metal interconnect structure and a metal interconnect structure to improve the metal diffusion problem in the metal interconnect structure.

[0004] To achieve the above-mentioned object and other related objects, the present invention provides a method for forming a metal interconnect structure, the method comprising:

[0005] Providing a substrate, the substrate comprising a first interlayer dielectric layer and a conductive layer formed in the first interlayer dielectric layer;

[0006] forming a through hole on the first interlayer dielectric layer, wherein the bottom of the through hole exposes a portion of the conductive layer;

[0007] sequentially forming a diffusion barrier layer and a seed layer on the inner wall of the through hole and the first interlayer dielectric layer on both sides of the through hole;

[0008] forming interconnection metal lines on the seed layer, the interconnection metal lines comprising a first interconnection metal line and a second interconnection metal line, the first interconnection metal line being filled in the through hole, the second interconnection metal line being located on the first interlayer dielectric layer and connected to the first interconnection metal line;

[0009] forming a self-aligned alloy region on a top wall and a side wall of the second interconnect metal line;

[0010] A second interlayer dielectric layer is formed on the self-aligned alloy region.

[0011] In an example of the present invention, forming interconnect metal lines on the seed layer includes:

[0012] Forming a patterned photoresist layer on the seed layer at both sides of the through hole, wherein the patterned photoresist layer has an opening exposing a portion of the seed layer, the opening is located above the through hole, and the width of the opening is greater than the width of the through hole;

[0013] Using the patterned photoresist layer as a mask, metal is filled in the through hole and the opening to form interconnected metal lines.

[0014] In one example of the present invention, forming a self-aligned alloy region on the top wall and the side wall of the second interconnect metal line includes:

[0015] forming an alloy coating layer on the top wall and the side wall of the second interconnect metal line;

[0016] The alloy cladding layer is annealed to allow the material of the alloy cladding layer to react with the second interconnection metal line on the surface layer to form a self-aligned alloy region.

[0017] In an example of the present invention, the material of the interconnection metal line includes copper, and the material of the alloy coating layer includes any one of aluminum, manganese, cobalt, tin, palladium, carbon, calcium, magnesium and hafnium.

[0018] In an example of the present invention, before forming a through hole on the first interlayer dielectric layer, the method further includes: forming an etching stop layer on the first interlayer dielectric layer, and when forming the through hole, sequentially etching the etching stop layer and the first interlayer dielectric layer.

[0019] In an example of the present invention, the etching stop layer includes silicon nitride or silicon carbonitride.

[0020] In an example of the present invention, before forming the second interlayer dielectric layer on the self-aligned alloy region, the method further includes removing the etch stop layer exposed on the first interlayer dielectric layer.

[0021] In an example of the present invention, before forming the second interlayer dielectric layer on the self-aligned alloy region, the method further includes: forming a cap layer on the self-aligned alloy region and the exposed first interlayer dielectric layer.

[0022] In an example of the present invention, while forming the second interlayer dielectric layer on the self-aligned alloy region, an air gap is formed between adjacent interconnect metal lines.

[0023] The present invention also provides a metal interconnect structure, which is formed by any of the above-mentioned forming methods, and the metal interconnect structure comprises:

[0024] A substrate, the substrate comprising a first interlayer dielectric layer and a conductive layer formed in the first interlayer dielectric layer;

[0025] A through hole is formed in the first interlayer dielectric layer and exposes a portion of the conductive layer;

[0026] a diffusion barrier layer formed on the inner wall of the through hole and a portion of the first interlayer dielectric layer on both sides of the through hole;

[0027] a seed layer formed on the diffusion barrier layer;

[0028] Interconnection metal lines are formed on the seed layer, the interconnection metal lines include a first interconnection metal line and a second interconnection metal line, the first interconnection metal line is filled in the through hole, and the second interconnection metal line is located on the first interlayer dielectric layer and connected to the first interconnection metal line;

[0029] A self-aligned alloy region formed on a top wall and a side wall of the second interconnect metal line;

[0030] A second interlayer dielectric layer is formed on the self-aligned alloy region.

[0031] The method for forming a metal interconnect structure of the present invention provides a self-aligned alloy region on the top wall of the interconnect metal line and the side wall adjacent to the upper dielectric layer. The alloy region is more stable than the metal in the interconnect metal line, and the alloy has a pinning effect, which can ensure that the grain boundary does not migrate, thereby improving electromigration and time-dependent dielectric breakdown, and improving the stability and reliability of the metal interconnect structure.

[0032] In addition, the self-aligned alloy process of the present invention has low requirements on equipment, has no risk of being "stuck in the neck", and has better applicability and cost-effectiveness for processes above the 14nm node. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 A flow chart of a method for forming a metal interconnect structure according to an embodiment of the present invention;

[0035] Figure 2 A schematic diagram of the structure of a substrate in an embodiment of a method for forming a metal interconnect structure of the present invention;

[0036] Figure 3A schematic diagram of a structure of forming an etching stop layer in an embodiment of a method for forming a metal interconnect structure of the present invention;

[0037] Figure 4 A schematic diagram of a structure for forming a through hole in an embodiment of a method for forming a metal interconnect structure of the present invention;

[0038] Figure 5 A schematic diagram of a structure of forming a diffusion barrier layer and a seed layer in a method for forming a metal interconnect structure of the present invention in one embodiment;

[0039] Figure 6 A schematic structural diagram of a patterned photoresist layer formed in an embodiment of a method for forming a metal interconnect structure of the present invention;

[0040] Figure 7 A schematic diagram of a structure of forming interconnection metal lines in an embodiment of a method for forming a metal interconnection structure of the present invention;

[0041] Figure 8 A schematic diagram of a structure for removing a patterned photoresist layer and a seed layer and a diffusion layer on a first interlayer dielectric layer in a method for forming a metal interconnect structure of the present invention in one embodiment;

[0042] Fig. 9 A schematic diagram of a structure of an alloy coating layer formed in an embodiment of a method for forming a metal interconnect structure of the present invention;

[0043] Fig.10 A schematic diagram of a structure of forming a self-aligned alloy region in an embodiment of a method for forming a metal interconnect structure of the present invention;

[0044] Fig.11 A schematic diagram of a structure in which a portion of an unreacted alloy coating layer and a portion of an etching stop layer are removed in a method for forming a metal interconnect structure of the present invention in one embodiment;

[0045] Fig.12 A schematic diagram of a structure of forming a cap layer in an embodiment of a method for forming a metal interconnect structure of the present invention;

[0046] Fig.13 FIG. 4 is a schematic structural diagram of a metal interconnect structure in one embodiment of the present invention.

[0047] Component number description

[0048] 100, base; 110, substrate; 120, first interlayer dielectric layer; 121, conductive layer; 122, through hole; 123, etch stop layer; 124, diffusion barrier layer; 125, seed layer; 126, patterned photoresist layer; 1261, opening; 127, interconnect metal line; 1271, first interconnect metal line; 1272, second interconnect metal line; 128, alloy coating layer; 129, self-aligned alloy region; 130, cap layer; 131, second interlayer dielectric layer; 132, air gap. DETAILED DESCRIPTION

[0049] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0050] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0051] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0052] In the present invention, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0053] Electromigration (EM) refers to the phenomenon in which metal atoms gradually move due to momentum transfer caused by high current density in metal conductors, which may eventually lead to wire breakage or formation of gaps.

[0054] Time-Dependent Dielectric Breakdown (TDDB) refers to the breakdown phenomenon that occurs when a dielectric material is subjected to a constant voltage after a certain period of time.

[0055] The present invention provides a method for forming a metal interconnection structure and a metal interconnection structure, wherein a self-aligned alloy region is formed on the top wall and side wall of an interconnection metal line, and the stability of the alloy region is utilized to prevent the interconnection metal from diffusing into a surrounding dielectric layer, thereby improving EM and TDDB phenomena and improving the stability and reliability of the metal interconnection structure.

[0056] See also Figure 1 The present invention provides a method for forming a metal interconnect structure, the method comprising the following steps:

[0057] S1. providing a substrate, the substrate comprising a first interlayer dielectric layer and a conductive layer formed in the first interlayer dielectric layer;

[0058] S2, forming a through hole on the first interlayer dielectric layer, wherein a portion of the conductive layer is exposed at the bottom of the through hole;

[0059] S3, sequentially forming a diffusion barrier layer and a seed layer on the inner wall of the through hole and the first interlayer dielectric layer on both sides of the through hole;

[0060] S4, forming interconnection metal lines on the seed layer, the interconnection metal lines comprising a first interconnection metal line and a second interconnection metal line, the first interconnection metal line is filled in the through hole, and the second interconnection metal line is located on the first interlayer dielectric layer and connected to the first interconnection metal line;

[0061] S5, forming a self-aligned alloy region on the top wall and sidewall of the second interconnect metal line;

[0062] S6. Form a second interlayer dielectric layer on the self-aligned alloy region.

[0063] Combine the following Figures 2 to 13 The various steps of the method for forming the metal interconnection structure of the present invention are described in detail.

[0064] See also Figure 2 , perform step S1 to provide a substrate 100 . The substrate 100 in this step includes a substrate 110 , a first interlayer dielectric layer 120 , and a conductive layer 121 formed in the first interlayer dielectric layer 120 .

[0065] The substrate 110 may be any material that meets the requirements of integrated circuits in the art. As an example, the substrate 110 is selected from a semiconductor substrate, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) or other III / V compound semiconductors. In addition to the semiconductor materials listed above, the substrate 110 may also be Si / SiGe, Si / SiC, silicon on insulator (SOI), germanium on insulator (GOI) or silicon germanium on insulator (SGOI), and the like. In other embodiments, the substrate 110 may also be selected from insulating materials, conductive materials, and the like, wherein the insulating material may be an organic insulator, an inorganic insulator, or a combination thereof; the conductive material includes but is not limited to metals, alloys, metal silicides, metal nitrides, or a combination thereof. This application is described in detail by taking the substrate 110 as a semiconductor substrate as an example, on which one or more semiconductor devices, such as transistors, memories, sensors, and the like, may be manufactured.

[0066] The first interlayer dielectric layer 120 is formed on the substrate 110 and is used to support the interconnection metal line 127 in the later stage. The first interlayer dielectric layer 120 can be made of any dielectric material, including inorganic dielectric materials or organic dielectric materials. In some embodiments, the first interlayer dielectric layer 120 includes but is not limited to dielectric materials such as silicon oxide (SiO2), silicon nitride (SiN), hydrogen silsesquioxane polymer (HSQ), methane silsesquioxane polymer (MSQ), methyl silicate compounds, and carbon-doped oxides. The first interlayer dielectric layer 120 can be formed by conventional deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), etc. A conductive layer 121 is provided in the first interlayer dielectric layer 120, and the conductive layer 121 is electrically connected to the semiconductor device on the substrate 110. The conductive layer 121 may be any structure that can be electrically connected to a semiconductor device, such as a metal wire, a Damascus structure, or other conventional conductive structures in the art. In the present application, the conductive layer 121 includes a diffusion barrier layer, a seed layer, and an interconnecting metal wire that are sequentially arranged. The material selection of each layer can refer to the detailed description below.

[0067] See also Figure 3 and Figure 4 , executing step S2 , forming a through hole 122 on the first interlayer dielectric layer 120 .

[0068] In this step, the through hole 122 penetrates along the thickness direction of the first interlayer dielectric layer 120, and the bottom of the through hole 122 exposes a portion of the conductive layer 121. The through hole 122 can be formed by conventional technical means in the art, for example, first spin-coating a photoresist on the first interlayer dielectric layer 120, forming a patterned photoresist through exposure and development, and the patterned photoresist exposes a portion of the first interlayer dielectric layer 120; then, using the patterned photoresist as a mask, an etching process such as reactive ion etching (RIE) is used to remove the first interlayer dielectric layer 120 not covered by the photoresist, and after etching, a conventional ashing or stripping process is used to remove the photoresist to form the through hole 122. The width of the through hole 122 can be set according to actual needs, for example, it can be a submicron width of 20nm to 200nm.

[0069] See also Figure 3 In one embodiment, before forming the through hole 122, the method further includes: forming an etching stop layer 123 on the first interlayer dielectric layer 120. That is, before forming the through hole 122, the etching stop layer 123 is first formed on the first interlayer dielectric layer 120, and the subsequently formed through hole 122 sequentially penetrates the etching stop layer 123 and the first interlayer dielectric layer 120 along the thickness direction to expose a portion of the conductive layer 121. The provision of the etching stop layer 123 can effectively protect the first interlayer dielectric layer 120 below during the etching process to avoid etching damage thereto, thereby reducing its reliability and K value shift.

[0070] The material of the etching stop layer 123 includes but is not limited to silicon nitride (SiN) and silicon carbonitride (SiCN). The etching stop layer 123 can be formed by conventional techniques in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0071] See also Figure 5 , executing step S3 , sequentially forming a diffusion barrier layer 124 and a seed layer 125 on the inner wall of the through hole 122 and the first interlayer dielectric layer 120 on both sides of the through hole 122 .

[0072] The diffusion barrier layer 124 is formed on the bottom wall, side wall and first interlayer dielectric layer 120 on both sides of the through hole 122, and is used to prevent the metal in the interconnection metal line 127 from diffusing into the surrounding first interlayer dielectric layer 120, thereby improving reliability and electromigration characteristics. The material of the diffusion barrier layer 124 can be, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN) or any combination thereof. The diffusion barrier layer 124 can be formed by deposition processes such as PVD, CVD or ALD.

[0073] The seed layer 125 is formed on the diffusion barrier layer 124. The seed layer 125 can promote the subsequent electrochemical plating process of the interconnection metal line 127 and ensure good adhesion between the interconnection metal line 127 and the underlying structure. The seed layer 125 can be selected from one of copper (Cu), titanium (Ti), chromium (Cr), cobalt (Co), and ruthenium (Ru), or any alloy of two or more. In this embodiment, the seed layer 125 is made of copper. The seed layer 125 can be formed by sputtering or deposition, such as CVD, PVD, ALD and other processes.

[0074] See also Figure 6 and Figure 7 , performing step S4 to form interconnection metal lines 127 on the seed layer 125 .

[0075] The interconnection metal line 127 formed in this step includes a first interconnection metal line 1271 and a second interconnection metal line 1272. The first interconnection metal line 1271 is filled in the through hole 122, and can "wrap" the conductive layer 121 below, which not only increases the contact area, but also improves the firmness of the contact; the second interconnection metal line 1272 is located above the first interlayer dielectric layer 120 and covers the seed layer 125 on both sides of the through hole 122. The interconnection metal line 127 can be selected from an alloy composed of one or more of aluminum (Al), copper (Cu), tungsten (W), silver (Ag), cobalt (Co), and ruthenium (Ru), such as copper-aluminum alloy, and other materials with lower resistivity. Further, the interconnection metal line 127 is selected from copper.

[0076] In one embodiment, the interconnect metal line 127 is formed by an electrochemical copper plating (ECP) process. The specific process is as follows:

[0077] First, a patterned photoresist layer 126 is formed on the seed layer 125 on the first interlayer dielectric layer 120. The patterned photoresist layer 126 has at least one opening 1261, and the opening 1261 exposes a portion of the seed layer 125. The formation process of the patterned photoresist layer 126 is exemplified as follows: a photoresist layer is spin-coated on the seed layer 125 on both sides of the through hole 122, and an opening 1261 is formed on the photoresist layer by exposure and development. The opening 1261 is located above the through hole 122, and the width of the opening 1261 is greater than the width of the through hole 122.

[0078] Then, the patterned photoresist layer 126 is used as a mask, and an ECP process is used to form an interconnection metal line 127 on the seed layer 125. Due to the shielding of the photoresist layer, during the ECP process, the interconnection metal line 127 is only deposited in the opening 1261, and the portion covered by the photoresist layer is not deposited. And because the width of the opening 1261 is greater than the width of the through hole 122, the interconnection metal line 127 finally formed includes a first interconnection metal line 1271 filled in the through hole 122 and a second interconnection metal line 1272 located above the first interconnection metal line 1271 and filled in the opening 1261. After the first interconnection metal line 1271 is filled in the through hole 122, the second interconnection metal line 1272 is continuously deposited, so that an upper-layer interconnection can be formed, and the upper-layer second interconnection metal line 1272 can protect the filling metal in the through hole 122 from physical or chemical damage in subsequent process steps.

[0079] See also Figure 7 and Figure 8 After step S4 is completed, it also includes: a process of removing the patterned photoresist layer 126 and the seed layer 125 and the diffusion barrier layer 124 exposed on the first interlayer dielectric layer 120. Among them, the patterned photoresist layer 126 can be removed by a conventional removal process in the art, such as ashing or stripping process. After removing the patterned photoresist layer 126, the seed layer 125 under the photoresist layer is exposed, so the present application adopts an etching process to sequentially remove the exposed seed layer 125 and the diffusion barrier layer 124. The etching process can be wet etching or dry etching, which is not limited here.

[0080] See also Figures 9 to 11 After removing the patterned photoresist layer 126 and the exposed seed layer 125 and the diffusion barrier layer 124, step S5 is performed to form a self-aligned alloy region 129 on the top wall and side wall of the second interconnect metal line 1272, and the pinning effect of the alloy is used to prevent the metal in the interconnect metal line 127 from diffusing into the surrounding dielectric layer, thereby improving the metal's resistance to electromigration.

[0081] In one embodiment, the formation process of the self-aligned alloy region 129 includes: firstly forming an alloy coating layer 128 on the top wall and the side wall of the second interconnect metal line 1272, and then annealing the alloy coating layer 128 to diffuse the material of the alloy coating layer 128 into the interconnect metal line 127, so as to form an alloy region on the surface of the interconnect metal line 127 that is self-aligned with the opening 1261 of the interconnect metal line 127, which is called the self-aligned alloy region 129. The material of the alloy coating layer 128 is selected from a material that is easy to diffuse into the interconnect metal line 127 at high temperature. In this embodiment, the interconnect metal line 127 is selected from metal copper, and the alloy coating layer 128 is selected from a material that is easy to diffuse into copper at high temperature, for example, any one of aluminum (Al), manganese (Mn), cobalt (Co), tin (Sn), palladium (Pd), carbon (C), calcium (Ca), magnesium (Mg) and hafnium (Hf). The alloy coating layer 128 can be formed by conventional chemical vapor deposition (CVD), atomic layer deposition (ALD) and other processes. In the formation process, the alloy coating layer 128 is deposited on all exposed parts of the wafer structure (i.e., the top wall, side wall and etching stop layer 123 of the second interconnect metal line 1272).

[0082] The deposition thickness of the alloy coating layer 128 should not be too thick, otherwise it will affect the resistance of the interconnecting metal line 127. In this embodiment, the deposition thickness of the alloy coating layer 128 is 0.1nm to 200nm, further, it can be 10 to 100nm, and further, it can be 50nm. In the subsequent annealing process, the material in the alloy coating layer 128 (with an oxygen potential higher than that of bulk copper) diffuses into the interconnecting metal line 127, thereby forming an alloying region on the surface of the interconnecting metal line 127, thereby enhancing the strength of the copper material interface and improving the resistance of copper to electromigration. In addition, the position of the alloying region has the least effect on the copper interconnection resistance.

[0083] In this step, the temperature of the annealing treatment can be selected according to the materials of the alloy coating layer 128 and the interconnecting metal wire 127. For example, the temperature of the annealing treatment can be 200 to 600°C, and further, the temperature of the annealing treatment is 400°C. During the annealing treatment process, on the one hand, the alloy coating layer 128 reacts with the interconnecting metal wire 127 to form an alloy layer, and on the other hand, heat energy can be used to help rearrange the metal atoms inside the interconnecting metal wire 127, eliminate the stress introduced during the electroplating process, and reduce the risk of cracking and deformation; it can also promote grain growth, improve the microstructure, reduce the defects that may be generated during the electroplating process, and improve the conductivity and mechanical properties of the interconnecting metal wire 127.

[0084] After the annealing treatment is completed, only the position of the alloy cladding layer 128 in contact with the interconnection metal line 127 undergoes diffusion reaction, forming a self-aligned alloy region 129 aligned with the opening 1261 of the interconnection metal line 127. The remaining positions of the alloy cladding layer 128 that are not in contact with the interconnection metal line 127 remain in the original state. Therefore, in order to prevent the remaining part of the alloy cladding layer 128 from causing adverse effects on the overall structure, before performing the next step, the remaining alloy cladding layer 128 and the etch stop layer 123 exposed on the first interlayer dielectric layer 120 need to be removed. The removal method can adopt an etching process, including but not limited to wet etching and / or dry etching.

[0085] See also Fig.12 In one embodiment, after removing the unreacted alloy coating layer 128 and the exposed etching stop layer 123, the step of forming a cap layer 130 is also included. The cap layer 130 can be coated on the outside of the self-aligned alloy region 129 and the exposed first interlayer dielectric layer 120 through a deposition process. The material of the cap layer 130 can be selected from insulating materials such as SiO2, Si3N4, and SiON. The setting of the cap layer 130 can protect the interconnected metal wires from chemical and physical damage and prevent accidental short circuits between different conductive layers. It can also improve the bonding force between the interconnected metal wires and the subsequently formed interlayer dielectric layer. In other embodiments, the cap layer 130 may not be formed, and step S6 is directly performed.

[0086] See also Fig.13 , perform step S6 to form a second interlayer dielectric layer 131.

[0087] The second interlayer dielectric layer 131 is formed on the first interlayer dielectric layer 120, and covers the interconnection metal line 127, the self-aligned alloy region 129 and the cap layer 130 (if the cap layer 130 is not provided, the cap layer 130 is not covered). The second interlayer dielectric layer 131 can be composed of any suitable low-k dielectric material, including but not limited to the dielectric materials listed in the first interlayer dielectric layer 120, which can be the same as the material of the first interlayer dielectric layer 120, or different from the material of the first interlayer dielectric layer 120. The second interlayer dielectric layer 131 can also be formed by conventional deposition methods in the art such as CVD, PVD, and PECVD. In addition, since the distance between adjacent metal interconnect structures of the present application is set to be less than the height of the interconnection metal line, an air gap 132 is generated during the formation of the second interlayer dielectric layer 131. The air gap 132 has a lower dielectric constant than the interlayer dielectric layer material, and therefore, the formation of the air gap 132 advantageously reduces the parasitic capacitance between the metal interconnect structures.

[0088] See also Fig.13 Based on the same inventive concept, the present invention also provides a metal interconnect structure, which is prepared by the above-mentioned formation method of the present invention.

[0089] Specifically, the metal interconnect structure includes: a substrate 100 , a through hole 122 , a diffusion barrier layer 124 , a seed layer 125 , an interconnect metal line 127 and a second interlayer dielectric layer 131 .

[0090] The base 100 includes a substrate 110, a first interlayer dielectric layer 120 and a conductive layer 121 formed in the first interlayer dielectric layer 120. One or more semiconductor devices, such as transistors, memories, sensors, etc., can be manufactured on the substrate 110; the first interlayer dielectric layer 120 is formed on the substrate 110 and is used to support the subsequent formation of interconnection metal lines 127; the conductive layer 121 is arranged in the first interlayer dielectric layer 120 and is electrically connected to the semiconductor devices on the substrate 110.

[0091] The through hole 122 is formed in the first interlayer dielectric layer 120 , and a portion of the conductive layer 121 is exposed at the bottom thereof.

[0092] The diffusion barrier layer 124 is formed on the bottom wall, side wall and the first interlayer dielectric layer 120 on both sides of the through hole 122, and is used to prevent the metal in the interconnection metal line 127 from diffusing into the surrounding first interlayer dielectric layer 120, thereby improving reliability and electromigration characteristics. The material of the diffusion barrier layer 124 can be, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN) or any combination thereof.

[0093] The seed layer 125 is formed on the diffusion barrier layer 124. The seed layer 125 can provide a conductive base to facilitate the subsequent electroplating process of the interconnection metal line 127 and ensure good adhesion between the interconnection metal line 127 and the underlying structure. The seed layer 125 can be selected from copper (Cu), titanium (Ti), chromium (Cr), cobalt (Co), ruthenium (Ru) or any alloy of two or more thereof.

[0094] The interconnection metal line 127 is formed on the seed layer 125. In the present application, the interconnection metal line 127 includes a first interconnection metal line 1271 and a second interconnection metal line 1272. The first interconnection metal line 1271 is filled in the through hole 122, and the second interconnection metal line 1272 is located on the first interlayer dielectric layer 120 and connected to the first interconnection metal line 1271.

[0095] The self-aligned alloy region 129 is formed on the top wall and sidewall of the second interconnect metal line 1272. The self-aligned alloy region 129 is formed by the diffusion of the deposited alloy coating layer 128 material into the interconnect metal line 127, and the material of the alloy coating layer 128 is selected from any one of aluminum (Al), manganese (Mn), cobalt (Co), tin (Sn), palladium (Pd), carbon (C), calcium (Ca), magnesium (Mg) and hafnium (Hf).

[0096] The second interlayer dielectric layer 131 is formed in the self-aligned alloy region 129 and is connected to the first interlayer dielectric layer 120 .

[0097] Furthermore, the metal interconnect structure further includes an etch stop layer 123 , and the etch stop layer 123 is located between the first interlayer dielectric layer 120 and the diffusion barrier layer 124 on both sides of the through hole 122 .

[0098] Furthermore, the metal interconnect structure further includes a cap layer 130, which is located between the first interlayer dielectric layer 120 and the second interlayer dielectric layer 131 and covers the self-aligned alloy region 129 and the exposed diffusion barrier layer 124 and the seed layer 125. The material of the cap layer 130 can be selected from insulating materials such as SiO2, Si3N4, SiON, etc. The provision of the cap layer 130 can protect the interconnect metal wires from chemical and physical damage and prevent accidental short circuits between different conductive layers, and can also improve the bonding force between the interconnect metal wires and the interlayer dielectric layer.

[0099] The present invention sets a self-aligned alloy region on the top wall of the interconnect metal line and the side wall adjacent to the upper dielectric layer. The alloy region is more stable than the metal in the interconnect metal line, which can effectively improve the diffusion problem of the interconnect metal into the surrounding dielectric layer, thereby improving the electromigration and time-dependent dielectric breakdown phenomena, and improving the stability and reliability of the metal interconnect structure. Therefore, the present invention effectively overcomes some practical problems in the prior art and has high utilization value and use significance.

[0100] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for forming a metal interconnect structure, It is characterized in that include: Providing a substrate, the substrate comprising a first interlayer dielectric layer and a conductive layer formed in the first interlayer dielectric layer; forming a through hole on the first interlayer dielectric layer, wherein the bottom of the through hole exposes a portion of the conductive layer; sequentially forming a diffusion barrier layer and a seed layer on the inner wall of the through hole and the first interlayer dielectric layer on both sides of the through hole; forming interconnection metal lines on the seed layer, the interconnection metal lines comprising a first interconnection metal line and a second interconnection metal line, the first interconnection metal line being filled in the through hole, the second interconnection metal line being located on the first interlayer dielectric layer and connected to the first interconnection metal line; forming a self-aligned alloy region on a top wall and a side wall of the second interconnect metal line; forming a second interlayer dielectric layer on the self-aligned alloy region; Wherein, forming interconnect metal lines on the seed layer comprises: Forming a patterned photoresist layer on the seed layer at both sides of the through hole, wherein the patterned photoresist layer has an opening exposing a portion of the seed layer, the opening is located above the through hole, and the width of the opening is greater than the width of the through hole; Using the patterned photoresist layer as a mask, filling metal in the through hole and the opening to form interconnected metal lines; Forming a self-aligned alloy region on the top wall and the side wall of the second interconnect metal line, comprising: forming an alloy coating layer on the top wall and the side wall of the second interconnect metal line; The alloy cladding layer is annealed to allow the material of the alloy cladding layer to react with the second interconnection metal line on the surface layer to form a self-aligned alloy region.

2. The forming method according to claim 1, It is characterized in that The material of the interconnection metal line includes copper, and the material of the alloy coating layer includes any one of aluminum, manganese, cobalt, tin, palladium, carbon, calcium, magnesium and hafnium.

3. The forming method according to claim 1, It is characterized in that Before forming the through hole on the first interlayer dielectric layer, the method further includes: forming an etching stop layer on the first interlayer dielectric layer, and etching the etching stop layer and the first interlayer dielectric layer in sequence when forming the through hole.

4. The forming method according to claim 3, It is characterized in that The etch stop layer includes silicon nitride or silicon carbonitride.

5. The forming method according to claim 3, It is characterized in that Before forming the second interlayer dielectric layer on the self-aligned alloy region, the method further includes removing the etch stop layer exposed on the first interlayer dielectric layer.

6. The forming method according to claim 1, It is characterized in that Before forming the second interlayer dielectric layer on the self-aligned alloy region, the method further includes: forming a cap layer on the self-aligned alloy region and the exposed first interlayer dielectric layer.

7. The forming method according to claim 1, It is characterized in that While forming a second interlayer dielectric layer on the self-aligned alloy region, an air gap is formed between adjacent interconnection metal lines.

8. A metal interconnect structure, It is characterized in that The metal interconnect structure is formed by the forming method according to any one of claims 1 to 7, wherein the metal interconnect structure comprises: A substrate, the substrate comprising a first interlayer dielectric layer and a conductive layer formed in the first interlayer dielectric layer; A through hole is formed in the first interlayer dielectric layer and exposes a portion of the conductive layer; a diffusion barrier layer formed on the inner wall of the through hole and a portion of the first interlayer dielectric layer on both sides of the through hole; a seed layer formed on the diffusion barrier layer; Interconnection metal lines are formed on the seed layer, the interconnection metal lines include a first interconnection metal line and a second interconnection metal line, the first interconnection metal line is filled in the through hole, and the second interconnection metal line is located on the first interlayer dielectric layer and connected to the first interconnection metal line; A self-aligned alloy region formed on a top wall and a side wall of the second interconnect metal line; A second interlayer dielectric layer is formed on the self-aligned alloy region.

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