A wide frequency range clock data recovery circuit and frequency band adjustment method

Abstract

The invention discloses a wide frequency range clock data recovery circuit and a frequency band adjustment method, wherein a frequency detection circuit FD generates a frequency error signal based on the frequency error between the clock frequency of the recovered clock and the data rate of the input signal; a phase detection circuit PD generates a phase error signal based on the phase error between the clock phase of the recovered clock and the data sequence of the input signal; an adjustable voltage-current converter is controlled by the frequency error signal and the phase error signal to generate a charge-discharge current; a frequency band self-switching circuit generates a corresponding V / I converter gain coefficient, a loop filter coefficient and a frequency divider frequency division coefficient, and sends the corresponding adjustable coefficient of the switching frequency band to the adjustable voltage-current converter, the adjustable loop filter LF and the adjustable frequency divider. The circuit can perform clock data recovery on serial data in a wide frequency range, improve the frequency coverage of the CDR, and ensure loop stability.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a wide frequency range clock data recovery circuit and a frequency band adjustment method. Background Art

[0002] With the continuous increase of information flow, the traditional parallel interface technology is difficult to meet the needs of high-speed and stable information transmission due to the limitation of non-ideal factors, and is gradually replaced by high-speed serial interface technology. Serial high-speed interface not only reduces the complexity of interconnection between interfaces, but also has the advantages of strong anti-interference ability and high communication rate. It is widely used in high-energy physics experiments, digital communications, high-speed signal transmission and other fields. The clock and data recovery (CDR) circuit is the core module of the serial data interface. It is used to receive high-speed serial signals and recover stable synchronous clock and data from them. The operating frequency range of the CDR circuit directly affects the frequency range of the receivable high-speed serial signals.

[0003] However, with the improvement of system integration, in many scenarios, it is necessary to integrate multi-channel CDR circuits in the chip and process input signals with a wide frequency range. Although the advancement of semiconductor technology and the development of integrated circuit design technology have provided a good design foundation for high-performance CDR circuits, and a smaller-sized process can be used to implement CDR circuits with higher speed and wider frequency range, low-cost, low-power, low-area, cost-effective wide-frequency range CDR circuits are easier to integrate in the chip, so that CDR circuits will have a wider range of applications. Therefore, it is necessary to design a CDR circuit with a wide frequency range and high integration. At present, there are many implementation methods for wide-frequency range CDR circuits in the prior art, such as using a multi-band voltage-controlled oscillator VCO (Voltage Controlled Oscillator), switching between different frequency bands VCO, using digital filters or adjustable filters, etc. However, these methods will bring additional area consumption, power consumption, or require the filter to be placed outside the chip, making the system more complicated and not conducive to circuit integration. Summary of the invention

[0004] The purpose of the present invention is to provide a wide frequency range clock data recovery circuit and a frequency band adjustment method, which can perform clock data recovery on serial data in a wide frequency range, improve the frequency coverage of CDR, ensure loop stability, and require less power consumption, thereby having good breadth and practicability.

[0005] The objective of the present invention is achieved through the following technical solutions:

[0006] A wide frequency range clock data recovery circuit, the clock data recovery CDR circuit comprising:

[0007] An adjustable voltage-to-current converter, used for adjusting an error conversion coefficient of the adjustable voltage-to-current converter when switching frequency bands;

[0008] An adjustable loop filter LF, used for filtering the charging and discharging currents generated by the adjustable voltage-to-current converter;

[0009] A voltage-controlled oscillator (VCO) is used to convert the average voltage component containing clock information into a change in the output clock frequency;

[0010] An adjustable frequency divider for synchronously adjusting the frequency division coefficient when switching frequency bands;

[0011] A frequency band self-switching circuit, used for performing self-switching of the frequency band using a frequency band automatic switching method according to a comparison result of a configurable comparator, and sending an adjustable coefficient corresponding to the switched frequency band to the adjustable voltage-current converter, the adjustable loop filter LF and the adjustable frequency divider;

[0012] The data recovery circuit is used to sample the input data using the divided clock. After the locking process is completed, the output result is the recovered data.

[0013] A frequency band adjustment method for a wide frequency range clock data recovery circuit, the method comprising:

[0014] Step 1: After the frequency band self-switching module is powered on and reset, each module in the clock data recovery (CDR) circuit is reset;

[0015] Step 2, the frequency detection circuit FD generates a corresponding frequency error signal based on the frequency error between the clock frequency of the recovered clock and the data rate of the input signal; the phase detection circuit PD generates a corresponding phase error signal based on the phase error between the clock phase of the recovered clock and the data sequence of the input signal;

[0016] Step 3: Using the frequency error signal and the phase error signal, the adjustable voltage-to-current converter and the adjustable loop filter LF generate an error control voltage, so that the output clock of the voltage-controlled oscillator VCO is close to the input signal frequency, and the output clock of the adjustable frequency divider is synchronously adjusted, thus completing a clock feedback adjustment;

[0017] Step 4, the frequency band self-switching module resets the error control voltage, and synchronously adjusts the various adjustable coefficients in the clock data recovery CDR circuit to enter the next frequency band;

[0018] Step 5: Use the recovered clock CLK of the input signal data The lock detection is performed in the decision circuit, and the recovered clock CLK is used after the lock detection is completed.data Recover the data in the input signal and complete the data and clock recovery in the input signal.

[0019] It can be seen from the technical solution provided by the present invention that the above circuit and method can perform clock data recovery on serial data in a wide frequency range, thereby improving the frequency coverage of CDR and ensuring loop stability. At the same time, the required power consumption is small, and it has good breadth and practicality, and is easy to integrate into chips. Especially when applied to high-speed data transmission chips, the advantages of wide frequency range and low power consumption are obvious. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0021] Figure 1 A schematic diagram of the structure of a wide frequency range clock data recovery (CDR) circuit provided by an embodiment of the present invention;

[0022] Figure 2 A schematic diagram of a process of the method according to an embodiment of the present invention;

[0023] Figure 3 The synchronous clock eye diagram recovered from the 400 Mbps input signal in the example of the present invention;

[0024] Figure 4 This is the synchronous clock eye diagram recovered from the 1.2 Gbps input signal in the example of the present invention. DETAILED DESCRIPTION

[0025] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments, and do not constitute a limitation of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] The following will further describe the embodiments of the present invention in detail in conjunction with the accompanying drawings. The contents not described in detail in the embodiments of the present invention belong to the prior art known to professionals in the field. In the embodiments of the present invention, if specific conditions are not specified, they are carried out according to the conditions of normal conditions in the field or the manufacturer's recommendations. If the manufacturer is not specified in the reagents or instruments in the embodiments of the present invention, they are all conventional products that can be purchased commercially.

[0027] like Figure 1 The figure shows a schematic diagram of the structure of a wide frequency range clock data recovery CDR circuit provided by an embodiment of the present invention, wherein the clock data recovery CDR circuit includes a frequency detection circuit FD (Frequency Detection), a phase detection circuit PD (Phase Detection), an adjustable voltage-current (V / I) converter, an adjustable loop filter LF (Loop Filter), a voltage-controlled oscillator VCO, an adjustable frequency divider, a configurable comparator, a frequency band self-switching circuit, a decision circuit and a data recovery circuit, wherein:

[0028] The frequency detection circuit FD generates a corresponding frequency error signal based on the frequency error between the clock frequency of the recovered clock and the data rate of the input signal; the phase detection circuit PD generates a corresponding phase error signal based on the phase error between the clock phase of the recovered clock and the data sequence of the input signal;

[0029] The four adjustable control terminals of the adjustable voltage-current converter are connected to a frequency band self-switching circuit that generates an adjustable coefficient, and are used to adjust the error conversion coefficient of the adjustable voltage-current converter when the frequency band is switched;

[0030] The adjustable loop filter LF is used to filter the charging and discharging current generated by the adjustable voltage-to-current converter;

[0031] The voltage control end of the voltage controlled oscillator VCO is connected to the output end of the adjustable loop filter LF, and is used to convert the average voltage component containing clock information into a change in the output clock frequency;

[0032] The adjustable control terminal of the adjustable frequency divider is connected to the frequency band self-switching circuit, and is used to synchronously adjust the frequency division coefficient when the frequency band is switched;

[0033] One input end of the configurable comparator is connected to the output end of the adjustable loop filter LF, and one input end is connected to the configurable adjustable threshold; the output end of the configurable comparator is connected to the frequency band self-switching circuit;

[0034] The frequency band self-switching circuit performs frequency band self-switching by using a frequency band automatic switching method according to the comparison result of the configurable comparator, generates corresponding voltage-current converter gain coefficient, loop filter coefficient and frequency divider frequency division coefficient, and sends the adjustable coefficient of the corresponding switching frequency band to the adjustable voltage-current converter, the adjustable loop filter LF and the adjustable frequency divider;

[0035] One input end of the decision circuit is connected to the divided clock output end of the adjustable frequency divider, and the other input end is connected to the input signal processed by the phase detection circuit PD, and the output result is used as a flag signal of whether the clock data recovery CDR circuit is locked;

[0036] The data recovery circuit uses the divided-frequency clock to sample the input data, and after the locking process is completed, the output result is the recovered data.

[0037] In a specific implementation, the connection relationship between the various parts in the clock data recovery CDR circuit is:

[0038] The frequency detection circuit FD and the phase detection circuit PD have two input terminals respectively, one input terminal is connected to the input signal, and the other input terminal is connected to the recovered clock after the clock generated by the voltage controlled oscillator VCO is divided by the adjustable frequency divider;

[0039] The output ends of the frequency detection circuit FD and the phase detection circuit PD are respectively connected to the input ends of the adjustable voltage-current converter, and the adjustable voltage-current converter is controlled to generate a charge-discharge current through a frequency error signal and a phase error signal;

[0040] The adjustable control end of the adjustable resistor R in the adjustable loop filter LF is connected to the frequency band self-switching circuit, and is used to adjust the filter coefficient when the frequency band is switched;

[0041] The clock signal at the output end of the voltage controlled oscillator VCO is connected to the input end of the adjustable frequency divider after being driven, and the output end of the adjustable frequency divider is respectively connected to the input ends of the frequency detection circuit FD, the phase detection circuit PD, the data recovery circuit and the decision circuit;

[0042] The input end of the frequency band self-switching circuit is connected to the comparison result output end of the configurable comparator, and the three groups of output ends are respectively connected to the adjustable voltage-current converter, the adjustable loop filter LF and the adjustable frequency divider;

[0043] One input end of the data recovery circuit is connected to the frequency-divided clock output end of the adjustable frequency divider, and the other input end is connected to the input signal.

[0044] In the specific implementation, Figure 1 As shown, the adjustable loop filter LF is composed of an adjustable resistor R and two capacitors C1 and C2, wherein:

[0045] One end of the adjustable resistor R is connected to the phase charge and discharge current output end of the adjustable voltage-current converter and the charging end of the capacitor C2, and the other end is connected to the frequency charge and discharge current output end of the adjustable voltage-current converter and the charging end of the capacitor C1;

[0046] The discharge terminals of capacitors C1 and C2 are grounded.

[0047] Based on the above clock data recovery CDR circuit, an embodiment of the present invention further provides a frequency band adjustment method for a wide frequency range clock data recovery CDR circuit based on frequency band self-switching, such as Figure 2 FIG. 1 is a flow chart of a method according to an embodiment of the present invention, wherein the method comprises:

[0048] Step 1: After the frequency band self-switching module is powered on and reset, each module in the clock data recovery (CDR) circuit is reset;

[0049] In this step, the adjustment coefficient of the adjustable frequency divider and the gain coefficient of the adjustable voltage-to-current converter are reset, that is, set to the highest value; the adjustment coefficient of the adjustable loop filter LF is reset, that is, set to the lowest value; the error control voltage V ctrl Set it to the highest value so that the clock frequency generated by the voltage-controlled oscillator VCO is at the lowest value of the tuning range;

[0050] After reset is completed, the initial clock CLK generated by the voltage-controlled oscillator VCO vco After gain driving, it is transmitted to the adjustable divider, and the initial clock CLK divided by the adjustable divider is div This is the minimum value of the frequency band of the clock data recovery (CDR) circuit.

[0051] Step 2, the frequency detection circuit FD generates a corresponding frequency error signal based on the frequency error between the clock frequency of the recovered clock and the data rate of the input signal; the phase detection circuit PD generates a corresponding phase error signal based on the phase error between the clock phase of the recovered clock and the data sequence of the input signal;

[0052] In this step, the input signal is driven to enter the frequency detection circuit FD and the phase detection circuit PD respectively;

[0053] In the frequency detection circuit FD, the initial clock CLK is divided by the adjustable frequency divider. div The frequency error between the clock frequency and the input signal data rate generates a corresponding frequency error signal V PD ;

[0054] When the error signal range is small, the phase detection circuit PD is switched to perform phase alignment. The phase detection circuit PD uses the transition edge of the input signal to align the initial clock CLK. div Sampling is performed based on the input signal and the initial clock CLK div The relationship between the leading, lagging or no data jump between them generates the corresponding phase error signal V FD .

[0055] Step 3: Using the frequency error signal and the phase error signal, the adjustable voltage-to-current converter and the adjustable loop filter LF generate an error control voltage, so that the output clock of the voltage-controlled oscillator VCO is close to the input signal frequency, and the output clock of the adjustable frequency divider is synchronously adjusted, thus completing a clock feedback adjustment;

[0056] In this step, the phase error signal V FD and frequency error signal V PD Separately control the V / I of the adjustable voltage-to-current converter FD Converters and V / I PD converter, the initial clock CLK div The phase error and frequency error of the input signal are converted into the corresponding charge and discharge current I CP ;

[0057] The adjustable loop filter LF is used for charging and discharging current I CP Perform low-pass filtering to remove high-frequency components and obtain the error control voltage V of the voltage-controlled oscillator VCO. ctrl ;

[0058] The voltage controlled oscillator VCO has an error control voltage V ctrl Under the control of the output clock CLK vco The frequency is adjusted synchronously with the adjustable divider output clock; then it enters the frequency detection circuit FD and the phase detection circuit PD for error detection, completing a clock feedback adjustment.

[0059] Step 4, the frequency band self-switching module resets the error control voltage, and synchronously adjusts the various adjustable coefficients in the clock data recovery CDR circuit to enter the next frequency band;

[0060] In this step, when the output clock CLK of the voltage controlled oscillator VCO vco The frequency reaches the maximum value of the tuning range, and the clock CLK after the adjustable divider is divided div There is still a frequency error between the input signal frequency and the input signal frequency, that is, when the input signal frequency exceeds the frequency band range under the current adjustment coefficient, the configurable comparator will control the error voltage V of the voltage controlled oscillator VCO ctrl Compare with the preset threshold value, and when it is lower than the threshold value, the frequency band self-switching module is triggered to switch the frequency band automatically, and reset the error control voltage V of the voltage-controlled oscillator VCO. ctrl , and synchronously adjust the V / I converter gain coefficient, loop filter coefficient and divider frequency coefficient;

[0061] After the synchronous adjustment of each adjustable coefficient is completed, the clock data recovery CDR circuit uses the frequency detection circuit FD and the phase detection circuit PD to detect the frequency error and phase error again until the input signal is synchronized with the recovered clock, or the frequency band self-switching module is triggered to enter the next frequency band.

[0062] In a specific implementation, multiple frequency bands can be set according to the bandwidth index that the clock data recovery CDR circuit needs to meet, and there are overlapping parts when switching between frequency bands to avoid the need to re-perform the clock data recovery process after the frequency band is switched due to excessive jitter of the input signal.

[0063] Step 5: Use the recovered clock CLK of the input signal data The lock detection is performed in the decision circuit, and the recovered clock CLK is used after the lock detection is completed. data Recover the data in the input signal and complete the data and clock recovery in the input signal.

[0064] It is worth noting that the contents not described in detail in the embodiments of the present invention belong to the prior art known to those skilled in the art. For example, although the present invention may provide demonstrations of parameters including specific values, it should be understood that the parameters do not need to be exactly equal to the corresponding values, but can be approximated to the corresponding values ​​within an acceptable error tolerance or design constraint.

[0065] The following is a specific example to illustrate the circuit and frequency band adjustment method of the embodiment of the present invention. This example is based on a 130 nm CMOS process to complete the complete exemplary implementation of the present invention, which can cover the input signal rate of 400Mbps-1.2 Gbps. The transfer function of the clock data recovery CDR circuit described in this example is analyzed, and its closed-loop transfer function as follows:

[0066] (1)

[0067] Among them, K PFD K is the overall gain of the frequency detection circuit FD, the phase detection circuit PD and the adjustable voltage-to-current converter; PD Gain of frequency detection circuit FD; K VCO is the gain of the voltage controlled oscillator VCO; R is the resistance value in the adjustable loop filter LF; C is the capacitance value in the adjustable loop filter LF; N is the frequency division coefficient of the adjustable divider; S is a complex variable.

[0068] The closed loop transfer function Analysis, by adjusting K PFD , K VCO The parameter values ​​of K, R, C and N can adjust the gain of the clock data recovery CDR circuit, and further adjust the frequency band coverage of the clock data recovery CDR circuit; due to the adjustment of KVCO The voltage-controlled oscillator VCO needs to have multiple frequency bands, and the capacitor in the adjustable loop filter LF will occupy a large area. In a chip with a high degree of integration, K VCO and C are not suitable as adjustment factors.

[0069] Further analysis of the transfer function yields equations (2) and (3):

[0070] (2)

[0071] (3)

[0072] in: ,

[0073] Where C1 and C2 are the two capacitance values ​​in the adjustable loop filter LF; , are the variables introduced.

[0074] Therefore, the gain K of the voltage controlled oscillator VCO is VCO When the capacitance C in the adjustable loop filter LF is fixed, the following relationship can be obtained:

[0075] (4)

[0076] (5)

[0077] From formulas (4) and (5), we can see that: on the basis of ensuring loop stability, by synchronously changing the frequency division coefficient N of the adjustable divider, the gain K PFD With the adjustable resistance value R in the loop filter LF, clock and data recovery of input signals with a wide frequency range is achieved.

[0078] The tuning range of the voltage-controlled oscillator VCO selected in the circuit is 800 Mbps–2 Gbps to cover the maximum input signal data rate. To cover the minimum input signal data rate, the frequency band self-switching circuit is divided into five input signal bands, namely: when the divider is divided by 1, the frequency band coverage range is 800 Mbps–2 Gbps; when it is divided by 2, the frequency band coverage range is 400 Mbps–1Gbps; when it is divided by 4, the frequency band coverage range is 200 Mbps–500 Mbps; when it is divided by 8, the frequency band coverage range is 100 Mbps–250 Mbps; when it is divided by 16, the frequency band coverage range is 50 Mbps–125 Mbps.

[0079] The frequency band adjustment process of the wide frequency range CDR circuit based on frequency band self-switching in the above-mentioned example is as follows:

[0080] Step 1: After the frequency band self-switching circuit is powered on and reset, reset each module of the CDR circuit. First, set the adjustable divider adjustment coefficient to 16 division, the adjustable voltage-to-current converter gain coefficient to 1 gain, the adjustable loop filter LF adjustment coefficient to 16 times R value, and the voltage-controlled oscillator VCO error control voltage V ctrl Set to the maximum value of 1.2 V, the clock frequency generated by the voltage controlled oscillator VCO is at the lowest value of its tuning range, that is, 800 MHz.

[0081] After reset is completed, the initial clock CLK generated by the voltage-controlled oscillator VCO vco The buffer driver transmits the initial clock CLK to the adjustable divider. div is the lowest value of the frequency band of the CDR circuit, i.e. 50 MHz;

[0082] Step 2: Set the input signal data rate to 400 Mbps-1.2 Gbps. After being driven, the input signal enters the frequency detection circuit FD and the phase detection circuit PD respectively. In the frequency detection circuit FD, the input data is used to detect the initial clock CLK. div Sampling to generate frequency error signal V PD When the error signal range is small, switch to the phase detection circuit PD for phase alignment, and use the transition edge of the input signal in the phase detection circuit PD to align the initial clock CLK div Sampling is performed based on the input signal and CLK div The relationship between the leading, lagging or no data jump between them generates a phase error signal V FD ;

[0083] Step 3: Frequency Error Signal V PD and phase error signal V FD Separately control the V / I of the adjustable voltage-to-current converter PD Converters and V / I FD converter, the clock CLK div The frequency error and phase error of the input signal are converted into the corresponding charge and discharge current I CP ; The adjustable loop filter LF is connected to the charging and discharging current I CP Perform low-pass filtering to remove high-frequency components and obtain the error control voltage V of the voltage-controlled oscillator VCO with smaller fluctuations. ctrl .

[0084] The error control voltage V of the voltage controlled oscillator VCO at the output of the adjustable loop filter LF ctrl The output clock CLK is gradually increased. vco The frequency of the adjustable divider output clock CLK divAfter synchronous adjustment, the error detection is performed in the frequency detection circuit FD and the phase detection circuit PD to complete a clock feedback adjustment.

[0085] Step 4: When the output clock CLK of the voltage controlled oscillator VCO vco When the frequency reaches the maximum value of the tuning range, that is, 2GHz, the divided clock CLK div There is still a frequency error between 125 MHz and the input signal frequency, which exceeds the adjustable frequency band range of CDR under the current control coefficient. At this time, the frequency band self-switching function of the CDR circuit is triggered, and the error control voltage V ctrl Reset to 1.2 V and change the adjustable parameters of each module synchronously, that is, adjust the divider coefficient to 8, adjust the V / I conversion circuit gain to 2 times, and set the LF filter adjustment coefficient to 8 times R value. Adjust to the next frequency band and repeat the above steps until the divided clock CLK div The CDR circuit recovers the input signal synchronization clock CLK. data ;

[0086] Step 5: Use the recovered clock CLK of the input signal data The lock detection is performed in the decision circuit, and the recovered clock CLK is used after the lock detection is completed. data The data in the input signal is further recovered to complete the data and clock recovery in the input signal.

[0087] This example uses input signals with data rates of 400 Mbps and 1.2 Gbps as examples. Figure 3 The figure shows the synchronous clock eye diagram recovered from the 400 Mbps input signal in the example of the present invention, the peak-to-peak value of the clock jitter is 116 ps (0.046 UI), and the RMS (Root Mean Square) value of the jitter is 11.4 ps (0.0046 UI); Figure 4 The figure shows the synchronous clock eye diagram recovered from the 1.2 Gbps input signal of the example of the present invention. The peak-to-peak value of the clock jitter is 79 ps (0.094 UI), and the RMS value of the jitter is 18.45 ps (0.022 UI).

[0088] It can be seen that the CDR circuit based on frequency band self-switching in this example can realize clock and data recovery of input signals with data rates from 400 Mbps to 1.2 Gbps while ensuring loop stability.

[0089] In summary, the circuit and method described in the embodiments of the present invention have the following advantages:

[0090] 1) The circuit and method described in the embodiment of the present invention obtain adjustable parameters in the CDR loop under the premise of ensuring loop stability, and can meet the requirements of clock and data recovery for input signals in a wide frequency range;

[0091] 2) The frequency band self-switching method of the present application synchronously changes the frequency division ratio of the frequency division circuit in the CDR loop, and synchronously changes the circuit-related parameters. On the basis of ensuring the stability of the loop, it greatly expands the data rate range that the CDR circuit can receive, breaking through the data rate range limitation of the traditional CDR that only relies on the VCO's own pulling degree to achieve serial data reception;

[0092] 3) In this application, the parameter adjustment of the LF filter only requires changing the R value, and the fixed C value can maximize the control of the area of ​​the CDR circuit.

[0093] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims. The information disclosed in the background technology section of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or in any form that the information constitutes prior art known to those skilled in the art.

Claims

1. A wide frequency range clock data recovery circuit, characterized in that: The clock data recovery (CDR) circuit comprises: An adjustable voltage-to-current converter, used for adjusting an error conversion coefficient of the adjustable voltage-to-current converter when switching frequency bands; An adjustable loop filter LF, used for filtering the charging and discharging currents generated by the adjustable voltage-to-current converter; A voltage-controlled oscillator (VCO) is used to convert the average voltage component containing clock information into a change in the output clock frequency; An adjustable frequency divider for synchronously adjusting the frequency division coefficient when switching frequency bands; A frequency band self-switching circuit, used for performing self-switching of the frequency band using a frequency band automatic switching method according to a comparison result of a configurable comparator, and sending an adjustable coefficient corresponding to the switched frequency band to the adjustable voltage-current converter, the adjustable loop filter LF and the adjustable frequency divider; A data recovery circuit is used to sample input data using a divided clock. After the locking process is completed, the output result is the recovered data; The connection relationship between the various parts in the clock data recovery (CDR) circuit is as follows: The frequency detection circuit FD and the phase detection circuit PD have two input terminals respectively, one input terminal is connected to the input signal, and the other input terminal is connected to the recovered clock after the clock generated by the voltage controlled oscillator VCO is divided by the adjustable frequency divider; The output ends of the frequency detection circuit FD and the phase detection circuit PD are respectively connected to the input ends of the adjustable voltage-current converter, and the adjustable voltage-current converter is controlled to generate a charge-discharge current through the frequency error signal and the phase error signal; The adjustable control end of the adjustable resistor R in the adjustable loop filter LF is connected to the frequency band self-switching circuit, which is used to adjust the filter coefficient when the frequency band is switched; The clock signal at the output end of the voltage controlled oscillator VCO is connected to the input end of the adjustable frequency divider after being driven, and the output end of the adjustable frequency divider is respectively connected to the input end of the frequency detection circuit FD, the phase detection circuit PD, the data recovery circuit and the decision circuit; The input end of the frequency band self-switching circuit is connected to the comparison result output end of the configurable comparator, and the three groups of output ends are respectively connected to the adjustable voltage-current converter, the adjustable loop filter LF and the adjustable frequency divider; One input end of the data recovery circuit is connected to the frequency-divided clock output end of the adjustable frequency divider, and the other input end is connected to the input signal.

2. The wide frequency range clock data recovery circuit according to claim 1, characterized in that: The adjustable loop filter LF is composed of an adjustable resistor R and two capacitors C1 and C2, wherein: One end of the adjustable resistor R is connected to the phase charge and discharge current output end of the adjustable voltage-current converter and the charging end of the capacitor C2, and the other end is connected to the frequency charge and discharge current output end of the adjustable voltage-current converter and the charging end of the capacitor C1; The discharge terminals of capacitors C1 and C2 are grounded.

3. A frequency band adjustment method for a wide frequency range clock data recovery circuit, characterized in that: The method comprises: Step 1: After the frequency band self-switching module is powered on and reset, each module in the clock data recovery (CDR) circuit is reset; Step 2, the frequency detection circuit FD generates a corresponding frequency error signal based on the frequency error between the clock frequency of the recovered clock and the data rate of the input signal; the phase detection circuit PD generates a corresponding phase error signal based on the phase error between the clock phase of the recovered clock and the data sequence of the input signal; Step 3: Using the frequency error signal and the phase error signal, the adjustable voltage-to-current converter and the adjustable loop filter LF generate an error control voltage, so that the output clock of the voltage-controlled oscillator VCO is close to the input signal frequency, and the output clock of the adjustable frequency divider is synchronously adjusted, thus completing a clock feedback adjustment; Step 4, the frequency band self-switching module resets the error control voltage, and synchronously adjusts the various adjustable coefficients in the clock data recovery CDR circuit to enter the next frequency band; Step 5: Use the recovered clock CLK of the input signal data The lock detection is performed in the decision circuit, and the recovered clock CLK is used after the lock detection is completed. data Recover the data in the input signal and complete the data and clock recovery in the input signal; Among them, the connection relationship between the various parts in the clock data recovery CDR circuit is: The frequency detection circuit FD and the phase detection circuit PD have two input terminals respectively, one input terminal is connected to the input signal, and the other input terminal is connected to the recovered clock after the clock generated by the voltage controlled oscillator VCO is divided by the adjustable frequency divider; The output ends of the frequency detection circuit FD and the phase detection circuit PD are respectively connected to the input ends of the adjustable voltage-current converter, and the adjustable voltage-current converter is controlled to generate a charge-discharge current through the frequency error signal and the phase error signal; The adjustable control end of the adjustable resistor R in the adjustable loop filter LF is connected to the frequency band self-switching circuit, which is used to adjust the filter coefficient when the frequency band is switched; The clock signal at the output end of the voltage controlled oscillator VCO is connected to the input end of the adjustable frequency divider after being driven, and the output end of the adjustable frequency divider is respectively connected to the input end of the frequency detection circuit FD, the phase detection circuit PD, the data recovery circuit and the decision circuit; The input end of the frequency band self-switching circuit is connected to the comparison result output end of the configurable comparator, and the three groups of output ends are respectively connected to the adjustable voltage-current converter, the adjustable loop filter LF and the adjustable frequency divider; One input end of the data recovery circuit is connected to the frequency-divided clock output end of the adjustable frequency divider, and the other input end is connected to the input signal.

4. The frequency band adjustment method of the wide frequency range clock data recovery circuit as claimed in claim 3, characterized in that: In step 1, specifically, the adjustment coefficient of the adjustable frequency divider and the gain coefficient of the adjustable voltage-to-current converter are reset, that is, set to the highest value; the adjustment coefficient of the adjustable loop filter LF is reset, that is, set to the lowest value; the error control voltage V ctrl Set it to the highest value so that the clock frequency generated by the voltage-controlled oscillator VCO is at the lowest value of the tuning range; After reset is completed, the initial clock CLK generated by the voltage-controlled oscillator VCO vco After gain driving, it is transmitted to the adjustable divider, and the initial clock CLK divided by the adjustable divider is div This is the minimum value of the frequency band of the clock data recovery (CDR) circuit.

5. The frequency band adjustment method of the wide frequency range clock data recovery circuit as claimed in claim 4, characterized in that: In step 2, the input signal is driven to enter the frequency detection circuit FD and the phase detection circuit PD respectively; In the frequency detection circuit FD, the initial clock CLK is divided by the adjustable frequency divider. div The frequency error between the clock frequency and the input signal data rate generates a corresponding frequency error signal V PD ; When the error signal range is small, the phase detection circuit PD is switched to perform phase alignment. The phase detection circuit PD uses the transition edge of the input signal to align the initial clock CLK. div Sampling is performed based on the input signal and the initial clock CLK div The relationship between the leading, lagging or no data jump between them generates the corresponding phase error signal V FD .

6. The frequency band adjustment method of the wide frequency range clock data recovery circuit as claimed in claim 5, characterized in that: In step 3, the phase error signal V FD and frequency error signal V PD Separately control the V / I of the adjustable voltage-to-current converter FD Converters and V / I PD converter, the initial clock CLK div The phase error and frequency error of the input signal are converted into the corresponding charge and discharge current I CP ; The adjustable loop filter LF is used for charging and discharging current I CP Perform low-pass filtering to remove high-frequency components and obtain the error control voltage V of the voltage-controlled oscillator VCO. ctrl ; The voltage controlled oscillator VCO has an error control voltage V ctrl Under the control of the output clock CLK vco The frequency is adjusted synchronously with the adjustable divider output clock; then it enters the frequency detection circuit FD and the phase detection circuit PD for error detection, completing a clock feedback adjustment.

7. The frequency band adjustment method of the wide frequency range clock data recovery circuit as claimed in claim 6, characterized in that: In step 4, when the output clock CLK of the voltage controlled oscillator VCO vco The frequency reaches the maximum value of the tuning range, and the clock CLK after the adjustable divider is divided div There is still a frequency error between the input signal frequency and the input signal frequency, that is, when the input signal frequency exceeds the frequency band range under the current adjustment coefficient, the configurable comparator will control the error voltage V of the voltage controlled oscillator VCO ctrl Compare with the preset threshold value, and when it is lower than the threshold value, the frequency band self-switching module is triggered to switch the frequency band automatically, and the error control voltage V of the voltage-controlled oscillator VCO is reset. ctrl , and synchronously adjust the V / I converter gain coefficient, loop filter coefficient and divider frequency coefficient; After the synchronization adjustment of each coefficient is completed, the clock data recovery CDR circuit uses the frequency detection circuit FD and the phase detection circuit PD to detect the frequency error and phase error again until the input signal is synchronized with the recovered clock, or the frequency band self-switching module is triggered to enter the next frequency band.

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