Graphics processor simulation method and system

Abstract

The present invention provides a simulation method and system for a graphics processor. The method comprises: generating a first program code corresponding to a second type of graphics processor through a first application program interface; converting the first program code into a second program code corresponding to the first type of graphics processor through a second application program interface; generating an executable file corresponding to the first type of graphics processor based on the second program code through a compiler; establishing a simulation execution environment; instructing the first type of graphics processor to execute the executable file based on the simulation execution environment; and recording the execution status of the executable file. In this way, the execution result of the second type of graphics processor for the first program code can be effectively evaluated in the absence of the second type of graphics processor.

Description

Technical Field

[0001] The present invention relates to a processor simulation technology, and in particular to a graphics processor simulation method and system. Background Art

[0002] With the advancement of technology, people's requirements for computer information processing efficiency are gradually increasing. Therefore, new processors are continuously being developed to meet higher computing requirements than ever before. However, during the design and development phase of new processors, software developers also need to simultaneously develop related software or firmware based on the system architecture of the new processors to be used with the new processors. However, before obtaining test samples of the new processors, the software or firmware designed by software developers cannot be actually installed on the new processors for running tests.

[0003] In the prior art, before obtaining a test sample of a new processor, software developers generally verify the designed software or firmware through hardware simulation or software simulation. Among them, although the hardware simulation method can directly simulate the hardware test environment of the new processor, the hardware simulator needs to spend a lot of time and manpower to develop before the test sample of the new processor appears, which is not cost-effective in practice. On the other hand, the software simulation method is limited by the fact that the performance of the hardware executing the simulation program itself cannot match the performance of the new processor, so it cannot fully reflect the problems that may occur when the new processor runs the designed software or firmware.

[0004] Therefore, there is an urgent need for a new processor simulation technology to improve the problem that it is difficult to test software or firmware designed for the new processor in the traditional way. Summary of the invention

[0005] The invention provides a simulation method and system for a graphics processor, which can improve the problem that it is difficult to test software or firmware designed for a new processor in the traditional way.

[0006] An embodiment of the present invention provides a simulation method for a graphics processor, which includes: generating a first program code corresponding to a second type of graphics processor through a first application program interface; converting the first program code into a second program code corresponding to the first type of graphics processor through a second application program interface; generating an executable file corresponding to the first type of graphics processor based on the second program code through a compiler; establishing a simulation execution environment; instructing the first type of graphics processor to execute the executable file based on the simulation execution environment to simulate the behavior of the second type of graphics processor executing the first program code; and recording the execution status of the executable file.

[0007] Another embodiment of the present invention provides a graphics processor simulation system, which includes a processor and a storage circuit. The storage circuit is connected to the processor. The processor is used to execute the graphics processor simulation method.

[0008] Based on the above, after the first program code corresponding to the second type of graphics processor is generated through the first application program interface, the first program code can be automatically converted into the second program code corresponding to the first type of graphics processor through the second application program interface. Then, through the compiler, the executable file corresponding to the first type of graphics processor can be automatically generated based on the second program code. In addition, after the simulation execution environment is established, the first type of graphics processor can execute the executable file based on the simulation execution environment to simulate the behavior of the second type of graphics processor executing the first program code, and the execution status of the executable file can be recorded. In this way, the execution result of the second type of graphics processor for the first program code can be effectively evaluated in the absence of the second type of graphics processor (such as a new type of processor), thereby improving the problem that it is traditionally difficult to test software or firmware designed for the second type of graphics processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of a simulation system of a graphics processor according to an embodiment of the present invention;

[0010] Figure 2 is a schematic diagram of a simulation system for running a graphics processor according to an embodiment of the present invention;

[0011] Figure 3 is a schematic diagram of establishing a simulation execution environment according to an embodiment of the present invention;

[0012] Figure 4 is a schematic diagram of establishing a simulation execution environment according to an embodiment of the present invention;

[0013] Figure 5 is a schematic diagram of establishing a simulation execution environment according to an embodiment of the present invention;

[0014] Figure 6 FIG. 4 is a flowchart of a simulation method of a graphics processor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0016] As described above, in the prior art, before obtaining a test sample of a new processor, software developers generally verify the software or firmware running with the new processor through hardware simulation or software simulation. However, whether hardware simulation or software simulation is used to verify the designed software or firmware, there are cost, technical and / or performance defects.

[0017] The graphics processor simulation method and system proposed in the present invention can improve the problem that it is difficult to test software or firmware designed for new processors by performing automatic code conversion and simulating the execution environment of new graphics processors through existing graphics processors. Furthermore, the graphics processor simulation method and system proposed in the present invention can effectively evaluate the execution result of the new processor for the first program code when there is no new processor.

[0018] Figure 1 FIG. 1 is a schematic diagram of a simulation system of a graphics processor according to an embodiment of the present invention. Figure 1 The system (also referred to as a graphics processor simulation system) 10 can be implemented in a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a server, or a computer installed in any carrier, and the present invention is not limited thereto.

[0019] In one embodiment, the graphics processor simulation system 10 includes a processor 11 and a storage circuit 12. The processor 11 may be used to be responsible for the overall or partial operation of the graphics processor simulation system 10. For example, the processor 11 may include a central processing unit (CPU) or other programmable general-purpose or special-purpose microprocessor, a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD) or other similar devices or a combination of these devices.

[0020] The storage circuit 12 is connected to the processor 11. The storage circuit 12 is used to store data. For example, the storage circuit 12 may include a volatile storage circuit and a non-volatile storage circuit. The volatile storage circuit is used to store data volatilely. For example, the volatile storage circuit may include a random access memory (RAM) or a similar volatile storage medium. The non-volatile storage circuit is used to store data non-volatilely. For example, the non-volatile storage circuit may include a read-only memory (ROM), a solid state disk (SSD), a traditional hard disk drive (HDD) or a similar non-volatile storage medium.

[0021] In one embodiment, the graphics processor simulation system 10 may further include a graphics processor (also referred to as a first-type graphics processor) 13. The number of the first-type graphics processor 13 may be one or more, and the present invention is not limited thereto. In one embodiment, the graphics processor simulation system 10 does not have a new type of processor (also referred to as a second-type graphics processor) to be simulated (i.e., emulated).

[0022] In one embodiment, the GPU simulation system 10 may further include various circuits or devices required in practice, such as a communication circuit, a screen, a mouse, a keyboard, a touch panel, or a power management circuit, etc., which are not described in detail here.

[0023] In one embodiment, the storage circuit 12 may be used to store an application programming interface (API) (also referred to as a first application programming interface) 101, an application programming interface (also referred to as a second application programming interface) 102, and a compiler 103. The application programming interface 101 corresponds to the second type of graphics processor. The application programming interface 102 and the compiler 103 correspond to the first type of graphics processor 13.

[0024] In one embodiment, the processor 11 may run an application program interface 101. Through the application program interface 101, the processor 11 may generate a program code (also referred to as a first program code) corresponding to the second type of graphics processor. For example, the processor 11 may receive a user operation through a user interface (not shown). The user operation is used to execute the writing of the program code. According to the user operation, the processor 11 may generate the first program code through the application program interface 101.

[0025] In one embodiment, the first program code may be used to instruct the second type of graphics processor to perform at least one operation (also referred to as a target operation). For example, the target operation may include a logical operation and / or access to a memory. In addition, the type of target operation that the first program code may instruct the second type of graphics processor to perform is not limited thereto.

[0026] It should be noted that the first program code is designed or written to be used with the second type of graphics processor (e.g., executed by the second type of graphics processor) to comply with the operating characteristics (or operating logic) of the second type of graphics processor. For example, the user may design the first program code based on the second type of graphics processor that is expected to be used in the future (e.g., the system architecture or computing architecture of the second type of graphics processor). Alternatively, from another perspective, the first program code is not designed or written to be used with the first type of graphics processor 13 (e.g., executed by the first type of graphics processor 13). Therefore, the first program code may not comply with the operating characteristics (or operating logic) of the first type of graphics processor 13.

[0027] In one embodiment, the processor 11 may run the application program interface 102. Through the application program interface 102, the processor 11 may automatically convert the first program code into a program code corresponding to the first type of graphics processor 13 (also referred to as the second program code). For example, the code content of the first program code may be different from the code content of the second program code. For example, compared with the first program code, the second program code is designed or written to be used with the first type of graphics processor 13 (for example, executed by the first type of graphics processor 13) to conform to the operating characteristics (or operating logic) of the first type of graphics processor 13. In one embodiment, through the application program interface 102, the processor 11 may automatically generate the second program code according to the first program code.

[0028] In one embodiment, during the execution of code conversion, the application program interface 102 may query or reference a code conversion model (or a code conversion program). The code conversion model (or the code conversion program) may be used to replace at least a portion of the code (also referred to as the first sub-code) in the first program code with a specific code (also referred to as the second sub-code) to generate a second program code. In this way, compared with the first sub-code, the second sub-code is more suitable for instructing the first type graphics processor 13 to perform the target operation. In one embodiment, through the application program interface 102, the processor 11 may replace the first sub-code in the first program code with the corresponding second sub-code one by one to generate the second program code.

[0029] In one embodiment, the processor 11 may run a compiler 103. Through the compiler 103, the processor 11 may generate an executable file 104 corresponding to the first type graphics processor 13 based on the second program code. For example, the executable file 104 may include binary code. The processor 11 may store the executable file 104 in the storage circuit 12.

[0030] In one embodiment, the processor 11 may establish an execution environment (also referred to as a simulation execution environment) 105 corresponding to the first type of graphics processor 13 in the storage circuit 12. The simulation execution environment 105 may be used to simulate the execution environment corresponding to the second type of graphics processor. Then, the processor 11 may instruct the first type of graphics processor 13 to execute the executable file 104 based on the simulation execution environment 105 to simulate the behavior of the second type of graphics processor executing the first program code.

[0031] In one embodiment, the processor 11 may record the execution status of the executable file 104. For example, the execution status of the executable file 104 may reflect the result of the first type of graphics processor 13 executing the executable file 104 based on the simulation execution environment 105. For example, the processor 11 may record the execution status of the executable file 104 in log information. Thereafter, the developer may evaluate whether the behavior of the simulated second type of graphics processor executing the first program code is erroneous or defective based on the log information. If the behavior of the simulated second type of graphics processor executing the first program code is erroneous or defective, the developer may try to modify the first program code and repeat the above operation through the simulation system 10 of the graphics processor until the design, writing or optimization of the first program code is completed.

[0032] Figure 2 FIG. 1 is a schematic diagram of a simulation system for running a graphics processor according to an embodiment of the present invention. Figure 1 and Figure 2In one embodiment, the processor 11 can generate a program code 21 (i.e., a first program code) corresponding to the second type of graphics processor through an application program interface 101 corresponding to a non-existent second type of graphics processor (i.e., a new type of graphics processor). Through an application program interface 102 corresponding to the first type of graphics processor 13 (i.e., an existing graphics processor), the processor 11 can automatically convert the first program code into a program code 22 (i.e., a second program code) corresponding to the first type of graphics processor 13. Then, through a compiler 103, the processor 11 can generate an executable file 104 corresponding to the first type of graphics processor based on the second program code. At the same time, the processor 11 can establish a simulation execution environment 105 to simulate the execution environment corresponding to the second type of graphics processor. After obtaining the executable file 104 and establishing the simulation execution environment 105, the processor 11 can instruct the first type of graphics processor 13 to execute the executable file 104 based on the simulation execution environment 105 to simulate the behavior of the second type of graphics processor executing the program code 21. Thereafter, according to the execution result of the simulated second type of graphics processor for the first program code, the developer can efficiently modify and / or optimize the first program code.

[0033] In other words, even if the second-type graphics processor does not exist at present, by simulating the behavior of the second-type graphics processor executing the program code 21 by using the first-type graphics processor 13 with similar characteristics and / or hardware performance in combination with the simulation execution environment 105, the first program code designed to be executed by the second-type graphics processor can be modified and / or optimized efficiently. In this way, the problem of the difficulty in testing software or firmware designed for the second-type graphics processor (i.e., the new processor) can be improved.

[0034] Figure 3 FIG. 1 is a schematic diagram of establishing a simulation execution environment according to an embodiment of the present invention. Figure 1 and Figure 3 In one embodiment, the first type of graphics processor 13 includes operation units 31 (1) to 31 (n). The total number of operation units 31 (1) to 31 (n) can be set according to practical needs, and the present invention is not limited thereto. The operation units 31 (1) to 31 (n) respectively include memories (also referred to as internal memories) 301 (1) to 301 (n). For example, the memory 301 (i) can be set inside the operation unit 31 (i), where i is any integer from 1 to n. In addition, it is assumed that the storage circuit 12 includes a memory (also referred to as an external memory) 32. For example, the memory 301 (i) and the memory 32 can both include random access memory or other types of memory.

[0035] In one embodiment, the processor 11 may use the memory 32 to simulate the memories 301(1)-301(n) to establish the simulation execution environment 105. For example, the processor 11 may divide the memory 32 into storage spaces 302(1)-302(n). The processor 11 may use the storage spaces 302(1)-302(n) to respectively simulate the storage spaces of the memories 301(1)-301(n). For example, the storage space (also referred to as the first storage space) 302(j) may be used to simulate the storage space of the memory (also referred to as the first internal memory) 301(j), and the storage space (also referred to as the second storage space) 302(k) may be used to simulate the storage space of the memory (also referred to as the second internal memory) 301(k), wherein j is any integer from 1 to n, k is any integer from 1 to n, and j is not equal to k.

[0036] In other words, in the simulation execution environment 105, the storage space 302(j) can be used to replace the storage space of the memory 301(j), and the storage space 302(k) can be used to replace the storage space of the memory 301(k). That is, in the simulation execution environment 105, the access to the memory 301(j) by default will be directed or replaced by the access to the storage space 302(j), and the access to the memory 301(k) by default will be directed or replaced by the access to the storage space 302(k).

[0037] In one embodiment, the processor 11 may bind the storage space 302(j) to the index information (also referred to as the first index information) corresponding to the operation unit (also referred to as the first operation unit) 31(j) to establish an access mechanism corresponding to the storage space 302(j). Thereafter, when at least one of the operation units 31(1)-31(n) (also referred to as the first target operation unit) wants to access (e.g., store or store) the storage space 302(j), the processor 11 (or the memory controller) may determine the storage space 302(j) from the memory 32 according to the first index information. For example, according to the first index information and the capacity of the divided single storage space, the processor 11 may determine the location (e.g., offset value) of the storage space 302(j) in the memory 32. Then, the processor 11 (or the memory controller) may read and / or write data to the storage space 302(j).

[0038] On the other hand, the processor 11 may bind the storage space 302(k) to the index information (also referred to as the second index information) corresponding to the operation unit (also referred to as the second operation unit) 31(k) to establish an access mechanism corresponding to the storage space 302(k). Thereafter, when at least one of the operation units 31(1)-31(n) (i.e., the first target operation unit) wants to access (e.g., store or store data in) the storage space 302(k), the processor 11 (or the memory controller) may determine the storage space 302(k) from the memory 32 according to the second index information and perform data reading and / or writing on the storage space 302(k).

[0039] In one embodiment, due to the inherent characteristics (e.g., hardware architecture) of the first-type graphics processor 13, the first-type graphics processor 13 does not support cross-processing unit access to the memories 301(1)-301(n). For example, due to the inherent characteristics (e.g., hardware architecture) of the first-type graphics processor 13, the processing unit 31(j) cannot access (e.g., store / receive) the internal memory 301(k) of the processing unit 31(k). However, the second-type graphics processor to be simulated can support cross-processing unit access to the internal memory.

[0040] In one embodiment, in the simulation execution environment 105, even if the hardware of the first type of graphics processor 13 is currently used as the execution subject to simulate the second type of graphics processor to execute the first program code, the established simulation execution environment 105 can enable the first type of graphics processor 13 to support cross-calculation unit access to the internal memory. In this way, the simulation operation executed by the first type of graphics processor 13 can be closer to the behavior of the second type of graphics processor actually executing the first program code, thereby effectively improving the simulation accuracy.

[0041] Figure 4 FIG. 1 is a schematic diagram of establishing a simulation execution environment according to an embodiment of the present invention. Figure 1 , Figure 3 and Figure 4 In one embodiment, the processor 11 may change the arrangement of data in the memory 32 to establish the simulation execution environment 105. For example, assume that the data D1(1)-D1(4), D2(1)-D2(4), D3(1)-D3(4) and D4(1)-D4(4) are preset to be stored in at least one of the memories 301(1)-301(n) based on the arrangement 41. In the simulation execution environment 105, the processor 11 may adjust the data D1(1)-D1(4), D2(1)-D2(4), D3(1)-D3(4) and D4(1)-D4(4) to be stored in at least one of the storage spaces 302(1)-302(n) based on the arrangement 42.

[0042] Compared with arrangement 41, arrangement 42 is helpful for simulating batch access to data D1(1)-D1(4), D2(1)-D2(4), D3(1)-D3(4) and / or D4(1)-D4(4) which is not supported by the first type GPU 13 but supported by the second type GPU. Thus, the simulation operation executed by the first type GPU 13 can be closer to the behavior of the second type GPU actually executing the first program code, thereby effectively improving the simulation accuracy.

[0043] Figure 5 FIG. 1 is a schematic diagram of establishing a simulation execution environment according to an embodiment of the present invention. Figure 1 and Figure 5 In one embodiment, the memories 301(1)-301(n) include barrier caches 401(1)-401(n) respectively. The barrier cache 401(i) is used to store barrier data corresponding to the operation unit 31(i). For example, the barrier data stored in the barrier cache 401(i) can be used to control whether the operation unit 31(i) can continue to execute the next task in the schedule.

[0044] In one embodiment, when using the memory 32 to simulate the operation of the memories 301(1)-301(n), the processor 11 may divide the barrier cache spaces 402(1)-402(n) in the memory 32. The barrier cache spaces 402(1)-402(n) may be used to simulate the barrier caches 401(1)-401(n), respectively. Thereafter, in the simulation execution environment 105, the barrier cache spaces 402(1)-402(n) may be used to replace the barrier caches 401(1)-401(n) in the operation units 31(1)-31(n), respectively.

[0045] In one embodiment, the processor 11 may bind the barrier cache space 402 (j) to the index information (i.e., the first index information) corresponding to the operation unit 31 (j) to establish an access mechanism corresponding to the barrier cache space 402 (j). Thereafter, the processor 11 may determine the barrier cache space 402 (j) from the memory 32 according to the first index information and access (or update) the barrier data in the barrier cache space 402 (j). Similarly, the processor 11 may bind the barrier cache space 402 (k) to the index information (i.e., the second index information) corresponding to the operation unit 31 (k) to establish an access mechanism corresponding to the barrier cache space 402 (k). Thereafter, the processor 11 may determine the barrier cache space 402 (k) from the memory 32 according to the second index information and access (or update) the barrier data in the barrier cache space 402 (k).

[0046] In one embodiment, due to the characteristics of the first-type graphics processor 13 itself (e.g., hardware architecture), the first-type graphics processor 13 does not support cross-operating unit access to the barrier cache 401 (1) ~ 401 (n). For example, due to the characteristics of the first-type graphics processor 13 itself (e.g., hardware architecture), the operating unit 31 (j) cannot access (e.g., access) the barrier cache 401 (k) inside the operating unit 31 (k). However, the second-type graphics processor to be simulated can support cross-operating unit access to the barrier cache. For example, by performing cross-operating unit access to the barrier cache (e.g., updating barrier data across operating units), the second-type graphics processor can synchronize and control the threads of multiple operating units.

[0047] In one embodiment, in the simulation execution environment 105, even if the hardware of the first type of graphics processor 13 is currently used as the execution subject to simulate the second type of graphics processor executing the first program code, the established simulation execution environment 105 can enable the first type of graphics processor 13 to support access to the barrier cache across computing units, so as to simulate the thread synchronization control of multiple computing units supported by the second type of graphics processor. In this way, the simulation operation executed by the first type of graphics processor 13 can also be made closer to the behavior of the second type of graphics processor actually executing the first program code, thereby effectively improving the simulation accuracy.

[0048] Please go back Figure 2 In one embodiment, after the program code 21 (i.e., the first program code) is converted into the program code 22 (i.e., the second program code), the operation instructing the first type of graphics processor 13 to execute in the program code 22 will match the configuration in the simulation execution environment 105. Figure 3 For example, suppose that originally in the program code 21, the operation indicated by a first subcode includes access to the memory 301 (i). In the process of generating the program code 22, by replacing the first subcode with the second subcode, the access to the memory 301 (i) will be replaced by access to the storage space 302 (i) in the program code 22. Thus, after the executable file 104 corresponding to the program code 22 is generated, by executing the executable file 104, in the case where the second type of graphics processor is supposed to access a specific memory (e.g., the memory 301 (i)), the first type of graphics processor 13 can access the storage space 302 (i) instead of the memory 301 (i).

[0049] akin, Figure 4 and Figure 5The changes in the operation behavior of the first-type graphics processor 13 caused by operating in the simulation execution environment 105 shown in the embodiment can be achieved by replacing the corresponding first sub-code with an appropriate second sub-code to drive the first-type graphics processor 13 to subsequently perform the specified action. In this way, the compatibility of the first-type graphics processor 13 when operating with the simulation execution environment 105 can be improved, and the stability of the system operation can be improved.

[0050] Figure 6 FIG. 1 is a flowchart of a simulation method of a graphics processor according to an embodiment of the present invention. Figure 6 In step S601, a first program code corresponding to the second type of graphics processor is generated through a first application program interface. In step S602, the first program code is converted into a second program code corresponding to the first type of graphics processor through a second application program interface. In step S603, an executable file corresponding to the first type of graphics processor is generated based on the second program code through a compiler. In step S604, a simulation execution environment is established. In step S605, the first type of graphics processor is instructed to execute the executable file based on the simulation execution environment to simulate the behavior of the second type of graphics processor executing the first program code. In step S606, the execution status of the executable file is recorded.

[0051] However, Figure 6 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Figure 6 Each step in the above process can be implemented as multiple program codes or circuits, which is not limited by the present invention. Figure 6 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0052] In summary, the graphics processor simulation method and system provided in the embodiments of the present invention can improve the problem that it is difficult to test software or firmware designed for new processors by performing automatic code conversion and simulating the execution environment of new graphics processors through existing graphics processors. Furthermore, the graphics processor simulation method and system proposed in the present invention can effectively evaluate the execution result of the new processor for the first program code when there is no new processor.

[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for simulating a graphics processor, characterized in that: include: Generate a first program code corresponding to the second type of graphics processor through a first application program interface; converting the first program code into a second program code corresponding to a first type of graphics processor through a second application program interface; Generate, by a compiler, an executable file corresponding to the first type of graphics processor based on the second program code; Establishing a simulation execution environment, including: changing the arrangement of data in the external memory to simulate batch access to the data supported by the second type of graphics processor; instructing the first-type graphics processor to execute the executable file based on the simulation execution environment to simulate the behavior of the second-type graphics processor executing the first program code; and Record the execution status of the executable file.

2. The method for simulating a graphics processor according to claim 1, characterized in that: The first program code is used to instruct the second-type graphics processor to execute at least one target operation.

3. The method for simulating a graphics processor according to claim 1, characterized in that: The step of converting the first program code into the second program code corresponding to the first type of graphics processor through the second application program interface includes: The first subcode in the first program code is replaced by the second subcode to generate the second program code.

4. The method for simulating a graphics processor according to claim 3, characterized in that: Compared with the first sub-code, the second sub-code is more suitable for instructing the first-type graphics processor to execute at least one target operation.

5. The method for simulating a graphics processor according to claim 1, characterized in that: The first type of graphics processor includes a plurality of computing units, and the step of establishing the simulation execution environment further includes: The external memory is used to emulate internal memories of the plurality of operation units.

6. The method for simulating a graphics processor according to claim 5, characterized in that: The plurality of operation units include a first operation unit and a second operation unit, the internal memory includes a first internal memory and a second internal memory, the first internal memory is arranged in the first operation unit, the second internal memory is arranged in the second operation unit, and the step of using the external memory to simulate the internal memories of the plurality of operation units includes: dividing a first storage space and a second storage space in the external memory; Using the first storage space to simulate the storage space of the first internal memory; and The second storage space is used to simulate a storage space of the second internal memory.

7. The method for simulating a graphics processor according to claim 6, characterized in that: The step of using the external memory to simulate the internal memory of the plurality of computing units also includes: Binding the first storage space to first index information corresponding to the first operation unit to establish an access mechanism corresponding to the first storage space; and The second storage space is bound to second index information corresponding to the second operation unit to establish an access mechanism corresponding to the second storage space.

8. The method for simulating a graphics processor according to claim 1, characterized in that: The first type of graphics processor includes a plurality of computing units, and the steps of establishing the simulation execution environment include: An external memory is used to simulate the barrier caches of the multiple computing units, so as to simulate the thread synchronization control of the multiple computing units supported by the second-type graphics processor.

9. A graphics processor simulation system, characterized in that: include: processor; as well as a storage circuit connected to the processor, The processor is used to execute the graphics processor simulation method according to any one of claims 1 to 8.

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