Delay compensation circuit, method and computer storage medium based on ADC sampling

Abstract

The present application proposes a delay compensation circuit, method and computer storage medium based on ADC sampling. By implementing the method of the embodiment of the present application: obtaining a first frequency of an input signal and setting a first sampling time range; controlling the first switch of a compensation module to be disconnected to disconnect the electrical connection between an input module and a bias module; controlling the second switch of the compensation module to continuously perform on-off operations based on the first frequency; controlling an analog-to-digital converter to sample a first electrical signal at a sampling target position within a first sampling time range with a first step length; and analyzing based on the first electrical signal, the first step length and the first sampling time range to obtain a first target delay result, delay compensation can be performed on circuits with different structures. The circuit using the present method has high compatibility. The present method and circuit can also be used for delay compensation based on different ADC sampling circuit structures, which is beneficial to improving the accuracy of delay compensation.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and in particular to a delay compensation circuit, method and computer storage medium based on ADC sampling. Background Art

[0002] With the development of power devices, their power levels have increased, and the corresponding switching frequency and corresponding control requirements have become higher and higher, which has brought about an increase in the sampling requirements of analog-to-digital converters. The accuracy and real-time performance of sampling need to be guaranteed. In practical applications, in order to ensure the accuracy of sampling, a certain amount of filtering will be appropriately added, which will cause a certain delay in data sampling. At low switching frequencies, this delay accounts for a small proportion and is mostly ignored, but when the switching frequency is high, this delay will have a great impact on sampling.

[0003] There are two traditional delay compensation methods. The first is to estimate the delay time based on the RC parameters of the circuit. As a delay parameter, the delay parameter obtained by this method is only an approximate value and cannot accurately reflect the delay parameter. The second is the actual measurement method, which measures the delay based on the actual input and output. As a circuit delay parameter, the parameters measured by this method are only suitable for this circuit, and there will be differences between different circuits. At the same time, after running for a period of time, the device parameters will also change, and the compensation value parameters will deviate from the actual value. Summary of the invention

[0004] The embodiments of the present application provide a delay compensation circuit, method and computer storage medium based on ADC sampling, which can make the delay compensation more accurate and more versatile.

[0005] In a first aspect, an embodiment of the present application provides a delay compensation circuit based on ADC sampling, the circuit comprising: a compensation module, a bias module and a processing module; a first end of the compensation module is connected to a first end of the bias module; a second end of the bias module is connected to a first end of the processing module; wherein,

[0006] The compensation module is used to generate a first electrical signal. The compensation module includes a first switch, a second switch and a first resistor. The first end of the first switch is used for signal input. The first end of the second switch is grounded. The second end of the second switch is connected to the first end of the first resistor. The second end of the first resistor is connected to the first end of the bias module as the first end of the compensation module.

[0007] The bias module is used to perform signal bias processing on the first electrical signal to obtain a second electrical signal, and the bias module includes a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, and a first operational amplifier; wherein the first end of the second resistor is connected to the second end of the first switch as the third end of the bias module, and the second end of the second resistor is connected to the first end of the first operational amplifier; the first end of the first operational amplifier is also connected to the second end of the first resistor as the first end of the bias module; the first end of the third resistor is connected to the reference voltage end, the second end of the third resistor is connected to the second end of the first operational amplifier, the first end of the first capacitor is connected to the first end of the first operational amplifier, and the second end of the first capacitor is grounded; the first end of the first operational amplifier is connected to the third end of the first operational amplifier, the third end of the first operational amplifier is connected to the first end of the third resistor, the first end of the second capacitor is respectively connected to the second end of the fourth resistor and the first end of the processing module, and the second end of the second capacitor is grounded;

[0008] The processing module is used to calculate the second electrical signal to obtain a target delay result.

[0009] In a possible embodiment, the circuit also includes an input module, the input end of the input module is connected to the third end of the bias module; wherein the input signal input by the input module is a signal to be delayed compensated; and the first end of the first switch is connected to the input end of the input module.

[0010] In a possible embodiment, the processing module includes a controller and an analog-to-digital converter, a first end of the analog-to-digital converter is connected to the first end of the second capacitor and the second end of the fourth resistor as the first end of the processing module, and a second end of the analog-to-digital converter is connected to the controller;

[0011] The controller is used to obtain a first frequency of an input signal, generate a second frequency according to the first frequency, and control the second switch to switch at the second frequency; the controller is also used to control the first switch to switch;

[0012] When the first switch is closed, the input terminal of the input module and the third terminal of the bias module are disconnected.

[0013] In a second aspect, an embodiment of the present application provides a delay compensation method based on ADC sampling, which is applied to a controller of a delay compensation system, wherein the controller is located in a processing module of the delay compensation system, and the delay compensation system further includes an input module, a compensation module, a bias module, and an analog-to-digital converter having a sequential connection relationship, wherein the analog-to-digital converter is located in the processing module, and the second end of the analog-to-digital converter is connected to the controller, and the first end of the analog-to-digital converter serves as the first end of the processing module. The compensation module includes a second switch, a first switch, and a first resistor, wherein the first end of the second switch is grounded, the second end of the second switch is connected to the first end of the first resistor, the first end of the first switch is connected to the input end of the input module, the second end of the first switch is connected to the third end of the bias module, the second end of the first resistor is connected to the first end of the bias module as the first end of the compensation module, and the second end of the bias module is connected to the first end of the processing module; the method includes:

[0014] Obtaining a first frequency of an input signal and setting a first sampling time range, wherein the input signal is generated by an input module, and the first sampling time range is used to limit the sampling time length of an analog-to-digital converter, and the analog-to-digital converter is used to sample an analog signal and convert the signal into a digital signal;

[0015] Controlling the first switch of the compensation module to be turned off to disconnect the electrical connection between the input module and the bias module;

[0016] Controlling the second switch of the compensation module to continuously perform on-off operations based on the first frequency;

[0017] Controlling the analog-to-digital converter to sample a first electrical signal at a sampling target position within a first sampling time range with a first step length, wherein the first electrical signal is an analog signal;

[0018] A first target delay result is obtained by analyzing the first electrical signal, the first step length, and the first sampling time range, and the input signal is delayed compensated by the first target delay result.

[0019] In a possible embodiment, obtaining a first target delay result by analyzing the first electrical signal includes:

[0020] Acquire a second electrical signal, where the second electrical signal is a digital signal processed by a bias module and an analog-to-digital converter;

[0021] generating a first waveform diagram of a sampling target position according to the second electrical signal and the first step length;

[0022] A first target delay result is obtained according to the rising edge of the first waveform of the sampling target position, the first step length, and the reference waveform.

[0023] In a possible embodiment, the method further includes:

[0024] Controlling the analog-to-digital converter to sample the third electrical signal at the sampling target position within a second sampling time range with a second step length, wherein the second sampling time range is used to limit the sampling time length of the controller;

[0025] A second target delay result is obtained by analyzing the third electrical signal, the second step length, and the second sampling time range, and the input signal is delayed compensated again with the second target delay result.

[0026] In a third aspect, an embodiment of the present application provides a delay compensation device based on ADC sampling, which is applied to a controller of a delay compensation system, wherein the controller is located in a processing module of the delay compensation system, and the delay compensation system further includes an input module, a compensation module, a bias module, and a processing module analog-to-digital converter having a sequential connection relationship, wherein the analog-to-digital converter is located in the processing module, and the second end of the analog-to-digital converter is connected to the controller, and the first end of the analog-to-digital converter serves as the first end of the processing module, the compensation module includes a second switch, a first switch, and a first resistor, and the processing module includes a controller, wherein the first end of the second switch is grounded, the second end of the second switch is connected to the first end of the first resistor, the first end of the first switch is connected to the input end of the input module, the second end of the first switch is connected to the third end of the bias module, the second end of the first resistor is connected to the first end of the bias module as the first end of the compensation module, and the second end of the bias module is connected to the first end of the processing module; the device includes:

[0027] an acquisition module, used to acquire a first frequency of an input signal generated by the input module, and to set a first sampling time range, wherein the first sampling time range is used to limit a sampling time length of the analog-to-digital converter, and the analog-to-digital converter is used to sample an analog signal and convert the signal into a digital signal;

[0028] A first control module, used for controlling the first switch of the compensation module to be disconnected, so as to disconnect the electrical connection state between the input module and the bias module;

[0029] A second control module, used for controlling the second switch of the compensation module to continuously perform on-off operations based on the first frequency;

[0030] A sampling module, used for controlling the analog-to-digital converter to sample a first electrical signal at a sampling target position within a first sampling time range with a first step length, wherein the first electrical signal is an analog signal;

[0031] The analysis module is used to obtain a first target delay result by analyzing the first electrical signal, the first step length and the first sampling time range, and to perform delay compensation on the input signal with the first target delay result.

[0032] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium on which a delay compensation program is stored. The delay compensation program includes program instructions, which, when executed by a processor, cause the processor to execute some or all of the steps described in the second aspect.

[0033] In a fifth aspect, an embodiment of the present application provides a computer program product, wherein the computer program product includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute some or all of the steps described in the second aspect of the embodiment of the present application. The computer program product may be a software installation package.

[0034] It can be seen that the delay compensation method based on ADC sampling described in the present application is applied to the controller of the delay compensation system, and the delay compensation system also includes an input module, a compensation module, a bias module, and, obtains the first frequency of the input signal, and sets the first sampling time range, the input signal is generated by the input module, and the first sampling time range is used to limit the time length of the controller sampling; the first switch of the control compensation module is disconnected to disconnect the electrical connection state between the input module and the bias module; the second switch of the control compensation module is continuously turned on and off based on the first frequency; the analog-to-digital converter is controlled to sample the first electrical signal of the sampling target position within the first sampling time range with the first step length; based on the first electrical signal, the first step length and the first sampling time range, the first target delay result is analyzed to obtain the first target delay result, and the input signal is delayed compensated with the first target delay result. In this way, the method can be used to compensate for the delay of circuits with different structures, and the circuit using the method has high compatibility. The method and circuit can also be used for delay compensation based on different ADC sampling circuit structures, which is conducive to improving the accuracy of delay compensation. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background technology, the drawings required for use in the embodiments of the present invention or the background technology will be described below.

[0036] Figure 1 It is a circuit architecture diagram of a delay compensation circuit based on ADC sampling provided in an embodiment of the present application;

[0037] Figure 2 It is a structural schematic diagram of a delay compensation circuit based on ADC sampling provided in an embodiment of the present application;

[0038] Figure 3It is a structural schematic diagram of another delay compensation circuit based on ADC sampling provided in an embodiment of the present application;

[0039] Figure 4 It is a flowchart of a delay compensation method based on ADC sampling provided in an embodiment of the present application;

[0040] Figure 5 It is a waveform diagram based on ADC sampling provided in an embodiment of the present application;

[0041] Figure 6 It is a structural schematic diagram of a delay compensation device based on ADC sampling proposed in an embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0043] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or electronic device that includes a series of steps or units is not limited to the listed steps or units, but in an optional example also includes steps or units that are not listed, or in an optional example also includes other steps or units inherent to these processes, methods, products, or electronic devices.

[0044] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0045] The following is a brief introduction to the relevant names involved in this application:

[0046] ADC: Analog-to-Digital Converter, its main function is to convert continuously changing analog signals into discrete digital signals. The working principle of ADC is usually to periodically sample the input analog voltage and quantize each sampled value into a corresponding digital code.

[0047] See also Figure 1 , Figure 1 is a circuit architecture diagram of a delay compensation circuit based on ADC sampling provided in an embodiment of the present application, such as Figure 1 As shown, the delay compensation circuit 100 based on ADC sampling includes: a compensation module 110, a bias module 120 and a processing module 130; the first end of the compensation module 110 is connected to the first end of the bias module 120; the second end of the bias module 120 is connected to the first end of the processing module 130; wherein,

[0048] The compensation module 110 is used to generate a first electrical signal; the bias module 120 is used to perform signal bias processing on the first electrical signal to obtain a second electrical signal; and the processing module 130 is used to calculate the second electrical signal to obtain a target delay result.

[0049] Among them, when the delay compensation circuit 100 based on ADC sampling performs delay compensation, the compensation module 110 can be program-controlled by the processing module 130, and the control can be through wireless sensing control or circuit connection control. The processing module 130 controls the compensation module 110 so that there is an electrical signal in the circuit. The bias module 120 collects the first electrical signal in the circuit, and biases the first electrical signal to obtain a second electrical signal, and then transmits the second electrical signal to the processing module 130. The processing module 130 performs delay calculation based on the second electrical signal to obtain the target delay result.

[0050] It should be noted that the above-mentioned bias operation refers to setting an appropriate static voltage or current for the circuit by using appropriate circuit elements and techniques, so that the circuit can have a stable and reliable output under normal working conditions. Its main function is to shift the operating point of the AC signal amplifier circuit to a suitable range to ensure that the signal can be correctly amplified and kept in the linear region. The bias operation in this scheme can be a DC bias operation, because the input AC signal has positive and negative polarities, and the DC bias operation can convert the signal with positive and negative polarities into a signal with only a single polarity, such as only positive polarity.

[0051] In one possible embodiment, see Figure 2 , Figure 2 is a schematic diagram of a delay compensation circuit based on ADC sampling provided in an embodiment of the present application, such as Figure 2As shown, the circuit further includes an input module, the input end of the input module is connected to the third end of the bias module 120; wherein the input signal input by the input module is a signal to be delayed compensated.

[0052] Among them, the input module is used to input an electrical signal with an amplified amplitude. The electrical signal output by the input module has a certain frequency, which may come from a specific power electronic device in the input module. For example, the frequency of the input signal can be the switching frequency of the power device. The above-mentioned power device includes a MOS tube, an IGBT, etc. The above-mentioned power device can also be other devices, which are not limited here. It should be noted that the above-mentioned IGBT is the abbreviation of insulated gate bipolar transistor (IGBT), which is a composite fully controlled voltage-driven power semiconductor device. The above-mentioned MOS tube is called metal-oxide-semiconductor field-effect transistor (MOS), which is a semiconductor device that uses electric field effect to control current.

[0053] In one possible embodiment, see Figure 2 The compensation module 110 includes: a first switch K1, a second switch K2 and a first resistor R1; the first end of the second switch K2 is grounded, and the second end of the second switch K2 is connected to the first end of the first resistor R1; the first end of the first switch K1 is connected to the input end of the input module, and the second end of the first switch K1 is connected to the third end of the bias module 120; the second end of the first resistor is connected to the first end of the bias module 120 as the first end of the compensation module 110.

[0054] The input module and the third end of the bias module 120 are connected via a first switch K1 .

[0055] The first switch K1 and the second switch K2 may be devices with on / off functions that can be wirelessly controlled, or devices with on / off functions that can be connected by wires; specifically, they may be mechanical switches, electronic switches, photoelectric switches, etc. Specifically, they may be push switches, CMOS switches, or optical MOS switches, etc. The on-resistance of the CMOS switches and optical MOS switches is negligible compared to the circuit impedance. The first switch K1 and the second switch K2 may be the same switch or different switches, which are not specifically limited here.

[0056] It should be noted that a CMOS (complementary metal-oxide-semiconductor) switch is an electronic switch made of complementary metal oxide semiconductor technology. It usually consists of a P channel and an N channel. When the control signal is at a high level, the N channel is turned on, the P channel is turned off, and the switch is turned on; when the control signal is at a low level, the P channel is turned on, the N channel is turned off, and the switch is turned off. An optical MOS (metal-oxide-semiconductor) switch is a metal-oxide-semiconductor switch that uses an optical signal to control conduction and disconnection. It usually includes a photosensitive element. When receiving an optical signal of a specific wavelength and intensity, it changes the conduction state of the internal channel, thereby realizing the switching function. The processing module 130 may include a control program corresponding to a CMOS switch or an optical MOS switch to control the on and off of the CMOS switch or the optical MOS switch.

[0057] In one possible embodiment, see Figure 2 ,like Figure 2 As shown, the bias module 120 includes a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, and a first operational amplifier OPA1; wherein, the first end of the first resistor R1 is connected to the second end of the first switch K1 as the third end of the bias module 120, and the second end of the first resistor R1 is connected to the first end of the first operational amplifier OPA1; the first end of the first operational amplifier OPA1 is also connected to the second end of the second resistor R2 as the first end of the bias module 120; the first end of the third resistor R3 is connected to the reference voltage terminal Vref, the second end of the third resistor R3 is connected to the second end of the first operational amplifier OPA1, the first end of the first capacitor C1 is connected to the first end of the first operational amplifier OPA1, and the second end of the first capacitor C1 is grounded GND; the first end of the first operational amplifier OPA1 is connected to the third end of the first operational amplifier OPA1, the third end of the first operational amplifier OPA1 is connected to the first end of the third resistor R3, the first end of the second capacitor C2 is respectively connected to the second end of the fourth resistor R4 and the first end of the processing module 130, and the second end of the second capacitor C2 is grounded.

[0058] In one possible embodiment, see Figure 2 ,like Figure 2As shown, the processing module 130 includes a controller MCU and an analog-to-digital converter ADC, wherein the first end of the analog-to-digital converter ADC is connected to the first end of the second capacitor C2 and the second end of the fourth resistor R4 as the first end of the processing module 130, and the second end of the analog-to-digital converter ADC is connected to the controller MCU; wherein the controller MCU is used to obtain a first frequency of an input signal, and to generate a second frequency according to the first frequency, and to control the second switch K2 to switch at the second frequency; the controller MCU is also used to control the first switch K1 to switch; when the first switch K1 is closed, the input end of the input module and the third end of the bias module 120 are disconnected.

[0059] The analog-to-digital converter ADC may be a part of the controller MCU or an independent device, which is not limited here.

[0060] When the controller MCU receives an instruction to enter the delay compensation state, or when the controller determines that it is necessary to enter the delay compensation state, the first control module Ctrl1 in the controller MCU controls the first switch K1 to turn off, and the second control module Ctrl2 in the controller MCU controls K2 to continuously turn on and off at the frequency of the input signal of the input module; wherein the first resistor R1 and the second resistor R2 have the same resistance value, so when K1 is turned off, the third end of the bias module 120 is disconnected from the input end of the input module, and the GND-second switch K2-first resistor R1-first end of the input module is turned on. When the first resistor R1 and the second resistor R2 have the same resistance value and the on-off frequency of K2 is the same as the frequency of the input module, it can be considered that the GND-second switch K2-first resistor R1-first end of the input module branch simulates the input module-first switch K1-second resistor R2-third end of the input module branch. The frequencies of the first frequency and the second frequency can be the same. The first control module Ctrl1 and the second control module Ctrl2 may be hardware and software components in the controller MCU, and may be physical components, virtual components, or physical and virtual components, and are used to control the first switch K1 and the second switch K2, respectively.

[0061] Among them, when the second switch K2 is turned on and off, the bias module 120 can collect electrical signals at different points in the circuit. The bias module 120 can bias the collected electrical signals, and then transmit the biased electrical signals to the controller MCU, which analyzes and processes them, and finally obtains the delay compensation value of the circuit.

[0062] In one possible embodiment, see Figure 3 , Figure 3 is a schematic diagram of the structure of another delay compensation circuit based on ADC sampling provided in an embodiment of the present application, such as Figure 3 As shown, the above-mentioned input module may include: a second operational amplifier OPA2, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8; wherein, a first end of the fifth resistor R5 is connected to the first input source A_IN, a second end of the fifth resistor R5 is connected to the first end of the second operational amplifier OPA2, a first end of the sixth resistor R6 is connected to the second input source A_REF_IN, a second end of the sixth resistor R6 is connected to the second end of the second operational amplifier OPA2, a first end of the seventh resistor R7 is connected to the second end of the fifth resistor R5 and the first end of the second operational amplifier OPA2, a second end of the seventh resistor R7 is grounded GND, a first end of the eighth resistor R8 is connected to the second end of the sixth resistor R6 and the second end of the second operational amplifier OPA2, a second end of the eighth resistor R8 is connected to the third end of the second operational amplifier OPA2, and the third end of the second operational amplifier OPA2 is used as the input end of the input module, and is connected to the third end of the bias module 120 through the first switch K1, that is, connected to the first end of the second resistor in the bias module 120 through the first switch K1.

[0063] It should be noted that Figure 3 Other devices in Figure 2 The same as in , no repetitive description is given here.

[0064] The input module has an amplifier effect, which may be a differential amplifier, and performs signal amplification on the input A_IN and A_REF_IN, and outputs the amplified signal from the input end of the input module.

[0065] Specifically, the resistance value of the fifth resistor R5 is the same as the resistance value of the sixth resistor R6 , the resistance value of the seventh resistor R7 is the same as the resistance value of the eighth resistor R8 , and the voltage Vinput at the input end=R7 / R5 (A_IN-A_REF_IN).

[0066] In this way, the delay compensation circuit based on ADC sampling proposed in the embodiment of the present application can also be connected to the circuit of the present method when based on different ADC sampling circuit structures, and the present circuit can be used to perform more accurate delay compensation, which is beneficial to improving the accuracy of delay compensation.

[0067] See also Figure 4 , Figure 4 1 is a flow chart of a delay compensation method based on ADC sampling provided by an embodiment of the present application. The method is applied to a controller of a delay compensation system. The delay compensation system also includes an input module, a compensation module, a bias module and an analog-to-digital converter. The compensation module includes a second switch and a first switch. The method includes:

[0068] S410, obtaining a first frequency of an input signal and setting a first sampling time range, wherein the input signal is generated by an input module, and the first sampling time range is used to limit the sampling time length of an analog-to-digital converter, and the analog-to-digital converter is used to sample analog signals and convert the signals into digital signals.

[0069] Among them, when the controller receives an instruction to enter the delay compensation state, or when the controller determines that it is necessary to enter the delay compensation state, it starts to obtain the first frequency of the input signal. The first frequency can be the electrical signal output by the input module. The electrical signal output by the input module has a certain frequency, which may come from a specific power electronic device in the input module. For example, the frequency of the input signal can be the switching frequency of the power device, and the above-mentioned power device includes a transistor, etc.

[0070] The first sampling time range may be user-defined or selected according to a preset range, and the first sampling time range limits the time length of the controller sampling.

[0071] In a possible embodiment, the delay compensation system further includes an analog-to-digital converter, and the analog-to-digital converter is used to perform signal acquisition within a first sampling time range according to an acquisition instruction of the controller.

[0072] S420, controlling the first switch of the compensation module to be turned off to disconnect the electrical connection between the input module and the bias module.

[0073] Among them, the controller controls the first switch in the compensation module to turn off, and the controller can control the first switch through wireless sensing control or through circuit connection control. When the first switch is disconnected, the electrical connection between the input module and the bias module is disconnected.

[0074] S430, controlling the second switch of the compensation module to continuously perform on-off operations based on the first frequency.

[0075] The controller controls the second switch in the compensation module to perform continuous on-off operation at a frequency obtained based on the first frequency. When the second switch is turned on, the bias module is connected to the branch of the compensation module and is connected to the ground.

[0076] In a possible embodiment, after the first frequency is acquired, the first frequency of switching the power device on and off is converted into a second frequency that can be achieved by the switch, and the first frequency and the second frequency may be the same.

[0077] S440, controlling an analog-to-digital converter to sample a first electrical signal at a sampling target position within a first sampling time range with a first step length, wherein the first electrical signal is an analog signal.

[0078] Among them, see Figure 2 or Figure 3 The sampling target position can be set between the bias module and the analog-to-digital converter. The first step length can be a preset step length, and the setting of the step length can affect the accuracy of the compensation value.

[0079] The first electrical signal is continuously acquired within a first sampling time range. When the time reaches the first sampling time range, the acquisition is stopped, and the sampled first electrical signal is biased and subjected to analog-to-digital conversion processing.

[0080] S450, analyzing the first electrical signal, the first step length, and the first sampling time range to obtain a first target delay result, and performing delay compensation on the input signal using the first target delay result.

[0081] Among them, after the first electrical signal is generated, the first electrical signal is transmitted to the bias module through the circuit, and the bias module biases the first electrical signal. Since the bias module is connected to the analog-to-digital converter, and the analog-to-digital converter generally only receives positive polarity signals, the bias module here adds a DC bias to the first electrical signal so that the second electrical signal is raised and becomes a first electrical signal including only positive polarity, which is input to the analog-to-digital converter; the analog-to-digital converter converts the first electrical signal into an analog-to-digital signal to obtain a digital signal.

[0082] Specifically, obtaining the first target delay result based on the analysis of the first electrical signal includes: obtaining a second electrical signal, the second electrical signal being a digital signal processed by a bias module and an analog-to-digital converter; generating a first waveform diagram of a sampling target position based on the second electrical signal and the first step length; obtaining the first target delay result based on the rising edge of the first waveform diagram of the sampling target position, the first step length and the reference waveform diagram.

[0083] The second electrical signal is a digital signal, that is, the first electrical signal after bias processing and analog-to-digital conversion. The second electrical signal also has a first step length, and a first waveform diagram of a sampling target position is generated according to the second electrical signal.

[0084] The reference waveform diagram is an ideal electrical signal waveform diagram without any delay, and the reference waveform diagram may be preset.

[0085] When collecting signals, sampling may be performed in a first sampling period within a first sampling time range, that is, the first sampling time range may include one or more first sampling periods, and the specific length of the first sampling period is not limited herein.

[0086] For examples, see Figure 5 , Figure 5 is a waveform diagram based on ADC sampling provided in an embodiment of the present application, such as Figure 5As shown, in the first sampling time range, when the first switch K1 is turned off, the second switch K2 is continuously turned on and off at the first frequency, so that the waveform diagram of the electrical signal at the sampling target position is as shown in the figure. From the reference waveform diagram in the waveform diagram, take the rising point of the waveform and the falling edge when the second switch K2 is disconnected as the reference zero point, and compare the rising point of the waveform of the first waveform diagram of the sampling target position with the reference zero point in the reference waveform diagram to obtain the delay time. The first sampling period T preset in the system is obtained. The first sampling period T can be the length of a period of time, which is used to limit the number of steps for calculating the delay. Then, N sampling points are obtained according to the first sampling period T and the first step. If the first step is t, N=T / t is rounded, and the required delay time can be obtained according to the N sampling points. Specifically, the T1 value of the sampling point where the waveform rises is determined, and then according to T N The value and the falling edge T0 when the second switch is turned off are subtracted to obtain ΔT1, and the first target delay result ΔT1 is obtained.

[0087] After obtaining the first target delay result, the first target delay result is saved and used as a subsequent delay compensation for the input signal.

[0088] In a possible embodiment, the method also includes: controlling the analog-to-digital converter to sample a third electrical signal at the sampling target position within a second sampling time range with a second step size, the second sampling time range being used to limit the time length of the controller sampling; analyzing based on the third electrical signal, the second step size and the second sampling time range to obtain a second target delay result, and using the second target delay result to delay compensate the input signal again.

[0089] When collecting signals, sampling may be performed in the second sampling time range with a second sampling period, that is, the second sampling time range may include one or more second sampling periods, and the specific time length of the second sampling period is not limited herein.

[0090] If a more accurate delay compensation value is required, the above-mentioned sampling process with the first step length is repeated with a second step length to obtain a third electrical signal. The third electrical signal may be an analog signal, and a fourth electrical signal is obtained by performing bias processing and analog-to-digital conversion on the third electrical signal, and the fourth electrical signal is a digital signal. The third electrical signal has a second step length, and a second waveform diagram of the sampling target position is generated according to the fourth electrical signal.

[0091] Among them, the second sampling time range can be the same as the first sampling time range, or different from the first sampling time range. The second sampling time range can be determined by the first target delay result ΔT. For example, the second sampling time range can be ΔT1-Δt0 to ΔT1+Δt0, and the above Δt0 can be 1 second or other time lengths, which is not limited here. The specific determination method of the above second sampling time range can also be other, which is not limited here.

[0092] The second step length may be different from the first step length, or may be the same as the first step length. When the second step length is different from the first step length, it may be smaller than the first step length, so as to make the delay result more accurate.

[0093] Among them, after performing a second sampling and delay result calculation based on the second sampling time range and the second step size, a second target delay result is obtained. The second target delay result can be used as the final compensation time, or it can be obtained based on the first target delay result and the second target delay result.

[0094] In a possible embodiment, the method further includes: obtaining a final target delay result according to the first target delay result and the second target delay result.

[0095] Among them, after performing the second sampling and delay result calculation based on the second sampling time range and the second step length, the second target delay result is obtained, which can be the second target delay result as the final compensation time, or it can be calculated again based on the first target delay result, the first step length, the second target delay result, and the second step length. Specifically, the final compensation time can be calculated by the following formula: ΔT=(ΔT1-Δt0)×s1+ΔT2×s2. Among them, ΔT1 is the first target delay result, ΔT2 is the second target delay result, s1 is the first step length, and s2 is the second step length.

[0096] It should be noted that Figure 5 The embodiment is similar to the description, and the second target delay result is obtained according to the second step length.

[0097] After the second target delay result is obtained, the second target delay result is saved and used as a subsequent delay compensation for the input signal.

[0098] In a possible embodiment, the method further includes: controlling the analog-to-digital converter to sample the 2nth electrical signal of the sampling target position with the nth step length within the nth sampling time range, the 2nth electrical signal of the sampling target position being a digital signal of the 2n-1th electrical signal after bias processing and analog-to-digital conversion, and the nth sampling time range being used to limit the time length of the controller sampling; analyzing based on the 2nth electrical signal, the nth step length and the nth sampling time range to obtain the nth target delay result, and again delay compensating the input signal with the nth target delay result. Wherein, n is a positive integer.

[0099] When collecting signals, sampling may be performed in the nth sampling period within the nth sampling time range, that is, the nth sampling time range may include one or more nth sampling periods, and the specific length of the nth sampling period is not limited herein.

[0100] If a more accurate delay compensation value is required, the above sampling process is repeated with the nth step length to obtain the 2n-1th electrical signal. The 2n-1th electrical signal can be an analog signal, and the 2nth electrical signal is obtained by biasing and converting the 2n-1th electrical signal into an analog-to-digital signal, and the 2nth electrical signal is a digital signal. The 2n-1th electrical signal has the nth step length, and the nth waveform diagram of the sampling target position is generated according to the 2nth electrical signal.

[0101] The nth sampling time range may be the same as or different from other sampling time ranges. The nth sampling time range may be determined by the n-1th target delay result ΔT. For example, the nth sampling time range may be ΔT n-1 -Δt n0 to ΔT n-1 +Δt n0 , the above Δt n0 It can be 1 second or other time lengths, which are not limited here. The specific method for determining the above-mentioned nth sampling time range can also be other methods, which are not limited here.

[0102] The nth step length may be different from other step lengths or may be the same as other step lengths, so as to make the delay result more accurate.

[0103] Among them, after performing the nth sampling and delay result calculation based on the nth sampling time range and the nth step length, the nth target delay result is obtained. The nth target delay result can be used as the final compensation time, or it can be obtained based on the nth target delay result and the n-1th target delay result.

[0104] It can be seen that in this embodiment, the first frequency of the input signal is obtained, and the second sampling time range is set. The input signal is generated by the input module, and the second sampling time range is used to limit the time length of the controller sampling; the first switch of the control compensation module is disconnected to disconnect the electrical connection state between the input module and the bias module; the second switch of the control compensation module is continuously turned on and off based on the first frequency; the analog-to-digital converter is controlled to sample the first electrical signal of the sampling target position within the first sampling time range with the first step length; the first target delay result is obtained by analyzing based on the first electrical signal, the first step length and the first sampling time range, and the input signal is delayed compensated with the first target delay result. In this way, the method can be used to perform delay compensation on circuits with different structures, and the circuit using the method has high compatibility. The method and circuit can also be used to perform delay compensation based on different ADC sampling circuit structures, which is conducive to improving the accuracy of delay compensation.

[0105] See also Figure 6 , Figure 6 6 is a schematic diagram of a delay compensation device based on ADC sampling according to an embodiment of the present application. The delay compensation device based on ADC sampling 600 includes: an acquisition module 610, a first control module 620, a second control module 630, a sampling module 640 and an analysis module 650, wherein:

[0106] An acquisition module 610, configured to acquire a first frequency of an input signal generated by the input module, and to set a first sampling time range, wherein the first sampling time range is used to limit a sampling time length of the analog-to-digital converter, and the analog-to-digital converter is used to sample an analog signal and convert the signal into a digital signal;

[0107] A first control module 620, configured to control the first switch of the compensation module to be disconnected, so as to disconnect the connection between the input module and the bias module;

[0108] A second control module 630, configured to control the second switch of the compensation module to continuously perform on-off operations based on the first frequency;

[0109] A sampling module 640 is used to control the analog-to-digital converter to sample a first electrical signal at a sampling target position within the first sampling time range with a first step length, wherein the first electrical signal is an analog signal;

[0110] The analysis module 650 is used to obtain a first target delay result by analyzing the first electrical signal, the first step length and the first sampling time range, and to perform delay compensation on the input signal based on the first target delay result.

[0111] In a possible implementation, the analysis module 650, in obtaining the first target delay result by analyzing the first electrical signal, is specifically configured to:

[0112] Acquire a second electrical signal, where the second electrical signal is a digital signal processed by the bias module and the analog-to-digital converter;

[0113] generating a first waveform diagram of a sampling target position according to the second electrical signal and the first step length;

[0114] The first target delay result is obtained according to the rising edge of the first waveform of the sampling target position and the first step length.

[0115] In a possible implementation, the sampling module 640 is further specifically configured to: control the analog-to-digital converter to sample a third electrical signal at the sampling target position within the first sampling time range with a second step size.

[0116] In one possible implementation, the analysis module 650, in terms of obtaining the first target delay result based on the analysis of the first electrical signal, is also specifically used to: obtain the second target delay result based on the analysis of the third electrical signal, the first step length and the first sampling time range, and perform delay compensation on the input signal again with the second target delay result.

[0117] It is worth noting that the specific functional implementation of the delay compensation device 600 based on ADC sampling can be found in the above Figure 4 The description of the delay compensation method based on ADC sampling shown in the figure, for example, the sampling module 640 is used to implement the relevant content of executing S440. The various units or modules in the delay compensation device 600 based on ADC sampling can be respectively or completely combined into one or several other units or modules to constitute, or one (some) of the units or modules can be further divided into multiple functionally smaller units or modules to constitute, which can achieve the same operation without affecting the realization of the technical effects of the embodiments of the present invention. The above-mentioned units or modules are divided based on logical functions. In actual applications, the functions of one unit (or module) are implemented by multiple units (or modules), or the functions of multiple units (or modules) are implemented by one unit (or module).

[0118] It can be seen that the delay compensation device based on ADC sampling described in the embodiment of the present application obtains the first frequency of the input signal and sets the first sampling time range. The input signal is generated by the input module, and the first sampling time range is used to limit the time length of the controller sampling; the first switch of the control compensation module is disconnected to disconnect the electrical connection state between the input module and the bias module; the second switch of the control compensation module is continuously turned on and off based on the first frequency; the analog-to-digital converter is controlled to sample the first electrical signal of the target position within the first sampling time range with the first step length; the first target delay result is obtained by analyzing based on the first electrical signal, the first step length and the first sampling time range, and the input signal is delayed compensated with the first target delay result. In this way, the method can be used to perform delay compensation on circuits of different structures, and the circuit using the method has high compatibility. The method and circuit can also be used to perform delay compensation based on different ADC sampling circuit structures, which is conducive to improving the accuracy of delay compensation.

[0119] An embodiment of the present application also provides a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, wherein the computer program enables a computer to execute part or all of the steps of any method described in the above method embodiments, and the above computer includes an electronic device.

[0120] The embodiment of the present application also provides a computer program product, the computer program product includes a non-transitory computer-readable storage medium storing a computer program, the computer program is operable to cause a computer to execute some or all of the steps of any method described in the method embodiment. The computer program product may be a software installation package, and the computer includes an electronic device.

[0121] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0122] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0123] In the several embodiments provided in the present application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the above-mentioned units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0124] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0125] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0126] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a memory, including a number of instructions to enable a computer electronic device (which can be a personal computer, electronic device or network electronic device, etc.) to perform all or part of the steps of the above-mentioned methods in each embodiment of the present application. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk and other media that can store program codes.

[0127] Those skilled in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable memory, which may include a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0128] The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A delay compensation circuit based on ADC sampling, characterized in that: The circuit comprises: a compensation module, a bias module and a processing module; the first end of the compensation module is connected to the first end of the bias module; the second end of the bias module is connected to the first end of the processing module; wherein, The compensation module is used to generate a first electrical signal, and the compensation module includes a first switch, a second switch and a first resistor, wherein the first end of the first switch is used to connect the input signal, the first end of the second switch is grounded, the second end of the second switch is connected to the first end of the first resistor, and the second end of the first resistor is connected to the first end of the bias module as the first end of the compensation module; The bias module is used to perform signal bias processing on the first electrical signal to obtain a second electrical signal, and the bias module includes a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, and a first operational amplifier; wherein, The first end of the second resistor is connected to the second end of the first switch as the third end of the bias module, and the second end of the second resistor is connected to the first end of the first operational amplifier; the first end of the first operational amplifier is also connected to the second end of the first resistor as the first end of the bias module; the first end of the third resistor is connected to the reference voltage end, the second end of the third resistor is connected to the second end of the first operational amplifier, the first end of the first capacitor is connected to the first end of the first operational amplifier, and the second end of the first capacitor is grounded; the first end of the first operational amplifier is connected to the third end of the first operational amplifier, the third end of the first operational amplifier is connected to the first end of the third resistor, the first end of the second capacitor is respectively connected to the second end of the fourth resistor and the first end of the processing module, and the second end of the second capacitor is grounded; The processing module is used to calculate the second electrical signal to obtain a target delay result.

2. The circuit according to claim 1, characterized in that The circuit also includes an input module, the input end of the input module is connected to the third end of the bias module; wherein the input signal input by the input module is a signal to be delayed compensated; and the first end of the first switch is connected to the input end of the input module.

3. The circuit according to claim 2, characterized in that The processing module includes a controller and an analog-to-digital converter, wherein the first end of the analog-to-digital converter is connected to the first end of the second capacitor and the second end of the fourth resistor as the first end of the processing module, and the second end of the analog-to-digital converter is connected to the controller; The controller is used to obtain the first frequency of the input signal, generate a second frequency according to the first frequency, and control the second switch to switch at the second frequency; the controller is also used to control the first switch to switch; When the first switch is closed, the input terminal of the input module and the third terminal of the bias module are disconnected.

4. A delay compensation method based on ADC sampling, characterized in that: A controller applied to a delay compensation system, the controller is located in a processing module of the delay compensation system, the delay compensation system also includes an input module, a compensation module, a bias module and an analog-to-digital converter having a sequential connection relationship, the analog-to-digital converter is located in the processing module, the second end of the analog-to-digital converter is connected to the controller, the first end of the analog-to-digital converter serves as the first end of the processing module, the compensation module includes a second switch, a first switch and a first resistor, the first end of the second switch is grounded, the second end of the second switch is connected to the first end of the first resistor, the first end of the first switch is connected to the input end of the input module, the second end of the first switch is connected to the third end of the bias module, the second end of the first resistor is connected to the first end of the bias module as the first end of the compensation module, and the second end of the bias module is connected to the first end of the processing module; the method includes: Acquire a first frequency of an input signal generated by the input module, and set a first sampling time range, wherein the first sampling time range is used to limit the sampling time length of the analog-to-digital converter, and the analog-to-digital converter is used to sample analog signals and convert the signals into digital signals; Controlling the first switch of the compensation module to be turned off, so as to disconnect the electrical connection between the input module and the bias module; Controlling the second switch of the compensation module to continuously perform on-off operations based on the first frequency; Controlling the analog-to-digital converter to sample a first electrical signal at a sampling target position within the first sampling time range with a first step length, wherein the first electrical signal is an analog signal; A first target delay result is obtained by analyzing the first electrical signal, the first step length, and the first sampling time range, and the input signal is delayed compensated using the first target delay result.

5. The method according to claim 4, characterized in that The obtaining a first target delay result by analyzing the first electrical signal includes: Acquire a second electrical signal, where the second electrical signal is a digital signal processed by the bias module and the analog-to-digital converter; generating a first waveform diagram of a sampling target position according to the second electrical signal and the first step length; The first target delay result is obtained according to the rising edge of the first waveform of the sampling target position, the first step length and the reference waveform.

6. The method according to claim 4, characterized in that The method further comprises: Controlling the analog-to-digital converter to sample a third electrical signal at a sampling target position within a second sampling time range with a second step length, wherein the second sampling time range is used to limit a sampling time length of the controller; A second target delay result is obtained by analyzing the third electrical signal, the second step length, and the second sampling time range, and the input signal is delayed compensated again with the second target delay result.

7. A delay compensation device based on ADC sampling, characterized in that: A controller applied to a delay compensation system, the controller is located in a processing module of the delay compensation system, the delay compensation system also includes an input module, a compensation module, a bias module and an analog-to-digital converter having a sequential connection relationship, the analog-to-digital converter is located in the processing module, the second end of the analog-to-digital converter is connected to the controller, the first end of the analog-to-digital converter serves as the first end of the processing module, the compensation module includes a second switch, a first switch and a first resistor, the first end of the second switch is grounded, the second end of the second switch is connected to the first end of the first resistor, the first end of the first switch is connected to the input end of the input module, the second end of the first switch is connected to the third end of the bias module, the second end of the first resistor is connected to the first end of the bias module as the first end of the compensation module, and the second end of the bias module is connected to the first end of the processing module; the device includes: an acquisition module, used to acquire a first frequency of an input signal generated by the input module, and to set a first sampling time range, wherein the first sampling time range is used to limit a sampling time length of the analog-to-digital converter, and the analog-to-digital converter is used to sample an analog signal and convert the signal into a digital signal; a first control module, configured to obtain a first frequency of an input signal generated by the input module, and to set a first sampling time range, wherein the first sampling time range is used to limit a sampling time length of the analog-to-digital converter, and the analog-to-digital converter is used to sample an analog signal and convert the signal into a digital signal; A second control module, used for controlling the first switch of the compensation module to be disconnected, so as to disconnect the electrical connection between the input module and the bias module; A sampling module, used for controlling the analog-to-digital converter to sample a first electrical signal at a sampling target position within the first sampling time range with a first step length, wherein the first electrical signal is an analog signal; An analysis module is used to obtain a first target delay result by analyzing the first electrical signal, the first step length and the first sampling time range, and to perform delay compensation on the input signal based on the first target delay result.

8. A computer-readable storage medium, characterized in that: A delay compensation program is stored, including execution instructions. When a processor of an electronic device executes the execution instructions, the processor executes the method as claimed in any one of claims 4 to 6.

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