A bumping method for surface soldering of a packaging substrate, a packaging substrate, and a packaging structure

Abstract

The application discloses a bump manufacturing method for packaging substrate surface welding, a packaging substrate and a packaging structure. The bump manufacturing method comprises the following steps: firstly, a nickel-palladium-gold plating treatment is performed on a substrate on which a solder resist layer has been manufactured; then a first solder resist window matching the size of a C4 area of a chip is formed on the front surface of the substrate, a first dry film is attached, and exposure and development treatment is performed; then the copper layer of the window area is etched and thinned; then the film is removed, a second dry film is attached again, exposure and development treatment is performed, and a conductive bump structure is electroplated on the thinned copper layer; finally, the substrate is subjected to a brown or black process treatment to form a protective film. The method is suitable for a high-performance chip packaging substrate requiring bump manufacturing in the C4 area of the substrate. The diameter and pitch of the bumps are greatly reduced relative to conventional substrates, more and higher-density interconnections can be achieved. Moreover, the bump area is free of solder resist, the solder resist layer does not hinder the bump area, and the flow and filling of the packaging underfill adhesive are facilitated.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit board processing, in particular to a method for manufacturing bumps for surface welding of a packaging substrate, a packaging substrate and a packaging structure. Background Art

[0002] The flip-chip packaging substrates (FCCSP and FCBGA) used for packaging high-performance computing chips (CPU, GPU, FPGA, etc.) usually need to make a bump array in the controlled collapse component connection area (Controlled Collapse Component Connection, referred to as C4 area) on the front of the substrate where the chip is mounted. The bumps are used to mount the chip during the chip packaging process and to solder with the solder bumps on the chip. The bump array on the substrate corresponds one-to-one with the bumps on the chip. The bumps are usually higher than the solder mask and have a flat top, which helps to improve the interconnection yield and reliability between the chip and the substrate. As more and more functions are integrated on the chip per unit area, the distributed input / output pins are also increasing, requiring more and higher-density interconnections between the chip and the substrate, thereby requiring the bump density in the C4 area on the substrate to continue to increase, that is, the bump diameter and pitch to continue to shrink.

[0003] As shown in the attached picture Figures 1-1 to 1-5 The figure shows a conventional process flow chart for producing bumps on the surface of a substrate. Figure 1-1 The figure shows a substrate with a completed surface solder mask layer. The substrate has multiple layers of copper conductor circuits, such as a first circuit layer 100, a second circuit layer 200, a third circuit layer 300, and a fourth circuit layer 400. Insulating material is filled between the layers, and interconnections are achieved through via structures 000. The first circuit layer 100 of the substrate is covered with a first solder mask layer 110, and the fourth circuit layer 400 is covered with a second solder mask layer 410. First and second solder mask openings 111, 411 are formed in the first and second solder mask layers 110, 410. The area formed by the first solder mask opening 111 is region C4, which is used for mounting a chip. Bumps are required at the locations of the first solder mask openings 111 to mount the chip and achieve interconnection with the chip. Figure 1-2 As shown, solder balls or solder paste are homogeneously printed at the first solder resist opening 111, and then reflow soldered to form bumps 112, and the tops of the bumps 112 are round; Figure 1-3 As shown, the top of the bump 112 is flattened to make the bump surface flat, and finally the C4 area bump 113 is formed. The C4 area on the substrate surface forms a bump array with a flat top, thereby completing the bump production on the substrate surface. Figure 1-4 , which is a top view of a package substrate on which bumps have been fabricated, wherein the bump pitch is the center-to-center distance between two adjacent bumps. Figure 1-5 As shown, the Figure 1-1The substrate manufactured using the substrate surface bump processing process shown in 1-2 and 1-3 is used in a typical package structure after chip packaging. The bumps 113 in the C4 area fuse with the solder bumps on the chip 500 during the package soldering process to form an interconnection structure 114 between the chip and the substrate. The second solder resist openings 411 on the back of the substrate are used to implant solder balls to form the external pins 700 of the chip.

[0004] As can be seen from the above, the diameter and pitch of the bumps 113 in the C4 area are defined by the first solder resist layer 110. By coating a layer of solder resist on the substrate, exposing and developing the solder resist layer, and finally curing it, the window array of the first solder resist openings 111 in the C4 area is formed. However, the solder ball bumping process described above has the following limitations or disadvantages:

[0005] (1) Due to the physical and chemical properties of solder mask materials, stable mass production cannot be achieved when the solder mask opening is less than 50 microns and the pitch is less than 100 microns;

[0006] (2) When the solder ball bumps are flattened, the solder balls will collapse to a certain extent, reducing the actual spacing between the bumps. It is also difficult to produce bumps with extremely small spacing (pitch less than or equal to 100um);

[0007] (3) The process of printing small solder balls in the solder mask opening is usually used for ball planting, which requires the production of a stencil. It is easy to deviate during printing and there are fewer balls in the solder mask opening;

[0008] (4) The small solder balls used to make bumps are expensive.

[0009] Therefore, how to overcome the above-mentioned defects has become an important issue to be solved urgently by those skilled in the art. Summary of the Invention

[0010] The present invention overcomes the shortcomings of the above-mentioned technology and provides a method for manufacturing bumps for surface welding of a packaging substrate, a packaging substrate and a packaging structure.

[0011] To achieve the above object, the present invention adopts the following technical solutions:

[0012] In a first aspect, a method for fabricating bumps for soldering on a surface of a package substrate comprises the following steps:

[0013] Step A: Provide a substrate with a completed solder mask layer, and perform nickel-palladium-gold plating on the copper surface of the substrate at the solder mask opening 2411 corresponding to the surface of the conductive circuit layer 2400 on the back side of the substrate; and form a first solder mask window 2111 in the front side C4 area of ​​the substrate that matches the size of the chip C4 area.

[0014] Step B: applying the first dry film 2120 to both the front and back sides of the substrate, wherein the first dry film 2120 is not applied to the first solder resist window 2111 area;

[0015] The substrate is exposed and developed so that the copper layer in the first solder resist window 2111 area is exposed on the surface, and the other areas are covered by the first dry film 2120;

[0016] Step C: etching the copper layer exposed on the surface in the first solder resist window 2111 area to thin the copper layer exposed on the surface to form a thinned copper layer 2121; wherein the thinned copper layer 2121 is electrically connected to the back conductor line layer 2400 through the interlayer via 2000 in the substrate;

[0017] Step D: performing a film stripping process on the first dry film 2120;

[0018] Step E: A second dry film 2130 is applied to the substrate surface and subjected to exposure and development processing to form dry film windows 2131 on the surface of the thinned copper layer 2121. The second dry film 2130 has openings corresponding to the dry film windows 2131, so that the thinned copper layer 2121 in the area of ​​the dry film windows 2131 is exposed on the surface, while the other areas are covered by the second dry film 2130.

[0019] Step F: electroplating a conductive bump structure 213 at the dry film opening 2131 corresponding to the thinned copper layer 2121, wherein the conductive bump structure 213 is a copper / inert metal structure;

[0020] Step G, performing a film stripping process on the second dry film 2130;

[0021] Step H: performing a browning or blackening process on the substrate to form a copper oxide protection film 2134 on the side of the conductive bump structure 213 .

[0022] Preferably, the “electroplating the conductive bump structure 213 at the dry film opening 2131 corresponding to the thinned copper layer 2121” comprises the following steps:

[0023] Step F1, electroplating copper at the dry film opening 2131 to form an electroplated copper pillar 2132;

[0024] Step F2: electroplating one or more inert metal layers on top of the electroplated copper pillar 2132 to cover the inert metal structure 2133 on the surface of the electroplated copper pillar 2132 , thereby forming an electroplated copper / inert metal structure with the electroplated copper pillar 2132 .

[0025] Preferably, the first dry film 2120 is a photosensitive dry film, and the second dry film 2130 is a high-resolution dry film.

[0026] Preferably, the step A of “plating the copper surface at the solder resist opening 2411 corresponding to the surface of the back conductor circuit layer 2400 of the substrate with nickel-palladium-gold” includes:

[0027] A nickel layer, a palladium layer and a gold layer are deposited in sequence on the copper surface at the solder mask opening 2411 corresponding to the surface of the back conductor line layer 2400 of the substrate, wherein the nickel layer is 2-8um thick, the palladium layer is 0.05-0.15um thick and the gold layer is 0.1-0.2um thick, so as to ensure that the copper surface at the solder mask opening 2411 is completely covered by the nickel-palladium-gold layer and the gold layer is dense and has no voids.

[0028] Preferably, the thickness of the thinned copper layer 2121 is 0.3-1.5 μm. During the etching process of step C, it is necessary to ensure that the thinned copper layer 2121 is complete and continuous without exposing the insulating resin layer under the solder resist layer 110 .

[0029] Preferably, the height of the electroplated copper pillar 2132 is 10-50 μm; the thickness of each layer of the inert metal of the one or more inert metal layers in step F2 is 0.05 μm-1 μm.

[0030] Preferably, in step H, “performing a browning or blackening process on the substrate to form a copper oxide protective film 2134 on the side of the electroplated copper pillar 2132 ” includes:

[0031] An acidic oxidant solution is used to etch the copper surface on the substrate to form a copper oxide protective film 2134 on the side of the electroplated copper pillar 2132;

[0032] The thinned copper layer 2121 between the electroplated copper pillars 2132 is etched cleanly with an acidic oxidant solution to remove any copper residue, thereby preventing the conductive bump structures 213 from being electrically connected.

[0033] In a second aspect, a packaging substrate is provided, wherein the packaging substrate is a substrate obtained by the above-mentioned bump manufacturing method.

[0034] In the third aspect, a packaging structure includes a packaging substrate 100 and a chip 2500 soldered to the surface of the substrate. The packaging substrate 100 is the packaging substrate mentioned in the second aspect, and the solder bumps at the bottom of the chip 2500 are connected one-to-one with the conductive bump structure 213 of the packaging substrate 100.

[0035] Preferably, a filling glue layer 2600 is provided between the bottom of the chip 2500 and the surface of the packaging substrate, and solder balls 2700 are externally connected to the back surface of the packaging substrate 100 .

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] 1. Suitable for high-performance chip packaging substrates that require bump production in the C4 area of ​​the substrate.

[0038] 2. The bumps on the substrate are a copper / inert metal structure, that is, one or more layers of nickel, palladium, gold or other inert metals are electroplated on the top of the copper column. Such a bump structure not only enhances the corrosion resistance and oxidation resistance of the bumps, but also improves the long-term stability and reliability of the bumps; and unlike solder ball bumps, it does not need to be flattened, which can reduce the actual spacing between the bumps, so as to facilitate the production of bumps with extremely small pitch (less than or equal to 100um), so as to achieve more and higher density interconnections between the chip and the substrate.

[0039] 3. The side of the electroplated copper pillar is chemically oxidized by browning or blackening process to form a dense oxide protective film. The protective film can not only prevent further oxidation of the copper pillar, but also prevent the side wall of the copper pillar from short-circuiting with the solder in the package.

[0040] 4. Since the first solder resist window 2111 is formed in the C4 area on the front side of the substrate, there is no solder resist between the bumps in the C4 area of ​​the substrate, and there is no obstruction of the solder resist layer, which facilitates the filling of the bottom filler after the subsequent chip flip-chip welding, and is beneficial to the flow and filling of the bottom filler of the package.

[0041] 5. The bumps made by the present invention are mainly made of copper, which has the characteristics of higher thermal conductivity and lower resistivity compared with tin solder metal bumps, thus being more conducive to electrical conduction and heat dissipation during chip operation;

[0042] 6. The bumps of the present invention do not use expensive tiny solder balls, which can reduce production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 1 is a flow chart of a bump manufacturing method according to the first embodiment of the present invention.

[0044] Figures 1-1 to 1-5 Shown is a flow chart of a traditional process for producing bumps on the surface of a substrate.

[0045] Figure 2-1 This is a cross-sectional view of a substrate in step A that has been completed with a solder mask layer and nickel-gold plating on the solder surface.

[0046] Figure 2-2 It is a cross-sectional view of the substrate after the first dry film is attached to the surface of the substrate and exposed and developed in step B.

[0047] Figure 2-3 This is a cross-sectional view of the substrate after etching the copper surface of the first solder resist window in step C.

[0048] Figure 2-4 FIG. 4 is a cross-sectional view of the substrate after the first dry film is removed in step D.

[0049] Figure 2-5 This is a cross-sectional view of the substrate after the second dry film is attached to the surface of the substrate and exposed and developed in step E.

[0050] Figure 2-6 It is a cross-sectional view of the substrate of the electroplated conductive bump structure in step F.

[0051] Figure 2-7 FIG. 4 is a cross-sectional view of the substrate after the second dry film is removed in step G.

[0052] Figure 2-8 It is a cross-sectional view of the substrate during the browning or blackening process in step H.

[0053] Figure 2-9 It is a structural diagram of the packaging structure of Example 3 of this case. DETAILED DESCRIPTION

[0054] The following examples further illustrate the features of the present invention and other related features to facilitate understanding by those skilled in the art:

[0055] Example 1

[0056] like Figure 1 as well as Figure 2-1 to Figure 2-8 As shown, a method for manufacturing bumps for soldering on the surface of a package substrate comprises the following steps:

[0057] Step A: Provide a substrate with a completed solder mask layer, and perform nickel-palladium-gold plating on the copper surface at the solder mask opening 2411 corresponding to the surface of the back conductor line layer 2400 of the substrate; in the specific implementation, the nickel-palladium-gold plating adopts the mature chemical nickel-palladium-gold plating process of the packaging substrate industry, and the solutions used are all environmentally friendly solutions that will not pollute the environment. At the same time, compared with other precious metal surface treatment processes, the cost of nickel-palladium-gold surface treatment is lower, which helps to reduce the manufacturing cost of the product. The substrate with a completed solder mask layer includes at least: a front solder mask layer 2110 formed on the front of the substrate, and a back solder mask layer 2410 formed on the back of the substrate;

[0058] According to the size of the chip C4 area, a first solder resist window 2111 matching the size of the chip C4 area is formed in the substrate front C4 area, wherein the first solder resist window 2111 does not contain any solder resist layer;

[0059] Step B: affix the first dry film 2120 to both the front and back sides of the substrate, wherein the first dry film 2120 is not affixed to the first solder resist window 2111 area; the first dry film 2120 is an ordinary photosensitive dry film.

[0060] The substrate is exposed and developed so that the copper layer in the first solder resist window 2111 area is exposed on the surface, and the other areas are covered by the first dry film 2120;

[0061] Step C: Etching the copper layer exposed on the surface in the first solder resist window 2111 region using a chemical etching solution to thin the copper layer exposed on the surface to form a thinned copper layer 2121; wherein the thinned copper layer 2121 is electrically connected to the back conductor circuit layer 2400 through the interlayer via 2000 in the substrate;

[0062] Step D: stripping the first dry film 2120. In practice, stripping is usually accomplished by soaking the first dry film 2120 in a strong alkaline solution.

[0063] Step E: A second dry film 2130 is applied to the substrate surface and subjected to exposure and development processing to form dry film windows 2131 on the surface of the thinned copper layer 2121. The second dry film 2130 has openings corresponding to the dry film windows 2131, so that the thinned copper layer 2121 in the area of ​​the dry film windows 2131 is exposed on the surface, while the other areas are covered by the second dry film 2130.

[0064] Step F: electroplating a conductive bump structure 213 at the dry film window 2131 corresponding to the thinned copper layer 2121, wherein the conductive bump structure 213 is a copper / inert metal structure; during the electroplating process, in order to provide current to the dry film window 2131 area, this can be achieved by connecting the back conductor circuit layer 2400 to a power source.

[0065] The “electroplating the conductive bump structure 213 on the dry film window 2131 corresponding to the thinned copper layer 2121” includes the following steps:

[0066] F1. First, copper is electroplated at the dry film opening 2131 to form electroplated copper pillars 2132. The typical height of electroplated copper pillars 2132 is 10-50 μm. This height range provides sufficient conductive area, ensuring stable current transmission and reducing resistance, thereby optimizing electrical performance. It also allows for closer placement of bumps, further reducing bump pitch and achieving higher integration, thereby reducing signal attenuation and energy loss, and improving the overall performance of electronic products using this substrate.

[0067] F2. One or more layers of inert metal are then electroplated on top of the electroplated copper pillar 2132 to cover the surface of the copper pillar 132 with an inert metal structure 2133. This, together with the electroplated copper pillar 2132, forms the electroplated copper / inert metal structure, i.e., the bump described in this application. The inert metal generally refers to nickel, gold, palladium, etc. Any metal that is not corroded by common chemical etching solutions (such as sulfuric acid and hydrogen peroxide) can be used. The thickness of each layer of inert metal can be selected to be 0.05 μm to 1 μm, ensuring that the inert metal completely covers the top of the electroplated copper pillar 2132 without voids. In practice, typical metal layer combinations for the bump may include copper / nickel, copper / nickel / gold, copper / palladium, copper / nickel / palladium, copper / gold, or copper / palladium / gold.

[0068] Step G: performing a film stripping process on the second dry film 2130; the second dry film 2130 is a high-resolution dry film.

[0069] Step H: The substrate is subjected to a browning or blackening process to form a copper oxide protective film 2134 on the side of the electroplated copper pillar 2132. Browning and blackening are common copper surface treatment processes in the packaging substrate or PCB manufacturing process. Its main purpose is to use an acidic oxidant solution to corrode the copper surface and form a copper oxide protective film on the side of the electroplated copper pillar 2132. During specific implementation, the acidic oxidant solution can also etch the thinned copper layer 2121 between the electroplated copper pillars 2132 cleanly without copper residue, so that the copper pillar bumps are not conductive. Specifically, the oxide protective film 2134 can prevent the copper layer from being further oxidized and can also be bonded with the insulating resin with high reliability. Since the oxide protective film 2134 is not conductive and cannot be soldered with tin, it can play the role of solder resistance and insulation on the side of the bump during the welding process. Because the top surface of the electroplated copper pillars 2132 is also covered with an inert metal, it is protected from oxidation or etching by the chemical solution during the browning or blackening process, thus protecting the top of the electroplated copper pillars 2132. The inert metal nickel, palladium, or gold in the inert metal structure 2133 reacts with the high-temperature molten tin solder to form an intermetallic compound, thereby achieving solder joint interconnection.

[0070] As described above, the method for making bumps in this case is to first perform nickel-palladium-gold plating on the copper surface of the solder mask opening corresponding to the back conductor circuit layer of the substrate through step A, which can improve the corrosion resistance and wear resistance of the copper surface, increase the reliability and stability of the copper surface; and can make the copper surface have good conductivity, which can ensure that the back conductor circuit layer still maintains efficient electrical signal transmission capabilities after plating; then, through step A, a first solder mask opening 2111 of a size matching the C4 area of ​​the chip is set to facilitate the subsequent production of bumps matching the C4 area of ​​the chip, which is suitable for substrates used for high-performance chip packaging that require bump production in the C4 area of ​​the substrate, and can meet the needs of high-performance chip packaging. The setting of step B is to affix a first dry film 2120 to both the front and back sides of the substrate, wherein the dry film is not affixed in the first solder mask opening 2111 area to reserve a bump production area. Step C forms a thinned copper layer 2121, which is then electrically connected to the back conductor layer 2400 via the interlayer vias 2000 within the substrate. This facilitates interconnection between the thinned copper layer 2121 and the back conductor layer 2400, facilitating efficient current transfer from the back conductor layer 2400 to the thinned copper layer 2121 during subsequent electroplating. Thinning the copper layer also improves current distribution and further enhances conductivity. Step D strips the previously applied first dry film 2120 to facilitate subsequent processing. In the setting of step E, a dry film is again applied to the surface of the substrate so as to further form a finer bump structure on the surface of the thinned copper layer 2121; and the second dry film 2130 is set as a high-resolution dry film, so that the minimum window size can be reduced to 10 microns by using the high-resolution dry film, thereby reducing the diameter of the bump structure subsequently formed thereon, and accommodating more bumps in the same area while ensuring the spacing between the bumps to improve the integration. The arrangement of step F and steps F1 and F2 can first form electroplated copper pillars 2132 at the dry film openings 2131 and then electroplate one or more layers of inert metal on top of the electroplated copper pillars 2132, forming bumps with an electroplated copper / inert metal structure, thereby enhancing the corrosion resistance and oxidation resistance of the bumps and improving the long-term stability and reliability of the bumps. Moreover, unlike solder ball bumps, the above bump structure does not need to be flattened. On the one hand, it can reduce the actual spacing between the bumps to facilitate the production of bumps with an extremely small pitch of less than or equal to 100 μm, thereby achieving more and higher-density interconnections between the chip and the substrate. On the other hand, the bumps produced in this case are mainly copper, which has higher thermal conductivity and lower resistivity than bumps made of tin solder metal, thereby being more conducive to electrical conduction and heat dissipation during chip operation. In addition, the bumps in this case do not use expensive tiny solder balls, which can reduce production costs. In addition, the above bump production method eliminates solder mask between the bumps in the substrate C4 area, which is conducive to filling the bottom filler after subsequent chip flip-chip soldering.The step G is configured to strip the second dry film 2130. The step H is configured to form a brown layer or a black layer on the sidewall of the copper pillar, and the rough surface is more conducive to improving the adhesion with the chip bottom filler.

[0071] As a preferred embodiment, during specific production, the step A of "plating the copper surface of the back conductor line layer 2400 of the substrate at the corresponding solder resist opening 2411 with nickel palladium gold" includes:

[0072] A nickel layer, a palladium layer and a gold layer are deposited in sequence on the copper surface at the solder mask opening 2411 corresponding to the surface of the back conductor line layer 2400 of the substrate, wherein the nickel layer is 2-8um thick, the palladium layer is 0.05-0.15um thick and the gold layer is 0.1-0.2um thick, so as to ensure that the copper surface at the solder mask opening 2411 is completely covered by the nickel-palladium-gold layer and the gold layer is dense and has no voids.

[0073] As mentioned above, the thickness of the nickel layer is the thickest relative to the palladium layer and the gold layer because the nickel layer is designed as a base layer. The thicker nickel layer provides physical protection for the copper surface and enhances the overall wear resistance and impact resistance. The setting of the thickness range of 2-8um is based on a large amount of experimental data and actual production experience, which can meet the manufacturing needs of most electronic products. When the thickness of the nickel layer is less than 2um, the thinner nickel layer may not provide sufficient physical protection for the copper surface and is easily affected by external mechanical shock or chemical corrosion, resulting in damage to the conductor line inside the substrate. Moreover, a nickel layer that is too thin may cause its resistivity to increase, thereby affecting the current transmission efficiency and stability. If the nickel layer thickness exceeds 8um, on the one hand, it will increase the cost. On the other hand, a thicker nickel layer may generate greater internal stress during the deposition process, which may cause the coating to crack or peel off in subsequent processes or during use. Moreover, an excessively thick nickel layer may affect the deposition quality of subsequent palladium and gold layers, such as causing the palladium layer to be uneven or the gold layer to be incompletely covered. The palladium layer acts as a barrier layer, effectively preventing copper from migrating to the gold layer, avoiding problems such as poor solderability caused by copper migration, improving the chemical stability of the coating, and allowing the circuit board to maintain good solderability after high-temperature aging and high moisture exposure. The thickness range of 0.05-0.15um is set because the palladium layer below 0.05um may not be able to effectively block the migration of copper, causing the gold layer to be contaminated, affecting its performance and stability. A palladium layer exceeding 0.15um will increase material costs and a thicker palladium layer may generate greater internal stress during the deposition process, causing the coating to crack or peel. In addition, an overly thick palladium layer may affect the deposition quality of the subsequent gold layer, resulting in an uneven or incomplete gold layer. The dense and void-free design of the gold layer ensures low contact resistance and is suitable for high-frequency and high-speed packaging structures. In addition, the gold layer has good solderability and can quickly melt into the molten solder to form a stable solder joint; and its thickness range is 0.1-0.2um, so that the gold layer can save costs while ensuring good electrical connection and signal transmission between electronic components; when the thickness is less than 0.1um, the gold layer is too thin, which may cause the resistivity to rise, affecting the current transmission efficiency; or it is too thin to form a stable bump in the subsequent steps; and the thickness exceeds 0.2um, which will not only significantly increase the production cost, but may also generate large internal stress during the deposition process, causing the coating to crack or peel off. The nickel-palladium-gold treatment ensures complete coverage of the copper surface and improves the overall reliability and stability of the circuit board. In addition, the nickel layer and the gold layer are mainly used to protect the back conductor circuit layer 2400 on the back of the substrate that is not covered by the solder mask during the subsequent browning / blackening process to avoid being etched during the browning process; and the nickel-gold layer is a solderable coating that can be used for ball planting on the back after packaging.

[0074] As a preferred embodiment, the thickness of the thinned copper layer 2121 is 0.3-1.5 μm. Furthermore, during etching, the thinned copper layer 2121 is ensured to be complete and continuous, without exposing the insulating resin layer beneath the solder mask layer 110. Thus, the thinned copper layer 2121 is within the range of 0.3-1.5 μm. This thickness range not only ensures efficient current transmission but also avoids increased resistance due to an excessively thick copper layer. During the etching process, the thinned copper layer 2121 is ensured to be complete and continuous, without exposing the insulating resin layer beneath the solder mask layer 110, thereby preventing overetching, thus avoiding breakage or discontinuity in the copper layer and ensuring the substrate's conductive properties.

[0075] Example 2

[0076] like Figure 2-1 to Figure 2-8 2 is a cross-sectional diagram of the process of forming the packaging substrate of the second embodiment of the present invention.

[0077] A packaging substrate, the packaging substrate is the substrate manufactured by the bump manufacturing method in Example 1. Specifically, the packaging substrate is provided with at least two layers of conductor circuits inside, and the surface of the packaging substrate is provided with a solder resist layer, specifically a front solder resist layer 2110 formed on the front side of the substrate and a back solder resist layer 2410 formed on the back side of the substrate; the packaging substrate is provided with a solder resist opening 2411 in the back solder resist layer 2410 to expose a portion of the surface of the bottom back conductor circuit layer 2400, and the copper surface at the solder resist opening 2411 is covered with a nickel-palladium-gold layer 24110; the packaging substrate is provided with a solder resist opening 2411 in the front solder resist layer 2110 to expose a portion of the surface of the bottom back conductor circuit layer 2400, and the copper surface at the solder resist opening 2411 is covered with a nickel-palladium-gold layer 24110; the packaging substrate is provided with a solder resist opening 24110 in the front solder resist layer 2110 to expose a portion of the surface of the chip C The bump mounting areas of Zone 4 are matched in size and are not provided with solder mask. Multiple conductive bump structures 213 are provided on these bump mounting areas. These conductive bump structures 213 include copper-plated pillars 2132 formed by electroplating copper in the bump mounting areas, and inert metal structures 2133 electroplated on / covering the top surfaces of the copper pillars 2132. The inert metal structures 2133 include one or more inert metal layers. A copper oxide protective film 2134, treated with a browning or blackening process, is formed on the sidewalls of the copper pillars 2132. The topmost front conductor circuit layer 2100 of the substrate is electrically connected to the back conductor circuit layer 2400 via interlayer vias 2000. In a specific implementation, the bump mounting area and the conductive bump structure 213 thereof are formed by first forming a first solder resist window 2111 in step A of embodiment 1, then thinning the copper layer exposed on the surface in the area of ​​the first solder resist window 2111 in steps B and C to form a thinned copper layer 2121; then forming a dry film window 2131 on the surface of the thinned copper layer 2121 in steps D to H, and electroplating the conductive bump structure 213 at the dry film window 2131 corresponding to the thinned copper layer 2121, then stripping the second dry film 2130, and finally performing a browning or blackening process on the substrate to form the bump mounting area;

[0078] Example 3

[0079] like Figure 2-9 As shown, a packaging structure includes a packaging substrate 100 and a chip 2500 soldered to the surface of the substrate, wherein the packaging substrate 100 is the packaging substrate described in Example 2, and the solder bumps at the bottom of the chip 2500 are connected one-to-one with the conductive bump structure 213 of the packaging substrate 100. A filling glue layer 2600 is provided between the bottom of the chip 2500 and the surface of the packaging substrate, and a solder ball 2700 is externally connected to the back of the packaging substrate 100. In this way, due to the use of the packaging substrate described in Example 2, the bump manufacturing method adopted makes it possible for the bump area of ​​the packaging substrate to be free of solder mask and the obstruction of the solder mask layer, which is conducive to the flow and filling of the filling glue at the bottom of the package, thereby improving the reliability of the overall packaging structure. Moreover, the uniform filling of the filling glue layer 2600 helps to improve the heat dissipation performance of the packaging structure, so that the heat generated by the chip during operation can be dissipated to the outside more quickly, thereby extending the service life of the chip. In addition, the sidewall of the electroplated copper pillar 2132 of the package substrate is a brown layer or a black layer, and its rough surface is more conducive to improving the adhesion with the chip bottom filling glue and improving the stability of the package structure.

[0080] In summary, although the drawings in this case only show a typical four-layer conductor circuit (such as Figure 2-1 The substrate structure is numbered 2100, 2200, 2300, and 2400 from top to bottom. The present invention is not limited to the number of substrate circuit layers, and bumps can be made on the surface of a substrate after processing any layer of copper circuits. In addition, the bump diameter of the present invention is not defined by the solder mask on the surface of the substrate, but is formed by exposure and development of a high-resolution photosensitive dry film. The minimum window size of the high-resolution dry film can be up to 10 microns, which greatly reduces the bump diameter. There is no solder mask between the bumps in the C4 area of ​​the substrate, which is conducive to the filling of the glue layer 2600 after the chip is flip-chip soldered. The side wall of the electroplated copper column 2132 is a brown layer or a black layer, and its rough surface is more conducive to improving the adhesion with the filling glue at the bottom of the chip.

[0081] As mentioned above, this case protects a method for making bumps for surface welding of a packaging substrate, a packaging substrate, and a packaging structure. All technical solutions that are identical or similar to those in this case should be deemed to fall within the scope of protection of this case.

Claims

1. A method for producing bumps for soldering on the surface of a package substrate, characterized in that The steps include: Step A, providing a substrate with a completed solder mask layer, and performing nickel-palladium-gold plating on the copper surface at the solder mask opening (2411) corresponding to the surface of the back conductor circuit layer (2400) of the substrate; forming a first solder mask opening (2111) in the C4 area on the front side of the substrate that matches the size of the chip C4 area; Step B, applying a first dry film (2120) to both the front and back sides of the substrate, wherein the first dry film (2120) is not applied to the first solder resist window (2111) area; Performing exposure and development processing on the substrate so that the copper layer in the first solder resist window (2111) area is exposed on the surface, and other areas are covered by the first dry film (2120); Step C, etching the copper layer exposed on the surface in the first solder resist window (2111) area to thin the copper layer exposed on the surface to form a thinned copper layer (2121); wherein the thinned copper layer (2121) is connected to the back conductor line layer (2400) through the interlayer via hole (2000) inside the substrate; Step D, performing a film stripping process on the first dry film (2120); Step E: affixing a second dry film (2130) to the surface of the substrate and performing exposure and development treatment to form dry film windows (2131) on the surface of the thinned copper layer (2121); wherein the second dry film (2130) is provided with openings corresponding to the dry film windows (2131), so that the thinned copper layer (2121) in the area of ​​the dry film windows (2131) is exposed on the surface, and other areas are covered by the second dry film (2130); Step F, electroplating a conductive bump structure (213) at the dry film window (2131) corresponding to the thinned copper layer (2121), wherein the conductive bump structure (213) is a copper / inert metal structure; Step G, performing a film stripping process on the second dry film (2130); Step H, performing a browning or blackening process on the substrate to form a copper oxide protective film (2134) on the side of the conductive bump structure (213); The first dry film (2120) is a photosensitive dry film, and the second dry film (2130) is a high-resolution dry film.

2. The method for producing bumps for soldering on the surface of a package substrate according to claim 1, wherein The "electroplating of the conductive bump structure (213) at the dry film window (2131) corresponding to the thinned copper layer (2121)" comprises the following steps: Step F1, electroplating copper at the dry film window (2131) to form an electroplated copper pillar (2132); Step F2: electroplating one or more layers of inert metal on top of the electroplated copper pillar (2132) to cover the inert metal structure (2133) on the surface of the electroplated copper pillar (2132), thereby forming an electroplated copper / inert metal structure with the electroplated copper pillar (2132).

3. The method for producing bumps for soldering on the surface of a package substrate according to claim 1, wherein The step A of "plating the copper surface with nickel-palladium-gold at the solder mask opening (2411) corresponding to the surface of the back conductor circuit layer (2400) of the substrate" includes: A nickel layer, a palladium layer and a gold layer are sequentially deposited on the copper surface at the solder mask opening (2411) corresponding to the surface of the back conductor line layer (2400) of the substrate, wherein the nickel layer is 2-8um thick, the palladium layer is 0.05-0.15um thick and the gold layer is 0.1-0.2um thick, thereby ensuring that the copper surface at the solder mask opening (2411) is completely covered by the nickel-palladium-gold layer and the gold layer is dense and has no voids.

4. The method for producing bumps for soldering on the surface of a package substrate according to claim 1, wherein The thickness of the thinned copper layer (2121) is 0.3-1.5 μm; during the etching process of step C, it is necessary to ensure that the thinned copper layer (2121) is complete and continuous without exposing the insulating resin layer under the solder resist layer 110.

5. The method for producing bumps for soldering on the surface of a package substrate according to claim 2, wherein The height of the electroplated copper pillar (2132) is 10-50 μm; the thickness of each layer of the inert metal of the one or more inert metal layers in step F2 is 0.05 μm-1 μm.

6. The method for producing bumps for soldering on the surface of a package substrate according to claim 2, wherein In step H, "performing a browning or blackening process on the substrate to form a copper oxide protective film (2134) on the side of the conductive bump structure (213)" includes: An acidic oxidant solution is used to corrode the copper surface on the substrate to form a copper oxide protective film (2134) on the side of the electroplated copper pillar (2132); An acidic oxidant solution is used to simultaneously etch the thinned copper layer (2121) between the electroplated copper pillars (2132) cleanly without copper residue, thereby preventing conduction between the conductive bump structures (213).

7. A packaging substrate, characterized in that The packaging substrate is a substrate obtained by the manufacturing method according to any one of claims 1 to 6.

8. A packaging structure, characterized in that The invention comprises a packaging substrate (100) and a chip (2500) soldered to the surface of the substrate, wherein the packaging substrate (100) is the packaging substrate according to claim 7, and the solder bumps at the bottom of the chip (2500) are connected to the conductive bump structures (213) of the packaging substrate (100) in a one-to-one correspondence.

9. The packaging structure according to claim 8, characterized in that A filling glue layer (2600) is provided between the bottom of the chip (2500) and the surface of the packaging substrate, and a solder ball (2700) is externally connected to the back of the packaging substrate (100).

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