memory controller

Abstract

The present application discloses a memory controller, comprising: a plurality of first interfaces, wherein the first end of each first interface is connected to a plurality of master devices in a one-to-one correspondence, and the first interface is used to receive requests from the master devices; a conversion module, wherein the first end of the conversion module is connected to the second end of each first interface, and is used to convert burst transfer mode requests of the master devices received by each first interface into single transfer mode; an arbitration module, wherein the first end of the arbitration module is connected to the second end of the conversion module, and is used to determine a target request that wins arbitration among a plurality of parallel single transfer mode requests output by the conversion module at a target moment; a second interface, wherein the first end of the second interface is connected to the second end of the arbitration module, and the second end of the second interface is connected to a target memory, and the second interface is used to access the target memory at the target moment based on the target request output by the arbitration module.

Description

Technical Field

[0001] The present application relates to the technical field of system on chip, and in particular to a memory controller. Background Art

[0002] System on Chip (SoC) is an integrated circuit that combines hardware systems and embedded software. A memory area is usually designed in the SoC system to store intermediate variables used in software programming, such as stack data, or dynamic data for some applications in the SoC system. This memory area is usually implemented through a memory, such as static random access memory (SRAM). With the read and write performance of the memory, for example, the CPU, USB or other master devices (master) can temporarily store dynamic data in the memory through read and write methods, which is convenient for master devices to transfer data to each other, or for data caching of master devices.

[0003] The existing memory controller used for reading and writing data between the host device and the memory usually has only one first interface connected to the host device and one second interface connected to the memory, completing the conversion from the on-chip bus protocol of the first interface to the memory protocol of the second interface. Multiple host devices in the SoC system are connected to the first interface of the memory controller through the bus. When multiple host devices access the same memory controller at the same time, arbitration needs to be performed on the bus first, and the host device that wins the arbitration can access the memory through the memory controller.

[0004] However, the properties of the requests initiated by each master device (such as burst transmission) are different, and each master device has different delay sensitivity to access request reply data. For example, when the first master device that currently wins the arbitration occupies the memory controller for burst continuous data transmission, if the second master device that is extremely sensitive to delay also initiates a request, the second master device can only access the memory controller after the burst continuous data transmission of the first master device is completed. As a result, the second master device cannot receive reply data for a long time, the operating efficiency is reduced, and it is difficult to meet the indicators required by the SoC system. Summary of the invention

[0005] The purpose of the embodiment of the present application is to provide a memory controller to solve the problem of low operating efficiency when multiple master devices of a SoC system access a memory.

[0006] In order to solve the above technical problems, this specification is implemented as follows:

[0007] In a first aspect, a memory controller is provided, comprising:

[0008] A plurality of first interfaces, a first end of each first interface being connected to a plurality of master devices in a one-to-one correspondence, and the first interface being used to receive a request from the master device;

[0009] A conversion module, wherein a first end of the conversion module is connected to a second end of each first interface, and is used to convert a burst transmission mode request of a master device received by each first interface into a single transmission mode;

[0010] An arbitration module, wherein a first end of the arbitration module is connected to a second end of the conversion module, and is used to determine a target request that wins arbitration among a plurality of parallel single-transfer mode requests output by the conversion module at a target time;

[0011] A second interface, a first end of the second interface is connected to a second end of the arbitration module, a second end of the second interface is connected to a target memory, and the second interface is used to access the target memory based on a target request output by the arbitration module at the target time.

[0012] Optionally, the conversion module includes a plurality of sub-conversion modules.

[0013] The first end of each sub-conversion module is connected to the multiple first interfaces in a one-to-one correspondence, and the second end of each sub-conversion module is connected to the first end of the arbitration module, and is used to convert the burst transmission mode request of the master device received by the corresponding first interface into a single transmission mode and output it to the arbitration module.

[0014] Optionally, the sub-conversion module is specifically used to:

[0015] By converting the protocol of the first interface corresponding to the connection into a preset protocol, a single burst transfer mode request is converted into multiple single transfer mode requests, and the number of the multiple single transfer mode requests is determined by the burst length of the single burst transfer mode request.

[0016] Optionally, the protocol of the first interface is the AXI protocol, and the sub-conversion module includes a read conversion module and a write conversion module.

[0017] The read conversion module is used to convert a single burst transfer mode read request into multiple single transfer mode read requests by converting the protocol of the read request of the master device received by the corresponding first interface via the read channel at the target time into the preset protocol;

[0018] The write conversion module is used to convert a single burst transfer mode write request into multiple single transfer mode write requests by converting the protocol of the write request of the master device received by the corresponding first interface via the write channel at the target time into the preset protocol;

[0019] Wherein, the read channel is separated from the write channel.

[0020] Optionally, the protocol of the first interface is the AHB protocol, and the sub-conversion module is used to convert the request of a single burst transfer mode into multiple single transfer mode requests by converting the protocol of the request of the master device received by the corresponding first interface through a single channel at the target time into the preset protocol, and the request of the master device is a read request or a write request.

[0021] Optionally, the arbitration module is specifically used to:

[0022] Obtaining the priorities of multiple parallel single transfer mode requests output by the conversion module at the target time, wherein the priority of the request is related to different delay requirements of the master device sending the request, and the priorities of multiple single transfer mode requests converted from the same burst transfer mode request are the same;

[0023] Obtaining the polling order of the multiple requests in the parallel single transfer mode at the target time, wherein the request with the earlier polling order has a higher priority than the request with the later polling order;

[0024] Determine the target request that wins arbitration among the multiple parallel single transfer mode requests based on priority and polling order;

[0025] The preset protocol of the target request is converted into the protocol of the second interface and then output to the second interface.

[0026] Optionally, the arbitration module is specifically used to:

[0027] If the request in the single transfer mode with the highest priority includes a single, determining the request in the single transfer mode with the highest priority as the target request that wins the arbitration;

[0028] If the single transfer mode request with the highest priority includes multiple requests, the request with the highest polling order among the multiple single transfer mode requests with the highest priority is determined as the target request that wins the arbitration;

[0029] After the target request wins the arbitration, adjusting the polling weight of the first request, the first request being a request of the burst transmission mode before the target request is converted, and the polling weight is related to the burst length of the first request;

[0030] If at the current moment the first request corresponding to the converted single transfer mode request wins the arbitration so that the adjusted polling weight reaches the preset weight threshold, the first request is set to the last position in the polling sorting, and at the same time the polling weight of the first request is restored to the initial setting value.

[0031] Optionally, the arbitration module is further used to:

[0032] If at the current moment the request for the single transfer mode to which the first request corresponds is converted continuously wins arbitration so that the adjusted polling weight does not reach the preset weight threshold, and at the next moment the request for the single transfer mode to which the first request corresponds is not received, the position of the first request in the polling sort is set to the last, and at the same time the polling weight of the first request is restored to the initial setting value.

[0033] Optionally, the address space of the target memory is divided into a plurality of independent address spaces, and different independent address spaces are used to store data of different master devices. The number of the second interfaces is the same as the number of the plurality of independent address spaces.

[0034] The arbitration module includes a plurality of sub-arbitration modules, wherein the first end of each sub-arbitration module is respectively connected to the second end of the plurality of sub-conversion modules, and the second end of each sub-arbitration module is connected to a plurality of second interfaces in a one-to-one correspondence, and is used to determine a target request that wins arbitration among a plurality of parallel single-transfer mode requests output by each sub-conversion module at a target time, and access a corresponding independent address space through the correspondingly connected second interface.

[0035] Optionally, it also includes:

[0036] A decoding module is arranged between the target sub-conversion module and the plurality of sub-arbitration modules, and is used to determine the independent address space to be accessed by the request by decoding the address of the request output by the target sub-conversion module; and output the request to the sub-arbitration module corresponding to the independent address space to be accessed by the request.

[0037] Optionally, the multiple independent address spaces include a first address space and a second address space divided based on the address depth of the target memory, the first address space is used to store data of a first master device, the second address space is used to store data of a second master device, and the first master device and the second master device are different.

[0038] Optionally, the first address space further includes a first sub-address space and a second sub-address space divided based on a preset data unit, and the second address space further includes a third sub-address space and a fourth sub-address space divided based on the preset data unit;

[0039] The first sub-address space corresponds to an odd-numbered granularity address space among a plurality of address spaces obtained by dividing the first address space by the preset data unit, and the second sub-address space corresponds to an even-numbered granularity address space among a plurality of address spaces obtained by dividing the first address space by the preset data unit;

[0040] The third sub-address space corresponds to an odd-granularity address space among a plurality of address spaces obtained by dividing the second address space by the preset data unit, and the fourth sub-address space corresponds to an even-granularity address space among a plurality of address spaces obtained by dividing the second address space by the preset data unit.

[0041] In an embodiment of the present application, a memory controller includes: a plurality of first interfaces, a first end of each first interface is connected to a plurality of master devices in a one-to-one correspondence, and the first interface is used to receive a request from the master device; a conversion module, a first end of the conversion module is connected to a second end of each first interface, and is used to convert a burst transfer mode request of the master device received by each first interface into a single transfer mode; an arbitration module, a first end of the arbitration module is connected to a second end of the conversion module, and is used to determine a target request that wins arbitration among a plurality of parallel single transfer mode requests output by the conversion module at a target time; a second interface, a first end of the second interface is connected to a second end of the arbitration module, a second end of the second interface is connected to a target memory, and the second interface is used to output a target memory based on the arbitration module at the target time. The target memory is accessed through a target request. Thus, when there are multiple master devices that need to access the target memory at the same time, and the burst attributes of the requests initiated by each master device are different, the request of a high-delay-sensitive master device that has won the arbitration at the current moment can be preferentially inserted into the data block continuously transmitted by another master device through the converted single transfer mode request, so as to avoid the request of the master device of the continuously transmitted data block always occupying the memory controller, so that a delay-sensitive master device can quickly return data, and at the same time another master device can continuously throughput large data blocks, thereby improving the operating efficiency of the delay-sensitive master device to meet the indicators required by the SoC system, and will not affect the normal operation of the master device that continuously transmits data blocks, thereby improving the operating performance of the entire SoC system. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0043] Figure 1 It is a structural block diagram of a memory controller according to an embodiment of the present application.

[0044] Figure 2 It is a structural block diagram of the memory controller of the first embodiment of the present application.

[0045] Figure 3 It is a structural block diagram of a memory controller according to the second embodiment of the present application.

[0046] Figure 4It is a schematic diagram of the address space division of the memory in an embodiment of the present application.

[0047] Figure 5 It is a schematic diagram of the address decoding process of the request in the embodiment of the present application. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application. The numbering of the drawings in this application is only used to distinguish the various steps in the scheme, and is not used to limit the execution order of the various steps. The specific execution order is subject to the description in the specification.

[0049] In order to solve the problems existing in the prior art, the present application embodiment provides a memory controller 100, such as Figure 1 As shown, it includes: a plurality of first interfaces 10, a first end of each first interface 10 is connected to a plurality of master devices 20 in a one-to-one correspondence, and the first interface 10 is used to receive requests from the master devices 20; a conversion module 30, a first end of the conversion module 30 is connected to a second end of each first interface 10, and is used to convert burst transfer mode requests of the master devices 20 received by each first interface 10 into single transfer mode; an arbitration module 40, a first end of the arbitration module 40 is connected to a second end of the conversion module 30, and is used to determine a target request that wins arbitration among a plurality of parallel single transfer mode requests output by the conversion module 30 at a target time; a second interface 50, a first end of the second interface 50 is connected to a second end of the arbitration module 40, a second end of the second interface 50 is connected to a target memory 60, and the second interface 50 is used to access the target memory 60 based on the target request output by the arbitration module 40 at the target time.

[0050] The host device 20 sends a request for a read / write instruction to the memory controller 100 through the first interface 10 of the memory controller 100, so as to access the target memory 60 through the second interface 50 of the memory controller 100. The host device 20 includes, for example, a CPU, a USB, and the like, and the target memory 60 includes, for example, an SRAM memory, a synchronous dynamic random access memory (SDRAM), a double transfer speed random access memory (DDRAM), and the like. The first interface 10 is connected to each host device 20 through a bus, and the protocol of the first interface 10 corresponds to the bus protocol of the host connection, and the protocol of the second interface 20 corresponds to the protocol of the connected target memory 60.

[0051] The request sent by the master device 20 includes a burst transfer attribute or a single transfer attribute. Generally, if the target request sent by the master device 20 is in burst transfer mode, the target memory 60 can be accessed multiple times continuously by sending a target request once, so as to realize multiple continuous data transmissions of burst length, and a single access can realize a data transmission in single transfer mode. If the target request sent by the master device 20 is in single transfer mode, the target request can only be accessed once by sending a target request once, so as to realize a single data transmission. In the embodiment of the present application, a conversion module 30 is designed in the memory controller 100, which is used to convert the burst transfer mode request of the master device 20 received by the first interface 10 into a single transfer mode, that is, to convert a burst mode request into multiple single mode requests, and the converted request is to perform continuous data transmission at each time in single transfer mode.

[0052] Therefore, if there are multiple master devices 20 sending requests at the target time at the same time, for example, one master device 20 sends a first request in single mode and one master device 20 sends a second request in burst mode, the conversion module 30 converts both the first request and the second request into single mode requests after receiving them.

[0053] In the embodiment of the present application, an arbitration module 40 is designed in the memory controller 100 to arbitrate multiple single mode requests output by the target time conversion module 30, determine the request that wins the arbitration, and preferentially access the target memory 60 through the second interface 50.

[0054] The multiple single mode requests output by the target moment conversion module 30 include a single mode request converted from a burst mode and the original single mode request. If there are three single mode requests at the target moment, the arbitration module 40 arbitrates the three single mode requests. The single mode request of the master device that wins the arbitration can access the target memory 60 through the memory controller 100.

[0055] Optionally, the conversion module 30 includes multiple sub-conversion modules, the first end of each sub-conversion module is connected to the multiple first interfaces one by one, and the second end of each sub-conversion module is connected to the first end of the arbitration module, and is used to convert the burst transmission mode request of the master device received by the corresponding connected first interface into a single transmission mode and output it to the arbitration module.

[0056] In this embodiment, a sub-conversion module is designed to be connected to a first interface 10, that is, a sub-conversion module is designed to convert a request sent by a master device 20. The requests sent by different master devices 20 are converted by different sub-conversion modules to obtain single mode requests, and then the single mode requests of the corresponding master devices 20 are sent to the arbitration module 40 through each sub-conversion module.

[0057] The sub-conversion module is specifically used to convert a single burst transfer mode request into multiple single transfer mode requests by converting the protocol of the corresponding connected first interface into a preset protocol, and the number of multiple single transfer mode requests is determined by the burst length of the single burst transfer mode request.

[0058] The sub-conversion module converts the received request write / read protocol into a preset internal write / read protocol. The internal write / read protocol may include the request (request) and response (ack) of the command control channel, and the read data (rdData) and handshake signal (valid / ready) of the data channel. The response signal is used to perform back pressure according to whether the current request wins arbitration, and the handshake signal is used to wait for the read data to be returned from the target memory 60 after the read request is issued. The purpose of the conversion of the preset protocol is to convert complex transactions that may have information such as burst attributes into simple protocols where each transaction is a single transaction.

[0059] Due to the different protocols of the bus connecting the first interface 10 and the host device 20 , the number of channels between each sub-conversion module and the first interface 10 and the number of channels between each sub-conversion module and the arbitration module 40 are also different.

[0060] In one embodiment, the protocol of the first interface is the AXI protocol, and the sub-conversion module includes a read conversion module and a write conversion module. The read conversion module is used to convert a single burst transfer mode read request into multiple single transfer mode read requests by converting the protocol of the read request of the master device received by the corresponding first interface via the read channel at the target time into the preset protocol; the write conversion module is used to convert a single burst transfer mode write request into multiple single transfer mode write requests by converting the protocol of the write request of the master device received by the corresponding first interface via the write channel at the target time into the preset protocol; wherein the read channel is separated from the write channel.

[0061] The read channel and write channel of the AXI protocol are separated. The read channel includes a command control channel for transmitting read requests and responses and a data channel for transmitting read data. The write channel includes a command control channel for transmitting write requests and responses and a data channel for transmitting write data.

[0062] Combination Figure 2 , Figure 2 It is a structural block diagram of a memory controller corresponding to an embodiment when the protocol of the first interface is the AXI protocol.

[0063] exist Figure 2 In the example, for example, three first interfaces are included, namely, AXI0 interface, AXI1 interface and AXI2 interface, and the three first interfaces correspond to three sub-conversion modules. Since the read channel and write channel of the AXI protocol are separated, each sub-conversion module includes a read conversion module and a write conversion module. Among them, the AXI0 interface corresponds to the connection of the write conversion module AXIS_W0 and the read conversion module AXIS_R0, the AXI1 interface corresponds to the connection of the write conversion module AXIS_W1 and the read conversion module AXIS_R1, and the AXI2 interface corresponds to the connection of the write conversion module AXIS_W2 and the read conversion module AXIS_R2.

[0064] Each read conversion module converts the protocol of the read request of the master device received through the read channel at the target time into a preset protocol, thereby converting a single burst mode read request into multiple single mode read requests. Each write conversion module converts the protocol of the write request of the master device received through the write channel at the target time into a preset protocol, thereby converting a single burst mode write request into multiple single mode write requests.

[0065] The read conversion module and the write conversion module send the corresponding conversion requests to the arbitration module 40 at the target time. Figure 2 When the three first interfaces simultaneously receive read requests and write requests sent by the three master devices, six requests are converted accordingly, including write requests and read requests, and the six requests are simultaneously sent to the arbitration module 40 for arbitration.

[0066] In another embodiment, the protocol of the first interface is the AHB protocol, and the sub-conversion module is used to convert a single burst transfer mode request into multiple single transfer mode requests by converting the protocol of the request of the master device received by the corresponding first interface through a single channel at the target time into the preset protocol, and the request of the master device is a read request or a write request.

[0067] The AHB protocol has only one channel, and reading and writing cannot be performed at the same time.

[0068] Combination Figure 3 , Figure 3 It is a structural block diagram of a memory controller corresponding to an embodiment when the protocol of the first interface is the AHB protocol.

[0069] exist Figure 3In the example, for example, three first interfaces are included, namely, AHB0 interface, AHB1 interface and AHB2 interface, and the three first interfaces correspond to three sub-conversion modules. Since the read channel and write channel of the AHB protocol are one, each sub-conversion module performs protocol conversion of the request received by the corresponding channel, and the received request is a write request or a read request. If a write request is received at the target time, protocol conversion is performed on the write request; if a read request is received at the target time, protocol conversion is performed on the read request.

[0070] Among them, the AHB0 interface corresponds to the connection sub-conversion module AHB0_W / R, the AHB1 interface corresponds to the connection sub-conversion module AHB1_W / R, and the AHB2 interface corresponds to the connection sub-conversion module AHB2_W / R.

[0071] Each sub-conversion module converts the protocol of the read / write request of the master device received via a single channel at a target time into a preset protocol, thereby converting a single burst mode read / write request into multiple single modes.

[0072] Each sub-conversion module will respond to the conversion request at the target time and send it to the arbitration module at the same time. Figure 3 When the three first interfaces simultaneously receive read requests and / or write requests sent by three master devices, three single mode requests are correspondingly converted and the three requests are simultaneously sent to the arbitration module for arbitration.

[0073] In the embodiment of the present application, the arbitration module 40 may include one sub-arbitration module or multiple sub-arbitration modules. In the case of including one sub-arbitration module, the arbitration module 40 is used to arbitrate the requests sent by each conversion module at the target time.

[0074] The arbitration module is specifically used to: obtain the priority of multiple parallel single transfer mode requests output by the conversion module at the target moment, the priority of the request is related to the different delay requirements of the main device sending the request, and the priority of multiple single transfer mode requests converted from the same burst transfer mode request is the same; obtain the polling order of the multiple parallel single transfer mode requests at the target moment, the priority of the request with the earlier polling order is higher than the priority of the request with the later polling order; based on the priority and the polling order, determine the target request that wins the arbitration among the multiple parallel single transfer mode requests; convert the preset protocol of the target request into the protocol of the second interface and output it to the second interface.

[0075] For example, the arbitration module 40 can implement three fixed priorities 0, 1, and 2, where 0<1<2. If a request sent by a master device 20 is marked as priority "2", the request will win arbitration over a request with priority "0", and the priority will not change after winning the arbitration, and will remain the highest priority until the priority mark changes. The priority is related to the delay requirement of the master device, and the master device 20 that is extremely sensitive to delay has the highest priority. The priority of multiple single mode requests converted from the same burst mode request remains unchanged during continuous data transmission.

[0076] Specifically, the arbitration module is specifically used to: if the request of the single transfer mode with the highest priority includes a single one, then determine the request of the single transfer mode with the highest priority as the target request that wins the arbitration; if the request of the single transfer mode with the highest priority includes multiple requests, then determine the request with the highest polling order in the multiple requests of the single transfer mode with the highest priority as the target request that wins the arbitration; after the target request wins the arbitration, adjust the polling weight of the first request, the first request is the request of the burst transfer mode before the conversion corresponding to the target request, and the polling weight is related to the burst length of the first request; if at the current moment the first request corresponding to the converted single transfer mode request wins the arbitration so that the adjusted polling weight reaches the preset weight threshold, then set the first request at the end of the polling order, and at the same time restore the polling weight of the first request to the initial setting value.

[0077] If there is a master device 20 that sends a request marked with a fixed priority level of "2", the request is directly determined as the target request that wins the arbitration.

[0078] If there are two or more requests sent by the master devices 20 marked as priority "2" at the same time, the polling order of the requests is further combined to determine which request among the multiple requests with priority "2" wins the current arbitration. The polling order is used to further set the priority of multiple requests. If there are multiple requests with the same fixed priority, the priority of the request at the front in the polling order is higher than the priority of the request at the back, that is, the higher the priority in the polling order.

[0079] Then, the arbitration module 40 combines the fixed priority and the polling sort to determine the request with the highest priority, and then determines it as the target request that wins the arbitration, and further converts the preset protocol of the request, that is, the internal protocol converted by the conversion module 30, into the protocol of the second interface, so that the request can realize read / write access to the target memory 60 through the second interface.

[0080] If a request sent by a master device 20 temporarily fails to win arbitration in the arbitration module 40, the arbitration module 40 can be notified of the corresponding conversion module 30 through the ack signal in the internal write / read protocol. The conversion module 30 can choose whether to continue to inform the corresponding master device 20 at the next higher level according to the depth of its own first in first out (FIFO).

[0081] The arbitration winning request outputted by the arbitration module at the target time may be a single mode request originally sent by the master device 20, or may be a single mode request converted from a burst mode request sent by the master device 20. In the process of burst continuous data transmission of a burst mode request sent by a master device 20, if the arbitration winning request at the target time is a single mode request corresponding to another master device 20, the single mode request is preferentially inserted into the continuous data originally transmitted in burst by the previous master device 20. At the next moment, the request to access the target memory 60 is decided preferentially according to the arbitration result of the arbitration module 40.

[0082] In this way, when multiple master devices need to access the target memory 60 at the same time, and when the properties of the requests initiated by each master device are different, it can be avoided that the burst mode requests sent by the master device 20 always occupy the memory controller 100, so that the request of a delay-sensitive master device 20 can quickly and timely get reply data, improve the operation efficiency of the master device 20 that is extremely sensitive to delay, and thus meet the indicators required by the SoC system. At the same time, the purpose of continuous throughput of large data blocks by another master device 20 is achieved.

[0083] In the above embodiment, the arbitration module can also implement a predetermined number of programmable polling weights. The polling weight here refers to adding the concept of weight to the standard polling arbitration algorithm, that is, not only setting the polling order of each request, but also introducing a polling weight for each request in the polling order, where the weight is related to the maximum burst length of the request sent by the master device.

[0084] For example, the arbitration module receives 5 requests at the same time, including req0, req1, req2, req3, req4, and req5. The polling order corresponding to each request is 1: req0, 2: req1, 3: req3, 4: req5, and 5: req2 from the front to the back, and the initial setting values ​​of the polling weights corresponding to each request are: req0 is 4, req1 is 0, req2 is 255, re4 is 63, and re5 is 4. After winning each arbitration, the weight needs to be reduced by 1. Setting the weight to 0 means that after winning one arbitration, the request must reduce the priority of the polling order to the lowest, that is, the position in the polling order is set to the last.

[0085] Alternatively, the initial setting value of the polling weight corresponding to each request is set to 0. After each arbitration is won, the weight needs to be increased by 1 until the request reaches the corresponding weight threshold, and the position of the request in the polling order is set to the last.

[0086] req2 and req5 have the highest fixed priority, so the target request that wins the arbitration needs to be determined from req2 and req5 in combination with the polling order. Because req2's polling order is 5th and req5's polling order is 4th, req5 has a higher priority than req2 and wins this arbitration.

[0087] At the same time, the weight of req5 that wins arbitration needs to be adjusted, for example, from the initial setting value minus 1 to 4. After req5 wins arbitration 6 times, that is, after the next arbitration win with the weight adjusted to 0, the position of req5 in the polling sorting needs to be set to the last, that is, ranked 5th.

[0088] If the maximum burst length of the target request is 256, the weight can be set to 0-255. The weight is set to 255, which means that after the target request wins 256 consecutive arbitrations, the position of the request in the polling order must be set to the last, and the priority of the polling order is reduced to the lowest. In this embodiment, the arbitration module can implement 256 programmable polling weights.

[0089] Considering that weighted polling arbitration needs to cooperate with the burst attribute of the request to achieve the best effect, it can be further stipulated that the weight logic must respond to "continuous" requests. If a request is interrupted, the priority of the request must be immediately reduced to the lowest and the weight must be returned to the set value to facilitate the next possible burst length data transmission corresponding to the maximum weight.

[0090] Specifically, the arbitration module is also used for: if at the current moment the request for the single transmission mode converted to the corresponding first request continuously wins the arbitration so that the adjusted polling weight does not reach the preset weight threshold, and at the next moment the request for the single transmission mode converted to the corresponding first request is not received, then the position of the first request in the polling sort is set to the last, and at the same time the polling weight of the first request is restored to the initial setting value.

[0091] For example, if the weight configured by the arbitration module is 256, but the burst length of the first request is 128, then after the last single request of the first request is sent, the first request ends, and there are no other requests for the first request. If there are no other requests with higher priority entering at present, the priority of the first request remains unchanged, and the master device corresponding to the first request is in a state of occupying the memory controller but not issuing new requests. In other words, if the request is interrupted, the priority of the first request can be reduced to the lowest, and the weight can be returned to the initial setting value of 255, so that other master devices with access requirements and lower priority than the master device corresponding to the first request can win subsequent arbitration, and then the request can access the target memory through the memory controller.

[0092] Combine the following Figure 2 The embodiment and the example in Table 1 below describe the working principle of the arbitration module 40. Table 1 defines the maximum burst length and delay requirements of three master devices A, B, and C, and the three first ports of the memory controller.

[0093]

[0094] Assume that there are three types of master devices A / B / C in the SoC application environment.

[0095] Combination Figure 2 ,The maximum burst length of master A’s read / write requests is 4, and the latency requirement is high.,Master A corresponds to the AXI0 interface of the memory controller,,that is, the write / read request is executed by the sub-conversion modules AXIS_W0,AXIS_R0,correspondingly.

[0096] The maximum burst length of master B's write request is 256, but the maximum burst length of read request is only 1. According to the characteristics of master B, although the read request is single every time, if the single read data is delayed, the subsequent burst write request containing large batches of data will be seriously affected because the read information cannot be obtained, which will lead to the reduction of the overall performance of master B. The overall data latency requirement of master B is medium for reading and low for writing. Master B corresponds to the AXI1 interface of the memory controller, that is, the write / read request is executed by the sub-conversion modules AXIS_W1 and AXIS_R1.

[0097] The maximum burst length of the master C read request is 256, but the maximum burst length of the write request is only 1. According to the characteristics of the master C, although the write request is single each time, if the single write data is delayed, it will seriously affect the subsequent burst read request containing large batches of data because the write-back information cannot be obtained, which will lead to the reduction of the overall performance of the master C. The overall data latency requirement of the master C is medium for writing and low for reading. The master C corresponds to the AXI2 interface of the memory controller, that is, the write / read request is executed by the sub-conversion modules AXIS_W2 and AXIS_R2.

[0098] In combination with the characteristics of the three masters A / B / C in the SoC application environment, the priority of the AXIS_W0 / AXIS_R0 port corresponding to master A in the memory controller can be set to the highest (2). This ensures that the request of master A will win the arbitration first, thereby minimizing the delay and ensuring the performance of master A.

[0099] Combined with the characteristics of the three masters A / B / C in the SoC application environment, the priority of the AXIS_W1 port corresponding to master B in the memory controller can be set to low (0), and the priority of the AXIS_R1 port can be set to medium (1). At the same time, the polling weight of the AXIS_W1 port of master B can be set to 255 or 127. This can ensure that the write request of master B is still sent as block data in burst mode, occupying high bandwidth, and at the same time, it can also ensure that the read request of master B in single mode can be inserted between the block data of master B and master C, win arbitration first, and ensure the overall performance advantage of master B.

[0100] Combined with the characteristics of the three masters A / B / C in the SoC application environment, the priority of the AXIS_W2 port corresponding to the master C in the memory controller can be set to medium (1), and the priority of the AXIS_R2 port can be set to low (0). At the same time, the polling weight of the AXIS_R2 port of master C can be set to 255 or 127. This can ensure that the read request of master C is still sent in the form of block data, occupying high bandwidth, and at the same time, it can ensure that the single mode write request of master C can be inserted between the block data of master B and master C, win arbitration first, and ensure the overall performance advantage of master C.

[0101] In the embodiment of the present application, the burst transfer mode request sent by each master device 20 is converted into a single transfer mode through the conversion module 30, and provided to the arbitration module 40 for arbitration. In this way, the arbitration module 40 responds to the request of the single transfer mode every time it arbitrates, which can facilitate the execution of the arbitration algorithm. In addition, when the target memory 60 is SRAM, it is also convenient for the arbitration module 40 to directly convert the request of the single transfer mode into a request adapted to the SRAM protocol, because the interface instruction of the SRAM is also a single transfer, so it is convenient to directly convert. Furthermore, it is also convenient for the arbitration module 40 to perform the block data insertion operation, that is, the arbitration module 40 can insert the block data of the single transfer request into the original block data.

[0102] In the embodiment of the present application, through the memory controller of the above structure, the request of the master device 20 which is extremely sensitive to delay can be quickly and timely replied to, thereby improving the operation efficiency of the master device 20 which is extremely sensitive to delay. In addition, if the target memory is a dual-port memory, the requests of two master devices can be used to access the memory in parallel at the same time through a second interface.

[0103] To enable multiple master devices to access the target memory in parallel in a more efficient manner, in one embodiment, the arbitration module 40 includes multiple sub-arbitration modules, and the target memory 60 includes multiple independent address spaces.

[0104] Optionally, the address space of the target memory is divided into multiple independent address spaces, different independent address spaces are used to store data of different master devices, the number of the second interfaces is the same as the number of the multiple independent address spaces, and the arbitration module includes multiple sub-arbitration modules, the first end of each sub-arbitration module is respectively connected to the second end of the multiple sub-conversion modules, and the second end of each sub-arbitration module is connected to the multiple second interfaces in a one-to-one correspondence, and is used to determine the target request that wins the arbitration among the multiple parallel single transfer mode requests output by each sub-conversion module at the target moment, and access the corresponding independent address space through the correspondingly connected second interface.

[0105] That is, the plurality of second interfaces are connected to the plurality of independent address spaces in a one-to-one correspondence, and the plurality of sub-arbitration modules are connected to the plurality of second interfaces in a one-to-one correspondence.

[0106] Combination Figure 2 and Figure 3 In the embodiment, taking the target memory 60 as SRAM as an example, the address space of the SRAM is divided into two independent address spaces, namely the first address space 62 and the second address space 64. In this regard, two second interfaces are included, namely Figure 2The SRAM0 interface and SRAM1 interface of the first address space 62 and the second address space 64 are connected respectively. The arbitration module includes two sub-arbitration modules sram0_arbiter and sram1_arbiter, one end of which is connected to the SRAM0 interface and the SRAM1 interface respectively, and the other end is connected to each sub-conversion module respectively.

[0107] Among them, the sub-arbitration module sram0_arbiter is used to arbitrate multiple parallel single transfer mode requests output by each sub-conversion module at the target moment, and enables the target request that wins the arbitration to access the first address space 62 through the corresponding SRAM0 interface; the sub-arbitration module sram1_arbiter is used to arbitrate multiple parallel single transfer mode requests output by each sub-conversion module at the target moment, and enables the target request that wins the arbitration to access the second address space 64 through the corresponding SRAM1 interface.

[0108] In one embodiment, the multiple independent address spaces include a first address space and a second address space divided based on the address depth of the target memory, the first address space is used to store data of a first master device, and the second address space is used to store data of a second master device, and the first master device and the second master device are different.

[0109] The first master device here may include one or more master devices, and similarly, the second master device may include one or more master devices. For a specific master device, its data may be stored separately in one address space; the data of other multiple master devices may be stored simultaneously in another address space. If the number of divided address spaces is the same as the number of master devices connected to the first interface, the data of each master device may be stored separately in different address spaces in a one-to-one correspondence.

[0110] The sizes of the first address space and the second address space may be the same or different, depending on the requirements of the master device for storing data.

[0111] The address space for storing data of the master device is specified in real time according to program running. If the address space specified for storing the target master device is insufficient, part of the data of the target master device may also be stored in another address space.

[0112] If the memory controller 100 controls the first address space 62 and the second address space 64 at the same time, assuming that the total SRAM address space is 256KB, then according to the address depth, the first address space 62 is responsible for the 0-127KB address space, and the second address space 64 is responsible for the 128-255KB address space.

[0113] Furthermore, on the basis of the address space divided by the address depth, the first address space 62 and the second address space 64 may be divided respectively in combination with a concept definition similar to a "ping-pong" address.

[0114] Specifically, the first address space further includes a first sub-address space and a second sub-address space divided based on preset data units, and the second address space further includes a third sub-address space and a fourth sub-address space divided based on the preset data units.

[0115] Among them, the first sub-address space corresponds to an odd-granularity address space among a plurality of address spaces obtained by dividing the first address space with the preset data unit, and the second sub-address space corresponds to an even-granularity address space among a plurality of address spaces obtained by dividing the first address space with the preset data unit; the third sub-address space corresponds to an odd-granularity address space among a plurality of address spaces obtained by dividing the second address space with the preset data unit, and the fourth sub-address space corresponds to an even-granularity address space among a plurality of address spaces obtained by dividing the second address space with the preset data unit.

[0116] Thus, the SRAM can be divided into four independent address spaces. Correspondingly, the number of second interfaces is four, one-to-one connected to each address space, and the number of sub-arbitration modules is four, one-to-one connected to each second interface.

[0117] The four sub-arbitration modules respectively determine the target request that wins arbitration among the multiple parallel single transfer mode requests output by each sub-conversion module at the target time, and access the corresponding independent address space through the correspondingly connected second interface.

[0118] Combination Figure 4 The embodiment includes four arbitration sub-modules arbiter0, arbiter1, arbiter2, and arbiter3, which correspond to four address spaces sram0, sram1, sram2, and sram3 respectively. Each address space is responsible for a 64KB storage interval. According to the address depth, sram0 and sram1 are responsible for the 0-127KB address space, and sram2 and sram3 are responsible for the 128-255KB address space. Within each 128KB, the granularity is divided into 4KB as the preset data unit, and the address is divided in a "ping-pong" manner, that is, sram0 and sram2 are responsible for the 1st (128-255KB) address space. st ) / 3 (3 rd ) / 5 / 7 / …29 (29 th ) / / 31(31 th) 4KB odd-granularity address space, SRAM 1 and SRAM 3 take over the second (2 nd ) / 4(4 th ) / 6 / 8 / …30 (30 th ) / 32 (32 th ) 4KB even-granularity address space.

[0119] In the case of multiple sub-arbitration modules, each sub-arbitration module receives requests from multiple sub-conversion modules, which are requests for the address space corresponding to each sub-arbitration module. That is, the request sent by each master device needs to be address decoded, and after determining the address space accessed by the corresponding request, it is transmitted to the corresponding sub-arbitration module.

[0120] According to the address space division method of the above embodiment, when programming the software, the data of different master devices can be preset in two independent address spaces, such as 0-127KB and 128-255KB, according to the application scenario. In this way, in the case of 4 sub-arbitration modules, these 4 sub-arbitration modules can work independently and in parallel. Therefore, if the data of different master devices are in different SRAM address spaces, the data of at least 2 master devices can be read and written in parallel, which will greatly speed up the overall application efficiency of the SoC.

[0121] In addition, SRAM 0 and SRAM 2, SRAM 1 and SRAM 3 are divided with preset bytes as the granularity, and data is stored in a "ping-pong" manner. From the perspective of macro time, multiple master devices can still read and write accesses between SRAM 0 and SRAM 2, or SRAM 1 and SRAM 3 in parallel in a relatively random manner even without manual intervention in allocating variable data intervals. As a result, the average operating speed of multiple master devices is accelerated.

[0122] Here, for the AXI protocol, 4KB is selected as the granularity for internal SRAM division. Because according to the AXI protocol, a burst mode request is not allowed to exceed the 4KB boundary. Therefore, combining 4KB as the granularity can ensure that a burst mode request will not need to switch address spaces due to "ping-pong" space allocation, and thus ensure that the data of a burst mode request will not fall into two address spaces, nor will it enter two arbitration modules midway and require secondary arbitration.

[0123] Similarly, for the AHB protocol, 1KB can be selected as the granularity for internal SRAM division.

[0124] Optionally, the memory controller 100 also includes: a decoding module, which is arranged between the target sub-conversion module and the multiple sub-arbitration modules, and is used to determine the independent address space corresponding to the request by decoding the address of the request output by the target sub-conversion module; and output the request to the sub-arbitration module corresponding to the independent address space accessed by the request.

[0125] by Figure 2 For example, a decoding module 70 is provided between the write conversion module AXIS_W0 and the sub-arbitration module sram0_arbiter, and a decoding module 70 is also provided between the read conversion module AXIS_R0 and the sub-arbitration module sram0_arbiter. The decoding module 70 decodes the address of the write request output by the write conversion module AXIS_W0 to determine whether the address space corresponding to the write request is the first address space or the second address space, and outputs the corresponding write request to the corresponding address space, so that the write request is correspondingly written into the correct address space in the SRAM.

[0126] For the embodiment of the present application combining the address depth and the address space divided similar to "ping-pong", when decoding the requested address, it is necessary to combine two levels of decoding to realize the positioning of the address space.

[0127] Specifically, if Figure 5 As shown in the embodiment, the decoding module includes a two-level address decoding circuit of a first-level address decoding 72 and a second-level address decoding 74. The first-level address decoding 72 decodes the address of the request, for example, the 17th bit. If the 17th bit address is 0, it represents a request to access the address space of 0-127KB; if the 17th bit address is 1, it represents a request to access the address space of 128-255KB. The second-level address decoding 74 decodes the address of the request, for example, the 12th bit. If the 12th bit address is 0, it represents a request to access the address space of 1 / 3 / … / 31 (corresponding to Figure 5 1st / 3rd / ... / 31th) 4KB address space in the address space; if the 12th address is 1, it means access to the 2nd / 4th / ... / 32nd (corresponding to Figure 5 Request for 2nd / 4th / ... / 32th) 4KB of address space.

[0128] In an embodiment of the present application, a memory controller includes: a plurality of first interfaces, a first end of each first interface is connected to a plurality of master devices in a one-to-one correspondence, and the first interface is used to receive a request from the master device; a conversion module, a first end of the conversion module is connected to a second end of each first interface, and is used to convert a burst transfer mode request of the master device received by each first interface into a single transfer mode; an arbitration module, a first end of the arbitration module is connected to a second end of the conversion module, and is used to determine a target request that wins arbitration among a plurality of parallel single transfer mode requests output by the conversion module at a target time; a second interface, a first end of the second interface is connected to a second end of the arbitration module, a second end of the second interface is connected to a target memory, and the second interface is used to output a target memory based on the arbitration module at the target time. The target memory is accessed through a target request. Thus, when there are multiple master devices that need to access the target memory at the same time, and the burst attributes of the requests initiated by each master device are different, the request of a high-delay-sensitive master device that has won the arbitration at the current moment can be preferentially inserted into the data block continuously transmitted by another master device through the converted single transfer mode request, so as to avoid the request of the master device of the continuously transmitted data block always occupying the memory controller, so that a delay-sensitive master device can quickly return data, and at the same time another master device can continuously throughput large data blocks, thereby improving the operating efficiency of the delay-sensitive master device to meet the indicators required by the SoC system, and will not affect the normal operation of the master device that continuously transmits data blocks, thereby improving the operating performance of the entire SoC system.

[0129] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0130] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0131] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A memory controller, characterized in that: include: A plurality of first interfaces, a first end of each first interface being connected to a plurality of master devices in a one-to-one correspondence, and the first interface being used to receive a request from the master device; A conversion module, wherein a first end of the conversion module is connected to a second end of each first interface, and is used to convert a burst transmission mode request of a master device received by each first interface into a single transmission mode; An arbitration module, wherein a first end of the arbitration module is connected to a second end of the conversion module, and is used to determine a target request that wins arbitration among a plurality of parallel single-transfer mode requests output by the conversion module at a target time; a second interface, a first end of the second interface being connected to a second end of the arbitration module, a second end of the second interface being connected to a target memory, and the second interface being used to access the target memory based on a target request output by the arbitration module at the target time; The conversion module comprises a plurality of sub-conversion modules, wherein the first end of each sub-conversion module is connected to the plurality of first interfaces in a one-to-one correspondence, and the second end of each sub-conversion module is connected to the first end of the arbitration module, and is used to convert the burst transmission mode request of the master device received by the corresponding first interface into a single transmission mode and output it to the arbitration module; The sub-conversion module is specifically used to convert a single burst transfer mode request into multiple single transfer mode requests by converting the protocol of the corresponding connected first interface into a preset protocol, and the number of multiple single transfer mode requests is determined by the burst length of the single burst transfer mode request.

2. The memory controller according to claim 1, wherein: The protocol of the first interface is the AXI protocol, and the sub-conversion module includes a read conversion module and a write conversion module. The read conversion module is used to convert a single burst transfer mode read request into multiple single transfer mode read requests by converting the protocol of the read request of the master device received by the corresponding first interface via the read channel at the target time into the preset protocol; The write conversion module is used to convert a single burst transfer mode write request into multiple single transfer mode write requests by converting the protocol of the write request of the master device received by the corresponding first interface via the write channel at the target time into the preset protocol; Wherein, the read channel is separated from the write channel.

3. The memory controller according to claim 1, wherein: The protocol of the first interface is the AHB protocol, and the sub-conversion module is used to convert the protocol of the request of the master device received by the corresponding first interface through a single channel at the target time into the preset protocol, and convert the request of a single burst transfer mode into multiple single transfer mode requests, and the request of the master device is a read request or a write request.

4. The memory controller according to any one of claims 1 to 3, characterized in that: The arbitration module is specifically used for: Obtaining the priorities of multiple parallel single transfer mode requests output by the conversion module at the target time, wherein the priority of the request is related to different delay requirements of the master device sending the request, and the priorities of multiple single transfer mode requests converted from the same burst transfer mode request are the same; Obtaining the polling order of the multiple requests in the parallel single transfer mode at the target time, wherein the request with the earlier polling order has a higher priority than the request with the later polling order; Determine the target request that wins arbitration among the multiple parallel single transfer mode requests based on priority and polling order; The preset protocol of the target request is converted into the protocol of the second interface and then output to the second interface.

5. The memory controller according to claim 4, characterized in that: The arbitration module is specifically used for: If the request in the single transfer mode with the highest priority includes a single, determining the request in the single transfer mode with the highest priority as the target request that wins the arbitration; If the single transfer mode request with the highest priority includes multiple requests, the request with the highest polling order among the multiple single transfer mode requests with the highest priority is determined as the target request that wins the arbitration; After the target request wins the arbitration, adjusting the polling weight of the first request, the first request being a request of the burst transmission mode before the target request is converted, and the polling weight is related to the burst length of the first request; If at the current moment the first request corresponding to the converted single transfer mode request wins the arbitration so that the adjusted polling weight reaches the preset weight threshold, the first request is set to the last position in the polling sorting, and at the same time the polling weight of the first request is restored to the initial setting value.

6. The memory controller according to claim 5, characterized in that: The arbitration module is further used for: If at the current moment the request for the single transfer mode to which the first request corresponds is converted continuously wins arbitration so that the adjusted polling weight does not reach the preset weight threshold, and at the next moment the request for the single transfer mode to which the first request corresponds is not received, the position of the first request in the polling sort is set to the last, and at the same time the polling weight of the first request is restored to the initial setting value.

7. The memory controller according to claim 4, characterized in that: The address space of the target memory is divided into a plurality of independent address spaces, and different independent address spaces are used to store data of different master devices. The number of the second interfaces is the same as the number of the plurality of independent address spaces. The arbitration module includes a plurality of sub-arbitration modules, wherein the first end of each sub-arbitration module is respectively connected to the second end of the plurality of sub-conversion modules, and the second end of each sub-arbitration module is connected to a plurality of second interfaces in a one-to-one correspondence, and is used to determine a target request that wins arbitration among a plurality of parallel single-transfer mode requests output by each sub-conversion module at a target time, and access a corresponding independent address space through the correspondingly connected second interface.

8. The memory controller according to claim 7, characterized in that: Also includes: A decoding module is arranged between the target sub-conversion module and the plurality of sub-arbitration modules, and is used to determine the independent address space corresponding to the request by decoding the address of the request output by the target sub-conversion module; and output the request to the sub-arbitration module corresponding to the independent address space accessed by the request.

9. The memory controller according to claim 7, characterized in that: The multiple independent address spaces include a first address space and a second address space divided based on the address depth of the target memory, the first address space is used to store data of a first master device, the second address space is used to store data of a second master device, and the first master device and the second master device are different.

10. The memory controller according to claim 9, characterized in that: The first address space further includes a first sub-address space and a second sub-address space divided based on a preset data unit, and the second address space further includes a third sub-address space and a fourth sub-address space divided based on the preset data unit; The first sub-address space corresponds to an odd-numbered granularity address space among a plurality of address spaces obtained by dividing the first address space by the preset data unit, and the second sub-address space corresponds to an even-numbered granularity address space among a plurality of address spaces obtained by dividing the first address space by the preset data unit; The third sub-address space corresponds to an odd-granularity address space among a plurality of address spaces obtained by dividing the second address space by the preset data unit, and the fourth sub-address space corresponds to an even-granularity address space among a plurality of address spaces obtained by dividing the second address space by the preset data unit.

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