A method for evaluating the size of modular combinational logic

Abstract

The present invention relates to a module combination logic size evaluation method, belonging to the field of electronic design automation, the method comprises the following steps: constructing an initial logic tree; judging in turn whether there is a subtree with the same structure under a certain node from the top to the bottom of the logic tree, if so, deleting the node and one of the subtrees with the same structure, connecting the remaining subtrees with the same structure to the parent node of the node; judging in turn whether there is a subtree with the same structure under different nodes from the top to the bottom of the logic tree, if so, deleting some of the subtrees with the same structure and retaining only one subtree with the same structure, and connecting the corresponding nodes to the only subtree retained; estimating the logic scale according to the simplified logic tree. The method makes the binary tree method faster without losing accuracy, and meets the demand for rapid estimation of the module combination logic scale in the RTL segmentation scenario.

Description

Technical Field

[0001] The invention belongs to the field of electronic design automation (EDA), and in particular relates to a module combination logic size evaluation method. Background Art

[0002] The design of a chip consists of many modules and the communication signals between modules. The design logic of the chip can be expressed in a relatively high-level language at the RTL level, such as Verilog, VHDL, etc., or it can be expressed by a lower-level netlist. The netlist contains specific gate-level structures and the connections (net) between gates. The conversion process from high-level language to low-level language is called logic synthesis. The object of segmentation can be a netlist or an RTL language. The former belongs to the late segmentation and the latter belongs to the early segmentation. If you want to perform a parallel process of logic synthesis, you must perform an early segmentation at the RTL level to divide the entire RTL into different sub-parts.

[0003] The segmentation process is to divide the chip design into a specified number of sub-parts, each of which is called a sub-design. During the segmentation process, the sub-designs are required to be equal or similar in size to achieve resource balance between the sub-designs. There are many standards for measuring module size, such as power consumption, logical scale, and physical size. Generally speaking, the logical scale of the module is the most commonly used standard.

[0004] If the combinational logic is synthesized, a gate-level netlist will be obtained, and the logic scale can be directly obtained. The obtained logic scale is also the most accurate, but the combinational synthesis process often consumes a lot of time and computing resources, which is very costly. The main difficulty in estimating the size of module logic lies in the estimation of combinational logic. Sequential logic is related to the number of states of the state machine in the module, and the merging operation of the same state machine is also relatively easy, that is, states with the same sub-state and output can be merged, while the simplification process of combinational logic involves more complex situations, so it is more difficult to estimate.

[0005] Existing RTL-level segmentation often synthesizes the module combination logic and then gives the logic size of the module. Although this method has more accurate results, it consumes too much time and is not suitable for the rapid segmentation requirements of the RTL level, because the RTL-level segmentation itself has the characteristics of pre-layout in the early stage and requires faster result output. Therefore, a method is needed to quickly and roughly estimate the logic size of the RTL-level module and directly perform RTL-level segmentation without going through the synthesis process. A logical expression is a meaningful formula that connects relational expressions or logical quantities with logical operators. The value of a logical expression is a logical value, that is, "true" or "false". When the compilation system gives the result of a logical operation, the number 1 represents "true" and the number 0 represents "false". However, when judging whether a quantity is "true", 0 represents "false" and non-0 represents "true". The so-called logical size is the sum of the number of operations between adjacent variables in the logical expression.

[0006] The prior art often uses two technical means in the process of logic conversion and simplification. The first is the tabular method. The idea is to first extract the variable combinations whose expressions are "true" according to the truth table; then group the above combinations according to the number of "true" variables; finally, match the variable combinations in adjacent groups that differ by 1 in the number of "true" variables, merge only one variable that is a different variable combination, and update the table; repeat the above steps until further simplification is impossible. The advantage of this method is that it can obtain the simplest form of the logical expression, and the disadvantage is that the amount of calculation is huge and the result cannot be obtained quickly. However, in the segmentation scenario, it is necessary to quickly obtain a simplified logical expression and estimate the logical resources, so this method is difficult to meet the current needs of large-scale design segmentation.

[0007] The second method is the binary tree method, that is, each layer of the tree node represents a variable, and the node has two child nodes to the left and right. One of the child nodes is the situation when the variable corresponding to the parent node is "true", and the other child node corresponds to the parent node is "not". The leaf nodes of the whole tree are "true" or "not", "true" is represented by "1", and "not" is represented by "0", and the result of the expression is obtained. The process of the binary tree method is to merge the same subtrees and eliminate redundant nodes layer by layer from the leaf node, that is, from the bottom to the top, until the above operation is performed to the top node. Finally, starting from the top node, all the paths from the vertex to the leaf node of the variable are taken, and the path where the expression is "true" is formed into a logical expression. Compared with the table method, this method is faster, but in the demand for rapid estimation, it still has a large time complexity due to the cumbersome operation steps. Summary of the invention

[0008] The present invention provides a module combination logic size evaluation method to solve the problems of huge calculation amount, complicated operation steps and slow estimation speed in the existing module combination logic size evaluation method.

[0009] In order to solve the above technical problems, the technical solution provided by the present invention is:

[0010] The present invention relates to a module combination logic size evaluation method, which comprises the following steps:

[0011] S1. Construct the initial logic tree;

[0012] S2. From the top to the bottom of the logic tree, find out whether there is a subtree with the same structure under a certain node. If so, delete the node and one of the subtrees with the same structure, and connect the remaining subtrees with the same structure to the parent node of the node;

[0013] S3. From the top to the bottom of the logic tree, find out whether there are subtrees with the same structure under different nodes. If so, delete some of the subtrees with the same structure and keep only one subtree with the same structure, and connect the corresponding nodes to the only subtree that is kept.

[0014] S4. Estimate the logic size based on the simplified logic tree obtained from S2 and S3.

[0015] Preferably, the specific method for determining whether two subtrees are subtrees of the same structure in S2 and S3 is:

[0016] Step (1). Create two queue structures;

[0017] Step (2). Push the top nodes of the two subtrees into two queue structures respectively;

[0018] Step (3). Determine whether the two queues are the same. If they are, proceed to the next step. Otherwise, output that the subtree structures are different and end the determination.

[0019] Step (4). Pop the node in the queue structure, and push the child nodes of the popped node into the two queue structures in order;

[0020] Step (5). Determine whether both queues have not pushed in child nodes. If so, output the child node structures are the same and end the determination. If not, proceed to step (6).

[0021] Step (6). Determine whether only one queue pushes the child node. If so, the output subtree structure is different and the determination ends. If not, return to step (3).

[0022] Preferably, before creating two queue structures in step (1), count whether the number of nodes in the two subtrees of the node is the same. If the number of nodes is different, determine that the subtree structures are different and end the determination. If they are the same, start step (1).

[0023] Preferably, the S4 searches for all logic paths from the top node to the bottom node of the simplified logic tree based on the simplified logic tree, constructs a logic expression, and determines the logic scale based on the logic expression.

[0024] Preferably, when S4 searches for all logical paths from the top node to the bottom node of the simplified logic tree, all logical paths with the bottom node having a value of 1 as the end point are searched and corresponding logical expressions L1 are constructed, and the logic scale is determined based on the logical expression L1.

[0025] Preferably, the specific steps of S4 acquiring the logical path are:

[0026] S4.1. Build a queue and a set of driver nodes for each node;

[0027] S4.2. Push the top node into the queue;

[0028] S4.3. Pop up the node that first enters the queue. If the pop-up node has child nodes, determine whether the child nodes of the pop-up node are already in the queue. If the child nodes of the pop-up node are already in the queue, add the pop-up node as the driver node of the child node to the driver node set of the child node. If the child nodes of the pop-up node are not in the queue, bring the child nodes of the pop-up node into the queue in order from the smallest to the largest node layer, and use the top node as the driver node of the node brought in and put it into the driver node set of the node brought in. If the pop-up node does not have child nodes, do not perform any operation;

[0029] S4.4. Determine whether there is a node in the queue. If so, return to S4.3. If not, start from the bottom node with a value of 1 and recursively search for the driver node of the driver node until the top node position, output all path combinations to form the final logical path.

[0030] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0031] The module combination logic size evaluation method disclosed by the present invention first searches for whether there are subtrees with the same structure under a certain node for an initial logic tree. If so, the node and one of the subtrees with the same structure are deleted, and the remaining subtrees with the same structure are connected to the parent node of the node; then searches for whether there are subtrees with the same structure under different nodes. If so, some of the subtrees with the same structure are deleted and only the only subtree with the same structure is retained, and the corresponding nodes are all connected to the only retained subtree, thereby deleting redundant variables and obtaining a simplified logic tree; finally, according to the simplified logic tree, a full path search algorithm is used to quickly obtain logic paths with all logic expressions being "1", so that the binary tree method is faster without losing accuracy, and meets the demand for rapid estimation of the module combination logic size in the RTL segmentation scenario. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a flow chart of a module combination logic size evaluation method according to the present invention;

[0033] Figure 2 is a schematic diagram of the structure of the initial logic tree in the embodiment;

[0034] Figure 3 This is a schematic diagram of operations when there are subtrees with the same structure under the same node;

[0035] Figure 4 This is a schematic diagram of the operation when there are subtrees with the same structure under different parent nodes;

[0036] Figure 5 It is the flow chart of S2 and S3 to determine whether two subtrees have the same structure;

[0037] Figure 6 It is a simplified logical tree structure diagram. DETAILED DESCRIPTION

[0038] In order to further understand the content of the present invention, the present invention is described in detail in conjunction with examples. The following examples are used to illustrate the present invention but are not used to limit the scope of the present invention.

[0039] See attached Figure 1 As shown, the present invention relates to a module combination logic size evaluation method comprising the following steps:

[0040] S1. Construct the initial logic tree: record the different logical combinations of the values ​​of each variable in the module in the "true" and "false" states and the results of the corresponding logical expressions as the bottom nodes (leaf nodes) of the logic tree. The leaf nodes are represented by "1" when they are "true" and "0" when they are "false". According to the order of variable numbering, each variable constitutes a layer of the logic tree. Each node has two child nodes, which represent the "true" or "false" situations of the variable represented by the parent node. The dotted line represents "false" and the solid line represents "true". Any path from the top node to the leaf node (including the connection between nodes) is called a logic path. The form of the initial logic tree is as follows: Figure 2 As shown in the figure, there are four variables a, b, c, and d in the logic tree, which form the 1st, 2nd, 3rd, and 4th layers of the tree in order. "True" and "false" are represented by "1" and "0" respectively, forming the leaf nodes of the tree. The leaf nodes are also the final logical values ​​of the logical expressions. The nodes and paths from the vertex to the leaf nodes constitute the logical path, for example Figure 2 The leftmost logic path a→b→c→d→0 means that when a, b, c, and d are all "not", the value of the logical expression is "not".

[0041] S2. Find out whether there is a subtree with the same structure under a certain node. If so, delete the node and one of the subtrees with the same structure, and connect the remaining subtrees with the same structure to the parent node of the node. In this process, you can search from the top to the bottom of the logic tree to find out whether there is a subtree with the same structure under a certain node, as shown in the following figure. Figure 2 As shown in FIG. 1 , it is a schematic diagram of the structure of the initial logic tree shown in this embodiment. From the schematic diagram of the structure of the initial logic tree, it can be seen that the two subtrees under the b node on the left side of the initial logic tree are subtrees with the same structure, which are represented by T1 and T2 respectively. Figure 3 As shown, one of the subtrees (T1 or T2) under the b node is deleted, and the remaining subtrees with the same structure are connected to the parent node of the node (a node).

[0042] After this step, the subtrees with the same parent node are processed, and there may still be subtrees with the same structure but not belonging to the same parent node in the processed logical tree.

[0043] S3. Search for subtrees with the same structure under different nodes in turn. If so, delete some subtrees with the same structure and keep only one subtree with the same structure, and connect all corresponding nodes to the only subtree that is kept. In this process, you can search for subtrees with the same structure under different nodes from the top to the bottom of the logic tree. Figure 4As shown, assuming that two parent nodes N and M have two subtree structures T1 and T2 respectively, and the two subtrees T1 and T2 have the same structure, then delete one of the subtrees T1 or T2, and connect both node N and node M to the only retained subtree T1 or T2.

[0044] Since, when two subtrees have the same structure, they must have the same number of nodes. Therefore, when S2 and S3 are looking for subtrees with the same structure, for the two subtrees, we can first count whether the number of nodes in the two subtrees is the same. If the number of nodes is different, we judge that the subtree structures are different and end the judgment. If they are the same, we proceed to the next step of judgment. In this way, we can save time in finding subtrees with the same structure. Figure 5 As shown, the specific method for S2 and S3 to determine whether two subtrees are subtrees of the same structure is:

[0045] Step (1). Create two queue structures;

[0046] Step (2). Push the top nodes of the two subtrees into two queue structures respectively;

[0047] Step (3). Determine whether the two queues are the same. If they are, proceed to the next step. Otherwise, output that the subtree structures are different and end the determination.

[0048] Step (4). Pop the node in the queue structure, and push the child nodes of the popped node into the two queue structures in order;

[0049] Step (5). Determine whether both queues have not pushed in child nodes. If so, output the child node structures are the same and end the determination. If not, proceed to step (6).

[0050] Step (6). Determine whether only one queue pushes the child node. If so, the output subtree structure is different and the determination ends. If not (both queues push the child node), return to step (3).

[0051] S4. Estimate the logic scale based on the simplified logic tree: After S2 and S3, Figure 2 The initial logic tree in can be simplified as follows Figure 6 The simplified logic tree shown in FIG. searches for all logic paths from the top node to the bottom node of the simplified logic tree and constructs a logic expression. Specifically, searches for all logic paths with the bottom node having a value of 1 as the end point and constructs the corresponding logic expression L1. The specific steps for obtaining the logic path are:

[0052] S4.1. Build a queue and a set of driver nodes for each node;

[0053] S4.2. Push the top node into the queue;

[0054] S4.3. Pop up the node that first enters the queue. If the pop-up node has child nodes, determine whether the child nodes of the pop-up node are already in the queue. If the child nodes of the pop-up node are already in the queue, add the pop-up node as the driver node of the child node to the driver node set of the child node. If the child nodes of the pop-up node are not in the queue, bring the child nodes of the pop-up node into the queue in order from the smallest to the largest node layer, and use the top node as the driver node of the node brought in and put it into the driver node set of the node brought in. If the pop-up node does not have child nodes, do not perform any operation;

[0055] S4.4. Determine whether there is a node in the queue. If so, return to S4.3. If not, start from the bottom node with a value of 1, recursively search for the driver node of the driver node until the top node position, output all path combinations, and form the final logical path;

[0056] Based on the above steps, we get Figure 6 For the simplified logic tree shown in the figure, when calculating the logic scale, the scale of all logic paths from the vertex to the leaf node with a value of 1 (true) should be calculated. Therefore, Figure 6 The logical expression L1 of the final logical path shown is F = ab + (-a)cd+a(-b)cd. In this logical expression, there is an AND operation between two variables (for example, ab represents the AND operation of variable a and variable b), "-" represents a NOT operation, and "+" represents an OR operation, and the final logical scale is 10 (the total number of AND operations, NOT operations, and OR operations).

[0057] The present invention is described in detail above in conjunction with the embodiments, but the contents described are only preferred embodiments of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made according to the scope of application of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A module combination logic size assessment method, which is applied to the RTL segmentation scenario, is characterized by: It includes the following steps: S1. Construct the initial logic tree; S2. From the top to the bottom of the logic tree, find out whether there is a subtree with the same structure under a certain node. If so, delete the node and one of the subtrees with the same structure, and connect the remaining subtrees with the same structure to the parent node of the node; S3. From the top to the bottom of the logic tree, find out whether there are subtrees with the same structure under different nodes. If so, delete some of the subtrees with the same structure and keep only one subtree with the same structure, and connect the corresponding nodes to the only subtree that is kept. S4. Estimate the logic scale according to the simplified logic tree obtained in S2 and S3, specifically: based on the simplified logic tree, search for all logic paths from the top node to the bottom node of the simplified logic tree, and construct a logic expression, and determine the logic scale based on the logic expression; When searching for all logical paths from the top node to the bottom node of the simplified logic tree, all logical paths with the bottom node having a value of 1 as the end point are searched and the corresponding logical expression L1 is constructed. The logical scale is determined based on the logical expression L1. The specific steps for obtaining the logical path are as follows: S4.

1. Build a queue and a set of driver nodes for each node; S4.

2. Push the top node into the queue; S4.

3. Pop up the node that first enters the queue. If the pop-up node has child nodes, determine whether the child nodes of the pop-up node are already in the queue. If the child nodes of the pop-up node are already in the queue, add the pop-up node as the driver node of the child node to the driver node set of the child node. If the child nodes of the pop-up node are not in the queue, bring the child nodes of the pop-up node into the queue in order from the smallest to the largest node layer, and use the top node as the driver node of the node brought in and put it into the driver node set of the node brought in. If the pop-up node does not have child nodes, do not perform any operation; S4.

4. Determine whether there is a node in the queue. If so, return to S4.

3. If not, start from the bottom node with a value of 1 and recursively search for the driver node of the driver node until the top node position, output all path combinations to form the final logical path.

2. The module combination logic size evaluation method according to claim 1, characterized in that: The specific method for determining whether two subtrees are subtrees of the same structure in S2 and S3 is: Step (1). Create two queue structures; Step (2). Push the top nodes of the two subtrees into two queue structures respectively; Step (3). Determine whether the two queues are the same. If they are, proceed to the next step. Otherwise, output that the subtree structures are different and end the determination. Step (4). Pop the node in the queue structure, and push the child nodes of the popped node into the two queue structures in order; Step (5). Determine whether both queues have not pushed in child nodes. If so, output the child node structures are the same and end the determination. If not, proceed to step (6). Step (6). Determine whether only one queue pushes the child node. If so, the output subtree structure is different and the determination ends. If not, return to step (3).

3. The module combination logic size evaluation method according to claim 2, characterized in that: Before creating the two queue structures in step (1), first count whether the number of nodes in the two subtrees of the node is the same. If the number of nodes is not the same, then determine that the subtree structures are different and end the determination. If they are the same, then start step (1).

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