LED chip

Abstract

This application discloses a light-emitting diode (LED) chip. The LED chip includes a semiconductor stacked layer and an insulating layer; the insulating layer includes at least a first insulating layer and a second insulating layer; the insulating layer has a stepped structure, comprising a first step formed by the first insulating layer and a second step formed by the second insulating layer, with the first step extending beyond the second step in the horizontal direction. In this application, the insulating layer is formed by at least a first insulating layer and a second insulating layer, which can prevent cracks or complete layer fractures in the insulating layer, improving its reliability. Furthermore, since the first insulating layer extends a predetermined length beyond the second insulating layer in the horizontal direction, this extended portion can act as a buffer when a second structural layer is subsequently formed on the insulating layer, reducing the stress generated within the second structural layer and preventing cracks or complete layer fractures under stress, thus improving the reliability of the LED chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of light emitting diode, and in particular to a light emitting diode chip. BACKGROUND

[0002] The light emitting diode chip is widely used in various fields due to its high reliability, long service life and low power consumption. The insulating layer in the light emitting diode chip is mostly a single silicon oxide layer with a large thickness. When other structural layers are formed on the single silicon oxide layer, a large slope exists at the end or via hole of the single silicon oxide layer. When the other structural layers are formed on the single silicon oxide layer, a large stress is generated inside the other structural layers, which leads to cracks or layer breakage of the other structural layers, thereby reducing the reliability of the light emitting diode chip. SUMMARY

[0003] The purpose of the present application is to provide a light emitting diode chip, wherein the insulating layer is formed by at least a first insulating layer and a second insulating layer, and the first insulating layer exceeds the second insulating layer by a predetermined length in the horizontal direction, so as to reduce the stress generated inside the second insulating layer when the second structural layer is formed on the second insulating layer, avoid cracks or layer breakage of the second insulating layer under the action of stress, and improve the reliability of the light emitting diode chip.

[0004] In a first aspect, an embodiment of the present application provides a light emitting diode chip having a semiconductor stack layer and an insulating layer, the insulating layer including at least a first insulating layer and a second insulating layer formed on the upper surface of the first insulating layer; the insulating layer has a step structure including a first step formed by the first insulating layer and a second step formed by the second insulating layer, and the first step exceeds the second step in the horizontal direction.

[0005] In a possible implementation, the thickness of the second insulating layer is greater than the thickness of the first insulating layer, and the thickness of the second insulating layer is equal to or greater than 1 μm.

[0006] In a possible implementation, the length L1 by which the first step exceeds the second step is equal to or greater than 50 nm and less than or equal to 5000 nm.

[0007] In a possible implementation, when the first insulating layer is an atomic layer deposition layer, the length L1 by which the first step exceeds the second step is equal to or greater than 100 nm and less than or equal to 5000 nm.

[0008] In a possible implementation, when the first insulating layer is a high-density plasma chemical vapor deposition (HDPCVD) layer, the length L1 by which the first step exceeds the second step is equal to or greater than 50 nm and less than or equal to 100 nm.

[0009] In a possible implementation, an angle a1 between the side surface of the first step and the horizontal direction is smaller than an angle a2 between the side surface of the second step and the horizontal direction.

[0010] In a possible implementation, the side surface of the second step is a slope surface, and an angle a2 between the slope surface and the horizontal direction is between 20° and 40°, between 40° and 60°, or between 60° and 70°.

[0011] In a possible implementation, an angle a1 between the side surface of the first step and the horizontal direction decreases in the vertical direction, and the angle a1 is between 10° and 30° or between 30° and 45°.

[0012] In a possible implementation, the insulating layer is provided with a through hole penetrating the insulating layer, and a side wall of the through hole is configured as the step structure.

[0013] An end portion of the insulating layer is configured as the step structure.

[0014] In a possible implementation, when the first insulating layer is an atomic layer deposition layer, a thickness of the first insulating layer is between 30 nm and 200 nm.

[0015] The second insulating layer is a high-density plasma chemical vapor deposition (HDPCVD) layer, a plasma chemical vapor deposition (PECVD) layer, or an evaporation deposition layer.

[0016] In a possible implementation, when the first insulating layer is a high-density plasma chemical vapor deposition (HDPCVD) layer, a thickness of the first insulating layer is between 400 nm and 1000 nm.

[0017] The second insulating layer is an evaporation deposition layer.

[0018] In a possible implementation, the first insulating layer and the second insulating layer are prepared by the same preparation process, and the first insulating layer and the second insulating layer are made of different materials. The materials of the first insulating layer and the second insulating layer include one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide.

[0019] In a possible implementation, the material of the first insulating layer is aluminum oxide.

[0020] In a possible implementation, the second insulating layer is a distributed Bragg reflector (DBR).

[0021] In a possible implementation, the insulating layer further includes a third insulating layer formed on an upper surface of the second insulating layer, and the step structure further includes a third step formed by the third insulating layer. A length L2 by which the second step exceeds the third step in the horizontal direction is smaller than a length L1 by which the first step exceeds the second step.

[0022] In a possible implementation, the insulating layer is formed with a second structure layer away from the surface of the first insulating layer, and the second structure layer has an extension ratio δ equal to or less than 50%.

[0023] In a possible implementation, the second structure layer is made of one of nickel, gold, titanium, chromium, indium tin oxide, titanium oxide, silicon oxide, aluminum oxide, silicon nitride, titanium nitride, and aluminum nitride.

[0024] In a possible implementation, the insulating layer is formed with a first structure layer close to the surface of the first insulating layer, and the first structure layer is a transparent insulating layer, a transparent conductive layer, or a metal layer.

[0025] In a possible implementation, the semiconductor stack layer is the first structure layer, the insulating layer is formed on the semiconductor stack layer, and the second insulating layer is away from the semiconductor stack layer.

[0026] In a possible implementation, the light-emitting diode chip further includes:

[0027] The substrate is the first structure layer; the semiconductor stack layer forms a mesa structure on the substrate; the insulating layer covers at least the sidewall of the semiconductor stack layer and a part of the substrate other than the semiconductor stack layer; and the second insulating layer is away from the semiconductor stack layer.

[0028] In a second aspect, an embodiment of the present application provides an insulating layer, which includes at least:

[0029] a first insulating layer and a second insulating layer formed on the surface of the first insulating layer;

[0030] a step structure including a first step formed by the first insulating layer and a second step formed by the second insulating layer, the first step exceeding the second step in the horizontal direction.

[0031] In a possible implementation, the thickness of the second insulating layer is greater than the thickness of the first insulating layer, and the thickness of the second insulating layer is equal to or greater than 1 μm.

[0032] In a possible implementation, the length L1 by which the first step exceeds the second step is equal to or greater than 50 nm and less than or equal to 5000 nm.

[0033] In a possible implementation, when the first insulating layer is an atomic layer deposition layer, the length L1 by which the first step exceeds the second step is equal to or greater than 100 nm and less than or equal to 5000 nm.

[0034] In one possible implementation, when the first insulating layer is a high-density plasma chemical vapor deposition (HDPCVD) layer, the length L1 of the first step exceeding the second step is equal to or greater than 50 nm and less than or equal to 100 nm.

[0035] In one possible implementation, the angle α1 between the side of the first step and the horizontal direction is smaller than the angle α2 between the side of the second step and the horizontal direction.

[0036] In one possible implementation, the side of the second step is a sloping surface, and the angle α2 between the sloping surface and the horizontal direction is between 20° and 40°, 40° and 60° or 60° and 70°.

[0037] In one possible implementation, the angle α1 between the side of the first step and the horizontal direction decreases in the vertical direction, and the angle α1 is between 10° and 30° or between 30° and 45°.

[0038] In one possible implementation, the insulating layer has a through-hole that penetrates the insulating layer, and the sidewall of the through-hole is configured with the aforementioned stepped structure;

[0039] The ends of the insulating layer are configured with the aforementioned stepped structure.

[0040] In one possible implementation, when the first insulating layer is an atomic layer deposition layer, the thickness of the first insulating layer is between 30 and 200 nm.

[0041] The second insulating layer is a high-density plasma chemical vapor deposition (HDPCVD) layer, a plasma chemical vapor deposition (PECVD) layer, or a vapor deposition layer.

[0042] In one possible implementation, when the first insulating layer is a high-density plasma chemical vapor deposition (HDPCVD) layer, the thickness of the first insulating layer is between 400 and 1000 nm.

[0043] The second insulating layer is a vapor-deposited layer.

[0044] In one possible implementation, the first insulating layer and the second insulating layer are prepared by the same preparation process, and the materials used to prepare the first insulating layer and the second insulating layer are different; the materials used to prepare the first insulating layer and the second insulating layer include one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide or titanium oxide.

[0045] In one possible implementation, the first insulating layer is made of aluminum oxide.

[0046] In one possible implementation, the second insulating layer is a distributed Bragg mirror (DBR).

[0047] In one possible implementation, the insulating layer further includes a third insulating layer formed on the upper surface of the second insulating layer; the stepped structure further includes a third step formed by the third insulating layer; and the length L2 of the second step extending beyond the third step in the horizontal direction is less than the length L1 of the first step extending beyond the second step.

[0048] Compared with the prior art, this application has at least the following beneficial effects:

[0049] In this application, the insulating layer is formed by at least a first insulating layer and a second insulating layer, which can prevent cracks or complete fractures in the insulating layer, thereby improving its reliability. Furthermore, if the first insulating layer extends horizontally beyond a predetermined length of the second insulating layer, this extended portion can act as a buffer when the second structural layer is subsequently formed on the insulating layer, reducing the stress generated within the second structural layer and preventing cracks or complete fractures under stress, thus improving the reliability of the LED chip. Additionally, if the portion of the first insulating layer extending horizontally beyond the second insulating layer is located at the end of the insulating layer, this extended portion can also prevent moisture from entering, thus preventing aging and failure of the LED chip. Attached Figure Description

[0050] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 This is a cross-sectional schematic diagram of a light-emitting diode chip according to an embodiment of this application;

[0052] Figure 2 This is a cross-sectional schematic diagram of a light-emitting diode chip according to an embodiment of this application;

[0053] Figure 3 This is a cross-sectional schematic diagram of a light-emitting diode chip according to an embodiment of this application;

[0054] Figure 4 This is a cross-sectional schematic diagram of a light-emitting diode chip according to an embodiment of this application;

[0055] Figure 5 This is a cross-sectional schematic diagram of a light-emitting diode chip according to an embodiment of this application;

[0056] Figure 6 This is a cross-sectional schematic diagram of a light-emitting diode chip according to an embodiment of this application;

[0057] Figure 7 This is a cross-sectional schematic diagram of a light-emitting diode chip according to an embodiment of this application;

[0058] Figure 8 This is a cross-sectional schematic diagram of a light-emitting diode chip according to an embodiment of this application;

[0059] Figure 9 This is a cross-sectional schematic diagram of a light-emitting diode chip according to an embodiment of this application;

[0060] Figure 10 This is a cross-sectional schematic diagram of a light-emitting diode chip according to an embodiment of this application;

[0061] Figure 11 This is a schematic cross-sectional view of an insulating layer according to an embodiment of this application;

[0062] Figure 12 This is a schematic cross-sectional view of an insulating layer according to an embodiment of this application;

[0063] Figure 13 This is a schematic cross-sectional view of an insulating layer according to an embodiment of this application;

[0064] Figure 14 This is a cross-sectional schematic diagram of an insulating layer according to an embodiment of this application.

[0065] Illustration:

[0066] 10 Insulating layer; 11 First insulating layer; 12 Second insulating layer; 13 Third insulating layer; 14 Stepped structure; 20 First structural layer; 30 Second structural layer; 40 Semiconductor stacked layer; 50 Substrate;

[0067] 110 Substrate; 120 Semiconductor stacked layer; 121 Type 1 semiconductor layer; 122 Active layer; 123 Type 2 semiconductor layer; 130 Current blocking layer; 140 Transparent conductive layer; 151 First electrode; 152 Second electrode; 160 Protective layer; 171 First pad; 172 Second pad;

[0068] 210 Substrate; 220 Semiconductor stacked layer; 221 First type semiconductor layer; 222 Active layer; 223 Second type semiconductor layer; 230 Transparent conductive layer; 240 Reflective layer; 251 First electrode; 252 Second electrode; 260 First protective layer; 271 First pad; 272 Second pad; 280 Second protective layer;

[0069] 310 Substrate; 320 Semiconductor stacked layer; 321 First type semiconductor layer; 322 Active layer; 323 Second type semiconductor layer; 330 Transparent conductive layer; 340 First protective layer; 350 Reflective layer; 360 Second protective layer; 370 First electrode; 380 Second electrode; 390 Third protective layer;

[0070] 410 Substrate; 420 Semiconductor stacked layer; 421 First type semiconductor layer; 422 Active layer; 423 Second type semiconductor layer; 430 Current blocking layer; 440 Transparent conductive layer; 451 First electrode; 452 Second electrode; 453 Interconnect electrode; 460 Protective layer; 471 First pad; 472 Second pad. Detailed Implementation

[0071] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or operated through other different specific embodiments, and various details in this application can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application.

[0072] In the description of this application, it should be noted that the terms "upper", "lower", "height", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this application is usually placed when in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0073] According to one aspect of this application, a light-emitting diode chip is provided. See also Figure 1 and Figure 2 The light-emitting diode chip includes a semiconductor stacked layer 40 and an insulating layer 10. The insulating layer 10 includes at least a first insulating layer 11 and a second insulating layer 12 formed on the upper surface of the first insulating layer 11, and the insulating layer 10 has a stepped structure 14. The stepped structure 14 includes a first step formed by the first insulating layer 11 and a second step formed by the second insulating layer 12, wherein the first step extends beyond the second step in the horizontal direction, or it can be described as the first insulating layer 11 extending beyond the second insulating layer 12 in the horizontal direction.

[0074] The insulating layer 10 is formed of at least a first insulating layer 11 and a second insulating layer 12, which can prevent cracks or complete breakage of the insulating layer 10 and improve the reliability of the insulating layer 10. Furthermore, the first insulating layer 11 extends horizontally beyond the second insulating layer 12 by a predetermined length. This extended portion can act as a buffer when the second structural layer 30 is subsequently formed on the insulating layer 10, reducing the stress generated inside the second structural layer 30 and preventing cracks or complete breakage of the second structural layer 30 under stress, thereby improving the reliability of the light-emitting diode chip.

[0075] In one implementation, see Figure 1 and Figure 2 An insulating layer 10 has a first structural layer 20 formed on its surface near the first insulating layer 11. The first structural layer 20 is a transparent insulating layer, a transparent conductive layer, or a metal layer. A second structural layer 30 is formed on the surface of the insulating layer 10 away from the first insulating layer 11. The second structural layer 30 covers the upper surface of the insulating layer 10 and the stepped structure 14. The elongation δ of the second structural layer 30 is equal to or less than 50%. According to the elongation δ relationship between the metals: aluminum 70.92%, silver 54.38%, copper 53.2%, nickel 48.4%, gold 35%, platinum 24.2%, titanium 24.94%, chromium 20.99%, and tungsten 8.84%, the preferred material for the second structural layer 30 is one of nickel, gold, titanium, chromium, indium tin oxide, titanium oxide, silicon oxide, aluminum oxide, silicon nitride, titanium nitride, or aluminum nitride.

[0076] As an alternative implementation, see [link to relevant documentation]. Figure 5 The semiconductor stacked layer 40 serves as the first structural layer 20, the insulating layer 10 is formed on the semiconductor stacked layer 40, and the second insulating layer 12 is located away from the semiconductor stacked layer 40.

[0077] As an alternative implementation, see [link to relevant documentation]. Figure 6 The light-emitting diode chip also includes a substrate 50. The substrate 50 serves as the first structural layer 20, the semiconductor stacked layer 40 forms a mesa structure on the substrate 50, the insulating layer 10 covers at least the sidewalls of the semiconductor stacked layer 40 and a portion of the substrate 50 excluding the semiconductor stacked layer 40; the second insulating layer 12 is located away from the semiconductor stacked layer 40.

[0078] In one embodiment, the thickness of the second insulating layer 12 is greater than the thickness of the first insulating layer 11, and the thickness of the second insulating layer 12 is equal to or greater than 1 μm. Because the second insulating layer 12 has a larger thickness, the second step has a larger slope. When the second structural layer 30 is formed on the second step, the portion of the first step that extends beyond the second step can better buffer the second structural layer 30, reducing the stress generated inside the second structural layer 30 and preventing cracks or complete fracture of the second structural layer 30 under stress.

[0079] See Figure 1 and Figure 2 The angle α1 between the side of the first step and the horizontal direction is smaller than the angle α2 between the side of the second step and the horizontal direction. Preferably, the angle α1 between the side of the first step and the horizontal direction decreases vertically, and this angle α1 is between 10° and 30° or 30° and 45°. The side of the second step is a sloping surface, and the angle α2 between the sloping surface and the horizontal direction is between 20° and 40°, 40° and 60° or 60° and 70°.

[0080] As an alternative implementation, see [link to relevant documentation]. Figure 3 The sides of the first and second steps are vertical.

[0081] In one implementation, see Figure 1 and Figure 2 The stepped structure 14 is located at the end or middle portion of the insulating layer 10. The insulating layer 10 has a through-hole penetrating it, and the sidewall of the through-hole is configured as the stepped structure 14. Figure 1 The end of the insulating layer 10 is configured as a stepped structure 14. Figure 2 When the stepped structure 14 is located at the end of the insulating layer 10, the portion of the first insulating layer 11 that extends beyond the second insulating layer 12 in the horizontal direction can block moisture from entering, thus preventing the light-emitting diode chip from aging and failing.

[0082] In one embodiment, the materials used to prepare the first insulating layer 11 and the second insulating layer 12 include one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. Preferably, the first insulating layer 11 is made of aluminum oxide, as the first insulating layer 11 prepared using aluminum oxide has good water resistance. The second insulating layer 12 is a distributed Bragg reflector (DBR).

[0083] When the first insulating layer 11 is an atomic layer deposition layer, the thickness of the first insulating layer 11 is between 30 and 200 nm, preferably between 30 and 100 nm; or, between 100 and 150 nm; or, between 150 and 200 nm. When the first insulating layer 11 is a high-density plasma chemical vapor deposition (HDPCVD) layer, the thickness of the first insulating layer 11 is between 400 and 1000 nm, preferably between 400 and 600 nm; or, between 600 and 800 nm; or, between 800 and 1000 nm.

[0084] The density of the first insulating layer 11 is greater than the maximum density of the second insulating layer 12. The first insulating layer 11 and the second insulating layer 12 can be prepared using different processes, and the materials used in their preparation can be the same or different. For example, when the first insulating layer 11 is an atomic layer deposition layer, the second insulating layer 12 can be a high-density plasma chemical vapor deposition (HDPCVD) layer, a plasma chemical vapor deposition (PECVD) layer, or a vapor deposition layer. When the first insulating layer 11 is a high-density plasma chemical vapor deposition (HDPCVD) layer, the second insulating layer 12 can be a vapor deposition layer. The first insulating layer 11 and the second insulating layer 12 can also be prepared using the same process, but the materials used in their preparation can be different. For example, both the first insulating layer 11 and the second insulating layer 12 can be atomic layer deposition layers, or both can be high-density plasma chemical vapor deposition (HDPCVD) layers.

[0085] Since the density of the first insulating layer 11 is greater than the maximum density of the second insulating layer 12, when the insulating layer 10 is etched using a dry etching method or a wet etching method, the etching rate of the first insulating layer 11 is less than the etching rate of the second insulating layer 12. Therefore, a stepped structure 14 is formed in the insulating layer 10. Preferably, the dry etching method is inductively coupled plasma (ICP).

[0086] In one implementation, see Figure 1~Figure 3 The first step extends horizontally beyond the second step by a length L1 equal to or greater than 50 nm and less than or equal to 5000 nm. This length L1 is related to the density between the first insulating layer 11 and the second insulating layer 12; the greater the difference in density between the first insulating layer 11 and the second insulating layer 12, the larger L1 is. For example, when the first insulating layer 11 is an atomic layer deposition layer, L1 is equal to or greater than 100 nm and less than or equal to 5000 nm. When the first insulating layer 11 is a high-density plasma chemical vapor deposition (HDPCVD) layer, L1 is equal to or greater than 50 nm and less than or equal to 100 nm.

[0087] In one implementation, see Figure 4 The insulating layer 10 also includes a third insulating layer 13 formed on the upper surface of the second insulating layer 12. Correspondingly, the stepped structure 14 also includes a third step formed by the third insulating layer 13. In the horizontal direction, the length L2 of the second step extending beyond the third step is less than the length L1 of the first step extending beyond the second step.

[0088] The thickness of the third insulating layer 13 is equal to or greater than the thickness of the second insulating layer 12, and the density of the third insulating layer 13 is equal to or less than the minimum density of the second insulating layer 12. The third insulating layer 13, the first insulating layer 11, and the second insulating layer 12 can be prepared using different processes. For example, the first insulating layer 11 can be an atomic layer deposition layer, the second insulating layer 12 can be a high-density plasma chemical vapor deposition (HDPCVD) layer, and the third insulating layer 13 can be a vapor deposition layer. Alternatively, the third insulating layer 13, the first insulating layer 11, and the second insulating layer 12 can be prepared using the same process, but the materials used to prepare the third insulating layer 13, the first insulating layer 11, and the second insulating layer 12 can be different.

[0089] The LED chip provided in this embodiment was tested under different conditions to verify its reliability:

[0090] The LED chip provided in this embodiment was subjected to aging tests under different conditions: 1) 85℃ +1500mA; 2) 115℃ +1500mA; 3) high temperature and high humidity; 4) dual 85℃ +15mA and 5) -45℃ to 125℃ cold and hot cycle. The LED chips after the tests all showed high reliability.

[0091] The following example illustrates the specific implementation structure of a light-emitting diode (LED) chip: Example 1

[0092] See Figure 7 This embodiment provides a flip-chip light-emitting diode (LED) chip. Figure a is an overall structural diagram of the LED chip, and Figure b is an enlarged view of the area within the black box in Figure a. The LED chip includes a substrate 110 and a semiconductor stacked layer 120 located on the upper surface of the substrate 110. The semiconductor stacked layer 120 forms a mesa structure on the upper surface of the substrate 110. The semiconductor stacked layer 120 includes a first type semiconductor layer 121, an active layer 122, and a second type semiconductor layer 123 arranged sequentially from bottom to top, and has a groove extending from the second type semiconductor layer 123 into the interior of the first type semiconductor layer 121, the groove exposing a portion of the first type semiconductor layer 121.

[0093] Preferably, the first type semiconductor layer 121 is an N-type semiconductor layer, the second type semiconductor layer 123 is a P-type semiconductor layer, and the active layer 122 is a multilayer quantum well layer. The substrate 110 is a sapphire flat substrate or a sapphire patterned substrate.

[0094] In one embodiment, the light-emitting diode chip further includes a current blocking layer 130, a transparent conductive layer 140, an electrode layer, a protective layer 160, and a pad layer arranged in sequence. The current blocking layer 130 is formed on the upper surface of the second type semiconductor layer 123, and the length of the transparent conductive layer 140 is greater than the length of the current blocking layer 130, so that the transparent conductive layer 140 covers the upper surface and sidewalls of the current blocking layer 130. The electrode layer includes a first electrode 151 electrically connected to the first type semiconductor layer 121 and a second electrode 152 electrically connected to the second type semiconductor layer 123. The pad layer includes a first pad 171 electrically connected to the first electrode 151 and a second pad 172 electrically connected to the second electrode 152. The protective layer 160 covers the upper surface and sidewalls of the semiconductor stacked layer 120 and the area on the upper surface of the substrate 110 other than the semiconductor stacked layer 120.

[0095] In this structure, the electrode layer corresponds to the first structural layer, the pad layer corresponds to the second structural layer, and the protective layer 160 corresponds to the insulating layer. Through-holes are formed in the protective layer 160 at positions corresponding to the first electrode 151 and the second electrode 152. The first pad 171 fills the through-holes and is electrically connected to the first electrode 151, and the second pad 172 fills the through-holes and is electrically connected to the second electrode 152. As shown in Figure b, the sidewalls of the through-holes in the protective layer 160 are configured with the aforementioned stepped structure.

[0096] Preferably, the material used to prepare the current blocking layer 130 is an oxide of silicon, specifically including one or more of silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0097] Preferably, the transparent conductive layer 140 is generally made of a conductive material with transparent properties. In this embodiment, the transparent conductive layer 140 is made of indium tin oxide, which mainly serves as an ohmic contact and a lateral current spreader.

[0098] Preferably, the first electrode 151 and the second electrode 152 are both made of Au or an alloy of Au. The structure and materials of the protective layer 160 are the same as those of the insulating layer provided in the above embodiments. Example 2

[0099] See Figure 8This embodiment provides a flip-chip light-emitting diode (LED) chip. Figure a is an overall structural diagram of the LED chip, and Figure b is an enlarged view of the area within the black box in Figure a. The LED chip includes a substrate 210 and a semiconductor stack layer 220 located on the upper surface of the substrate 210. The semiconductor stack layer 220 forms a mesa structure on the upper surface of the substrate 210. The semiconductor stack layer 220 includes a first type semiconductor layer 221, an active layer 222, and a second type semiconductor layer 223 arranged sequentially from bottom to top, and has a groove extending from the second type semiconductor layer 223 into the interior of the first type semiconductor layer 221, the groove exposing a portion of the first type semiconductor layer 221.

[0100] Preferably, the first type semiconductor layer 221 is an N-type semiconductor layer, the second type semiconductor layer 223 is a P-type semiconductor layer, and the active layer 222 is a multilayer quantum well layer. The substrate 210 is a sapphire flat substrate or a sapphire patterned substrate.

[0101] In one embodiment, the light-emitting diode chip further includes a transparent conductive layer 230, a reflective layer 240, an electrode layer, a first protective layer 260, a first pad 271, a second protective layer 280, and a second pad 272 arranged in sequence. The transparent conductive layer 230 is formed on the upper surface of the second type semiconductor layer 223, and the length of the reflective layer 240 is greater than the length of the transparent conductive layer 230, so that the reflective layer 240 covers the upper surface and sidewalls of the transparent conductive layer 230. The electrode layer includes a first electrode 251 electrically connected to the first type semiconductor layer 221 and a second electrode 252 electrically connected to the second type semiconductor layer 223.

[0102] The first pad 271 is electrically connected to the first electrode 251, and the second pad 272 is electrically connected to the second electrode 252. The height of the upper surface of the first pad 271 is less than the height of the upper surface of the second pad 272, and a second protective layer 280 is formed between the first pad 271 and the second pad 272. The second pad 272 is continuously or intermittently disposed on the upper surface of the second protective layer 280. Both the first protective layer 260 and the second protective layer 280 cover the upper surface and sidewalls of the semiconductor stacked layer 220, as well as the area on the upper surface of the substrate 210 excluding the semiconductor stacked layer 220.

[0103] In this design, the electrode layer corresponds to the first structural layer described above, the pad layer corresponds to the second structural layer described above, and the first protective layer 260 and the second protective layer 280 correspond to the insulating layer described above. A through-hole is formed in the first protective layer 260 at the position corresponding to the first electrode 251, and the first pad 271 fills the through-hole and is electrically connected to the first electrode 251. A through-hole is formed in the second protective layer 280 at the position corresponding to the second electrode 252, and the second pad 272 fills the through-hole and is electrically connected to the second electrode 252. As shown in Figure b, the sidewalls of the through-holes in the second protective layer 280 are configured with the aforementioned stepped structure. Similarly, the sidewalls of the through-holes in the first protective layer 260 are also configured with the aforementioned stepped structure.

[0104] Preferably, the transparent conductive layer 230 is generally made of a conductive material with transparent properties. In this embodiment, the transparent conductive layer 230 is made of indium tin oxide, which mainly serves as an ohmic contact and a lateral current spreader.

[0105] Preferably, the reflective layer 240 is made of silver. The first electrode 251 and the second electrode 252 are both made of Au or an alloy of Au. The structure and materials of the first protective layer 260 and the second protective layer 280 are the same as those of the insulating layer provided in the above embodiments. Example 3

[0106] See Figure 9 This embodiment provides a vertically structured light-emitting diode (LED) chip. Figure a is an overall structural diagram of the LED chip, and Figure b is an enlarged view of the area within the black box in Figure a. The LED chip includes a substrate 310, a semiconductor stacked layer 320, and a functional layer located between the substrate 310 and the semiconductor stacked layer 320. The two sides of the semiconductor stacked layer 320 are offset from the two sides of the substrate 310, and the two sides of the functional layer are aligned with the two sides of the substrate 310, i.e., the semiconductor stacked layer 320 forms a mesa structure on the upper surface of the substrate 310. A third protective layer 390 covers a portion of the surface and sidewalls of the semiconductor stacked layer 320, as well as the area on the upper surface of the substrate 310 other than the semiconductor stacked layer 320. This third protective layer 390 can be the insulating layer provided in the above embodiment.

[0107] The semiconductor stack 320 includes a first type semiconductor layer 321, an active layer 322 and a second type semiconductor layer 323 arranged sequentially from top to bottom, and has a groove extending from the second type semiconductor layer 323 into the interior of the first type semiconductor layer 321, the groove exposing a portion of the first type semiconductor layer 321.

[0108] Preferably, the first type semiconductor layer 321 is an N-type semiconductor layer, the second type semiconductor layer 323 is a P-type semiconductor layer, and the active layer 322 is a multilayer quantum well layer. The substrate 310 is made of GaAs, Ge, Si, Cu, Mo, WCu, or MoCu.

[0109] In one embodiment, the functional layer includes a transparent conductive layer 330, a first protective layer 340, a reflective layer 350, a second protective layer 360, and a first electrode 370 electrically connected to a first type semiconductor layer 321, arranged in sequence. The transparent conductive layer 330 is connected to a second type semiconductor layer 323, and the first electrode 370 is connected to a substrate 310. A second electrode 380 is provided in the area above the functional layer, excluding the semiconductor stacked layer 320. The first protective layer 340 has an opening communicating with the reflective layer 350 and the second electrode 380. The reflective layer 350 fills the opening and is electrically connected to the second electrode 380.

[0110] In this structure, the transparent conductive layer 330 corresponds to the first structural layer, the reflective layer 350 corresponds to the second structural layer, and the first protective layer 340 corresponds to the insulating layer. The height of the first protective layer 340 is greater than the height of the transparent conductive layer 330, and it covers the periphery of the transparent conductive layer 330 to electrically isolate the transparent conductive layer 330 from the reflective layer 350. The bottom of the first protective layer 340 has a through-hole connecting the reflective layer 350 and the transparent conductive layer 330. The reflective layer 350 fills the through-hole and is electrically connected to the transparent conductive layer 330. As shown in Figure b, the sidewall of the through-hole in the first protective layer 340 is configured with the aforementioned stepped structure. Similarly, the sidewall of the opening in the first protective layer 340 connecting the reflective layer 350 and the second electrode 380 is also configured with the aforementioned stepped structure.

[0111] The semiconductor stacked layer 320 can be equivalent to the first structural layer mentioned above, and the third protective layer 390 can be equivalent to the insulating layer mentioned above. Other structural layers can be deposited on the third protective layer 390.

[0112] Preferably, the transparent conductive layer 330 is generally made of a conductive material with transparent properties. In this embodiment, the transparent conductive layer 330 is made of indium tin oxide, which mainly serves as an ohmic contact and a lateral current spreader.

[0113] Preferably, the material used to fabricate the second electrode 380 includes any combination of Au, Ti, Al, Cr, Pt, TiW alloys, or Ni. The material used to fabricate the first electrode 370 includes Au or an alloy of Au.

[0114] Preferably, the structure and materials of the first protective layer 340 and the second protective layer 360 are the same as those of the insulating layer provided in the above embodiments. Example 4

[0115] See Figure 10 This embodiment provides a high-voltage structure light-emitting diode (LED) chip. Figure a is an overall structural diagram of the LED chip, and Figure b is an enlarged view of the area within the black box in Figure a. The LED chip includes a substrate 410 and a plurality of spaced semiconductor stacked layers 420, with adjacent semiconductor stacked layers 420 separated by dicing. Each semiconductor stacked layer 420 includes a first type semiconductor layer 421, an active layer 422, and a second type semiconductor layer 423 arranged sequentially from bottom to top, and has a groove extending from the second type semiconductor layer 423 into the interior of the first type semiconductor layer 421, the groove exposing a portion of the first type semiconductor layer 421.

[0116] In one embodiment, the light-emitting diode chip further includes a current blocking layer 430, a transparent conductive layer 440, an electrode layer, a protective layer 460, and a pad layer arranged in sequence. The current blocking layer 430 covers the upper surface of the second type semiconductor layer 123, the sidewalls of the semiconductor stack 420, and a portion of the dicing. The transparent conductive layer 440 covers a portion of the current blocking layer 430. The electrode layer includes a first electrode 451 electrically connected to the first type semiconductor layer 421, a second electrode 452 electrically connected to the second type semiconductor layer 423, and interconnect electrodes 453 connecting adjacent semiconductor stack layers 420. The pad layer includes a first pad 471 electrically connected to the first electrode 451 and a second pad 472 electrically connected to the second electrode 452. The protective layer 460 covers the upper surface, sidewalls, and dicing of the semiconductor stack 420.

[0117] In this configuration, substrate 410 corresponds to the first structural layer, interconnect electrode 453 corresponds to the second structural layer, and current blocking layer 430 corresponds to the insulating layer. As shown in Figure b, the end of current blocking layer 430 is configured with the stepped structure described above.

[0118] In the electrode layer, the first electrode 451 and the second electrode 452 correspond to the first structural layer described above, the pad layer corresponds to the second structural layer described above, and the protective layer 460 corresponds to the insulating layer described above. Through-holes are respectively formed in the protective layer 460 at positions corresponding to the first electrode 451 and the second electrode 452. The first pad 471 fills the through-hole and is electrically connected to the first electrode 451, and the second pad 472 fills the through-hole and is electrically connected to the second electrode 452. Similarly, the sidewalls of the through-holes in the protective layer 460 are also configured with the stepped structure described above.

[0119] Preferably, the current blocking layer 430 is made of silicon oxide, specifically one or more of silicon oxide, silicon nitride, silicon carbide or silicon oxynitride.

[0120] Preferably, the transparent conductive layer 440 is generally made of a conductive material with transparent properties. In this embodiment, the transparent conductive layer 440 is made of indium tin oxide, which mainly serves as an ohmic contact and a lateral current spreader.

[0121] Preferably, the first electrode 451, the second electrode 452, and the interconnect electrode 453 are all made of Au or an alloy of Au. The structure and materials of the protective layer 460 are the same as those of the insulating layer provided in the above embodiments.

[0122] It should be noted that the structures of the light-emitting diode chips involved in Embodiments 1, 2, 3 and 4 are merely exemplary. In addition to the above-mentioned flip-chip structure light-emitting diode chips, vertical structure light-emitting diode chips and high-voltage structure light-emitting diode chips, the light-emitting diode chips claimed in this application are also applicable to light-emitting diode chips with other structures.

[0123] According to one aspect of this application, an insulating layer is provided. See also Figure 11 and Figure 12 The insulating layer 10 includes at least a first insulating layer 11 and a second insulating layer 12 formed on the upper surface of the first insulating layer 11. The insulating layer 10 has a stepped structure 14, which includes a first step formed by the first insulating layer 11 and a second step formed by the second insulating layer 12. The first step extends beyond the second step in the horizontal direction, or it can be described as the first insulating layer 11 extending beyond the second insulating layer 12 in the horizontal direction.

[0124] The insulating layer 10 is formed of at least a first insulating layer 11 and a second insulating layer 12, which can prevent cracks or complete breakage of the insulating layer 10 and improve the reliability of the insulating layer 10. Furthermore, the first insulating layer 11 extends horizontally beyond the second insulating layer 12 by a predetermined length. This extended portion can buffer the second structural layer 30 during the subsequent process of forming the second structural layer 30 on the insulating layer 10, reducing the stress generated inside the second structural layer 30 and preventing cracks or complete breakage of the second structural layer 30 under stress, thereby improving the reliability of the light-emitting diode chip using this insulating layer.

[0125] In one embodiment, the thickness of the second insulating layer 12 is greater than the thickness of the first insulating layer 11, and the thickness of the second insulating layer 12 is equal to or greater than 1 μm. Because the second insulating layer 12 has a larger thickness, the second step has a larger slope. When the second structural layer 30 is formed on the second step, the portion of the first step that extends beyond the second step can better buffer the second structural layer 30, reducing the stress generated inside the second structural layer 30 and preventing cracks or complete fracture of the second structural layer 30 under stress.

[0126] See Figure 11 and Figure 12 The angle α1 between the side of the first step and the horizontal direction is smaller than the angle α2 between the side of the second step and the horizontal direction. Preferably, the angle α1 between the side of the first step and the horizontal direction decreases vertically, and this angle α1 is between 10° and 30° or 30° and 45°. The side of the second step is a sloping surface, and the angle α2 between the sloping surface and the horizontal direction is between 20° and 40°, 40° and 60° or 60° and 70°.

[0127] As an alternative implementation, see [link to relevant documentation]. Figure 13 The sides of the first and second steps are vertical.

[0128] In one implementation, see Figure 11 and Figure 12 The stepped structure 14 is located at the end or middle portion of the insulating layer 10. The insulating layer 10 has a through-hole penetrating it, and the sidewall of the through-hole is configured as the stepped structure 14. Figure 11 The end of the insulating layer 10 is configured as a stepped structure 14. Figure 12 When the stepped structure 14 is located at the end of the insulating layer 10, the portion of the first insulating layer 11 that extends beyond the second insulating layer 12 in the horizontal direction can block moisture from entering, thus preventing the light-emitting diode chip from aging and failing.

[0129] In one embodiment, the materials used to prepare the first insulating layer 11 and the second insulating layer 12 include one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. Preferably, the first insulating layer 11 is made of aluminum oxide, as the first insulating layer 11 prepared using aluminum oxide has good water resistance. The second insulating layer 12 is a distributed Bragg reflector (DBR).

[0130] When the first insulating layer 11 is an atomic layer deposition layer, the thickness of the first insulating layer 11 is between 30 and 200 nm, preferably between 30 and 100 nm; or, between 100 and 150 nm; or, between 150 and 200 nm. When the first insulating layer 11 is a high-density plasma chemical vapor deposition (HDPCVD) layer, the thickness of the first insulating layer 11 is between 400 and 1000 nm, preferably between 400 and 600 nm; or, between 600 and 800 nm; or, between 800 and 1000 nm.

[0131] The density of the first insulating layer 11 is greater than the maximum density of the second insulating layer 12. The first insulating layer 11 and the second insulating layer 12 can be prepared using different processes, and the materials used in their preparation can be the same or different. For example, when the first insulating layer 11 is an atomic layer deposition layer, the second insulating layer 12 can be a high-density plasma chemical vapor deposition (HDPCVD) layer, a plasma chemical vapor deposition (PECVD) layer, or a vapor deposition layer. When the first insulating layer 11 is a high-density plasma chemical vapor deposition (HDPCVD) layer, the second insulating layer 12 can be a vapor deposition layer. The first insulating layer 11 and the second insulating layer 12 can also be prepared using the same process, but the materials used in their preparation can be different. For example, both the first insulating layer 11 and the second insulating layer 12 can be atomic layer deposition layers, or both can be high-density plasma chemical vapor deposition (HDPCVD) layers.

[0132] Since the density of the first insulating layer 11 is greater than the maximum density of the second insulating layer 12, when the insulating layer 10 is etched using a dry etching method or a wet etching method, the etching rate of the first insulating layer 11 is less than the etching rate of the second insulating layer 12. Therefore, a stepped structure 14 is formed in the insulating layer 10. Preferably, the dry etching method is inductively coupled plasma (ICP).

[0133] In one implementation, see Figure 11~Figure 13 The first step extends horizontally beyond the second step by a length L1 equal to or greater than 50 nm and less than or equal to 5000 nm. The magnitude of this length L1 is related to the density between the first insulating layer 11 and the second insulating layer 12; the greater the difference in density between the first insulating layer 11 and the second insulating layer 12, the larger L1 is. For example, when the first insulating layer 11 is an atomic layer deposition layer, L1 is equal to or greater than 100 nm and less than or equal to 5000 nm. When the first insulating layer 11 is a high-density plasma chemical vapor deposition (HDPCVD) layer, L1 is equal to or greater than 50 nm and less than or equal to 100 nm.

[0134] In one implementation, see Figure 14 The insulating layer 10 also includes a third insulating layer 13 formed on the upper surface of the second insulating layer 12. Correspondingly, the stepped structure 14 also includes a third step formed by the third insulating layer 13. In the horizontal direction, the length L2 of the second step extending beyond the third step is less than the length L1 of the first step extending beyond the second step.

[0135] The thickness of the third insulating layer 13 is equal to or greater than the thickness of the second insulating layer 12, and the density of the third insulating layer 13 is equal to or less than the minimum density of the second insulating layer 12. The third insulating layer 13, the first insulating layer 11, and the second insulating layer 12 can be prepared using different processes. For example, the first insulating layer 11 can be an atomic layer deposition layer, the second insulating layer 12 can be a high-density plasma chemical vapor deposition (HDPCVD) layer, and the third insulating layer 13 can be a vapor deposition layer. Alternatively, the third insulating layer 13, the first insulating layer 11, and the second insulating layer 12 can be prepared using the same process, but the materials used to prepare the third insulating layer 13, the first insulating layer 11, and the second insulating layer 12 can be different.

[0136] According to one aspect of this application, a method for preparing the insulating layer in the above embodiments is provided. The preparation method includes the following steps:

[0137] S1. Prepare a first insulating layer 11 and a second insulating layer 12. The thickness of the second insulating layer 12 is greater than the thickness of the first insulating layer 11, and the thickness of the second insulating layer 12 is equal to or greater than 1 μm.

[0138] The density of the first insulating layer 11 is greater than the maximum density of the second insulating layer 12. The first insulating layer 11 and the second insulating layer 12 can be fabricated using different processes, and the materials used include one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. For example, the first insulating layer 11 can be fabricated by atomic layer deposition, and the second insulating layer 12 can be fabricated by high-density plasma chemical vapor deposition (HDPCVD), plasma chemical vapor deposition (PECVD), or vapor deposition. Alternatively, the first insulating layer 11 can be fabricated by HDPCVD, and the second insulating layer 12 can be fabricated by vapor deposition.

[0139] The first insulating layer 11 and the second insulating layer 12 can also be prepared using the same preparation process, but the materials used to prepare the first insulating layer 11 and the second insulating layer 12 are different. For example, the first insulating layer 11 and the second insulating layer 12 can both be prepared by atomic layer deposition, or the first insulating layer 11 and the second insulating layer 12 can both be prepared by high-density plasma chemical vapor deposition (HDPCVD).

[0140] Preferably, the first insulating layer 11 is made of alumina, and the first insulating layer 11 made of alumina has good waterproof properties. The second insulating layer 12 is a distributed Bragg reflector (DBR).

[0141] S2. Etch the insulating layer 10 and form a step structure 14 on the insulating layer 10. The step structure 14 includes a first step formed by the first insulating layer 11 and a second step formed by the second insulating layer 12. The first step extends beyond the second step in the horizontal direction, or it can be described as the first insulating layer 11 extending beyond the second insulating layer 12 in the horizontal direction.

[0142] The angle α1 between the side of the first step and the horizontal direction is smaller than the angle α2 between the side of the second step and the horizontal direction. Preferably, the angle α1 between the side of the first step and the horizontal direction decreases in the vertical direction, and this angle α1 is between 10° and 30° or 30° and 45°. The side of the second step is a sloping surface, and the angle α2 between the sloping surface and the horizontal direction is between 20° and 40°, 40° and 60° or 60° and 70°.

[0143] As an alternative implementation, the sides of the first and second steps are vertical surfaces.

[0144] Preferably, the first step extends horizontally beyond the second step by a length L1 equal to or greater than 50 nm and less than or equal to 5000 nm. The magnitude of this length L1 is related to the density between the first insulating layer 11 and the second insulating layer 12; the greater the difference in density between the first insulating layer 11 and the second insulating layer 12, the larger L1 is. For example, when the first insulating layer 11 is an atomic layer deposition layer, L1 is equal to or greater than 100 nm and less than or equal to 5000 nm. When the first insulating layer 11 is a high-density plasma chemical vapor deposition (HDPCVD) layer, L1 is equal to or greater than 50 nm and less than or equal to 100 nm.

[0145] In one embodiment, in step S1, a first insulating layer 10, a second insulating layer 12, and a third insulating layer 13 are prepared; in step S2, the insulating layer 10 is etched, and a step structure 14 is formed on the insulating layer 10, the step structure 14 further comprising a third step formed by the third insulating layer 13. In the horizontal direction, the length L2 by which the second step extends beyond the third step is less than the length L1 by which the first step extends beyond the second step.

[0146] As can be seen from the above technical solutions, the insulating layer 10 in this application is formed by at least a first insulating layer 11 and a second insulating layer 12, which can prevent cracks or complete breakage of the insulating layer and improve the reliability of the insulating layer. Furthermore, if the first insulating layer 11 extends horizontally beyond a predetermined length of the second insulating layer 12, this extended portion can act as a buffer when the second structural layer 30 is subsequently formed on the insulating layer 10, reducing the stress generated inside the second structural layer 30 and preventing cracks or complete breakage of the second structural layer 30 under stress, thus improving the reliability of the light-emitting diode chip. In addition, if the portion of the first insulating layer 11 extending horizontally beyond the second insulating layer 12 is located at the end of the insulating layer 10, this extended portion can also block moisture from entering, preventing aging and failure of the light-emitting diode chip.

[0147] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and substitutions can be made without departing from the technical principles of this application, and these improvements and substitutions should also be considered within the scope of protection of this application.

Claims

1. A light emitting diode chip having a semiconductor stack layer, a transparent conductive layer and an insulating layer, characterized by, The insulating layer is formed on the transparent conductive layer, and comprises at least a first insulating layer and a second insulating layer formed on the upper surface of the first insulating layer; the insulating layer is provided with a through hole penetrating the insulating layer, and the through hole is provided with a metal layer; The thickness of the second insulating layer is greater than the thickness of the first insulating layer, and the thickness of the second insulating layer is equal to or greater than 1 μm, and the thickness of the first insulating layer is 30-200 nm or 400-1000 nm; The side surface of the second insulating layer is projected on the first plane, and the side surface of the first insulating layer is projected on the first plane, and the angle α1 between the side surface of the first insulating layer and the horizontal direction is less than the angle α2 between the side surface of the second insulating layer and the horizontal direction, wherein the first plane is the plane on which the lower surface of the first insulating layer is located.

2. The light emitting diode chip of claim 1, wherein, The length L1 by which the lower surface of the first insulating layer exceeds the lower surface of the second insulating layer is equal to or greater than 50 nm and less than or equal to 5000 nm.

3. The light emitting diode chip of claim 1, wherein, When the first insulating layer is an atomic layer deposition layer, the length L1 by which the lower surface of the first insulating layer exceeds the lower surface of the second insulating layer is equal to or greater than 100 nm and less than or equal to 5000 nm.

4. The light emitting diode chip of claim 1, wherein, When the first insulating layer is a high-density plasma chemical vapor deposition layer, the length L1 by which the lower surface of the first insulating layer exceeds the lower surface of the second insulating layer is equal to or greater than 50 nm and less than or equal to 100 nm.

5. The light emitting diode chip of claim 1, wherein, The side surface of the second insulating layer is a slope surface, and the angle α2 between the slope surface and the horizontal direction is between 20-40°, 40-60° or 60-70°.

6. The light emitting diode chip of claim 1, wherein, The angle α1 between the side surface of the first insulating layer and the horizontal direction decreases in the vertical direction, and the angle α1 is between 10-30° or 30-45°.

7. The light emitting diode chip of claim 1, wherein, When the first insulating layer is an atomic layer deposition layer, the thickness of the first insulating layer is between 30-200 nm. The second insulating layer is a plasma chemical vapor deposition layer or an evaporation deposition layer.

8. The light emitting diode chip of claim 1, wherein, When the first insulating layer is a high-density plasma chemical vapor deposition layer, the thickness of the first insulating layer is between 400-1000 nm. The second insulating layer is an evaporation deposition layer.

9. The light emitting diode chip of claim 1, wherein, The first insulating layer and the second insulating layer are prepared by the same preparation process, and the preparation materials of the first insulating layer and the second insulating layer are different; the preparation materials of the first insulating layer and the second insulating layer comprise one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide or titanium oxide.

10. The light emitting diode chip of claim 1, wherein, The preparation material of the first insulating layer is aluminum oxide.

11. The light emitting diode chip of claim 1, wherein, The second insulating layer is a distributed Bragg reflector.

12. The light emitting diode chip of claim 1, wherein, The insulating layer further comprises a third insulating layer formed on the upper surface of the second insulating layer; in the horizontal direction, the length L2 by which the lower surface of the second insulating layer exceeds the lower surface of the third insulating layer is less than the length L1 by which the lower surface of the first insulating layer exceeds the second insulating layer.

13. The light emitting diode chip of claim 1, wherein, The surface of the insulating layer close to the first insulating layer is provided with a first structure layer, and the first structure layer is a transparent insulating layer, a transparent conductive layer or a metal layer.

14. The light emitting diode chip of claim 1, wherein, The semiconductor stack layer is a first structure layer, the insulating layer is formed on the semiconductor stack layer, and the second insulating layer is away from the semiconductor stack layer.

15. The light emitting diode chip of claim 1, wherein, Further comprising: a substrate as a first structure layer; The semiconductor stack layer forms a mesa structure on the substrate, and the insulating layer covers at least the sidewall of the semiconductor stack layer and the part of the area of the substrate other than the semiconductor stack layer; The second insulating layer is away from the semiconductor stack layer.

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