Satellite communication terminal, communication control method, transceiver and storage medium

Abstract

The present application provides a satellite communication terminal, a communication control method, a transceiver and a storage medium, which relate to the field of communication technology and solve the problem in the existing related technology that the local oscillator frequency switching, locking and switching power amplification time in the low-orbit satellite communication system is long and cannot meet the communication requirements. The satellite communication terminal of this solution includes a terminal controller and a transceiver, which implements the low-orbit monitoring function through a group of SerDes transceiver components and a group of LVDS transceiver components. The entire set of monitoring transceiver interfaces can achieve fast control and full-duplex communication through two pairs of differential lines. In addition, the transceiver completes the fast switching of the working passband through unique internal control and software algorithms, and quickly and accurately configures the phase-locked loop to respond to external frequency switching requirements, so that the total time from the terminal controller sending the instruction to the transceiver local oscillator switching and completing the locking is short, thereby effectively meeting the communication requirements of low-orbit satellite communication.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a satellite communication terminal, a communication control method, a transceiver, and a storage medium. Background Art

[0002] With the development of satellite communications, low-orbit satellite communication networks are becoming more and more widely used. Some low-orbit satellite communication systems have high requirements for the monitoring response speed of terminal transceivers. The system is characterized by dividing the Ku-band transmit and receive passbands into several segments, and each segment corresponds to a different transmit and receive local oscillator frequency. When switching to satellites in different service areas, it is often necessary to switch the frequency band and local oscillator frequency, and the time from the start of switching to the completion of locking of the local oscillator frequency must be less than 400 microseconds.

[0003] However, existing technologies use RS232, RS422, RS485, or Ethernet for monitoring communications between the transceiver in the satellite communication terminal and the external control unit. These methods do not require high response times for monitoring communications. Existing monitoring communication methods using serial and Ethernet ports often meet communication requirements with transmission and response times exceeding milliseconds. However, this method struggles to meet the communication requirements of low-orbit satellite communication systems. Specifically, the time required to switch the local oscillator frequency from initialization to lock and to turn the power amplifier on and off is insufficient. This results in signal disconnection and short online time when switching between satellites in different service areas, preventing smooth and efficient high-capacity communication. Summary of the Invention

[0004] The present application provides a satellite communication terminal, a communication control method, a transceiver and a storage medium, which solves the problem in the existing related technologies that the local oscillator frequency switching and locking and the switching power amplifier in low-orbit satellite communication systems are long and cannot meet the communication requirements. The present solution can quickly switch and lock the local oscillator frequency, and at the same time control the switching transmitter power amplifier, with a short response time and able to meet the communication requirements, which helps to ensure the effectiveness and smoothness of large-capacity satellite communications.

[0005] In a first aspect, the present application provides a satellite communication terminal, which includes a terminal controller and a transceiver, specifically:

[0006] The terminal controller includes a first control unit, a SerDes transmitting component and an LVDS receiving component, the SerDes transmitting component is connected to the GPIO interface on the first control unit, and the SerDes transmitting component is also connected to the first UART interface on the first control unit, and the LVDS receiving component is connected to the second UART interface on the first control unit;

[0007] The transceiver includes a second control unit, a SerDes receiving component, an LVDS transmitting component, a phase-locked loop module and a silent control module; the SerDes receiving component is connected to the GPIO interface on the second control unit, and the SerDes receiving component is also connected to the third UART interface on the second control unit, the SerDes receiving component is connected to the SerDes transmitting component through a differential twisted pair, and the SerDes receiving component is used to receive the communication control signal sent by the SerDes transmitting component; the LVDS transmitting component is connected to the LVDS receiving component through a differential twisted pair, and the LVDS transmitting component is connected to the first UART interface of the second control unit. Four UART interfaces are connected, and the LVDS transmitting component is used to send a communication control signal to the LVDS receiving component; the phase-locked loop module is connected to the second control unit, and the phase-locked loop module is used to switch the local oscillator frequency of the transceiver; the first input control end of the silence control module is connected to the first control port of the second control unit, and the second input control end of the silence control module is connected to the second control port of the SerDes receiving component. The output end of the silence control module is connected to the control gate end of the power amplifier switch module of the transceiver, and the silence control module is used to control the power amplifier switch module to turn off when the first input control end or the second input control end receives a silence control signal.

[0008] In a second aspect, the present application further provides a communication control method, which is applied to the transceiver in the satellite communication terminal provided in the above aspect, the method comprising:

[0009] When receiving the synchronization information cyclically sent by the terminal controller, it establishes synchronization with the terminal controller and feeds back the status information corresponding to the synchronization lock state to the terminal controller after determining that it is in the synchronization lock state, so as to complete the transmission chain establishment;

[0010] Initialize the registers corresponding to the phase-locked loop module based on the preset configuration information;

[0011] Selecting a working passband from among a plurality of preset transmit passbands and receive passbands according to working passband information received through the SerDes receiving component, and adjusting the local oscillator frequency to a frequency corresponding to the working passband;

[0012] When receiving change information corresponding to a change in the working passband, the change information is analyzed to switch the local oscillator frequency according to the analysis result;

[0013] After completing locking of the local oscillator frequency after switching, a change completion message is sent to the terminal controller via the LVDS sending component.

[0014] In a third aspect, the present application further provides a transceiver, comprising:

[0015] one or more processors;

[0016] a storage device for storing one or more programs,

[0017] When one or more programs are executed by one or more processors, the one or more processors implement the communication control method of the present application.

[0018] In a fourth aspect, the present application also provides a storage medium storing computer-executable instructions, which are used to execute the communication control method of the present application when executed by a processor.

[0019] The satellite communication terminal of the present application solution includes a terminal controller and a transceiver, which implements the low-orbit monitoring function through a group of SerDes transceiver components and a group of LVDS transceiver components. The entire set of monitoring transceiver interfaces can achieve fast control and full-duplex communication through two pairs of differential lines, i.e., four communication lines. Moreover, the transceiver quickly and accurately configures the phase-locked loop to respond to external frequency switching requirements by quickly switching the working passband, so that the total time from the terminal controller sending the instruction to the transceiver local oscillator switching and completing the lock is short, thereby effectively meeting the communication requirements of low-orbit satellite communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of the structure of a satellite communication terminal provided in one embodiment of the present application;

[0021] Figure 2 A schematic diagram of the circuit structure of a silent control module provided in one embodiment of the present application;

[0022] Figure 3 A schematic diagram of the steps of a communication control method provided in one embodiment of the present application;

[0023] Figure 4 A schematic diagram of the steps for changing the working passband provided in one embodiment of the present application;

[0024] Figure 5 A waveform diagram showing the total time taken from the first control unit of the terminal controller issuing a switching interrupt instruction to the frequency synthesis of the transceiver completing the frequency switching to lock according to an embodiment of the present application;

[0025] Figure 6 A schematic diagram of the structure of a transceiver provided in one embodiment of the present application.

[0026] Reference numerals:

[0027] The first control unit 110 , the SerDes transmitting component 120 , the LVDS receiving component 130 , the second control unit 210 , the SerDes receiving component 220 , the LVDS transmitting component 230 , the phase-locked loop module 240 , and the silence control module 250 . DETAILED DESCRIPTION

[0028] The embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and examples. It will be understood that the specific embodiments described herein are merely used to explain the embodiments of the present application, rather than to limit the embodiments of the present application. It should also be noted that, for ease of description, only portions related to the embodiments of the present application, rather than all structures, are shown in the accompanying drawings. After reading this specification, those skilled in the art should be able to understand that, as long as the technical features do not contradict each other, any combination of the technical features may constitute an optional embodiment.

[0029] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the description of this application, "multiple" means two or more, and "several" means one or more.

[0030] With the development of satellite communications, low-orbit satellite communication networks are becoming increasingly widespread. However, these networks place high demands on transceiver monitoring, such as requiring the time from the initial local oscillator frequency switch to lock to be less than 400 microseconds. Serial communication methods used in existing technologies do not have high requirements for monitoring response speed, making the use of serial or Ethernet ports ineffective in meeting these time requirements.

[0031] For example, while switching the local oscillator frequency, the control unit may also control the transceiver to turn on and off the power amplifier, which requires sending corresponding instructions. If traditional serial communication methods (such as RS232 and RS485) are used, the time required to send and receive a single 10-bit, 7-byte instruction between the control unit and the transceiver reaches the millisecond level. Therefore, the time required to switch the local oscillator frequency from the beginning to the locked state in a low-orbit satellite communication system using serial communication methods is even longer, failing to meet the 400 microsecond requirement. Therefore, existing related art solutions are prone to signal disconnection and short online time when switching between different service area satellites, resulting in the inability to smoothly carry out high-capacity and efficient communication.

[0032] In this regard, the present application provides a satellite communication terminal, which can be used to interact with satellites in a low-orbit satellite communication system. The satellite communication terminal switches to satellites in different service areas by switching to corresponding local oscillator frequencies. Figure 1 This is a structural diagram of a satellite communication terminal provided in one embodiment of the present application. The satellite communication terminal includes a terminal controller and a transceiver, so as to realize switching and locking of the local oscillator frequency through communication between the terminal controller and the transceiver.

[0033] like Figure 1 As shown, the terminal controller includes a first control unit 110, a SerDes [short for SERializer (serializer) / DESerializer (deserializer)] transmitting component 120 and an LVDS (Low-Voltage Differential Signaling, low voltage differential signal) receiving component 130, and the transceiver includes a second control unit 210, a SerDes receiving component 220, an LVDS transmitting component 230, a phase-locked loop module 240 and a silent control module 250.

[0034] Specifically, the SerDes sending component 120 is connected to the GPIO interface on the first control unit 110, and the SerDes sending component 120 is also connected to the first UART interface on the first control unit 110, wherein the first UART interface is a sending interface, the SerDes receiving component 220 is connected to the SerDes sending component 120 via a differential twisted pair, the SerDes receiving component 220 is connected to the GPIO interface on the second control unit 210, and the SerDes receiving component 220 is also connected to the third UART interface on the second control unit 210, wherein the third UART interface is a receiving interface, and the SerDes receiving component 220 is used to receive the communication control signal sent by the SerDes sending component 120.

[0035] The LVDS receiving component 130 is connected to the second UART interface on the first control unit 110, where the second UART interface is a receiving interface. The LVDS transmitting component 230 is connected to the fourth UART interface of the second control unit 210, where the fourth UART interface is a transmitting interface. The LVDS transmitting component 230 and the LVDS receiving component 130 are connected via a differential twisted pair cable. The LVDS transmitting component 230 is used to send communication control signals to the LVDS receiving component 130. During operation, the second control unit 210 of the transceiver can transmit the locking status back to the terminal controller in real time via the LVDS transmitting component 230, so that the terminal controller can indicate the transmission chain status to the user.

[0036] The phase-locked loop module 240 is connected to the second control unit 210 for switching the local oscillator frequency of the transceiver, while the mute control module 250 is used to control the power amplifier switch module to shut down when a mute control signal is received at the first or second input control terminal. Specifically, the first input control terminal of the mute control module 250 is connected to the first control port of the second control unit 210, the second input control terminal of the mute control module 250 is connected to the second control port of the SerDes receiving component 220, and the output terminal of the mute control module 250 is connected to the control gate terminal of the power amplifier switch module of the transceiver.

[0037] It is understandable that the operating frequency information allocated by the terminal controller system is given to the parallel port of the SerDes transmitting component 120 through the GPIO of the internal first control unit 110. Through the transmission mode of the SerDes transceiver component (i.e., including the SerDes transmitting component 120 and the SerDes receiving component 220) between the terminal controller and the transceiver, the SerDes receiving component 220 of the transceiver receives the corresponding information and transmits it to the second control unit 210 of the transceiver to execute interrupt triggering, such as performing functions such as transmission and reception, and implementing corresponding local oscillator frequency switching for the receiving or transmitting phase-locked loop. The second control unit 210 configures the phase-locked loop module 240 by accurately configuring the integer and fractional registers of the phase-locked loop to complete the switching and locking of the local oscillator frequency. Accordingly, the transceiver can send information to the LVDS receiving component 130 of the terminal controller through the LVDS transmitting component 230 thereon to feedback the result of the response control terminal query or control instruction.

[0038] Therefore, the terminal controller and transceiver of this solution implement the low-orbit monitoring function through a set of SerDes transceiver components and a set of LVDS transceiver components. The entire set of monitoring transceiver interfaces can achieve fast control and full-duplex communication through two pairs of differential lines, that is, four communication lines. In addition, the total time from sending the command to the transceiver local oscillator switching and completing the lock is short, which can effectively meet the communication requirements of low-orbit satellite communications.

[0039] Figure 2This is a circuit structure diagram of a silent control module provided in an embodiment of the present application. In one embodiment, the silent control module includes a first current-limiting resistor R1, a second current-limiting resistor R2, an AND gate logic chip U1, a diode D1, a first voltage-dividing resistor R3, a second voltage-dividing resistor R4, and a third voltage-dividing resistor R5. The first AND gate input terminal of the AND gate logic chip U1 is connected to one end of the first current-limiting resistor R1, the second AND gate input terminal of the AND gate logic chip U1 is connected to one end of the second current-limiting resistor R2, the AND gate output terminal of the AND gate logic chip U1 is connected to the cathode terminal of the diode D1, and the anode terminal of the diode D1 is grounded. The first end of the first voltage-dividing resistor R3 is connected to the AND gate output terminal of the AND gate logic chip U1, the second end of the first voltage-dividing resistor R3 is connected to the control gate terminal of the power amplifier switch module, the first end of the second voltage-dividing resistor R4 is connected to the second end of the first voltage-dividing resistor R3, the second end of the second voltage-dividing resistor R4 is connected to a negative voltage, the first end of the third voltage-dividing resistor R5 is connected to the second end of the first voltage-dividing resistor R3, and the second end of the third voltage-dividing resistor R5 is grounded.

[0040] It can be understood that, as can be seen from the circuit structure of the silence control module, the AND gate logic chip U1 uses a two-input AND gate. Accordingly, the first and second AND gate input terminals of the AND gate logic chip U1 are each connected to a current-limiting resistor. Corresponding high and low voltage levels are connected to the first and second current-limiting resistors R1 and R2 to control the output of the AND gate logic chip U1. It should be noted that when selecting a corresponding AND gate logic chip, any logic gate on it can be used.

[0041] The first current-limiting resistor R1 is connected to the SerDes receiving component to receive the external input transmission silence command, thereby receiving the corresponding level signal to the first AND gate input terminal of the AND gate logic chip U1 through the SerDes receiving component; the second current-limiting resistor R2 is connected to the second control unit of the transceiver to receive the internal input transmission silence command, thereby receiving the corresponding level signal to the second AND gate input terminal of the AND gate logic chip U1 through the second control unit. Therefore, when a low-level silence control signal is received on any path, the AND gate logic chip U1 will output a low-level signal, so that the control gate terminal of the power amplifier switch module is connected to a low level, thereby turning off the power amplifier switch module. The calculation formula for the control gate terminal voltage is as follows:

[0042]

[0043] Among them, v g is the control gate terminal voltage of the power amplifier switch module, and v0 is the AND gate output voltage.

[0044] It can be seen that the use of the first voltage-dividing resistor R3, the second voltage-dividing resistor R4 and the third voltage-dividing resistor R5 can minimize the gate voltage at the output of the AND gate and be lower than the normal operating threshold point of the power amplifier switch module. By controlling the voltage at the control gate end of the power amplifier module, the satellite communication terminal can turn off the power amplifier switch module more quickly.

[0045] Figure 3 This is a schematic diagram of the steps of a communication control method provided in one embodiment of the present application. This method can be applied to the transceiver in the above-mentioned satellite communication terminal. In the satellite communication terminal, the terminal controller and the transceiver communicate through the SerDes transceiver component and the LVDS transceiver component, thereby switching and locking the local oscillator frequency. The specific steps are as follows:

[0046] Step S310: upon receiving the synchronization information cyclically sent by the terminal controller, establish synchronization with the terminal controller and after determining that the terminal is in the synchronization lock state, feed back the state information corresponding to the synchronization lock state to the terminal controller to complete the transmission chain establishment.

[0047] It is understandable that after the satellite communication terminal is powered on, the terminal controller and the transceiver are both powered on. Correspondingly, the terminal controller cyclically sends synchronization information to the transceiver, that is, the SerDes transmitting component on the terminal controller cyclically sends the synchronization information to the SerDes receiving component on the transceiver multiple times. After receiving the synchronization information, the transceiver establishes synchronization with the terminal controller. After determining that it is in a synchronous lock state, the transceiver feeds back status information to the terminal controller. The status information is used to indicate that the transceiver is in a synchronous lock state, that is, the LVDS transmitting component on it sends the status information to the LVDS receiving component of the terminal controller, thereby completing the establishment of the transmission chain. It is conceivable that in some embodiments, a corresponding delay time can also be set to wait for the confirmation of the synchronous lock state.

[0048] Step S320: Initialize and configure registers corresponding to the phase-locked loop module based on the preset configuration information.

[0049] The transceiver stores corresponding preset configuration information, which is used to configure the registers corresponding to the phase-locked loop module to complete initialization. Accordingly, the second control unit of the transceiver completes the initialization configuration of the startup after power-on, and then extracts the initial configuration information of the phase-locked loop register of the default frequency point from the internal memory, that is, the above-mentioned preset configuration information, such as disabling the general interrupt, selecting the external crystal oscillator as the clock source, configuring the external crystal oscillator frequency, disabling the phase-locked loop, setting the SYNR and REFDV registers according to the preset clock frequency, turning on the phase-locked loop, and other configuration steps, thereby realizing the initialization configuration of the registers corresponding to the phase-locked loop module to shorten the time for the subsequent local oscillator frequency to switch to the complete configuration register. It can be understood that by initializing the configuration of the phase-locked loop module, the transceiver can quickly switch frequencies by configuring the corresponding frequency division number in the future, which helps to reduce the total time from switching to locking.

[0050] Step S330 : selecting a working passband from among a plurality of preset transmission passbands and reception passbands according to the working passband information received by the SerDes receiving component, so as to adjust the local oscillator frequency corresponding to the working passband.

[0051] After completing the initial configuration of the phase-locked loop module, the transceiver waits for the system to assign the corresponding operating passband information. Upon receiving the operating passband information from the system, the terminal controller transmits it via its SerDes transmitter to the transceiver's SerDes receiver, enabling the transceiver to switch to the corresponding operating passband, such as the transmit or receive passband. This allows the transceiver to adjust its local oscillator frequency to the corresponding operating passband, allowing it to transmit or receive signals.

[0052] It is conceivable that the transceiver selects a corresponding working passband, that is, a corresponding working frequency, according to the working passband information sent, and enters a corresponding mode, such as a sending mode or a receiving mode, thereby completing the signal sending and receiving functions.

[0053] Step S340: When the change information corresponding to the change of the working passband is received, the change information is analyzed to switch the local oscillator frequency according to the analysis result.

[0054] It is understood that the change information is also sent by the terminal controller via its SerDes transmitting component to the transceiver's SerDes receiving component. Furthermore, upon receiving the change information, the transceiver parses it to determine the parsing result. For example, if the parsing determines that the change information carries changed passband information, the transceiver switches the local oscillator frequency after determining the parsing result. It is conceivable that when the changed passband information corresponds to the transmit passband, the transceiver will accordingly turn on the power amplifier switch module after the phase-locked loop is locked.

[0055] Step S350: After completing locking of the switched local oscillator frequency, a change completion message is sent to the terminal controller via the LVDS sending component.

[0056] After switching the local oscillator frequency, the transceiver locks it. The transceiver then transmits a corresponding change completion message to the LVDS receiving component of the terminal controller via its LVDS transmitting component, thereby providing feedback on the system-initiated change and enabling the terminal controller to confirm that the local oscillator frequency change has been completed. It is conceivable that the change completion message may carry a corresponding feedback value, such as feedback from internal memory or sensors. The transceiver transmits the change completion message to the LVDS transmitting component via the UART interface on the second control unit, and then transmits the message to the terminal controller via differential signaling between the LVDS transmitting component and the LVDS receiving component.

[0057] It can be seen that the transceiver quickly and accurately configures the phase-locked loop to respond to external frequency switching requirements by quickly switching the working passband, so that the total time from sending the instruction to the transceiver local oscillator switching and completing the lock is short, thereby effectively meeting the communication requirements of low-orbit satellite communications.

[0058] In one embodiment, the transmit passband and the receive passband correspond to different frequency ranges. Accordingly, the transceiver uses different address parameters to correspond to the transmit passband and the receive passband. That is, each transmit passband and each receive passband has a unique corresponding address parameter. Therefore, after receiving the operating passband information, the transceiver can determine the corresponding address parameter by parsing the operating passband information, and then select a target passband from the transmit passband and the receive passband according to the obtained address parameter. It is conceivable that the address parameter of the target passband is consistent with the obtained address parameter, thereby determining that the passband to be switched is the transmit passband or the receive passband, and using this as the operating passband for signal transmission or reception.

[0059] It should be noted that, in some embodiments, the address parameters corresponding to the transmitting passband are represented by two-bit binary, and the address parameters corresponding to the receiving passband are represented by three-bit binary. It can be understood that multiple interfaces are reserved in the GPIO interface on the second control unit of the transceiver to output the address parameters corresponding to the transmitting passband and the receiving passband, such as setting two GPIO interfaces corresponding to the transmitting passband and setting three GPIO interfaces corresponding to the receiving passband, respectively corresponding to different address bits in the address parameters, so that the address parameters corresponding to different passbands are different, so as to better perform passband switching.

[0060] Figure 4This is a schematic diagram of the steps for changing the operating passband provided in one embodiment of the present application. After the transceiver receives the change information corresponding to the change of the operating passband, the transceiver needs to parse the information to determine the corresponding address parameters, thereby switching the local oscillator frequency. The specific steps are as follows:

[0061] Step S410: When it is determined after analysis that the change information carries an interrupt enable signal corresponding to a low level, the running task is interrupted and the address parameter is determined according to the change information.

[0062] Step S420: Based on the address parameter, a target passband is selected from the transmitting passband or the receiving passband, and the target passband is used as the passband to be switched.

[0063] Step S430: Perform a write operation on the register corresponding to the phase-locked loop module according to the frequency division integer and the frequency division decimal corresponding to the passband to be switched to switch the local oscillator frequency.

[0064] It is understood that by parsing the change information, the transceiver can determine the signal content contained therein. If it is determined that the change information carries a corresponding low-level interrupt enable signal, the transceiver interrupts its running task and then determines the corresponding address parameters based on the passband to be switched indicated in the change information. It is conceivable that because the transmit passband and the receive passband each correspond to different address parameters, once the address parameters are determined, the selected passband can also be determined, and this passband is then used as the target passband.

[0065] The target passband serves as the passband to be switched, and the transceiver needs to configure the corresponding registers of the phase-locked loop module according to the corresponding frequency division integer and frequency division decimal. For example, an address table is provided in the transceiver, which records the address parameters corresponding to each transmit passband and each receive passband, and also records the frequency division integer and frequency division decimal corresponding to each passband. Therefore, the corresponding frequency division integer and frequency division decimal can be determined based on the selected passband. After determining the frequency division integer and frequency division decimal, the transceiver completes the writing of the register according to the frequency division integer and frequency division decimal. Accordingly, the phase-locked loop module is locked, thereby achieving the switching of the local oscillator frequency and completing the locking.

[0066] Therefore, the address parameters are used to associate the corresponding passbands so that the transceiver can quickly locate the passband to be switched when switching the local oscillator frequency, and then switch with the corresponding frequency division integer and frequency division decimal of the passband, thereby realizing the switching of the local oscillator frequency more quickly, which helps to reduce the time from switching the local oscillator frequency to completing frequency locking.

[0067] It should be noted that, in one embodiment, when the passband to be switched is any of the transmit passbands, after locking the phase-locked loop module, the transceiver uses the silence control module to turn on the power amplifier switch module. For example, the second control unit of the transceiver sends a signal instructing the first input control terminal of the silence control module to turn on the power amplifier switch module. By controlling the voltage at the control gate terminal of the power amplifier switch module, the transceiver can more quickly turn on the power amplifier switch module, thereby facilitating faster local oscillator frequency switching.

[0068] In one embodiment, if, after analysis, it is determined that the change information carries a corresponding low-level transmit muting signal, the transceiver sends a muting control signal to the muting control module, such as by sending the muting control signal to the second input control terminal of the muting control module via a SerDes receiving component, so that the second input control terminal of the muting control module receives a low-level signal. The muting control module then shuts down the power amplifier switch module, i.e., lowers the voltage at the control gate terminal of the power amplifier switch module to below the normal operating threshold of the power amplifier switch module, thereby causing the power amplifier switch module to enter an off state. Therefore, by lowering the voltage at the control gate terminal of the power amplifier switch module to below the normal operating threshold, the transceiver can more quickly shut down the power amplifier switch module, thereby facilitating faster local oscillator frequency switching.

[0069] In one embodiment, the operating frequency information assigned by the terminal controller system is given to the parallel port of the SerDes transmitting component through the GPIO of the internal first control unit. After the SerDes transmitting and receiving component (i.e., including the SerDes transmitting component and the SerDes receiving component) between the terminal controller and the transceiver receives the corresponding information through the transmission method, the SerDes receiving component of the transceiver transmits it to the second control unit of the transceiver to execute an interrupt trigger, such as performing functions such as transmission and reception, and implementing corresponding local oscillator frequency switching for the receiving or transmitting phase-locked loop. The second control unit configures the phase-locked loop module by accurately configuring the integer and fractional registers of the phase-locked loop to complete the switching and locking of the local oscillator frequency. Accordingly, the transceiver can send information to the LVDS receiving component of the terminal controller through the LVDS transmitting component thereon to feedback the results of the response control terminal query or control instruction.

[0070] Furthermore, during the local oscillator frequency switching process, the mute control module can be used to quickly turn the power amplifier switch on or off. In the mute control module, the AND logic chip U1 uses a two-input AND gate. Accordingly, the first and second AND gate inputs of the AND logic chip U1 are each connected to a current-limiting resistor. Corresponding high and low voltage levels are applied to the first and second current-limiting resistors R1 and R2 to control the output of the AND logic chip U1. The first current-limiting resistor R1 is connected to the SerDes receiver component to receive an externally inputted transmit mute command, which in turn transmits a corresponding voltage level signal to the first AND input of the AND logic chip U1 through the SerDes receiver component. The second current-limiting resistor R2 is connected to the second control unit of the transceiver to receive an internally inputted transmit mute command, which in turn transmits a corresponding voltage level signal to the second AND input of the AND logic chip U1 through the second control unit. Therefore, when a low-level mute control signal is applied to either path, the AND logic chip U1 outputs a low-level signal, causing the control gate of the power amplifier switch module to be connected to a low voltage, thereby shutting down the power amplifier switch module.

[0071] After the satellite communication terminal is powered on, the terminal controller and transceiver are also powered on. The terminal controller sends the synchronization information to the SerDes receiving component on the transceiver in a loop multiple times through the SerDes transmitting component on the terminal controller to complete the transmission chain establishment with the transceiver. After powering on, the transceiver can complete the initialization configuration of the registers corresponding to the phase-locked loop module through the preset configuration information. Accordingly, the transceiver selects the corresponding working passband according to the working passband information sent, that is, selects the corresponding operating frequency, and enters the corresponding mode, such as the transmitting mode or the receiving mode, to complete the signal transmission and reception function. For example, when receiving the changed passband information corresponding to the transmission passband, the transceiver will turn on the power amplifier switch module after the phase-locked loop is locked.

[0072] Figure 5 This is a waveform diagram of the total time taken from the first control unit of the terminal controller issuing a switching interrupt instruction to the transceiver frequency synthesis completing the frequency switching to lock, provided in one embodiment of the present application. In order to more clearly reflect the corresponding total time, the figure also partially enlarges the data display part, as shown in the circled area in the figure. Since the second control unit of the transceiver has configured the transceiver frequency synthesis of the transceiver according to the preset configuration information, after the transceiver receives the instruction, the second control unit only needs to configure the integer and fractional registers of the phase-locked loop module to achieve the switching and locking of the local oscillator frequency. The corresponding time is as follows Figure 5 As shown in the middle circle, the total time is 250.625 μs, which is lower than the time requirement of less than 400 μs for the low-orbit satellite communication system for the time from the start of switching the local oscillator frequency to the completion of locking.

[0073] Figure 6This is a structural diagram of a transceiver provided in one embodiment of the present application. The device is used to execute the communication control method provided in the above embodiment and has functional modules and beneficial effects corresponding to the execution method. As shown in the figure, the transceiver includes a processor 501, a memory 502, an input device 503 and an output device 504. The number of processors 501 can be one or more, and the figure takes one processor 501 as an example; the processor 501, the memory 502, the input device 503 and the output device 504 can be connected via a bus or other means, and the figure takes the connection via a bus as an example. The memory 502, as a computer-readable storage medium, can be used to store software programs, computer executable programs and modules, such as program instructions / modules corresponding to the communication control method in the embodiment of the present application. The processor 501 executes the corresponding various functional applications and data processing by running the software programs, instructions and modules stored in the memory 502, that is, realizes the above-mentioned communication control method.

[0074] The memory 502 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system and at least one application required for a function; the data storage area may store data recorded or created during use, etc. In addition, the memory 502 may include a high-speed random access memory and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 502 may further include a memory remotely located relative to the processor 501, and these remotely located memories may be connected to the device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0075] The input device 503 can be used to input corresponding digital or character information to the processor 501, and generate key signal input related to the user settings and function control of the device; the output device 504 can be used to send or display key signal output related to the user settings and function control of the device.

[0076] An embodiment of the present application also provides a storage medium storing computer-executable instructions, which, when executed by a processor, are used to perform relevant operations in the communication control method provided in any embodiment of the present application.

[0077] Computer-readable storage media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

[0078] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0079] Note that the above are only preferred embodiments of the present application and the technical principles employed. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present application. The scope of the present application is determined by the scope of the appended claims.

Claims

1. A satellite communication terminal, characterized in that: include: A terminal controller, the terminal controller comprising a first control unit, a SerDes transmitting component and an LVDS receiving component, the SerDes transmitting component being connected to a GPIO interface on the first control unit, and the SerDes transmitting component being further connected to a first UART interface on the first control unit, and the LVDS receiving component being connected to a second UART interface on the first control unit; A transceiver comprising a second control unit, a SerDes receiving component, an LVDS transmitting component, a phase-locked loop module, and a silence control module; The SerDes receiving component is connected to the GPIO interface on the second control unit, and the SerDes receiving component is also connected to the third UART interface on the second control unit. The SerDes receiving component is connected to the SerDes sending component through a differential twisted pair, and the SerDes receiving component is used to receive the communication control signal sent by the SerDes sending component; The LVDS transmitting component is connected to the LVDS receiving component via a differential twisted pair, the LVDS transmitting component is connected to the fourth UART interface of the second control unit, and the LVDS transmitting component is used to send a communication control signal to the LVDS receiving component; The phase-locked loop module is connected to the second control unit, and the phase-locked loop module is used to switch the local oscillator frequency of the transceiver; The first input control end of the silence control module is connected to the first control port of the second control unit, the second input control end of the silence control module is connected to the second control port of the SerDes receiving component, and the output end of the silence control module is connected to the control gate end of the power amplifier switch module of the transceiver. The silence control module is used to control the power amplifier switch module to turn off when the first input control end or the second input control end receives a silence control signal.

2. The satellite communication terminal according to claim 1, wherein The silent control module includes a first current limiting resistor, a second current limiting resistor, an AND gate logic chip, a diode, a first voltage dividing resistor, a second voltage dividing resistor and a third voltage dividing resistor; A first AND gate input terminal of the AND gate logic chip is connected to one end of the first current limiting resistor, a second AND gate input terminal of the AND gate logic chip is connected to one end of the second current limiting resistor, an AND gate output terminal of the AND gate logic chip is connected to the cathode end of the diode, and an anode end of the diode is grounded; The first end of the first voltage-dividing resistor is connected to the AND gate output end of the AND gate logic chip, the second end of the first voltage-dividing resistor is connected to the control gate end of the power amplifier switch module, the first end of the second voltage-dividing resistor is connected to the second end of the first voltage-dividing resistor, the second end of the second voltage-dividing resistor is connected to a negative voltage, the first end of the third voltage-dividing resistor is connected to the second end of the first voltage-dividing resistor, and the second end of the third voltage-dividing resistor is grounded.

3. A communication control method, characterized in that: The transceiver used in the satellite communication terminal according to any one of claims 1 to 2, the method comprising: Upon receiving synchronization information cyclically sent by the terminal controller, establishing synchronization with the terminal controller and feeding back state information corresponding to the synchronization lock state to the terminal controller after determining that the state is in the synchronization lock state, so as to complete the transmission chain establishment; Initialize the registers corresponding to the phase-locked loop module based on the preset configuration information; Selecting a working passband from among a plurality of preset transmit passbands and receive passbands according to working passband information received by the SerDes receiving component, and adjusting the local oscillator frequency to a local oscillator frequency corresponding to the working passband; When receiving change information corresponding to a change in the working passband, analyzing the change information to switch the local oscillator frequency according to the analysis result; After completing locking of the local oscillator frequency after switching, a change completion message is sent to the terminal controller via the LVDS sending component.

4. The communication control method according to claim 3, wherein: The selecting a working passband from a plurality of preset transmission passbands and reception passbands according to the working passband information received by the SerDes receiving component to adjust to a local oscillator frequency corresponding to the working passband includes: Determining, according to the working passband information received by the SerDes receiving component, an address parameter corresponding to the transmitting passband or the receiving passband, wherein the transmitting passband and the receiving passband are respectively set with different address parameters; Based on the address parameters, a target passband is selected from the transmission passband and the reception passband, and the target passband is used as a working passband.

5. The communication control method according to claim 4, characterized in that: The address parameter corresponding to the transmitting passband and the address parameter corresponding to the receiving passband are both expressed in binary. The address parameter corresponding to the transmitting passband is associated with two binary bits, and the address parameter corresponding to the receiving passband is associated with three binary bits.

6. The communication control method according to claim 3, wherein: When receiving the change information corresponding to the change of the working passband, parsing the change information to switch the local oscillator frequency according to the parsing result includes: If it is determined after parsing that the change information carries an interrupt enable signal corresponding to a low level, interrupting the running task and determining the address parameter according to the change information; Based on the address parameter, selecting a target passband from the transmit passband or the receive passband, and using the target passband as the passband to be switched; According to the frequency division integer and the frequency division decimal corresponding to the passband to be switched, a write operation is performed on the register corresponding to the phase-locked loop module to switch the local oscillator frequency.

7. The communication control method according to claim 6, wherein: After performing a write operation on a register corresponding to a phase-locked loop according to the frequency division integer and the frequency division decimal corresponding to the passband to be switched to switch the local oscillator frequency, the method further includes: In a case where the passband to be switched is any one of the transmission passbands, the power amplifier switch module is turned on by the silent control module after the phase-locked loop module is locked.

8. The communication control method according to claim 3 or 6, characterized in that: When receiving the change information corresponding to the change of the working passband, parsing the change information to switch the local oscillator frequency according to the parsing result includes: When it is determined after analysis that the change information carries a corresponding low-level transmission silence signal, a silence control signal is sent to the silence control module so as to turn off the power amplifier switch module through the silence control module.

9. A transceiver, characterized in that: include: one or more processors; A storage device for storing one or more programs, when the one or more programs are executed by the one or more processors, so that the one or more processors implement the communication control method according to any one of claims 3 to 8.

10. A storage medium storing computer executable instructions, characterized in that: When the computer-executable instructions are executed by a processor, the computer-executable instructions are used to perform the communication control method according to any one of claims 3 to 8.

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