A SONOS reading circuit

Abstract

The present invention provides a SONOS read circuit, comprising PMOS transistors P0-P3, NMOS transistors N0 and N1, inverters INV0 and INV1, SONOS cell tubes SN0 and SN1, FNPASS selection tubes FN0 and FN1, and a comparator; the sources of P2 and P3 are connected to a power supply voltage terminal; the gate of P2, the drain of P3, the gate of N0, the drain of N1 and the drain of P1 are connected, and the node connected thereto is denoted as VF; the gate of P3, the drain of P2, the drain of N0, the gate of N1 and the drain of P0 are connected, and the node connected thereto is denoted as VR; the source of P0 is connected to the input terminal of INV0 and the drain of SN0; the output terminal of INV0 is connected to the gate of P0; the source of P1 is connected to the input terminal of INV1 and the drain of SN1; the output terminal of INV1 is connected to the gate of P1; The source of the cell tube is connected to the drain of the FNPASS selection tube, and the source of the FNPASS selection tube is connected to the gate wl. The positive input of the comparator is connected to VR, the negative input is connected to VF, and its output serves as the output terminal SOUT of the circuit. The array area of ​​the circuit composition of the present invention is small, which greatly reduces product cost.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a SONOS reading circuit. Background Art

[0002] Sense amplifiers are used in NVM Memory (non-volatile memory) read circuits. General sense amplifier circuits are used to latch data.

[0003] Existing traditional SONOS cells and their read circuits are as follows Figure 1 As shown, it consists of four PMOS transistors P0-P3, six NMOS transistors N0-N5, two SONOS cell tubes SN0 and SN1, two FNPASS selection tubes FN0 and FN1, and an RS trigger RS. Figure 1 The LATCH in the figure is a latch circuit. Figure 1 The memory cell (array cell) is composed of a SONOS cell tube SN0 and a FNPASS selection tube FN1.

[0004] The sources of PMOS transistors P0-P3 are connected to the power supply voltage terminal vpwr. The gate and drain of PMOS transistor P0 are connected to the gate of PMOS transistor P1 and the drain of NMOS transistor N0, with the connection node denoted as VE. The drain of SONOS cell transistor SN0 is connected to the source of NMOS transistor N0, and its source is connected to the drain of FNPASS select transistor FN1. The source of FNPASS select transistor FN1 is grounded to vgnd. The gate of NMOS transistor NM0 is input to the clamp voltage Vlim, the gate of SONOS cell transistor SN0 is grounded to vgnd, and the gate of FNPASS select transistor FN1 is input to the power supply voltage vpwr. The gate and drain of PMOS transistor P3 are connected to the gate of PMOS transistor P2 and the drain of NMOS transistor N1. The drain of SONOS cell transistor SN1 is connected to the source of NMOS transistor N1, and its source is connected to the drain of FNPASS select transistor FN0. The source of FNPASS select transistor FN0 is grounded to vgnd. The gate of NMOS transistor N1 is connected to the clamp voltage Vlim. The gate of SONOS cell transistor SN1 is connected to ground vgnd. The gate of FNPASS select transistor FN0 is connected to the power supply voltage vpwr. The drain of PMOS transistor P1 is connected to the drain of NMOS transistor N4 and the drain of NMOS transistor N2, with the node they connect being denoted as VD0. The drain of PMOS transistor P2 is connected to the source of NMOS transistor N4 and the drain of NMOS transistor N3, with the node they connect being denoted as VD1. The gate of NMOS transistor N2 is connected to node VD1, and the gate of NMOS transistor N3 is connected to node VD0. The sources of NMOS transistors N2 and N3 are connected to the drain of NMOS transistor N5, which is connected to ground vgnd. The gate of NMOS transistor N4 is connected to the prepare signal PRE. The gate of NMOS transistor N5 is connected to the read signal READ. Node VD0 is connected to the R input terminal (reset terminal) of the RS flip-flop, node VD1 is connected to the S input terminal (set terminal) of the RS flip-flop, and the output terminal SOUT of the RS flip-flop serves as the output terminal of the circuit.

[0005] Figure 1 The current lref is the current flowing out of the drain of the PMOS transistor P1 and entering the node VD0; the current lcell is the current flowing out of the drain of the PMOS transistor P2 and entering the node VD1. Figure 1 For waveform diagrams of the circuit shown, see Figure 2As shown. The working principle of the above circuit is as follows: When reading a cell, the state of the Reference cell is opposite to that of the Array cell (that is, when the current of Icell is large, the current of Iref is small; when the current of Icell is small, the current of Iref is large); during PRE, VD0 and VD1 will be pulled to the same potential around Vt (threshold voltage); after PRE ends, it enters the sense process: When reading an erase cell, that is, reading a 0 cell, Icell > Iref, the NMOS transistor N2 quickly turns on, VD0 is pulled down, VD1 is pulled up, and SOUT outputs 0 (low level); when reading a progarm cell, that is, reading a 1 cell, Icell < Iref, the NMOS transistor N3 quickly turns on, VD1 is pulled down, VD0 is pulled up, and SOUT outputs 1 (high level).

[0006] The disadvantages of the above circuit are: The array area composed of the circuit is relatively large. Summary of the Invention

[0007] In view of this, the present invention provides a SONOS read circuit to solve the problem that the array area composed of the existing SONOS cell and its read circuit is relatively large.

[0008] The present invention provides a SONOS read circuit, including: four PMOS transistors P0 to P3, two NMOS transistors N0, N1, two inverters INV0, INV1, two SONOS cell transistors SN0, SN1, two FNPASS selection transistors FN0, FN1, and a comparator;

[0009] The sources of the PMOS transistors P2 and P3 are connected to the power supply voltage terminal vpwr; the gate of the PMOS transistor P2 is connected to the drain of the PMOS transistor P3, and the connected node is denoted as VF; the gate of the PMOS transistor P3 is connected to the drain of the PMOS transistor P2, and the connected node is denoted as VR;

[0010] The drain of the NMOS transistor N0 is connected to the node VR, and the gate is connected to the node VF; the drain of the NMOS transistor N1 is connected to the node VF, and the gate is connected to the node VR; the sources of the NMOS transistor N0 and the NMOS transistor N1 are connected to the ground;

[0011] The source of the PMOS transistor P0 is connected to the input terminal of the inverter INV0 and the drain of the SONOS cell transistor SN0; the output terminal of the inverter INV0 is connected to the gate of the PMOS transistor P0;

[0012] The source of PMOS transistor P1 is connected to the input terminal of inverter INV1 and the drain of SONOS cell transistor SN1; the output terminal of inverter INV1 is connected to the gate of PMOS transistor P1;

[0013] The source of SONOS cell transistor SN0 is connected to the drain of FNPASS selection transistor FN0, and the source and gate of FNPASS selection transistor FN0 are connected to word line wl; the source of SONOS cell transistor SN1 is connected to the drain of FNPASS selection transistor FN1, and the source and gate of FNPASS selection transistor FN1 are connected to word line wl; the gates of SONOS cell transistors SN0 and SN1 are grounded.

[0014] The positive input terminal of the comparator is connected to node VR, the negative input terminal is connected to node VF, and its output terminal serves as the output terminal SOUT of the circuit.

[0015] Preferably, the SONOS cell transistor SN0 and the FNPASS selection transistor FN0 constitute a storage unit.

[0016] Preferably, the SONOS cell transistor SN1 and the FNPASS selection transistor FN1 constitute a reference storage unit.

[0017] Preferably, when reading the circuit, the current states of the reference storage unit and the storage unit are opposite. When the current I1 of the reference storage unit is larger, the current I0 of the storage unit is smaller; when the current I1 of the reference storage unit is smaller, the current I0 of the storage unit is larger.

[0018] Preferably, when PRE is prepared, nodes VR and VF will be pulled down to zero potential, and the potential of word line wl is about 2V. <s

[0019] Preferably, after the preparation of PRE is completed, the comparison working process is entered:

[0020] When reading an erase unit, I0 > I1, NMOS transistor N0 is quickly turned on, the voltage of node VR is quickly pulled from 0 to above the threshold voltage Vt, and SOUT outputs 0;

[0021] When reading a programming unit, I0 < I1, NMOS transistor N1 is quickly turned on, the voltage of node VF is quickly pulled from 0 to above the threshold voltage Vt, and SOUT outputs 1.

[0022] The array area composed of the SONOS read circuit of the present invention is reduced by more than 1 / 3 compared to the array area composed of the existing traditional SONOS cell and its read circuit, greatly reducing the product cost. Description of the Drawings

[0023] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0024] Figure 1 Shown is a schematic diagram of the circuit structure of an existing traditional SONOS cell and its read circuit;

[0025] Figure 2 yes Figure 1 Waveform diagram;

[0026] Figure 3 Shown is a schematic diagram of the circuit structure of a SONOS read circuit according to an embodiment of the present invention;

[0027] Figure 4 yes Figure 3 Waveform diagram. DETAILED DESCRIPTION

[0028] The present invention is described below based on the following embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, certain specific details are described in detail. Those skilled in the art can fully understand the present invention without these details. To avoid obscuring the essence of the present invention, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0029] Furthermore, persons of ordinary skill in the art will appreciate that the figures provided herein are for illustration purposes only and are not necessarily drawn to scale.

[0030] Unless the context clearly requires otherwise, words like “include”, “comprising” and the like throughout this application should be interpreted as including rather than exclusive or exhaustive; that is, as meaning “including but not limited to”.

[0031] In the description of the present invention, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and should not be understood to indicate or imply relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0032] Figure 3 The circuit structure diagram of the SONOS read circuit according to the embodiment of the present invention is shown. Figure 3 As shown, the SONOS read circuit of the embodiment of the present invention is composed of four PMOS transistors P0-P3, two NMOS transistors N0 and N1, two inverters INV0 and INV1, two SONOS cell transistors SN0 and SN1, two FNPASS selection transistors FN0 and FN1, and a comparator. The specific circuit structure is as follows:

[0033] The sources of the PMOS transistors P2 and P3 are connected to the power supply voltage terminal vpwr.

[0034] The gate of the PMOS transistor P2 is connected to the drain of the PMOS transistor P3, and the node at which they are connected is denoted as VF. The gate of the PMOS transistor P3 is connected to the drain of the PMOS transistor P2, and the node at which they are connected is denoted as VR.

[0035] The drain of NMOS transistor N0 is connected to node VR, and the gate is connected to node VF. The drain of NMOS transistor N1 is connected to node VF, and the gate is connected to node VR. The sources of NMOS transistor N0 and NMOS transistor N1 are connected to ground.

[0036] The source of the PMOS transistor P0 is connected to the input of the inverter INV0 and the drain of the SONOS cell transistor SN0 , and the output of the inverter INV0 is connected to the gate of the PMOS transistor P0 .

[0037] The source of the PMOS transistor P1 is connected to the input of the inverter INV1 and the drain of the SONOS cell transistor SN1 , and the output of the inverter INV1 is connected to the gate of the PMOS transistor P1 .

[0038] The source of SONOS cell transistor SN0 is connected to the drain of FNPASS select transistor FN0, and the source and gate of FNPASS select transistor FN0 are connected to word line wl. The source of SONOS cell transistor SN1 is connected to the drain of FNPASS select transistor FN1, and the source and gate of FNPASS select transistor FN1 are connected to word line wl. The gates of SONOS cell transistors SN0 and SN1 are grounded.

[0039] The comparator has a positive input terminal connected to the node VR, a negative input terminal connected to the node VF, and an output terminal serving as the output terminal SOUT of the circuit.

[0040] In the embodiment of the present invention, the SONOS cell transistor SN0 and the FNPASS selection transistor FN0 are connected in series as a storage unit of the circuit, and the SONOS cell transistor SN1 and the FNPASS selection transistor FN1 are connected in series as a reference storage unit of the circuit.

[0041] Figure 3 The current l0 in is the memory cell current, and the current ll is the reference memory cell current. Figure 4 The waveform diagram of the circuit shown in the embodiment of the present invention is shown. The working principle of the circuit of the embodiment of the present invention is:

[0042] When reading a cell, the states of the reference cell and the array cell are opposite. That is, when the current I0 is large, the current I1 is small; when the current I0 is small, the current I1 is large.

[0043] During PRE, VR and VF will be pulled down to 0 potential; the wl potential is about 2V. After PRE ends, the sense process starts:

[0044] When reading an erase cell, I0 > I1, the NMOS transistor N0 quickly turns on, the voltage point VR is quickly pulled from 0 to above Vt, and SOUT outputs 0;

[0045] When reading a program cell, I0 < I1, the NMOS transistor quickly turns on, the voltage point VF is quickly pulled from 0 to above Vt, and SOUT outputs 1.

[0046] The array area composed of the SONOS read circuit of the present invention is reduced by more than 1 / 3 compared to the array area composed of the existing traditional SONOS cell and its read circuit, greatly reducing the product cost.

[0047] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A SONOS read circuit, characterized in that: Comprising: Four PMOS transistors P0 to P3, two NMOS transistors N0, N1, two inverters INV0, INV1, two SONOS cell transistors SN0, SN1, two FNPASS selection transistors FN0, FN1, and a comparator; The sources of PMOS transistors P2 and P3 are connected to the power supply voltage terminal vpwr; the gate of PMOS transistor P2 is connected to the drain of PMOS transistor P3, and the connected node is denoted as VF; the gate of PMOS transistor P3 is connected to the drain of PMOS transistor P2, and the connected node is denoted as VR; The drain of NMOS transistor N0 is connected to node VR, and the gate is connected to node VF; the drain of NMOS transistor N1 is connected to node VF, and the gate is connected to node VR; the sources of NMOS transistors N0 and N1 are connected to ground; The source of PMOS transistor P0 is connected to the input terminal of inverter INV0 and the drain of SONOS cell transistor SN0; the output terminal of inverter INV0 is connected to the gate of PMOS transistor P0; The source of PMOS transistor P1 is connected to the input terminal of inverter INV1 and the drain of SONOS cell transistor SN1; the output terminal of inverter INV1 is connected to the gate of PMOS transistor P1; The source of SONOS cell transistor SN0 is connected to the drain of FNPASS selection transistor FN0, and the source and gate of FNPASS selection transistor FN0 are connected to the word line wl; the source of SONOS cell transistor SN1 is connected to the drain of FNPASS selection transistor FN1, and the source and gate of FNPASS selection transistor FN1 are connected to the word line wl; the gates of SONOS cell transistors SN0 and SN1 are grounded; The positive input terminal of the comparator is connected to node VR, the negative input terminal is connected to node VF, and its output terminal serves as the output terminal SOUT of the circuit.

2. The SONOS read circuit according to claim 1, wherein: The SONOS cell transistor SN0 and the FNPASS selection transistor FN0 constitute a memory cell.

3. The SONOS read circuit according to claim 2, wherein: The SONOS cell transistor SN1 and the FNPASS selection transistor FN1 constitute a reference memory cell.

4. The SONOS read circuit according to claim 3, wherein: When reading the circuit, the current states of the reference memory cell and the memory cell are opposite. When the current I1 of the reference memory cell is larger, the current I0 of the memory cell is smaller; when the current I1 of the reference memory cell is smaller, the current I0 of the memory cell is larger.

5. The SONOS read circuit according to claim 1, wherein: When preparing PRE, nodes VR and VF will be pulled down to zero potential, and the potential of the word line wl is about 2V.

6. The SONOS read circuit according to claim 4, wherein: After the PRE preparation is completed, it enters the comparison working process: When reading the erase cell, I0 > I1, the NMOS transistor N0 is quickly turned on, the voltage of node VR is quickly pulled from 0 to above the threshold voltage Vt, and SOUT outputs 0; When reading the program cell, I0 < I1, the NMOS transistor N1 is quickly turned on, the voltage of node VF is quickly pulled from 0 to above the threshold voltage Vt, and SOUT outputs 1.

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