A TTL level conversion circuit

Abstract

The present invention discloses a TTL level conversion circuit, which belongs to the technical field of semiconductor integrated circuits. The level conversion module uses a plurality of D tubes connected in series to shift the input level to a first target level, and the D tube is a gallium arsenide depletion-type field effect tube; the inverter module includes a first-stage inverter and a second-stage inverter electrically connected in sequence; the first-stage inverter and the second inverter both include an inverting logic function unit, a power supply branch and a load unit, wherein the inverting logic function unit is electrically connected to the power supply branch and the load unit power supply branch respectively, and the field effect tubes in the inverting logic function unit, the power supply branch and the load unit are all D tubes. Advantages: All based on depletion-type field effect tubes and resistors, without using enhanced field effect tubes, a level conversion circuit that meets the requirements is designed, which promotes the simplification and miniaturization of monolithic microwave integrated circuits and greatly improves the applicability of the process.

Description

Technical Field

[0001] The invention relates to a TTL level conversion circuit, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] Many control-type monolithic microwave integrated circuits in semiconductor integrated circuits, such as attenuators, phase shifters, and switch chips, often integrate digital drivers on-chip or external digital drivers in order to control their on and off. The digital driver TTL (Transistor-Transistor Logic) circuit is responsible for outputting the commonly used +5V / 0V voltage to the on and off voltage required by the switch tube. The ED mode of gallium arsenide pHEMT is usually used to design TTL drive circuits. Compared with traditional HEMT tubes, pHEMT tubes have larger output resistance, higher transconductance, higher current handling capability, and lower noise.

[0003] It is known that most switch tubes used to design attenuators, phase shifters and switches are depletion-type field-effect tubes. Through the PDK manual provided by the manufacturer and the actual DC scanning results, it is determined that the turn-on voltage range of the switch tube is -0.7V~1V, and the turn-off voltage is -5V~-1V. Therefore, as long as the high and low levels output by the TTL level conversion circuit are within this range, it is sufficient to drive the switch tube to turn on and off.

[0004] The traditional TTL level conversion circuit is designed with ED mode, where the D tube acts as a load and the E tube (enhanced field effect tube) plays a key logic role. It mainly includes a level conversion module and an inverter module. The traditional inverter module is Figure 1 As shown, the source of the E tube is directly connected to the -5V power supply. However, according to the GaAs process libraries currently provided by major manufacturers, not all GaAs libraries contain both E tubes and D tubes, so there are certain limitations in the design. Summary of the invention

[0005] The technical problem to be solved by the present invention is to overcome the defects of the prior art and provide a TTL level conversion circuit.

[0006] In order to solve the above technical problems, the present invention is implemented by adopting the following technical solutions.

[0007] The invention discloses a TTL level conversion circuit, comprising a level conversion module and an inverter module;

[0008] The level conversion module uses a plurality of D-tubes connected in series to shift the input level to a first target level, and the D-tubes are gallium arsenide depletion-type field effect tubes;

[0009] The inverter module includes a first-stage inverter and a second-stage inverter which are electrically connected in sequence, wherein the first-stage inverter converts an input first target level into a second target level based on an inversion logic, and the second-stage inverter converts an input second target level into a third target level based on an inversion logic;

[0010] The first-stage inverter and the second-stage inverter each include an inverting logic functional unit, a power supply branch and a load unit, wherein the inverting logic functional unit is electrically connected to the power supply branch and the load unit power supply branch respectively, and the field effect transistors in the inverting logic functional unit, the power supply branch and the load unit are all D tubes;

[0011] The level conversion module is powered by a power supply branch of the first-stage inverter or the second-stage inverter.

[0012] Furthermore, the input level is 0V and 5V, the first target level corresponding to the input level is a negative voltage level and 0V, the second target level corresponding to the first target level is a -0.7V~1V level and a -5V~-1V level after the first inversion through the first stage inverter, and the third target level corresponding to the second target level is a -5V~-1V level and a -0.7V~1V level after the second inversion through the second stage inverter. The two-stage inverter plays an inversion role and improves the load carrying capacity by stabilizing the output voltage waveform.

[0013] Furthermore, the source and drain of each D tube in the plurality of D tubes connected in series are connected, the gate of the next D tube is connected to the source and drain or drain of the previous D tube, the gate of the first D tube is connected to the input level, and the source and drain or drain of the last D tube is connected to the inverter module as the first node a. Compared with the prior art, the present invention uses D tubes with connected sources and drains to form diodes, and controls the voltage through the gate, thereby achieving unidirectional conductivity and expanding the applicability of the process.

[0014] Furthermore, the level conversion module further includes a resistor R1, one end of the resistor R1 is connected to the first node a, and the other end of the resistor R1 is connected to the inverter module as the second node b. Compared with the prior art, the large resistor R1 in the present invention reduces the input control voltage V in of power consumption.

[0015] Further, the power supply branch of the first-stage inverter includes a sixth D tube and a second resistor R2, the second node b is connected to the drain of the sixth D tube, the source of the sixth D tube is connected to one end of the second resistor R2, and the other end of the second resistor R2 is respectively connected to a -5V power supply and a gate of the sixth D tube. Compared with the prior art, the connection method of the sixth D tube and the second resistor R2 in the present invention increases the resistance value of the power supply branch, thereby reducing the power consumption of the -5V power supply.

[0016] Further, the inverting logic functional unit of the first-stage inverter includes a third resistor R3 and a plurality of seventh D transistors connected in sequence; the load unit of the first-stage inverter includes an eighth D transistor and a fourth resistor R4;

[0017] The source of the previous seventh D tube is connected to the drain of the next seventh D tube, and the drain of the first seventh D tube is connected as the third node c to one end of the fourth resistor R4, the gate of the eighth D tube, and the second target level output terminal V out1 The source of the last seventh D tube is connected to one end of the third resistor R3 as the fourth node d, the other end of the third resistor R3 is connected to the -5V power supply, and the gates of all the seventh D tubes are connected to the second node b; the other end of the fourth resistor R4 is connected to the source of the eighth D tube, and the drain of the eighth D tube is grounded.

[0018] In the inverting circuit module, the seventh D tube plays a logical role. The source of the seventh D tube is connected in series with the third resistor R3 and connected to the -5V power supply to realize source resistance voltage division. By controlling the first resistor R1 in the power supply branch, the cut-off resistance of the sixth D tube, the cut-off resistance of the eighth D tube in the load unit, the resistance value of the fourth resistor R4, the size of the inverting logic tube seventh D tube and the resistance value of the third resistor R3, the inverter can be turned on when the input is high level and turned off when the input is low level, thereby completing the inverting function.

[0019] Furthermore, a fifth resistor R5 is provided between the first-stage inverter and the second-stage inverter, one end of the fifth resistor R5 is connected to the third node c, and the other end of the fifth resistor R5 is connected to the second-stage inverter as the fifth node e. Compared with the prior art, the large resistor R5 in the present invention reduces the input control voltage V in of power consumption.

[0020] Further, the power supply branch of the second-stage inverter includes a ninth D tube and a sixth resistor R6, the fifth node e is connected to the drain of the ninth D tube, the source of the ninth D tube is connected to one end of the sixth resistor R6, and the other end of the sixth resistor R6 is respectively connected to the -5V power supply and the gate of the ninth D tube. Compared with the prior art, the connection method of the ninth D tube and the second resistor R2 in the present invention increases the resistance value of the power supply branch, thereby reducing the power consumption of the -5V power supply.

[0021] Further, the inverting logic functional unit of the second-stage inverter includes a seventh resistor R7 and a plurality of tenth D tubes connected in sequence; the load unit of the second-stage inverter includes an eleventh D tube and an eighth resistor R8;

[0022] The source of the previous tenth D tube is connected to the drain of the next tenth D tube, and the drain of the first tenth D tube is respectively connected to one end of the eighth resistor R8, the gate of the eleventh D tube, and the third target level output terminal V out2The source of the last tenth D tube is connected to one end of the seventh resistor R7 as the sixth node f, the other end of the seventh resistor R7 is connected to the -5V power supply, and the gates of all the tenth D tubes are connected to the fifth node e; the other end of the eighth resistor R8 is connected to the source of the eleventh D tube, and the drain of the eleventh D tube is grounded.

[0023] In the inverting circuit module, the tenth D tube plays a logical role, and the source of the tenth D tube is connected in series with the seventh resistor R7 to the -5V power supply to realize source resistance voltage division. By controlling the sixth resistor R6 in the power supply branch, the cut-off resistance of the ninth D tube, the cut-off resistance of the eleventh D tube in the load unit, the resistance value of the eighth resistor R8, the size of the inverting logic tube tenth D tube and the resistance value of the seventh resistor R7, it can be ensured that the inverter is turned on when the input is high level, and the inverter is turned off when the input is low level, thereby completing the inverting function.

[0024] The beneficial effects achieved by the present invention are:

[0025] The circuits of the present invention are all based on depletion-type field effect transistors and resistors. Under the premise of not using enhancement-type field effect transistors, a level conversion circuit that meets the requirements is designed, which promotes the simplification and miniaturization of monolithic microwave integrated circuits and greatly improves the applicability of the process. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is the inverter module diagram of the traditional TTL drive circuit;

[0027] Figure 2 It is the overall architecture diagram of the present invention;

[0028] Figure 3 It is a specific circuit structure diagram of the present invention;

[0029] Figure 4 This is a transient simulation result diagram of a specific example 1 of the present invention. DETAILED DESCRIPTION

[0030] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.

[0031] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and the like are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", and the like may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0032] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood by specific circumstances.

[0033] Embodiment 1, as Figure 2 As shown, this embodiment introduces a TTL level conversion circuit, including a level conversion module and an inverter module;

[0034] The level conversion module uses a plurality of D-tubes connected in series to shift the input level to a first target level, and the D-tubes are gallium arsenide depletion-type field effect tubes;

[0035] The inverter module includes a first-stage inverter and a second-stage inverter which are electrically connected in sequence, wherein the first-stage inverter converts an input first target level into a second target level based on an inversion logic, and the second-stage inverter converts an input second target level into a third target level based on an inversion logic;

[0036] The first-stage inverter and the second-stage inverter each include an inverting logic functional unit, a power supply branch and a load unit, wherein the inverting logic functional unit is electrically connected to the power supply branch and the load unit power supply branch respectively, and the field effect transistors in the inverting logic functional unit, the power supply branch and the load unit are all D tubes;

[0037] The level conversion module is powered by a power supply branch of the first-stage inverter or the second-stage inverter.

[0038] The input levels are 0V and 5V, the first target level corresponding to the input level is a negative voltage level and 0V, the second target level corresponding to the first target level is a -0.7V~1V level and a -5V~-1V level after the first inversion through the first-stage inverter, and the third target level corresponding to the second target level is a -5V~-1V level and a -0.7V~1V level after the second inversion through the second-stage inverter.

[0039] The source and drain of each D tube in the plurality of D tubes connected in series are connected, the gate of the next D tube is connected to the source and drain or drain of the previous D tube, the gate of the first D tube is connected to the input level, and the source and drain or drain of the last D tube is connected to the inverter module as the first node a.

[0040] The level conversion module further includes a resistor R1 , one end of the resistor R1 is connected to a first node a, and the other end of the resistor R1 is connected to the inverter module as a second node b.

[0041] The power supply branch of the first-stage inverter includes a sixth D tube and a second resistor R2, the second node b is connected to the drain of the sixth D tube, the source of the sixth D tube is connected to one end of the second resistor R2, and the other end of the second resistor R2 is respectively connected to a -5V power supply and a gate of the sixth D tube.

[0042] The inverting logic functional unit of the first-stage inverter includes a third resistor R3 and a plurality of seventh D transistors connected in sequence; the load unit of the first-stage inverter includes an eighth D transistor and a fourth resistor R4;

[0043] The source of the first seventh D tube is connected to the drain of the next seventh D tube, and the drain of the first seventh D tube is connected as the third node c to one end of the resistor R4, the gate of the eighth D tube, and the second target level output terminal V out1 The source of the last seventh D tube is connected to one end of the third resistor R3 as the fourth node d, the other end of the third resistor R3 is connected to the -5V power supply, and the gates of all the seventh D tubes are connected to the second node b; the other end of the fourth resistor R4 is connected to the source of the eighth D tube, and the drain of the eighth D tube is grounded.

[0044] A fifth resistor R5 is further provided between the first-stage inverter and the second-stage inverter. One end of the fifth resistor R5 is connected to the third node c, and the other end of the fifth resistor R5 is connected to the second-stage inverter as a fifth node e.

[0045] The inverting logic functional unit of the second-stage inverter includes a seventh resistor R7 and a plurality of tenth D tubes connected in sequence; the load unit of the second-stage inverter includes an eleventh D tube and an eighth resistor R8;

[0046] The source of the first tenth D tube is connected to the drain of the next tenth D tube, and the drain of the first tenth D tube is respectively connected to one end of the resistor R8, the gate of the eleventh D tube, and the third target level output terminal V out2 The source of the last tenth D tube is connected to one end of the seventh resistor R7 as the sixth node f, the other end of the seventh resistor R7 is connected to the -5V power supply, and the gates of all the tenth D tubes are connected to the fifth node e; the other end of the eighth resistor R8 is connected to the source of the eleventh D tube, and the drain of the eleventh D tube is grounded.

[0047] The power supply branch of the second-stage inverter includes a ninth D tube and a sixth resistor R6, the fifth node e is connected to the drain of the ninth D tube, the source of the ninth D tube is connected to one end of the sixth resistor R6, and the other end of the sixth resistor R6 is respectively connected to the -5V power supply and the gate of the ninth D tube.

[0048] Embodiment 2, as shown in the figure, this embodiment introduces a TTL level conversion circuit, especially in the inverter module, the level shift module shifts the input 0V and 5V to a certain negative voltage level and a level around 0V. The negative voltage level and the level around 0V output by the level shift module are output through the first stage inverter V out1 The -0.7V~1V level and -5V~-1V level are output through the second stage inverter V out2 The voltage level is -5V~-1V and -0.7V~1V. The two-stage inverter serves to stabilize the output waveform; the present invention is only composed of a gallium arsenide depletion field effect tube and a resistor.

[0049] The first D-tube T1, the second D-tube T2, the third D-tube T3, the fourth D-tube T4 and the fifth D-tube T5 of the level shift module are connected to the source and drain respectively, the source or the drain of the fifth D-tube T5 is connected to one end of the first resistor, the other end of the first resistor is the second node b, the second node b is connected to the drain of the sixth D-tube T6, the sixth D-tube T6 is connected in series with the second resistor to form a large resistor, and the other end of the second resistor is connected to the -5V power supply.

[0050] The second node b is the input end of the inverter module, the second node b is connected to the drain of the sixth D tube, the other end of the sixth D tube is connected to the -5V power supply, the second node b is connected to the gate of the seventh D tube, the source of the seventh D tube is connected to the third resistor, the other end of the third resistor is connected to the -5V power supply; the drain of the seventh D tube is the third node c, the third node c leads to the output The drain of the seventh D tube is connected to the fourth resistor, the other end of the fourth resistor is connected to the source of the eighth D tube, the drain of the eighth D tube is grounded, and the source of the eighth D tube is connected in series with the fourth resistor to form a large resistor.

[0051] In the first stage inverter, the seventh D tube plays a key logical role. Compared with the E tube, the D tube has a higher V gs=0, so the third resistor is connected in series at the drain of the seventh D tube. By setting a suitable third resistor value, the seventh D tube can be turned on and off when a high or low level is input.

[0052] Second stage inverter: V out1 As the input end of the second-stage inverter, the input end is connected to one end of the fifth resistor, the other end of the fifth resistor is the fifth node e, the fifth node e is connected to the drain of the ninth D tube, the source of the ninth D tube is connected to the sixth resistor, the gate and drain of the ninth D tube are connected to form a large resistor, and are connected in series with the sixth resistor, the other end of the sixth resistor is connected to the power supply -5V; the fifth node e is connected to the tenth D tube, the source of the tenth D tube is connected to the seventh resistor, and the other end of the seventh resistor is connected to the -5V power supply; the drain of the tenth D tube is led to the output V out2 The drain of the tenth D tube is connected to the eighth resistor, the other end of the eighth resistor is connected to the eleventh D tube, the drain of the eleventh D tube is grounded, the gate and source of the eleventh D tube are connected to form a large resistor, and are connected in series with the eighth resistor.

[0053] In the second inverter, the tenth D tube plays a key logical role. Compared with the E tube, the D tube has a higher V gs =0, so the seventh resistor is connected in series to the drain of the tenth D tube. By setting a suitable value of the seventh resistor, the tenth D tube can complete the function of turning on and off when the input is high or low level.

[0054] Embodiment 3, this embodiment introduces a TTL level conversion circuit, such as Figure 3 As shown, in the level shift circuit, the first D-tube T1, the second D-tube T2, the third D-tube T3, the fourth D-tube T4, and the fifth D-tube T5 are connected with their sources and drains to form the first diode, the second diode, the third diode, the fourth diode, and the fifth diode. The fifth diode is connected to the first resistor R1 at the end, the other end of the first resistor R1 is the second node b, the second node b is connected to the drain of the sixth D-tube T6, and is connected in series with the second resistor R2 to form a large resistor, and the other end of the second resistor R2 is connected to V EE Power supply, V EE =-5V. If the sizes of the first D-tube T1, the second D-tube T2, the third D-tube T3, the fourth D-tube T4, and the fifth D-tube T5 are different, the corresponding forward conduction voltage drops may be different, so the size and number of the field effect tubes should be selected according to the specific situation.

[0055] First-stage inverter: The second node b is the input end of the inverter circuit. The second node b is connected to the sixth D-type transistor T6. The other end of the sixth D-type transistor T6 is connected to V EE The second node is connected to the gate of the seventh D transistor T7, the source of the seventh D transistor T7 is connected to the third resistor R3, and the other end of the third resistor R3 is connected to V EE The drain of the seventh D tube T7 is the third node c, and the third node c leads to the output V out1The drain of the seventh D-type transistor T7 is connected to the fourth resistor R4, the other end of the fourth resistor R4 is connected to the source of the eighth D-type transistor T8, the drain of the eighth D-type transistor T8 is grounded, and the source of the eighth D-type transistor T8 is connected in series with the fourth resistor R4 to form a large resistor. The seventh D-type transistor T7 plays a key role in logic. Compared with the E-type transistor, the D-type transistor has a higher voltage at V gs =0, so the third resistor R3 is connected in series to the drain of the seventh D-type transistor T7. By setting a suitable third resistor value, the seventh D-type transistor T7 can be turned on and off when a high or low level is input.

[0056] Second stage inverter: V out1 As the input end of the second-stage inverter, the input end is connected to the fifth resistor R5, the other end of the fifth resistor R5 is the fifth node e, the fifth node e is connected to the drain of the ninth D tube T9, the source of the ninth D tube T9 is connected to the sixth resistor R6, the gate and drain of the ninth D tube T9 are connected to form a large resistor, and are connected in series with the sixth resistor R6, the other end of the sixth resistor R6 is connected to V EE Power supply; the fifth node is connected to the tenth D tube T 10 ,Tenth D tube T 10 The source is connected to the seventh resistor R7, and the other end of the seventh resistor R7 is connected to V EE Power supply; tenth D tube T 10 The drain leads to the output V out2 ; Tenth D tube T 10 The drain is connected to the eighth resistor R8, and the other end of the eighth resistor R8 is connected to the eleventh D transistor T 11 , 11th D tube T 11 The drain is grounded, the eleventh D tube T 11 The gate and source are connected to form a large resistor, and are connected in series with the eighth resistor R8. The tenth transistor T plays a key role in logic. 10 Compared with E tube, D tube has a higher V gs = 0, it is already turned on, so in the tenth D tube T 10 The drain electrode is connected in series with the seventh resistor R7, and by setting a suitable seventh resistor value, the tenth transistor T 10 It can turn on and off when inputting high or low level.

[0057] TTL level conversion circuit principle:

[0058] When a +5V high level is input, the voltage difference across the first D-type transistor T1, the second D-type transistor T2, the third D-type transistor T3, the fourth D-type transistor T4, and the fifth D-type transistor T5 is sufficient, and the five diodes are turned on. The voltage drop of each diode is about 0.98V, and the level V at the first node a is a 5-0.98×5=0.1V; the sixth D tube T6 and the second resistor R2 are equivalent to a large resistor close to the cut-off state. Since the resistor cannot be infinite, a small current is allowed to exist in the actual circuit.

[0059] In the first inverter, the first resistor R1, the sixth D transistor T6, the second resistor R2 and V EE On the branch, the voltage V at the second node b can be obtained by the resistor voltage divider formula. b is (V EE -V a )×(R T6 / (R1+ R T6 )), the voltage V at the fourth point d is obtained by the resistor voltage division formula on the eighth D tube T8, the fourth resistor R4, the seventh D tube T7, the third resistor R3 and the -5V branch. d =5×(R3 / (R T8 + R3)), by controlling the cut-off voltage R of the first resistor R1 and the sixth D transistor T6 T6 , the cut-off voltage R of the eighth D tube T8 T8 , the size of the third resistor R3, to ensure (V b -V d )>V TH , the seventh D tube T7 is turned on, V out1 =V d ≈-3.4V;

[0060] Similarly, the voltage V at the fifth node e of the second inverter e is (V EE -V out1 )×(R T9 / (R5+ R T9 )), the voltage V at the sixth node f f =5×(R7 / (R T11 + R7)), by controlling the cut-off voltage R of the fifth resistor R5 and the ninth D tube T9 T9 、11th D tube T 11 The cut-off voltage R T11 , the size of the seventh resistor R7 is guaranteed to be (V e -V f )>V TH , the tenth D tube T 10 Cut-off, V out2 ≈-0.4V.

[0061] When the input is 0V low level, similar to the above principle, the level V at the first node a a 0-0.98×5≈-5V; V b ≈V a , the voltage V at the fourth point d d =5×(R3 / (R T8 + R3)), guaranteed (V b -V d ) is less than VTH , the seventh D tube T7 is cut off, V out1 =V c ≈-0.4V; the voltage of the fifth node e is V e is (V EE -V out1 )×(R T9 / (R5+ R T9 )), the voltage V at the sixth node f f =5×(R7 / (R T11 + R7)), guaranteed (V e -V f ) is less than V TH ,Tenth D tube T 10 On, V out2 =V f ≈-3.4V.

[0062] It should be noted that, in order to reduce DC power consumption, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 are large resistors of at least kilo-ohm level, and the sizes of the first D-tube T1, the second D-tube T2, the third D-tube T3, the fourth D-tube T4, the fifth D-tube T5, the sixth D-tube T6, the seventh D-tube T7, and the eighth D-tube T8 need to be determined according to the actual situation of the circuit.

[0063] Finally, the input 5V / 0V is converted into complementary high and low level output V based only on depletion field effect transistors and resistors. out1 -3.4V / -0.4V, V out2 The switching time is 17ns, and the maximum power consumption is -5V / 0.42µA. Figure 4 The complementary level output V out1 and V out2 It is sufficient to drive the switch tube in the control microwave integrated circuit to open and close, which promotes the simplification and miniaturization of monolithic microwave integrated circuits and greatly improves the process applicability.

[0064] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A TTL level conversion circuit, characterized in that: It includes a level conversion module and an inverter module; The level conversion module uses a plurality of D-tubes connected in series to shift the input level to a first target level, and the D-tubes are gallium arsenide depletion-type field effect tubes; The inverter module includes a first-stage inverter and a second-stage inverter which are electrically connected in sequence, wherein the first-stage inverter converts an input first target level into a second target level based on an inversion logic, and the second-stage inverter converts an input second target level into a third target level based on an inversion logic; The first-stage inverter and the second-stage inverter each include an inverting logic functional unit, a power supply branch and a load unit, wherein the inverting logic functional unit is electrically connected to the power supply branch and the load unit power supply branch respectively, and the field effect transistors in the inverting logic functional unit, the power supply branch and the load unit are all D tubes; The level conversion module is powered by a power supply branch of the first-stage inverter or the second-stage inverter; The source and drain of each D tube in the plurality of D tubes connected in series are connected, the gate of the next D tube is connected to the source and drain or drain of the previous D tube, the gate of the first D tube is connected to the input level, and the source and drain or drain of the last D tube is connected to the inverter module as the first node a; The level conversion module further includes a resistor R1, one end of the resistor R1 is connected to the first node a, and the other end of the resistor R1 is connected to the inverter module as a second node b; The power supply branch of the first-stage inverter includes a sixth D tube and a second resistor R2, the second node b is connected to the drain of the sixth D tube, the source of the sixth D tube is connected to one end of the second resistor R2, and the other end of the second resistor R2 is respectively connected to a -5V power supply and a gate of the sixth D tube.

2. The TTL level conversion circuit according to claim 1, characterized in that: The input levels are 0V and 5V, the first target level corresponding to the input level is a negative voltage level and 0V, the second target level corresponding to the first target level is a -0.7V~1V level and a -5V~-1V level after the first inversion through the first-stage inverter, and the third target level corresponding to the second target level is a -5V~-1V level and a -0.7V~1V level after the second inversion through the second-stage inverter.

3. The TTL level conversion circuit according to claim 1, characterized in that: The inverting logic functional unit of the first-stage inverter includes a third resistor R3 and a plurality of seventh D transistors connected in sequence; the load unit of the first-stage inverter includes an eighth D transistor and a fourth resistor R4; The source of the first seventh D tube is connected to the drain of the next seventh D tube, and the drain of the first seventh D tube is connected as the third node c to one end of the resistor R4, the gate of the eighth D tube, and the second target level output terminal V out1 The source of the last seventh D tube is connected to one end of the third resistor R3 as the fourth node d, the other end of the third resistor R3 is connected to the -5V power supply, and the gates of all the seventh D tubes are connected to the second node b; the other end of the fourth resistor R4 is connected to the source of the eighth D tube, and the drain of the eighth D tube is grounded.

4. The TTL level conversion circuit according to claim 3, characterized in that: A fifth resistor R5 is further provided between the first-stage inverter and the second-stage inverter. One end of the fifth resistor R5 is connected to the third node c, and the other end of the fifth resistor R5 is connected to the second-stage inverter as a fifth node e.

5. The TTL level conversion circuit according to claim 4, characterized in that: The inverting logic functional unit of the second-stage inverter includes a seventh resistor R7 and a plurality of tenth D tubes connected in sequence; the load unit of the second-stage inverter includes an eleventh D tube and an eighth resistor R8; The source of the first tenth D tube is connected to the drain of the next tenth D tube, and the drain of the first tenth D tube is respectively connected to one end of the resistor R8, the gate of the eleventh D tube, and the third target level output terminal V out2 The source of the last tenth D tube is connected to one end of the seventh resistor R7 as the sixth node f, the other end of the seventh resistor R7 is connected to the -5V power supply, and the gates of all the tenth D tubes are connected to the fifth node e; the other end of the eighth resistor R8 is connected to the source of the eleventh D tube, and the drain of the eleventh D tube is grounded.

6. The TTL level conversion circuit according to claim 5, characterized in that: The power supply branch of the second-stage inverter includes a ninth D tube and a sixth resistor R6, the fifth node e is connected to the drain of the ninth D tube, the source of the ninth D tube is connected to one end of the sixth resistor R6, and the other end of the sixth resistor R6 is respectively connected to the -5V power supply and the gate of the ninth D tube.

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