A high-precision second pulse synchronization method

Abstract

The invention discloses a high-precision second pulse synchronization method. In the master node, the clock module MMCM inside the FPGA is used to input the reference clock of 10MHz and output the reference clock; the phase relationship between the reference clock and the PPS is automatically detected by the internal logic of the FPGA; and the output phase of the clock module MMCM is adjusted by feedback so that the rising edge of the reference clock and the rising edge of the PPS are aligned to achieve second pulse synchronization. The method can achieve the locking of the master node reference clock of the clock synchronization network with 10MHz by only using the internal resources of the FPGA, and align the rising edge of the reference clock with the rising edge of the PPS, thereby solving the multi-phase problem of the reference clock and the PPS, so as to synchronize and distribute the PPS and 10MHz.

Description

Technical Field

[0001] The invention relates to the technical field of timing synchronization, and in particular to a high-precision second pulse synchronization method. Background Art

[0002] A timing system is a specialized network that provides a common concept of time to each node in a distributed system, that is, the clocks of all nodes jump at the same rate and show the same time at a certain moment. Accurate time synchronization is the primary requirement for many real-time applications, such as distributed control systems, industrial automation, and data acquisition systems, which all need to perform operations under very strict time constraints. Time synchronization is also very necessary in systems composed of large physical experimental devices. Each timing system requires an initial clock source as the reference clock for each node in the system. In most systems, the reference clock source needs to meet the requirements of long-term stability and can be traced back to the same time scale, such as UTC (Coordinated Universal Time) Coordinated World Time or TAI (International Atomic Time). Among them, clock sources such as atomic clocks and GPS disciplined oscillators are very widely used initial clock sources.

[0003] Atomic clocks calculate time by measuring the characteristic resonance frequency of atoms excited by laser or microwave radio frequency signals. They are one of the most stable time references currently available. Generally speaking, the time information of cesium atomic clocks is contained in the 10 MHz clock, PPS (Pulse Per Second) and UTC time code it outputs. Another way to obtain accurate time is to use a GPS transmitter to obtain the time information of the atomic clock on the GPS satellite. After receiving the code sequence sent by the satellite, the transmitter calculates the offset based on its own geographical location, sends it to the server to adjust the frequency and offset of the disciplined oscillator, and outputs the 10 MHz clock, PPS and UTC time. Among them, PPS is in the 10MHz clock domain, generated by 10MHz frequency division, and is used to indicate the rising edge of a certain second of UTC time. In the field of clock synchronization and distribution, PPS and 10MHz clocks are distributed through clock synchronization systems, such as the WR (White Rabbit) system. The master node of the synchronization system receives PPS and 10MHz signals, and then distributes them to each sub-node through multi-port distribution. Finally, the sub-node outputs PPS and 10MHz signals. The final system needs to meet the requirement that the PPS and 10MHz signals output by each sub-node are frequency locked with the PPS and 10MHz received by the master node respectively, and the rising edges are aligned, thus completing the synchronization and distribution of PPS and 10MHz.

[0004] The synchronization and distribution of PPS and 10MHz clocks are based on the reference clock synchronized by the clock synchronization distribution system (such as the WR system). Since the reference clock frequency is not necessarily an integer multiple of 10MHz, the rising edge of the master node reference clock is not necessarily aligned with the rising edge of PPS, resulting in the PPS signal output in the sub-node reference clock domain and the master node PPS phase being not fixed. In order to solve the multi-phase problem of the master node reference clock and PPS, the WR system uses SoftPLL to adjust the rising edge of the reference clock and the rising edge of PPS when the reference clock (62.5MHz and 125MHz) and 10MHz are locked. However, since SoftPLL requires the support of two external DACs and two VCXOs, the PI control algorithm for adjusting the frequency and phase is complex, and it runs in the soft-core CPU inside the field programmable gate array (FPGA), which is more troublesome to implement and difficult to develop. Summary of the invention

[0005] The purpose of the present invention is to provide a high-precision second pulse synchronization method, which can realize the clock synchronization network master node reference clock and 10MHz locking by only using the internal resources of FPGA, and align the reference clock rising edge and PPS rising edge, solving the multi-phase problem of the reference clock and PPS, so as to synchronize and distribute PPS and 10MHz.

[0006] The objective of the present invention is achieved through the following technical solutions:

[0007] A high-precision second pulse synchronization method, the method comprising:

[0008] Step 1: In the master node, the clock module MMCM inside the field programmable gate array FPGA is used to input a reference clock of 10 MHz and output a reference clock;

[0009] Step 2: Automatically detect the phase relationship between the reference clock and the pulse per second (PPS) through the internal logic of the FPGA;

[0010] Step 3: Feedback and adjust the output phase of the clock module MMCM so that the rising edge of the reference clock is aligned with the rising edge of the PPS to achieve second pulse synchronization.

[0011] It can be seen from the technical solution provided by the present invention that the above method can realize the locking of the reference clock and 10MHz of the clock synchronization network master node only by utilizing the internal resources of FPGA, and align the rising edge of the reference clock and the rising edge of PPS, thereby solving the multi-phase problem of the reference clock and PPS, facilitating the synchronization and distribution of PPS and 10MHz, reducing the complexity of synchronizing the PPS and 10MHz clock of the master node, improving the system compatibility of the master node, and reducing the dependence on external hardware. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0013] Figure 1 A schematic flow chart of a high-precision second pulse synchronization method provided by an embodiment of the present invention;

[0014] Figure 2 This is the pulse sequence timing diagram of the example 62.5MHz detecting 10MHz and PPS in the present invention;

[0015] Figure 3 This is a timing diagram of four phase relationships between 62.5MHz and PPS in the example of the present invention. DETAILED DESCRIPTION

[0016] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments, which does not constitute a limitation of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] like Figure 1 FIG. 1 is a flow chart of a high-precision second pulse synchronization method provided by an embodiment of the present invention, wherein the method comprises:

[0018] Step 1: In the master node, the clock module MMCM (Mixed-Mode Clock Manager) inside the field programmable gate array FPGA is used to output the reference clock with 10 MHz as the input reference clock;

[0019] In this step, assuming that the reference clock frequency of the clock synchronization network is F, the input 10MHz clock is multiplied to F by using the clock module MMCM inside the FPGA at the master node, wherein the clock module MMCM is set to zero delay mode ZeroDelay;

[0020] Define GCD(10,F) as the greatest common divisor of the 10MHz clock and F. For a 10MHz clock, the ratio of its rising edge to the reference clock is GCD(10,F) / 10.

[0021] Similarly, for the reference clock F, the ratio of its rising edge to the 10MHz clock is GCD(10,F) / F.

[0022] Step 2: The phase relationship between the reference clock and the pulse per second (PPS) is automatically detected by the internal logic of the FPGA.

[0023] In this step, the rising edge of the 10MHz clock is first detected using the reference clock F to obtain the rising edge pulse of the 10MHz clock. The interval of the rising edge pulse is based on the period of the reference clock F. There are two results: and , that is, the rounding down and rounding up of F / 10, recorded as in ;

[0024] Calculated based on the time when the rising edges coincide, the intervals of the pulse sequences are , where n is 10 / GCD(10,F)–1, indicating that there are n rising edge pulses and the interval between the next pulse is , the interval between one pulse and the next pulse is ;

[0025] Then, a counter cnt1 is constructed in the reference clock domain, and the rising edge pulse of the 10MHz clock is used as the reset signal. The maximum count value of the counter cnt1 is the interval between two rising edge pulses of the 10MHz clock, that is, and ;

[0026] Then, the reference clock F is used to detect the rising edge of PPS to obtain the rising edge pulse of PPS; wherein, PPS is in the 10MHz clock domain, generated by 10MHz frequency division, and is used to indicate the rising edge of a certain second of the coordinated universal time UTC;

[0027] Another counter cnt2 is constructed in the reference clock domain, and the rising edge pulse of PPS is used as the reset signal. Whenever the value of counter cnt1 is When the counter cnt2 is detected to be Stop when , and record the value of counter cnt2 at this time as m;

[0028] The phase relationship between the rising edge of the reference clock F and the rising edge of PPS is calculated by the following formula: for:

[0029] Among them, GCD (10, F) is the greatest common divisor of the 10 MHz clock and the reference clock F.

[0030] Step 3: Feedback and adjust the output phase of the clock module MMCM so that the rising edge of the reference clock is aligned with the rising edge of the PPS to achieve second pulse synchronization.

[0031] In this step, the interpolation fine phase adjustment mode of the clock module MMCM is used to adjust the phase offset of the reference clock F to align the rising edge of the reference clock F with the rising edge of the PPS.

[0032] Among them, the reference clock and PPS signal of the master and slave nodes are synchronized using conventional methods. Specifically: the synchronization of the reference clock adopts the WR PTP protocol. The basic idea is to measure the round-trip delay of the master and slave nodes, and obtain the downlink delay through a certain distribution ratio. The slave node then adjusts the phase and timestamp to compensate for the downlink delay, thereby synchronizing the reference clocks of the master and slave nodes; after the reference clock is synchronized, the PPS is output in the reference clock domain at the whole second of the slave node to achieve PPS synchronization of the master and slave nodes.

[0033] It is worth noting that the contents not described in detail in the embodiments of the present invention belong to the prior art known to professional and technical personnel in the field.

[0034] The following is an example of the process of the method of the present invention. In this example, the reference clock of the master node uses the same 62.5MHz as the WR, and receives the PPS and 10MHz signals output by the external atomic clock. The specific process is:

[0035] Step 1: Assume that the reference clock of WR is 62.5MHz, use MMCM to multiply 10MHz to 62.5MHz, and set MMCM to Zero Delay mode. Assume GCD(10, 62.5) = 2.5, then for 10MHz, the ratio of the rising edge to the 62.5MHz clock alignment is 2.5 / 10 = 1 / 4, and for 62.5MHz, the ratio of the rising edge to the 10MHz signal alignment is 2.5 / 62.5 = 1 / 25.

[0036] Step 2: Use the 62.5MHz reference clock to detect the rising edge of the 10MHz signal and obtain a series of 10MHz rising edge pulses, such as Figure 2 The figure shows the pulse sequence timing diagram of 62.5MHz detecting 10MHz and PPS in the example of the present invention. The pulse interval is based on the cycle of 62.5MHz. There are two cases, namely ,in The pulse sequence interval is 6, 6, 6, 7, and then it keeps looping.

[0037] Step 3: Construct counter cnt1 in the 62.5MHz reference clock domain, and use a 10MHz rising edge pulse as the reset signal. The counter count range of counter cnt1 is 0-5, 0-5, 0-5, 0-6, and then repeat this cycle.

[0038] Step 4: Reference Figure 2 , use 62.5MHz reference clock to detect the PPS rising edge and obtain the PPS rising edge pulse signal.

[0039] Step 5: Construct another counter cnt2 in the 62.5MHz reference clock domain, and use the rising edge of PPS as the reset signal. Whenever counter cnt1 counts to 5, cnt2 adds 1, and stops when cnt1 is detected to be 6. The counter value at this time is recorded as m. In this embodiment, m=2.

[0040] Step 6: Calculate the phase difference between the reference clock rising edge and the PPS rising edge:

[0041]

[0042] like Figure 3 The following are the timing diagrams of the four phase relationships between 62.5MHz and PPS in the example of the present invention, refer to Figure 3 :

[0043] The first case is that the rising edges of 62.5MHz and PPS are aligned; the second case is that the phase of 62.5MHz leads PPS by 90 degrees; the third case is that the phase of 62.5MHz leads PPS by 180 degrees; and the fourth case is that the phase of 62.5MHz leads PPS by 270 degrees.

[0044] Step 7: Use the interpolation fine phase adjustment mode of the MMCM to adjust the reference clock offset by 8 ns. At this point, the 62.5 MHz reference clock and the PPS rising edge are aligned.

[0045] Step 8: The 62.5MHz and PPS signals of the master and slave nodes can be synchronized using the WR network.

[0046] In summary, the method described in the embodiment of the present invention has the following advantages:

[0047] 1. The principle of this method is simple. Compared with traditional methods such as WR's SoftPLL solution, it reduces the complexity of the logic code and is easy to understand and write;

[0048] 2. This method can realize the function of aligning the reference clock and the rising edge of PPS inside the FPGA, without the need for complex circuit support, and is flexible in application and easy for hardware integration;

[0049] 3. This method uses MMCM to adjust the reference clock phase. The reference clock phase offset can be manually added as needed to compensate for the delay of the PPS signal on the transmission cable.

[0050] In addition, a person skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be implemented by instructing related hardware through a program, and the corresponding program can be stored in a computer-readable storage medium. The above-mentioned storage medium can be a read-only memory, a disk or an optical disk, etc.

[0051] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims. The information disclosed in the background technology section of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or in any form that the information constitutes prior art known to those skilled in the art.

Claims

1. A high-precision second pulse synchronization method, It is characterized in that The method comprises: Step 1: In the master node, the clock module MMCM inside the field programmable gate array FPGA is used to input a reference clock of 10 MHz and output a reference clock; Step 2: Automatically detect the phase relationship between the reference clock and the pulse per second (PPS) through the internal logic of the FPGA; The process of step 2 is specifically as follows: First, the reference clock F is used to detect the rising edge of the 10MHz clock to obtain the rising edge pulse of the 10MHz clock. The interval of the rising edge pulse is based on the period of the reference clock F. There are two results: and , that is, the rounding down and rounding up of F / 10, recorded as in ; Calculated based on the time when the rising edges coincide, the intervals of the pulse sequences are , where n is 10 / GCD(10,F)–1, indicating that there are n rising edge pulses and the interval between the next pulse is , the interval between one pulse and the next pulse is ; Then, a counter cnt1 is constructed in the reference clock domain, and the rising edge pulse of the 10MHz clock is used as the reset signal. The maximum count value of the counter cnt1 is the interval between two rising edge pulses of the 10MHz clock, that is, and ; Then, the reference clock F is used to detect the rising edge of PPS to obtain the rising edge pulse of PPS; Another counter cnt2 is constructed in the reference clock domain, and the rising edge pulse of PPS is used as the reset signal. Whenever the value of counter cnt1 is When the counter cnt2 is detected to be Stop when , and record the value of counter cnt2 at this time as m; The phase relationship between the rising edge of the reference clock F and the rising edge of PPS is calculated by the following formula: for: Among them, GCD (10, F) is the greatest common divisor of the 10MHz clock and the reference clock F; Step 3: Feedback and adjust the output phase of the clock module MMCM so that the rising edge of the reference clock is aligned with the rising edge of the PPS to achieve second pulse synchronization.

2. According to the high-precision second pulse synchronization method of claim 1, It is characterized in that In step 1, assuming that the reference clock frequency of the clock synchronization network is F, the input 10MHz clock is multiplied to F by using the clock module MMCM inside the FPGA at the master node, wherein the clock module MMCM is set to zero delay mode Zero Delay; Define GCD(10,F) as the greatest common divisor of the 10MHz clock and F. For a 10MHz clock, the ratio of its rising edge to the reference clock is GCD(10,F) / 10. Similarly, for the reference clock F, the ratio of its rising edge to the 10MHz clock is GCD(10,F) / F.

3. According to the high-precision second pulse synchronization method of claim 1, It is characterized in that In step 3, The interpolation fine phase adjustment mode of the clock module MMCM is used to adjust the phase offset of the reference clock F to align the rising edge of the reference clock F with the rising edge of the PPS. Among them, the reference clock and PPS signal of the master and slave nodes are synchronized using conventional methods. Specifically: the synchronization of the reference clock adopts the WR PTP protocol, which is to measure the round-trip delay of the master and slave nodes, and obtain the downlink delay through a certain distribution ratio. The slave node then adjusts the phase and timestamp to compensate for the downlink delay, thereby synchronizing the reference clocks of the master and slave nodes; after the reference clock is synchronized, the PPS is output in the reference clock domain at the whole second of the slave node to achieve PPS synchronization of the master and slave nodes.

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