A display control circuit

Abstract

This utility model relates to the field of IoT intelligent control technology, and in particular to a display control circuit applied to a smart cloud box device. It includes a CPU module, a WIFI / Bluetooth module, a display module, an audio codec module, an audio amplifier module, a transceiver module, a power supply module, and a step-down module. The WIFI / Bluetooth module, display module, audio codec module, audio amplifier module, transceiver module, and step-down module are all electrically connected to the CPU module. The CPU module uses an RK3399 processor chip, the display module uses a TC358772XBG display bridge chip, and the step-down module is also electrically connected to the power supply module. Through the organic combination of multiple modules, this display control circuit comprehensively solves the problem of insufficient display functionality in smart cloud boxes, improving display effect, response speed, and system compatibility.

Description

Technical Field

[0001] This utility model relates to the field of Internet of Things (IoT) intelligent control technology, and in particular to a display control circuit. Background Technology

[0002] The smart cloud box is an intelligent device integrating data acquisition, processing, and communication functions, enabling remote management and intelligent control of devices. With the rapid development of the Internet of Things (IoT) and smart homes, the smart cloud box plays an increasingly important role as a key node connecting various smart devices and cloud platforms. At the same time, as its functions continue to expand and application scenarios become increasingly diverse, user demands for smart cloud boxes are becoming more varied and complex. Especially in terms of display functionality, the smart cloud box not only needs to support multiple display interfaces and high-resolution output, but also must ensure display stability and low power consumption to adapt to the needs of different environments and applications. However, existing smart cloud box display modules still have shortcomings in terms of image clarity, response speed, and multi-interface compatibility, affecting the overall performance of the device and the user experience. Utility Model Content

[0003] In view of this, the present invention proposes a display control circuit, which aims to solve the problem of insufficient display function of existing smart cloud boxes.

[0004] This utility model proposes a display control circuit for use in a smart cloud box device, comprising a CPU module, a WIFI / Bluetooth module, a display module, an audio codec module, an audio amplifier module, a transceiver module, a power supply module, and a step-down module; wherein, the WIFI / Bluetooth module, the display module, the audio codec module, the audio amplifier module, the transceiver module, and the step-down module are all electrically connected to the CPU module, the CPU module uses an RK3399 processor chip, the display module uses a TC358772XBG display bridge chip, and the step-down module is also electrically connected to the power supply module.

[0005] Furthermore, the WIFI Bluetooth module includes an AP6275P type WIFI Bluetooth chip U6300, antenna ANT6300, antenna ANT6301, capacitors C6300, C6301, C6302, C6303, C6305, C6306, C6313, iron core inductor L6300, iron core inductor L6301, capacitors C6318, C6321, C6320, C6319, C6316, C6317, resistors R6305, C6315, C6314, R6302, C6311, C6312, C6340, C6341, C6307, C6308, C6304, C4, and antenna ANT6302;

[0006] Specifically, pins 1, 3, 4, 5, 6, 7, 8, 10, 11, 23, 27, 30, 32, and 39 of the WIFI Bluetooth chip U6300 are all grounded. Pin 2 of the WIFI Bluetooth chip U6300 is connected to one end of capacitor C6306 and one end of capacitor C6303. The other end of capacitor C6303 is connected to one end of capacitor C6301 and antenna ANT6301. The other ends of capacitors C6306 and C6301 are both grounded. Pin 9 of the WIFI Bluetooth chip U6300 is connected to one end of capacitor C6305 and one end of capacitor C6302. The other end of capacitor C6302 is connected to one end of capacitor C6300 and antenna ANT6300. The other ends of capacitors C6300 and C6305 are both grounded.

[0007] Pin 12 of the U6300 Wi-Fi / Bluetooth chip is connected to the PCIE20_PERSTn_1V8 signal terminal; pin 13 of the U6300 Wi-Fi / Bluetooth chip is connected to the XIN_WIFI signal terminal; pin 14 of the U6300 Wi-Fi / Bluetooth chip is connected to the XOUT_WIFI signal terminal; pin 15 of the U6300 Wi-Fi / Bluetooth chip is connected to the WIFI_REG_ON_H signal terminal; pin 16 of the U6300 Wi-Fi / Bluetooth chip is connected to the WIFI_WAKE_HOST_H signal terminal; and pin 17 of the U6300 Wi-Fi / Bluetooth chip is connected to the PCIE20_PERSTn_1V8 signal terminal. Pins 19 and 18 are both left floating. Pin 19 of the U6300 WIFI Bluetooth chip is connected to the I2S2_SDI_M0_BT signal terminal. Pin 20 of the U6300 WIFI Bluetooth chip is connected to the I2S2_SDO_M0_BT signal terminal. Pin 21 of the U6300 WIFI Bluetooth chip is connected to the I2S2_LRCK_M0_BT signal terminal. Pin 22 of the U6300 WIFI Bluetooth chip is connected to the I2S2_SCLK_M0_BT signal terminal. Pin 24 of the U6300 WIFI Bluetooth chip is connected to the PCIE20_WAKEn_1V8 signal terminal.

[0008] Pin 26 of the Wi-Fi Bluetooth chip U6300 is connected to one end of the iron-core inductor L6300. The other end of the iron-core inductor L6300 is connected to pin 25 of the Wi-Fi Bluetooth chip U6300 and one end of capacitor C6313. Pin 28 of the Wi-Fi Bluetooth chip U6300 is connected to one end of the iron-core inductor L6301. The other end of the iron-core inductor L6301 is connected to pin 29 of the Wi-Fi Bluetooth chip U6300 and one end of capacitor C6318. Pin 31 of the Wi-Fi Bluetooth chip U6300 is connected to the 32KOUT_WIFI signal terminal and one end of capacitor C6321. Pin 33 of the Wi-Fi Bluetooth chip U6300 is connected to the PCIE20_1_REFCLKN signal terminal through capacitor C6320. Pin 35 of the Wi-Fi Bluetooth chip U6300 is connected to... Capacitor C6319 is connected to the PCIE20_1_REFCLKP signal terminal. Pin 34 of the WIFI Bluetooth chip U6300 is connected to one end of capacitor C6316, one end of capacitor C6317, one end of resistor R6305, and the VCCIO_WL signal terminal. The other end of resistor R6305 is connected to the VCC_1V8_S3 signal terminal. Pin 36 of the WIFI Bluetooth chip U6300 is connected to one end of capacitor C6315, one end of capacitor C6314, one end of resistor R6302, and the VCC3V3_PCIEWL_VBAT signal terminal. The other end of resistor R6302 is connected to the VCC_3V3_S3 signal terminal. The other ends of capacitors C6313, C6318, C6321, C6316, and C6317 are all grounded.

[0009] Pin 37 of the U6300 Wi-Fi / Bluetooth chip is connected to the PCIE20_CLKREQn_1V8 signal terminal; pin 38 of the U6300 Wi-Fi / Bluetooth chip is connected to the BT_REG_ON_H signal terminal; pin 40 of the U6300 Wi-Fi / Bluetooth chip is connected to the UART9_RX_M0_BT signal terminal; and pin 41 of the U6300 Wi-Fi / Bluetooth chip is connected to the UART9_TX_M0_BT signal terminal. The U6300 Wi-Fi / Bluetooth chip... Pin 42 of the WIFI Bluetooth chip U6300 is connected to the UART9_CTSn_M0_BT signal terminal. Pin 43 of the WIFI Bluetooth chip U6300 is connected to the UART9_RTSn_M0_BT signal terminal. Pin 44 of the WIFI Bluetooth chip U6300 is connected to the PCIE20_1_TXN / SATA30_1_TXN signal terminal through capacitor C6341. Pin 45 of the WIFI Bluetooth chip U6300 is connected to the PCIE20_1_TXP signal terminal through capacitor C6340. The / SATA30_1_TXP signal terminal is connected to pin 46 of the U6300 Wi-Fi / Bluetooth chip via capacitor C6312. Pin 47 of the U6300 Wi-Fi / Bluetooth chip is connected to the PCIE20_1_RXN / SATA30_1_RXN signal terminal via capacitor C6311. Pin 49 of the U6300 Wi-Fi / Bluetooth chip is connected to the HOST_WAKE_BT_H signal terminal. Pin 50 of the WIFI Bluetooth chip U6300 is connected to the BT_WAKE_HOST_H signal terminal. Pin 48 of the WIFI Bluetooth chip U6300 is connected to one end of capacitor C6308 and one end of capacitor C6307. The other end of capacitor C6307 is connected to one end of capacitor C6304, one end of capacitor C4 and antenna ANT6302. The other end of capacitor C4 is connected to the TP1 test terminal. The other ends of capacitors C6308 and C6304 are both grounded.

[0010] Furthermore, the display module includes a TC358772XBG type display bridge chip U5700, resistors R5700, R5701, R5702, R5703, R5704 and R5705.

[0011] Specifically, pin C3 of the display bridge chip U5700 is connected to the VCC_1V8_S0 signal terminal via resistor R5700; pin C4 of the display bridge chip U5700 is left floating; pin D2 of the display bridge chip U5700 is connected to the TP5701 test terminal; pin D3 of the display bridge chip U5700 is connected to the TP5700 test terminal; pin E3 of the display bridge chip U5700 is connected to the TP5702 test terminal; and pin D4 of the display bridge chip U5700 is connected to the LCD_RST_L1 signal terminal. Pin D1 of the display bridge chip U5700 is connected to the REFCLK signal terminal. Pin G1 of the display bridge chip U5700 is connected to the VCC_1V8_S0 signal terminal through resistors R5703 and R5702. Pin H1 of the display bridge chip U5700 is connected to the VCC_1V8_S0 signal terminal through resistors R5704 and R5701. Pin D5 of the display bridge chip U5700 is grounded through resistor R5705. Pin G2 of the display bridge chip U5700 is connected to the MIPI_TX0_D0P1 signal terminal. Pin H2 is connected to the MIPI_TX0_D0N1 signal terminal. Pin G3 of the display bridge chip U5700 is connected to the MIPI_TX0_D1P1 signal terminal. Pin H3 of the display bridge chip U5700 is connected to the MIPI_TX0_D1N1 signal terminal. Pin G4 of the display bridge chip U5700 is connected to the MIPI_TX0_CLKP1 signal terminal. Pin H4 of the display bridge chip U5700 is connected to the MIPI_TX0_CLKN1 signal terminal. Pin G5 of the display bridge chip U5700 is connected to the MIPI_TX0_D1P1 signal terminal. At the 2P1 signal terminal, pin H5 of the display bridge chip U5700 is connected to the MIPI_TX0_D2N1 signal terminal, pin G6 of the display bridge chip U5700 is connected to the MIPI_TX0_D3P1 signal terminal, pin H6 of the display bridge chip U5700 is connected to the MIPI_TX0_D3N1 signal terminal, and pins A1, A7, A8, C1, C6, E1, E5, E6, F1, F4, F5, and H8 of the display bridge chip U5700 are all grounded;

[0012] The display bridge chip U5700 has its B2 pin connected to the LVDS1_D0P signal terminal, its A2 pin connected to the LVDS1_D0N signal terminal, its B3 pin connected to the LVDS1_D1P signal terminal, its A3 pin connected to the LVDS1_D1N signal terminal, its B4 pin connected to the LVDS1_D2P signal terminal, and its A4 pin connected to the LVDS1_D2N signal terminal. Pin B5 of the display bridge chip U5700 is connected to the LVDS1_CLK1P signal terminal; pin A5 of the display bridge chip U5700 is connected to the LVDS1_CLK1N signal terminal; pin B6 of the display bridge chip U5700 is connected to the LVDS1_D3P signal terminal; pin A6 of the display bridge chip U5700 is connected to the LVDS1_D3N signal terminal; pin C7 of the display bridge chip U5700 is connected to the LVDS0_D0P signal terminal; and pin C8 of the display bridge chip U5700 is connected to the LVDS0_D0N signal terminal. The display bridge chip U5700 has its D7 pin connected to the LVDS0_D1P signal terminal, its D8 pin connected to the LVDS0_D1N signal terminal, its E7 pin connected to the LVDS0_D2P signal terminal, its E8 pin connected to the LVDS0_D2N signal terminal, its F7 pin connected to the LVDS0_CLK0P signal terminal, and its F8 pin connected to the LVDS0_CLK signal terminal. At the ON signal terminal, pin G7 of the display bridge chip U5700 is connected to the LVDS0_D3P signal terminal, pin G8 of the display bridge chip U5700 is connected to the LVDS0_D3P signal terminal, pins F3, F6, B8, B1, E2, and E4 of the display bridge chip U5700 are all connected to the VDD1V2_LCD signal terminal, and pins D6, H7, B7, C5, C2, and F2 of the display bridge chip U5700 are all connected to the VCC_1V8_S0 signal terminal.

[0013] Furthermore, the power module includes a WC-PD25C012J type power chip U9009 and a polarized capacitor AC42; wherein, the first pin of the power chip U9009 is connected to the VIN+ signal terminal, the second pin of the power chip U9009 is connected to the VIN- signal terminal, the third and sixth pins of the power chip U9009 are both floating, the fourth and seventh pins of the power chip U9009 are both grounded, the fifth pin of the power chip U9009 is connected to the POE_12V signal terminal and the positive terminal of the polarized capacitor AC42 respectively, and the negative terminal of the polarized capacitor AC42 is grounded.

[0014] Furthermore, the step-down module includes an MP8759 type step-down chip U21057, a diode D9018, capacitors C217075, C217074, and C217073, resistors R2101, R2105, C217079, C217078, R2107, R89777, R89779, and R89780, a capacitor CC226, an iron-core inductor L21053, resistors R2102 and R2104, capacitors C2105, R2103, and R2106, polarized capacitors CC217, CC218, CC219, and CC220, and a resistor RR897.

[0015] In this configuration, pin 1 of the buck converter U21057 is connected to one end of resistor R2101, one end of capacitor C217073, one end of capacitor C217074, one end of capacitor C217075, the VCC12V_DCIN signal terminal, and the negative terminal of diode D9018. Pin 12 of the buck converter U21057 is connected to the other end of resistor R2101, one end of resistor R2105, and one end of capacitor C217079. Pin 4 of the buck converter U21057 is left floating. Pin 9 of the buck converter chip U21057 is connected to one end of capacitor C217078, one end of resistor R2107, and one end of resistor R89777. Pin 3 of the buck converter chip U21057 is connected to the other end of resistor R2107. Pin 6 of the buck converter chip U21057 is connected to the other end of resistor R89777 and one end of resistor R89779. Pins 2 and 10 of the buck converter chip U21057 are both grounded. Pin 5 of the buck converter chip U21057 is connected to... Connect one end of capacitor C2112 to the VCC5V0_SYS signal terminal. Pin 7 of the step-down chip U21057 is connected to one end of resistor R2102, one end of the iron-core inductor L21053, and one end of capacitor CC226. The other end of capacitor CC226 is connected to pin 8 of the step-down chip U21057 via resistor R89780. The other end of resistor R2102 is connected to one end of resistor R2104 and one end of capacitor C2105. The other end of resistor R2104 is connected to the step-down chip... Pin 11 of the voltage regulator chip U21057, one end of resistor R2103 and one end of resistor R2106, the other end of resistor R2103 is connected to the other end of iron core inductor L21053, the other end of capacitor C2105, the positive terminal of polarized capacitor CC217, one end of capacitor CC218, one end of capacitor CC219, one end of capacitor CC220 and one end of resistor RR897, the other end of resistor RR897 is connected to the VCC5V0_SYS signal terminal and the VCC5V0_USB signal terminal respectively;

[0016] The positive terminal of diode D9018, the other end of capacitor C217075, the other end of capacitor C217074, the other end of capacitor C217073, the other end of resistor R2105, the other end of capacitor C217079, the other end of capacitor C217078, the other end of resistor R89779, the other end of capacitor C2112, the other end of resistor R2106, the negative terminal of polarized capacitor CC217, the other end of capacitor CC218, the other end of capacitor CC219, and the other end of capacitor CC220 are all grounded.

[0017] Furthermore, the audio amplifier module includes an AD52058 type audio amplifier chip U7, resistors 10R57, 6R38, and AR1, capacitors 10C12, 10C11, 10C3, 10C1, and 10C2, resistors 10R2, 10C4, 10R1, 10R7, 10C25, 6R39, and AR2, capacitors 10C14, 10C27, 10C28, 10R58, and 10C87. 86. Capacitor 10C33, Capacitor 10C24, Capacitor 10C30, Inductor 10L3, Capacitor 10C31, Capacitor 10C32, WF-200-2 type speaker terminal 10J2, Inductor 10L4, Capacitor 10C29, Capacitor 10C7, Inductor 10L1, Capacitor 10C9, Capacitor 10C10, WF-200-2 type speaker terminal 10J1, Inductor 10L2, Capacitor 10C8, Capacitor 10C6, Capacitor 10C5, Capacitor 10C84 and Capacitor 10C85;

[0018] Specifically, pin 1 of the audio amplifier chip U7 is connected to pin 2 of the audio amplifier chip U7 and one end of resistor 10R57, while the other end of resistor 10R57 is connected to the SPK_CTL_H11 signal terminal. Pin 3 of the audio amplifier chip U7 is connected to one end of capacitor 10C1, pin 4 of the audio amplifier chip U7 is connected to one end of capacitor 10C2, pins 5, 6, and 13 of the audio amplifier chip U7 are all left floating, and pin 7 of the audio amplifier chip U7 is connected to one end of resistor 10R2. One end of capacitor 10C11 and one end of capacitor 10C3 are connected to the PVDD signal terminal. The other end of resistor 10R2 is connected to the PVDD signal terminal. Pin 8 of the audio amplifier chip U7 is connected to one end of capacitor 10C4, one end of resistor 10R7, one end of capacitor 10C25, the other end of capacitor 10C11, the other end of capacitor 10C3, and the AGND_AUDIO signal terminal. Pin 9 of the audio amplifier chip U7 is connected to the other end of capacitor 10C4 and one end of resistor 10R1. The other end of resistor 10R1 is connected to the PVDD signal terminal. The other end of capacitor 10R7, the other end of capacitor 10C25, and pin 10 of audio amplifier chip U7 are connected. The other end of capacitor 10C1 is connected to one end of capacitor 10C12, one end of resistor AR1, and one end of resistor 6R38. The other end of resistor 6R38 is connected to the HPL1 signal terminal. The other end of capacitor 10C2 is connected to the other end of capacitor 10C12, the other end of resistor AR1, and the AGND_AUDIO signal terminal. Pin 11 of audio amplifier chip U7 is connected to AGND_AUDI through capacitor 10C27. At the O signal terminal, pin 12 of the audio amplifier chip U7 is connected to one end of capacitor 10C28, pin 14 of the audio amplifier chip U7 is connected to the AGND_AUDIO signal terminal through resistor 10R58, pin 29 of the audio amplifier chip U7 is connected to the AGND_AUDIO signal terminal, the other end of capacitor 10C28 is connected to the AGND_AUDIO signal terminal through capacitor 10C14, the AGND_AUDIO signal terminal through capacitor AR2, and the HPR1 signal terminal through resistor 6R39;

[0019] Pin 28 of the audio amplifier chip U7 is connected to the PVDD signal terminal, pin 27 of the audio amplifier chip U7, one end of capacitor 10C87, one end of capacitor 10C86, one end of capacitor 10C33, and one end of capacitor 10C24. The other ends of capacitors 10C87, 10C86, 10C33, and 10C24 are all connected to the AGND_AUDIO signal terminal. Pin 26 of the audio amplifier chip U7 is connected to one end of capacitor 10C30. The other end of capacitor 10C30 is connected to pin 25 of the audio amplifier chip U7 and one end of inductor 10L3. Pin 2... Pin 4 is connected to the AGND_AUDIO signal terminal, one end of capacitor 10C31, and one end of capacitor 10C32, respectively. Pin 23 of the audio amplifier chip U7 is connected to one end of capacitor 10C29 and one end of inductor 10L4, respectively. The other end of inductor 10L4 is connected to the other end of capacitor 10C32 and pin 1 of speaker terminal 10J2, pin 2 of speaker terminal 10J2 is connected to the other end of inductor 10L3 and the other end of capacitor 10C31, pins 3 and 4 of speaker terminal 10J2 are grounded, and the other end of capacitor 10C29 is connected to pin 22 of the audio amplifier chip U7. Pin 21 of U7 is connected to one end of capacitor 10C7. Pin 20 of the audio amplifier chip U7 is connected to the other end of capacitor 10C7, one end of inductor 10L1, and the SPK1_1N signal terminal. Pin 19 of the audio amplifier chip U7 is connected to the AGND_AUDIO signal terminal, one end of capacitor 10C9, and one end of capacitor 10C10. Pin 18 of the audio amplifier chip U7 is connected to one end of capacitor 10C8, one end of inductor 10L2, and the SPK1_1P signal terminal. The other end of inductor 10L2 is connected to the other end of capacitor 10C10 and pin 1 of speaker terminal 10J1. Pin 2 of 1 is connected to the other end of inductor 10L1 and capacitor 10C9 respectively. Pins 3 and 4 of speaker terminal 10J1 are grounded. Pin 17 of audio amplifier chip U7 is connected to the other end of capacitor 10C8. Pin 16 of audio amplifier chip U7 is connected to pin 15 of audio amplifier chip U7, one end of capacitor 10C6, one end of capacitor 10C5, one end of capacitor 10C84, one end of capacitor 10C85 and PVDD signal respectively. The other ends of capacitors 10C6, 10C5, 10C84 and 10C85 are all connected to the AGND_AUDIO signal terminal.

[0020] Furthermore, the audio codec module includes an ES8388 type audio codec chip 7U1, resistors 10R50 and R244, capacitors C100 and C99, resistors R245, 10R49, 10R51, RR692, R89601, RR693, capacitors C101, C102, 6C89, 6C90, 6C84, 6C85, C103, and C104. Resistor R246, capacitor 10C78, capacitor 10C79, capacitor 10C80, capacitor 10C81, resistor R89627, capacitor C9651, resistor R89626, capacitor 6C100, capacitor 6C102, capacitor 6C103, capacitor 6C82, capacitor 6C81, capacitor 6C83, resistor R253, capacitor C107, resistor R252, resistor 6R76, resistor 6R77, capacitor C105, capacitor C5, resistor R5 and resistor R6;

[0021] Specifically, pin 1 of the audio codec chip 7U1 is connected to the I2S_MCLK signal terminal via resistor 10R50. Pin 2 of the audio codec chip 7U1 is connected to pin 3 of the audio codec chip 7U1, one end of resistor R245, one end of capacitor C99, and one end of resistor R244. The other end of resistor R244 is connected to the VCC_1V8_S0 signal terminal and one end of capacitor C100. The other end of capacitor C100 is grounded. Pin 4 of the audio codec chip 7U1 is connected to the other end of capacitor C99, the other end of resistor R245, and ground. Pin 5 of the audio codec chip 7U1 is connected to the I2S0_SCLK signal terminal via resistor 10R49. At the signal terminals, pin 6 of the audio codec chip 7U1 is connected to the I2S0_SDO0 signal terminal via resistor 10R51. Pin 7 of the audio codec chip 7U1 is connected to the I2S0_LRCK_TX signal terminal via resistor RR6921 and to the I2S0_LRCK_RX signal terminal via resistor RR89601. Pin 8 of the audio codec chip 7U1 is connected to the I2S0_SDI0 signal terminal via resistor RR693. Pin 9 of the audio codec chip 7U1 is left floating. Pin 10 of the audio codec chip 7U1 is grounded via capacitor C101 and to the ground via capacitor C102. Pin 11 of the audio codec chip 7U1 is connected to the I2S0_SDO0 signal terminal via resistor RR6921 and to the I2S0_LRCK_RX signal terminal via resistor RR89601. Capacitor 6C85 is connected to the HP1_OUT_R signal terminal. Pin 12 of the audio codec chip 7U1 is connected to the HP1_OUT_L signal terminal via capacitor 6C84. Pin 13 of the audio codec chip 7U1 is grounded. Pin 14 of the audio codec chip 7U1 is connected to the HP2_OUT_R signal terminal via capacitor 6C90. Pin 15 of the audio codec chip 7U1 is connected to the HP2_OUT_L signal terminal via capacitor 6C89. Pin 16 of the audio codec chip 7U1 is connected to one end of capacitor C104, one end of resistor R246, and the AU_VCC33 signal terminal. Pin 17 of the audio codec chip 7U1 is connected to capacitor C104. One end of capacitor C103 and the other end of resistor R247, the other ends of capacitors C103 and C104 are all grounded. Pin 18 of the audio codec chip 7U1 is grounded. Pin 19 of the audio codec chip 7U1 is grounded through capacitors 10C78 and 10C79 respectively. Pin 20 of the audio codec chip 7U1 is grounded through capacitors 10C80 and 10C81 respectively. Pin 21 of the audio codec chip 7U1 is connected to one end of capacitor 6C103. Pin 22 of the audio codec chip 7U1 is connected to one end of capacitor 6C102. The other end of capacitor 6C103 is connected to one end of capacitor 6C100 and the ground terminal respectively.The other end of capacitor 6C100 is connected to the other end of capacitor 6C102, the HP2_MIC signal terminal, and one end of resistor R89626. The other end of resistor R89626 is connected to one end of resistor R89627 and one end of capacitor C9651. The other end of capacitor C9651 is grounded. The other end of resistor R89627 is connected to the AU_VCC33 signal terminal. Pin 23 of the audio codec chip 7U1 is connected to one end of capacitor 6C82. Pin 24 of the audio codec chip 7U1 is connected to one end of capacitor 6C81. The other end of capacitor 6C82 is connected to one end of capacitor 6C83 and grounded. The other end of capacitor 6C83 is connected to the other end of capacitor 6C81, the HP1_MIC signal terminal, and one end of resistor R253. The other end of resistor R253 is connected to one end of resistor R252 and capacitor C102. One end of capacitor 107 is grounded, and the other end of resistor R252 is connected to the AU_VCC33 signal terminal. Pin 25 of the audio codec chip 7U1 is left floating. Pin 26 of the audio codec chip 7U1 is grounded via resistor 6R76 and connected to the VCC_1V8_S0 signal terminal via resistor 6R77. Pin 27 of the audio codec chip 7U1 is connected to one end of resistor R5 and one end of capacitor C5, with the other end of resistor R5 connected to the I2C1_SDA signal terminal. Pin 28 of the audio codec chip 7U1 is connected to one end of resistor R6 and one end of capacitor C105, with the other end of resistor R6 connected to the I2C1_SCL signal terminal. Pin 29 of the audio codec chip 7U1, the other ends of capacitors C105 and C5 are all connected to the AU_GND signal terminal.

[0022] Furthermore, the transceiver module includes an RTL8211F-CG type transceiver chip U6601 and a resistor R6628;Specifically, pin 1 of the transceiver chip U6601 is connected to the MDI0+ signal terminal; pin 2 of the transceiver chip U6601 is connected to the MDI0- signal terminal; pin 3 of the transceiver chip U6601 is connected to the VDD1V0_GEPHY signal terminal; pin 4 of the transceiver chip U6601 is connected to the MDI1+ signal terminal; pin 5 of the transceiver chip U6601 is connected to the MDI1- signal terminal; pin 6 of the transceiver chip U6601 is connected to the MDI2+ signal terminal; pin 7 of the transceiver chip U6601 is connected to the MDI2- signal terminal; pin 8 of the transceiver chip U6601 is connected to the VDD1V0_GEPHY signal terminal; pin 9 of the transceiver chip U6601 is connected to the MDI3+ signal terminal; and pin 10 of the transceiver chip U6601 is connected to the MDI3- signal terminal. Pin 11 of the transceiver chip U6601 is connected to the VCC3V3_EPHY signal terminal. Pin 12 of the transceiver chip U6601 is connected to the PHY_RSTB signal terminal; pin 13 of the transceiver chip U6601 is connected to the MAC_MDCLK signal terminal; pin 14 of the transceiver chip U6601 is connected to the MAC_MDIO signal terminal; pin 15 of the transceiver chip U6601 is connected to the PHY_TXD3 signal terminal; pin 16 of the transceiver chip U6601 is connected to the PHY_TXD2 signal terminal; pin 17 of the transceiver chip U6601 is connected to the PHY_TXD1 signal terminal; pin 18 of the transceiver chip U6601 is connected to the PHY_TXD0 signal terminal; pin 19 of the transceiver chip U6601 is connected to the PHY_TXEN signal terminal; pin 20 of the transceiver chip U6601 is connected to the PHY_TXCLK signal terminal; and pin 21 of the transceiver chip U6601 is connected to the VDD1V0_GEPHY signal terminal. Pin 22 of the transceiver chip U6601 is connected to the PHY_RXD3 / AD0 signal terminal; pin 23 of the transceiver chip U6601 is connected to the PHY_RXD2 / PLLOFF signal terminal; pin 24 of the transceiver chip U6601 is connected to the PHY_RXD1 / TXDLY signal terminal; pin 25 of the transceiver chip U6601 is connected to the PHY_RXD0 / RXDLY signal terminal; pin 26 of the transceiver chip U6601 is connected to the PHY_RXDV / AD2 signal terminal; pin 27 of the transceiver chip U6601 is connected to the PHY_RXCLK / AD1 signal terminal; pin 28 of the transceiver chip U6601 is connected to the VDDREG signal terminal; pin 29 of the transceiver chip U6601 is connected to the VCC3V3_EPHY signal terminal; and pin 30 of the transceiver chip U6601 is connected to the REGOUT signal terminal.

[0023] Pin 31 of the transceiver chip U6601 is connected to the PHY_INTB / PMEB signal terminal. Pin 32 of the transceiver chip U6601 is connected to the LED0 / CFG_EXT signal terminal; pin 33 of the transceiver chip U6601 is connected to the LED1 / CFG_LDO0 signal terminal; pin 34 of the transceiver chip U6601 is connected to the LED2 / CFG_LDO1 signal terminal; pin 35 of the transceiver chip U6601 is connected to the PHY_CLKO125 signal terminal; pin 36 of the transceiver chip U6601 is connected to the PHY_XTALI signal terminal; pin 37 of the transceiver chip U6601 is connected to the PHY_XTALO signal terminal; pin 38 of the transceiver chip U6601 is connected to the VDD1V0_GEPHY signal terminal; pin 39 of the transceiver chip U6601 is grounded through resistor R6628; pin 40 of the transceiver chip U6601 is connected to the VCC3V3_EPHY signal terminal; and pin 41 of the transceiver chip U6601 is grounded.

[0024] Compared with existing technologies, the beneficial effects of this utility model are as follows: A display control circuit, applied to a smart cloud box device, includes a CPU module, a WIFI / Bluetooth module, a display module, an audio codec module, an audio amplifier module, a transceiver module, a power supply module, and a step-down module; wherein, the WIFI / Bluetooth module, the display module, the audio codec module, the audio amplifier module, the transceiver module, and the step-down module are all electrically connected to the CPU module. The CPU module uses an RK3399 processor chip, the display module uses a TC358772XBG display bridge chip, and the step-down module is also electrically connected to the power supply module. The RK3399 processor chip, as a high-performance processor, possesses powerful graphics processing and multitasking capabilities, effectively improving the processing speed and response performance of display data. Combined with the TC358772XBG display bridge chip, it supports multiple display interfaces and high-resolution signal conversion, solving the shortcomings of traditional smart cloud box display modules in terms of compatibility and image clarity. Meanwhile, the integrated Wi-Fi and Bluetooth modules, audio codec and power amplifier modules, transceiver modules, and CPU modules work closely together to achieve synchronized audio and video processing and efficient data transmission, enhancing overall multimedia performance. The coordinated operation of the power supply module and the step-down module ensures stable power supply and low-power operation, guaranteeing the stability and continuity of the display function in various application environments. Through the organic combination of multiple modules, this display control circuit comprehensively solves the problem of insufficient display functionality in smart cloud boxes, improving display effects, response speed, and system compatibility, meeting the high-quality display requirements of smart cloud boxes in complex scenarios. Attached Figure Description

[0025] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0026] Figure 1 A structural block diagram of the display control circuit provided in the embodiments of this utility model;

[0027] Figure 2 A circuit structure diagram of the WIFI Bluetooth module provided in an embodiment of this utility model;

[0028] Figure 3 A circuit diagram of the display module provided in an embodiment of this utility model;

[0029] Figure 4 A circuit diagram of the power module provided in an embodiment of this utility model;

[0030] Figure 5 Circuit structure diagram of the step-down module provided in this embodiment of the utility model;

[0031] Figure 6 A circuit diagram of an audio power amplifier module provided for an embodiment of this utility model;

[0032] Figure 7 A circuit diagram of the audio encoding / decoding module provided in an embodiment of this utility model;

[0033] Figure 8 The circuit structure diagram of the transceiver module provided in the embodiment of this utility model. Detailed Implementation

[0034] The solutions in the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. Based on the embodiments of this utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this utility model.

[0035] It should be noted that if the embodiments of this utility model involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0036] Furthermore, if the embodiments of this utility model involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.

[0037] Please refer to Figure 1 As shown, this utility model proposes a display control circuit for use in a smart cloud box device, including a CPU module, a WIFI / Bluetooth module, a display module, an audio codec module, an audio amplifier module, a transceiver module, a power supply module, and a step-down module; wherein, the WIFI / Bluetooth module, the display module, the audio codec module, the audio amplifier module, the transceiver module, and the step-down module are all electrically connected to the CPU module, the CPU module uses an RK3399 processor chip, the display module uses a TC358772XBG display bridge chip, and the step-down module is also electrically connected to the power supply module.

[0038] Specifically, the RK3399 processor chip is a high-performance six-core heterogeneous architecture processor with powerful 4K multimedia processing capabilities and dual-screen display functionality. It supports a rich array of interfaces, such as dual USB 3.0 ports, and is widely used in industrial control, edge AI, and smart terminals, becoming an industry benchmark solution. Its compatibility with domestic development board ecosystems (such as Firefly and Forlinx) significantly lowers the development threshold for high-performance embedded systems. Furthermore, the RK3399 processor chip supports professional microphone circuitry, enabling high-quality voice capture to meet the communication needs of professionals and enhance the interactive experience and application breadth of devices.

[0039] Compared to existing technologies, the RK3399 processor chip, as a high-performance processor, possesses powerful graphics processing and multitasking capabilities, effectively improving the processing speed and response performance of display data. Combined with the TC358772XBG display bridge chip, it supports multiple display interfaces and high-resolution signal conversion, addressing the shortcomings of traditional smart cloud box display modules in terms of compatibility and image clarity. Simultaneously, the integrated WIFI / Bluetooth module, audio codec and power amplifier module, transceiver module, and CPU module work closely together to achieve synchronous audio and video processing and efficient data transmission, enhancing overall multimedia performance. The coordinated operation of the power supply module and buck module ensures stable power supply and low-power operation, guaranteeing the stability and continuity of display functions in various application environments. Through the organic integration of multiple modules, this display control circuit comprehensively solves the problems of insufficient display functions in smart cloud boxes, improving display effects, response speed, and system compatibility, meeting the high-quality display needs of smart cloud boxes in complex scenarios.

[0040] Please refer to Figure 2 As shown, in some embodiments of this application, the WIFI Bluetooth module includes an AP6275P type WIFI Bluetooth chip U6300, antenna ANT6300, antenna ANT6301, capacitors C6300, C6301, C6302, C6303, C6305, C6306, C6313, iron core inductor L6300, iron core inductor L6301, capacitors C6318, C6321, C6320, C6319, C6316, C6317, resistors R6305, C6315, C6314, R6302, capacitors C6311, C6312, C6340, C6341, C6307, C6308, C6304, C4, and antenna ANT6302;

[0041] Specifically, pins 1, 3, 4, 5, 6, 7, 8, 10, 11, 23, 27, 30, 32, and 39 of the WIFI Bluetooth chip U6300 are all grounded. Pin 2 of the WIFI Bluetooth chip U6300 is connected to one end of capacitor C6306 and one end of capacitor C6303. The other end of capacitor C6303 is connected to one end of capacitor C6301 and antenna ANT6301. The other ends of capacitors C6306 and C6301 are both grounded. Pin 9 of the WIFI Bluetooth chip U6300 is connected to one end of capacitor C6305 and one end of capacitor C6302. The other end of capacitor C6302 is connected to one end of capacitor C6300 and antenna ANT6300. The other ends of capacitors C6300 and C6305 are both grounded.

[0042] Pin 12 of the U6300 Wi-Fi / Bluetooth chip is connected to the PCIE20_PERSTn_1V8 signal terminal; pin 13 of the U6300 Wi-Fi / Bluetooth chip is connected to the XIN_WIFI signal terminal; pin 14 of the U6300 Wi-Fi / Bluetooth chip is connected to the XOUT_WIFI signal terminal; pin 15 of the U6300 Wi-Fi / Bluetooth chip is connected to the WIFI_REG_ON_H signal terminal; pin 16 of the U6300 Wi-Fi / Bluetooth chip is connected to the WIFI_WAKE_HOST_H signal terminal; and pin 17 of the U6300 Wi-Fi / Bluetooth chip is connected to the PCIE20_PERSTn_1V8 signal terminal. Pins 19 and 18 are both left floating. Pin 19 of the U6300 WIFI Bluetooth chip is connected to the I2S2_SDI_M0_BT signal terminal. Pin 20 of the U6300 WIFI Bluetooth chip is connected to the I2S2_SDO_M0_BT signal terminal. Pin 21 of the U6300 WIFI Bluetooth chip is connected to the I2S2_LRCK_M0_BT signal terminal. Pin 22 of the U6300 WIFI Bluetooth chip is connected to the I2S2_SCLK_M0_BT signal terminal. Pin 24 of the U6300 WIFI Bluetooth chip is connected to the PCIE20_WAKEn_1V8 signal terminal.

[0043] Pin 26 of the Wi-Fi Bluetooth chip U6300 is connected to one end of the iron-core inductor L6300. The other end of the iron-core inductor L6300 is connected to pin 25 of the Wi-Fi Bluetooth chip U6300 and one end of capacitor C6313. Pin 28 of the Wi-Fi Bluetooth chip U6300 is connected to one end of the iron-core inductor L6301. The other end of the iron-core inductor L6301 is connected to pin 29 of the Wi-Fi Bluetooth chip U6300 and one end of capacitor C6318. Pin 31 of the Wi-Fi Bluetooth chip U6300 is connected to the 32KOUT_WIFI signal terminal and one end of capacitor C6321. Pin 33 of the Wi-Fi Bluetooth chip U6300 is connected to the PCIE20_1_REFCLKN signal terminal through capacitor C6320. Pin 35 of the Wi-Fi Bluetooth chip U6300 is connected to... Capacitor C6319 is connected to the PCIE20_1_REFCLKP signal terminal. Pin 34 of the WIFI Bluetooth chip U6300 is connected to one end of capacitor C6316, one end of capacitor C6317, one end of resistor R6305, and the VCCIO_WL signal terminal. The other end of resistor R6305 is connected to the VCC_1V8_S3 signal terminal. Pin 36 of the WIFI Bluetooth chip U6300 is connected to one end of capacitor C6315, one end of capacitor C6314, one end of resistor R6302, and the VCC3V3_PCIEWL_VBAT signal terminal. The other end of resistor R6302 is connected to the VCC_3V3_S3 signal terminal. The other ends of capacitors C6313, C6318, C6321, C6316, and C6317 are all grounded.

[0044] Pin 37 of the U6300 Wi-Fi / Bluetooth chip is connected to the PCIE20_CLKREQn_1V8 signal terminal; pin 38 of the U6300 Wi-Fi / Bluetooth chip is connected to the BT_REG_ON_H signal terminal; pin 40 of the U6300 Wi-Fi / Bluetooth chip is connected to the UART9_RX_M0_BT signal terminal; and pin 41 of the U6300 Wi-Fi / Bluetooth chip is connected to the UART9_TX_M0_BT signal terminal. The U6300 Wi-Fi / Bluetooth chip... Pin 42 of the WIFI Bluetooth chip U6300 is connected to the UART9_CTSn_M0_BT signal terminal. Pin 43 of the WIFI Bluetooth chip U6300 is connected to the UART9_RTSn_M0_BT signal terminal. Pin 44 of the WIFI Bluetooth chip U6300 is connected to the PCIE20_1_TXN / SATA30_1_TXN signal terminal through capacitor C6341. Pin 45 of the WIFI Bluetooth chip U6300 is connected to the PCIE20_1_TXP signal terminal through capacitor C6340. The / SATA30_1_TXP signal terminal is connected to pin 46 of the U6300 Wi-Fi / Bluetooth chip via capacitor C6312. Pin 47 of the U6300 Wi-Fi / Bluetooth chip is connected to the PCIE20_1_RXN / SATA30_1_RXN signal terminal via capacitor C6311. Pin 49 of the U6300 Wi-Fi / Bluetooth chip is connected to the HOST_WAKE_BT_H signal terminal. Pin 50 of the WIFI Bluetooth chip U6300 is connected to the BT_WAKE_HOST_H signal terminal. Pin 48 of the WIFI Bluetooth chip U6300 is connected to one end of capacitor C6308 and one end of capacitor C6307. The other end of capacitor C6307 is connected to one end of capacitor C6304, one end of capacitor C4 and antenna ANT6302. The other end of capacitor C4 is connected to the TP1 test terminal. The other ends of capacitors C6308 and C6304 are both grounded.

[0045] Specifically, the AP6275P Wi-Fi and Bluetooth chip, launched by AMPAK, is a dual-mode wireless communication module supporting Wi-Fi 6 (802.11ax) and Bluetooth 5.3. Designed specifically for smart terminal devices, it meets the demands for high-speed, low-latency wireless connectivity. This chip utilizes 2T2R MIMO technology, achieving a theoretical speed of up to 1200Mbps in the 5GHz band, significantly improving wireless transmission speed and network stability. Simultaneously, it is compatible with the Bluetooth 5.3 standard, supporting BR / EDR / LE dual-mode and low-power transmission, enhancing device wireless compatibility and battery life, adapting to complex and ever-changing wireless environments, and improving the communication performance and user experience of smart cloud boxes.

[0046] Please refer to Figure 3 As shown, in some embodiments of this application, the display module includes a TC358772XBG type display bridge chip U5700, resistors R5700, R5701, R5702, R5703, R5704 and R5705.

[0047] Specifically, pin C3 of the display bridge chip U5700 is connected to the VCC_1V8_S0 signal terminal via resistor R5700; pin C4 of the display bridge chip U5700 is left floating; pin D2 of the display bridge chip U5700 is connected to the TP5701 test terminal; pin D3 of the display bridge chip U5700 is connected to the TP5700 test terminal; pin E3 of the display bridge chip U5700 is connected to the TP5702 test terminal; and pin D4 of the display bridge chip U5700 is connected to the LCD_RST_L1 signal terminal. Pin D1 of the display bridge chip U5700 is connected to the REFCLK signal terminal. Pin G1 of the display bridge chip U5700 is connected to the VCC_1V8_S0 signal terminal through resistors R5703 and R5702. Pin H1 of the display bridge chip U5700 is connected to the VCC_1V8_S0 signal terminal through resistors R5704 and R5701. Pin D5 of the display bridge chip U5700 is grounded through resistor R5705. Pin G2 of the display bridge chip U5700 is connected to the MIPI_TX0_D0P1 signal terminal. Pin H2 is connected to the MIPI_TX0_D0N1 signal terminal. Pin G3 of the display bridge chip U5700 is connected to the MIPI_TX0_D1P1 signal terminal. Pin H3 of the display bridge chip U5700 is connected to the MIPI_TX0_D1N1 signal terminal. Pin G4 of the display bridge chip U5700 is connected to the MIPI_TX0_CLKP1 signal terminal. Pin H4 of the display bridge chip U5700 is connected to the MIPI_TX0_CLKN1 signal terminal. Pin G5 of the display bridge chip U5700 is connected to the MIPI_TX0_D1P1 signal terminal. At the 2P1 signal terminal, pin H5 of the display bridge chip U5700 is connected to the MIPI_TX0_D2N1 signal terminal, pin G6 of the display bridge chip U5700 is connected to the MIPI_TX0_D3P1 signal terminal, pin H6 of the display bridge chip U5700 is connected to the MIPI_TX0_D3N1 signal terminal, and pins A1, A7, A8, C1, C6, E1, E5, E6, F1, F4, F5, and H8 of the display bridge chip U5700 are all grounded;

[0048] The display bridge chip U5700 has its B2 pin connected to the LVDS1_D0P signal terminal, its A2 pin connected to the LVDS1_D0N signal terminal, its B3 pin connected to the LVDS1_D1P signal terminal, its A3 pin connected to the LVDS1_D1N signal terminal, its B4 pin connected to the LVDS1_D2P signal terminal, and its A4 pin connected to the LVDS1_D2N signal terminal. Pin B5 of the display bridge chip U5700 is connected to the LVDS1_CLK1P signal terminal; pin A5 of the display bridge chip U5700 is connected to the LVDS1_CLK1N signal terminal; pin B6 of the display bridge chip U5700 is connected to the LVDS1_D3P signal terminal; pin A6 of the display bridge chip U5700 is connected to the LVDS1_D3N signal terminal; pin C7 of the display bridge chip U5700 is connected to the LVDS0_D0P signal terminal; and pin C8 of the display bridge chip U5700 is connected to the LVDS0_D0N signal terminal. The display bridge chip U5700 has its D7 pin connected to the LVDS0_D1P signal terminal, its D8 pin connected to the LVDS0_D1N signal terminal, its E7 pin connected to the LVDS0_D2P signal terminal, its E8 pin connected to the LVDS0_D2N signal terminal, its F7 pin connected to the LVDS0_CLK0P signal terminal, and its F8 pin connected to the LVDS0_CLK signal terminal. At the ON signal terminal, pin G7 of the display bridge chip U5700 is connected to the LVDS0_D3P signal terminal, pin G8 of the display bridge chip U5700 is connected to the LVDS0_D3P signal terminal, pins F3, F6, B8, B1, E2, and E4 of the display bridge chip U5700 are all connected to the VDD1V2_LCD signal terminal, and pins D6, H7, B7, C5, C2, and F2 of the display bridge chip U5700 are all connected to the VCC_1V8_S0 signal terminal.

[0049] Specifically, the TC358772XBG display bridge chip boasts powerful high-definition bridging capabilities, supports MIPIDSI 1.01 input, and can output dual-link LVDS signals to achieve high-bandwidth, high-speed data transmission. It supports smooth 60fps output at WUXGA resolution, ensuring clear, detailed, and responsive visuals, meeting the demands of complex applications such as high-resolution and multi-screen displays. Furthermore, the TC358772XBG display bridge chip exhibits excellent compatibility and stability, effectively reducing system design complexity and enhancing the display performance and overall user experience of smart devices.

[0050] Please refer to Figure 4 As shown, in some embodiments of this application, the power module includes a WC-PD25C012J type power chip U9009 and a polarized capacitor AC42; wherein, the first pin of the power chip U9009 is connected to the VIN+ signal terminal, the second pin of the power chip U9009 is connected to the VIN- signal terminal, the third and sixth pins of the power chip U9009 are both floating, the fourth and seventh pins of the power chip U9009 are both grounded, the fifth pin of the power chip U9009 is connected to the POE_12V signal terminal and the positive terminal of the polarized capacitor AC42 respectively, and the negative terminal of the polarized capacitor AC42 is grounded.

[0051] Specifically, the WC-PD25C012J power chip supports Power over Network (PoE) technology, enabling dual-function transmission of data and DC power via Ethernet cables (such as Cat.5e), and is compatible with various devices such as IP phones, cameras, and wireless access points. Its power supply modes include mid-line bridging and end-line bridging, utilizing idle wire pairs or data pairs to transmit power and data simultaneously, greatly simplifying cabling design. In industrial applications, this power chip replaces traditional power cables with a single network cable, significantly reducing the deployment cost of electronic factory monitoring systems (such as cameras and sensors). It also supports remote power-on and power-off management of PoE switches, enhancing network intelligence and redundancy, and meeting the high-efficiency power supply requirements of complex industrial environments.

[0052] Please refer to Figure 5As shown, in some embodiments of this application, the step-down module includes an MP8759 type step-down chip U21057, a diode D9018, capacitors C217075, C217074, and C217073, resistors R2101, R2105, C217079, C217078, R2107, R89777, R89779, and R89780, a capacitor CC226, an iron-core inductor L21053, resistors R2102 and R2104, capacitors C2105, R2103, and R2106, polarized capacitors CC217, CC218, CC219, and CC220, and a resistor RR897.

[0053] Specifically, the MP8759 buck converter is a high-performance synchronous buck converter with multi-mode energy efficiency management. It supports switching between USM (Ultra-Audio), PFM, and PWM modes, ensuring an efficiency of over 85% under light loads. It also optimizes load and line regulation through a DC automatic adjustment loop, achieving an output voltage accuracy of ±1%. This buck converter integrates multiple protection mechanisms, including overcurrent protection (OCP), overvoltage protection (OVP), undervoltage protection (UVP), and overtemperature protection. It can automatically recover operation after a fault, and its internal soft-start design effectively avoids inrush current impacts. Furthermore, the MP8759 buck converter supports enabling and disabling the chip via the logic level of the EN pin, while the PG pin provides a power status indication, facilitating system monitoring and control and improving the overall safety and reliability of power management.

[0054] Please refer to Figure 6 As shown in some embodiments of this application, the audio amplifier module includes an AD52058 type audio amplifier chip U7, resistors 10R57, 6R38, and AR1, capacitors 10C12, 10C11, 10C3, 10C1, and 10C2, resistors 10R2 and 10C4, 10R1 and 10R7, capacitor 10C25, resistor 6R39, resistor AR2, capacitors 10C14, 10C27, and 10C28, and resistors 10R58 and 10C87. Capacitors 10C86, 10C33, 10C24, 10C30, 10L3, 10C31, 10C32, WF-200-2 type speaker terminal 10J2, 10L4, 10C29, 10C7, 10L1, 10C9, 10C10, WF-200-2 type speaker terminal 10J1, 10L2, 10C8, 10C6, 10C5, 10C84, and 10C85.

[0055] Specifically, the AD52058 audio amplifier chip is a dual-channel Class D audio power amplifier chip with a wide power supply range and high output power, capable of stably driving dual-channel speakers and meeting the needs of medium-power audio applications. Its efficient Class D amplification technology not only improves the clarity and dynamic range of the audio output but also significantly reduces power consumption and heat generation. Comprehensive protection mechanisms, including overheat protection, overcurrent protection, and short-circuit protection, effectively ensure the safe operation of the chip and speakers, improving system reliability and durability. With its excellent performance and stability, the AD52058 audio amplifier chip is the preferred audio amplification solution for smart devices, significantly improving sound quality and user listening experience, and meeting diverse audio application needs.

[0056] Please refer to Figure 7 As shown in some embodiments of this application, the audio codec module includes an ES8388 type audio codec chip 7U1, resistors 10R50 and R244, capacitors C100 and C99, resistors R245, 10R49, 10R51, RR692, R89601, RR693, capacitors C101 and C102, capacitors 6C89, 6C90, 6C84, 6C85, and C103. C104, Resistor R246, Capacitor 10C78, Capacitor 10C79, Capacitor 10C80, Capacitor 10C81, Resistor R89627, Capacitor C9651, Resistor R89626, Capacitor 6C100, Capacitor 6C102, Capacitor 6C103, Capacitor 6C82, Capacitor 6C81, Capacitor 6C83, Resistor R253, Capacitor C107, Resistor R252, Resistor 6R76, Resistor 6R77, Capacitor C105, Capacitor C5, Resistor R5 and Resistor R6.

[0057] Specifically, the ES8388 audio codec chip is a low-power, high-fidelity audio codec chip with excellent audio processing capabilities and industrial-grade reliability, widely used in embedded audio solutions. Its low-power design effectively extends device battery life, supports Bluetooth audio transmission, and meets the needs of wireless audio applications. With its superior sound quality and stable performance, the ES8388 audio codec chip is the preferred solution for audio acquisition and playback in smart devices, improving the overall audio experience and system reliability.

[0058] Please refer to Figure 8 As shown, in some embodiments of this application, the transceiver module includes an RTL8211F-CG type transceiver chip U6601 and a resistor R6628.

[0059] Specifically, the RTL8211F-CG transceiver chip is a Gigabit Ethernet transceiver chip with advanced adaptive technology, capable of automatically correcting crossover sequences and polarity reversals. It supports transmission over CAT.5 cables up to 120 meters long, ensuring network connection stability and reliability. This transceiver chip integrates a DSP and AFE (analog front-end), effectively achieving crosstalk cancellation and echo cancellation, improving signal quality. Its built-in switching regulator and LDO power management module support a PHYRSTB core power-off mode, helping to optimize power consumption. Through these technological advantages, the RTL8211F-CG transceiver chip provides intelligent devices with an efficient and stable Gigabit network communication solution, providing a solid guarantee for high-speed data transmission and real-time screen updates for display modules, ensuring that the smart cloud box can still achieve smooth and high-definition display effects in complex network environments.

[0060] It should be noted that other pin connection structures and related component parameters not mentioned in the text description can be found in the attached diagram, and will not be elaborated upon here. Furthermore, the above connection layout is only an example; in actual applications, other connection schemes can be adopted according to specific requirements, and will not be further illustrated here.

[0061] The display control circuit provided in this embodiment integrates a high-performance RK3399 six-core processor, which has powerful multimedia processing capabilities and rich interface support, significantly improving the system's computing and graphics processing capabilities; in conjunction with the TC358772XBG display bridge chip, it achieves high-bandwidth MIPI. The DSI to dual-link LVDS high-definition signal conversion supports smooth WUXGA@60fps display, ensuring clear and detailed images. For audio, it employs the ES8388 low-power high-fidelity audio codec chip and the AD52058 dual-channel Class D power amplifier chip, providing high-quality audio acquisition and amplification to enhance the overall multimedia experience. Network communication is ensured by the RTL8211F-CG gigabit Ethernet transceiver, supporting long-distance stable transmission and efficient power management to ensure high-speed and stable data transmission. For wireless connectivity, it features the AP6275P WIFI / Bluetooth chip, supporting high-speed wireless network and Bluetooth audio transmission, enhancing the device's wireless interconnectivity. In terms of power management, it uses the WC-PD25C012J power chip and the MP8759 step-down chip to achieve efficient voltage regulation and step-down conversion, ensuring stable power supply while effectively reducing power consumption and heat. Overall, the display control circuit, through the organic integration of multiple modules, comprehensively improves the display performance, audio and video processing capabilities, network communication stability, wireless connectivity, and system energy efficiency of the smart cloud box. It solves the shortcomings of traditional devices in terms of display effect, response speed, sound quality, and communication efficiency, and meets the diverse needs of complex application environments.

[0062] It should be noted that the technical solutions of the various embodiments of this utility model can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.

[0063] The above description is only a part or preferred embodiment of this utility model. Neither the text nor the drawings should limit the scope of protection of this utility model. All equivalent structural transformations made using the content of this utility model specification and drawings under the overall concept of this utility model, or direct / indirect applications in other related technical fields, are included within the scope of protection of this utility model.

Claims

1. A display control circuit, applied to a smart cloud box device, characterized in that, It includes a CPU module, a WIFI / Bluetooth module, a display module, an audio codec module, an audio amplifier module, a transceiver module, a power supply module, and a step-down module; wherein, the WIFI / Bluetooth module, the display module, the audio codec module, the audio amplifier module, the transceiver module, and the step-down module are all electrically connected to the CPU module, the CPU module uses an RK3399 processor chip, the display module uses a TC358772XBG display bridge chip, and the step-down module is also electrically connected to the power supply module.

2. The display control circuit according to claim 1, characterized in that, The WIFI Bluetooth module includes an AP6275P type WIFI Bluetooth chip U6300, antenna ANT6300, antenna ANT6301, capacitors C6300, C6301, C6302, C6303, C6305, C6306, C6313, iron core inductor L6300, iron core inductor L6301, capacitors C6318, C6321, C6320, C6319, C6316, C6317, resistors R6305, C6315, C6314, R6302, C6311, C6312, C6340, C6341, C6307, C6308, C6304, C4, and antenna ANT6302; Specifically, pins 1, 3, 4, 5, 6, 7, 8, 10, 11, 23, 27, 30, 32, and 39 of the WIFI Bluetooth chip U6300 are all grounded. Pin 2 of the WIFI Bluetooth chip U6300 is connected to one end of capacitor C6306 and one end of capacitor C6303. The other end of capacitor C6303 is connected to one end of capacitor C6301 and antenna ANT6301. The other ends of capacitors C6306 and C6301 are both grounded. Pin 9 of the WIFI Bluetooth chip U6300 is connected to one end of capacitor C6305 and one end of capacitor C6302. The other end of capacitor C6302 is connected to one end of capacitor C6300 and antenna ANT6300. The other ends of capacitors C6300 and C6305 are both grounded. Pin 12 of the U6300 Wi-Fi / Bluetooth chip is connected to the PCIE20_PERSTn_1V8 signal terminal; pin 13 of the U6300 Wi-Fi / Bluetooth chip is connected to the XIN_WIFI signal terminal; pin 14 of the U6300 Wi-Fi / Bluetooth chip is connected to the XOUT_WIFI signal terminal; pin 15 of the U6300 Wi-Fi / Bluetooth chip is connected to the WIFI_REG_ON_H signal terminal; pin 16 of the U6300 Wi-Fi / Bluetooth chip is connected to the WIFI_WAKE_HOST_H signal terminal; and pin 17 of the U6300 Wi-Fi / Bluetooth chip is connected to the PCIE20_PERSTn_1V8 signal terminal. Pins 19 and 18 are both left floating. Pin 19 of the U6300 WIFI Bluetooth chip is connected to the I2S2_SDI_M0_BT signal terminal. Pin 20 of the U6300 WIFI Bluetooth chip is connected to the I2S2_SDO_M0_BT signal terminal. Pin 21 of the U6300 WIFI Bluetooth chip is connected to the I2S2_LRCK_M0_BT signal terminal. Pin 22 of the U6300 WIFI Bluetooth chip is connected to the I2S2_SCLK_M0_BT signal terminal. Pin 24 of the U6300 WIFI Bluetooth chip is connected to the PCIE20_WAKEn_1V8 signal terminal. Pin 26 of the Wi-Fi Bluetooth chip U6300 is connected to one end of the iron-core inductor L6300. The other end of the iron-core inductor L6300 is connected to pin 25 of the Wi-Fi Bluetooth chip U6300 and one end of capacitor C6313. Pin 28 of the Wi-Fi Bluetooth chip U6300 is connected to one end of the iron-core inductor L6301. The other end of the iron-core inductor L6301 is connected to pin 29 of the Wi-Fi Bluetooth chip U6300 and one end of capacitor C6318. Pin 31 of the Wi-Fi Bluetooth chip U6300 is connected to the 32KOUT_WIFI signal terminal and one end of capacitor C6321. Pin 33 of the Wi-Fi Bluetooth chip U6300 is connected to the PCIE20_1_REFCLKN signal terminal through capacitor C6320. Pin 35 of the Wi-Fi Bluetooth chip U6300 is connected to... Capacitor C6319 is connected to the PCIE20_1_REFCLKP signal terminal. Pin 34 of the WIFI Bluetooth chip U6300 is connected to one end of capacitor C6316, one end of capacitor C6317, one end of resistor R6305, and the VCCIO_WL signal terminal. The other end of resistor R6305 is connected to the VCC_1V8_S3 signal terminal. Pin 36 of the WIFI Bluetooth chip U6300 is connected to one end of capacitor C6315, one end of capacitor C6314, one end of resistor R6302, and the VCC3V3_PCIEWL_VBAT signal terminal. The other end of resistor R6302 is connected to the VCC_3V3_S3 signal terminal. The other ends of capacitors C6313, C6318, C6321, C6316, and C6317 are all grounded. Pin 37 of the U6300 Wi-Fi / Bluetooth chip is connected to the PCIE20_CLKREQn_1V8 signal terminal; pin 38 of the U6300 Wi-Fi / Bluetooth chip is connected to the BT_REG_ON_H signal terminal; pin 40 of the U6300 Wi-Fi / Bluetooth chip is connected to the UART9_RX_M0_BT signal terminal; and pin 41 of the U6300 Wi-Fi / Bluetooth chip is connected to the UART9_TX_M0_BT signal terminal. The U6300 Wi-Fi / Bluetooth chip... Pin 42 of the WIFI Bluetooth chip U6300 is connected to the UART9_CTSn_M0_BT signal terminal. Pin 43 of the WIFI Bluetooth chip U6300 is connected to the UART9_RTSn_M0_BT signal terminal. Pin 44 of the WIFI Bluetooth chip U6300 is connected to the PCIE20_1_TXN / SATA30_1_TXN signal terminal through capacitor C6341. Pin 45 of the WIFI Bluetooth chip U6300 is connected to the PCIE20_1_TXP signal terminal through capacitor C6340. The / SATA30_1_TXP signal terminal is connected to pin 46 of the U6300 Wi-Fi / Bluetooth chip via capacitor C6312. Pin 47 of the U6300 Wi-Fi / Bluetooth chip is connected to the PCIE20_1_RXN / SATA30_1_RXN signal terminal via capacitor C6311. Pin 49 of the U6300 Wi-Fi / Bluetooth chip is connected to the HOST_WAKE_BT_H signal terminal. Pin 50 of the WIFI Bluetooth chip U6300 is connected to the BT_WAKE_HOST_H signal terminal. Pin 48 of the WIFI Bluetooth chip U6300 is connected to one end of capacitor C6308 and one end of capacitor C6307. The other end of capacitor C6307 is connected to one end of capacitor C6304, one end of capacitor C4 and antenna ANT6302. The other end of capacitor C4 is connected to the TP1 test terminal. The other ends of capacitors C6308 and C6304 are both grounded.

3. The display control circuit according to claim 1, characterized in that, The display module includes a TC358772XBG type display bridge chip U5700, resistors R5700, R5701, R5702, R5703, R5704 and R5705. Specifically, pin C3 of the display bridge chip U5700 is connected to the VCC_1V8_S0 signal terminal via resistor R5700; pin C4 of the display bridge chip U5700 is left floating; pin D2 of the display bridge chip U5700 is connected to the TP5701 test terminal; pin D3 of the display bridge chip U5700 is connected to the TP5700 test terminal; pin E3 of the display bridge chip U5700 is connected to the TP5702 test terminal; and pin D4 of the display bridge chip U5700 is connected to the LCD_RST_L1 signal terminal. Pin D1 of the display bridge chip U5700 is connected to the REFCLK signal terminal. Pin G1 of the display bridge chip U5700 is connected to the VCC_1V8_S0 signal terminal through resistors R5703 and R5702. Pin H1 of the display bridge chip U5700 is connected to the VCC_1V8_S0 signal terminal through resistors R5704 and R5701. Pin D5 of the display bridge chip U5700 is grounded through resistor R5705. Pin G2 of the display bridge chip U5700 is connected to the MIPI_TX0_D0P1 signal terminal. Pin H2 is connected to the MIPI_TX0_D0N1 signal terminal. Pin G3 of the display bridge chip U5700 is connected to the MIPI_TX0_D1P1 signal terminal. Pin H3 of the display bridge chip U5700 is connected to the MIPI_TX0_D1N1 signal terminal. Pin G4 of the display bridge chip U5700 is connected to the MIPI_TX0_CLKP1 signal terminal. Pin H4 of the display bridge chip U5700 is connected to the MIPI_TX0_CLKN1 signal terminal. Pin G5 of the display bridge chip U5700 is connected to the MIPI_TX0_D1P1 signal terminal. At the 2P1 signal terminal, pin H5 of the display bridge chip U5700 is connected to the MIPI_TX0_D2N1 signal terminal, pin G6 of the display bridge chip U5700 is connected to the MIPI_TX0_D3P1 signal terminal, pin H6 of the display bridge chip U5700 is connected to the MIPI_TX0_D3N1 signal terminal, and pins A1, A7, A8, C1, C6, E1, E5, E6, F1, F4, F5, and H8 of the display bridge chip U5700 are all grounded; The display bridge chip U5700 has its B2 pin connected to the LVDS1_D0P signal terminal, its A2 pin connected to the LVDS1_D0N signal terminal, its B3 pin connected to the LVDS1_D1P signal terminal, its A3 pin connected to the LVDS1_D1N signal terminal, its B4 pin connected to the LVDS1_D2P signal terminal, and its A4 pin connected to the LVDS1_D2N signal terminal. Pin B5 of the display bridge chip U5700 is connected to the LVDS1_CLK1P signal terminal; pin A5 of the display bridge chip U5700 is connected to the LVDS1_CLK1N signal terminal; pin B6 of the display bridge chip U5700 is connected to the LVDS1_D3P signal terminal; pin A6 of the display bridge chip U5700 is connected to the LVDS1_D3N signal terminal; pin C7 of the display bridge chip U5700 is connected to the LVDS0_D0P signal terminal; and pin C8 of the display bridge chip U5700 is connected to the LVDS0_D0N signal terminal. The display bridge chip U5700 has its D7 pin connected to the LVDS0_D1P signal terminal, its D8 pin connected to the LVDS0_D1N signal terminal, its E7 pin connected to the LVDS0_D2P signal terminal, its E8 pin connected to the LVDS0_D2N signal terminal, its F7 pin connected to the LVDS0_CLK0P signal terminal, and its F8 pin connected to the LVDS0_CLK signal terminal. At the ON signal terminal, pin G7 of the display bridge chip U5700 is connected to the LVDS0_D3P signal terminal, pin G8 of the display bridge chip U5700 is connected to the LVDS0_D3P signal terminal, pins F3, F6, B8, B1, E2, and E4 of the display bridge chip U5700 are all connected to the VDD1V2_LCD signal terminal, and pins D6, H7, B7, C5, C2, and F2 of the display bridge chip U5700 are all connected to the VCC_1V8_S0 signal terminal.

4. The display control circuit according to claim 1, characterized in that, The power module includes a WC-PD25C012J type power chip U9009 and a polarized capacitor AC42. Pin 1 of the power chip U9009 is connected to the VIN+ signal terminal, pin 2 is connected to the VIN- signal terminal, pins 3 and 6 of the power chip U9009 are both floating, pins 4 and 7 of the power chip U9009 are both grounded, pin 5 of the power chip U9009 is connected to both the POE_12V signal terminal and the positive terminal of the polarized capacitor AC42, and the negative terminal of the polarized capacitor AC42 is grounded.

5. The display control circuit according to claim 1, characterized in that, The step-down module includes an MP8759 type step-down chip U21057, a diode D9018, capacitors C217075, C217074, and C217073, resistors R2101, R2105, C217079, C217078, R2107, R89777, R89779, and R89780, a capacitor CC226, an iron-core inductor L21053, resistors R2102 and R2104, capacitors C2105, R2103, and R2106, polarized capacitors CC217, CC218, CC219, and CC220, and a resistor RR897. In this configuration, pin 1 of the buck converter U21057 is connected to one end of resistor R2101, one end of capacitor C217073, one end of capacitor C217074, one end of capacitor C217075, the VCC12V_DCIN signal terminal, and the negative terminal of diode D9018. Pin 12 of the buck converter U21057 is connected to the other end of resistor R2101, one end of resistor R2105, and one end of capacitor C217079. Pin 4 of the buck converter U21057 is left floating. Pin 9 of the buck converter chip U21057 is connected to one end of capacitor C217078, one end of resistor R2107, and one end of resistor R89777. Pin 3 of the buck converter chip U21057 is connected to the other end of resistor R2107. Pin 6 of the buck converter chip U21057 is connected to the other end of resistor R89777 and one end of resistor R89779. Pins 2 and 10 of the buck converter chip U21057 are both grounded. Pin 5 of the buck converter chip U21057 is connected to... Connect one end of capacitor C2112 to the VCC5V0_SYS signal terminal. Pin 7 of the step-down chip U21057 is connected to one end of resistor R2102, one end of the iron-core inductor L21053, and one end of capacitor CC226. The other end of capacitor CC226 is connected to pin 8 of the step-down chip U21057 via resistor R89780. The other end of resistor R2102 is connected to one end of resistor R2104 and one end of capacitor C2105. The other end of resistor R2104 is connected to the step-down chip... Pin 11 of the voltage regulator chip U21057, one end of resistor R2103 and one end of resistor R2106, the other end of resistor R2103 is connected to the other end of iron core inductor L21053, the other end of capacitor C2105, the positive terminal of polarized capacitor CC217, one end of capacitor CC218, one end of capacitor CC219, one end of capacitor CC220 and one end of resistor RR897, the other end of resistor RR897 is connected to the VCC5V0_SYS signal terminal and the VCC5V0_USB signal terminal respectively; The positive terminal of diode D9018, the other end of capacitor C217075, the other end of capacitor C217074, the other end of capacitor C217073, the other end of resistor R2105, the other end of capacitor C217079, the other end of capacitor C217078, the other end of resistor R89779, the other end of capacitor C2112, the other end of resistor R2106, the negative terminal of polarized capacitor CC217, the other end of capacitor CC218, the other end of capacitor CC219, and the other end of capacitor CC220 are all grounded.

6. The display control circuit according to claim 1, characterized in that, The audio amplifier module includes an AD52058 audio amplifier chip U7, resistors 10R57, 6R38, and AR1, capacitors 10C12, 10C11, 10C3, 10C1, and 10C2, resistors 10R2 and 10C4, 10R1 and 10R7, capacitor 10C25, resistor 6R39, resistor AR2, capacitors 10C14, 10C27, and 10C28, resistors 10R58, 10C87, and 10C86. Capacitors 10C33, 10C24, 10C30, 10L3, 10C31, 10C32, WF-200-2 type speaker terminal 10J2, 10L4, 10C29, 10C7, 10L1, 10C9, 10C10, WF-200-2 type speaker terminal 10J1, 10L2, 10C8, 10C6, 10C5, 10C84, and 10C85; Specifically, pin 1 of the audio amplifier chip U7 is connected to pin 2 of the audio amplifier chip U7 and one end of resistor 10R57, while the other end of resistor 10R57 is connected to the SPK_CTL_H11 signal terminal. Pin 3 of the audio amplifier chip U7 is connected to one end of capacitor 10C1, pin 4 of the audio amplifier chip U7 is connected to one end of capacitor 10C2, pins 5, 6, and 13 of the audio amplifier chip U7 are all left floating, and pin 7 of the audio amplifier chip U7 is connected to one end of resistor 10R2. One end of capacitor 10C11 and one end of capacitor 10C3 are connected to the PVDD signal terminal. The other end of resistor 10R2 is connected to the PVDD signal terminal. Pin 8 of the audio amplifier chip U7 is connected to one end of capacitor 10C4, one end of resistor 10R7, one end of capacitor 10C25, the other end of capacitor 10C11, the other end of capacitor 10C3, and the AGND_AUDIO signal terminal. Pin 9 of the audio amplifier chip U7 is connected to the other end of capacitor 10C4 and one end of resistor 10R1. The other end of resistor 10R1 is connected to the PVDD signal terminal. The other end of capacitor 10R7, the other end of capacitor 10C25, and pin 10 of audio amplifier chip U7 are connected. The other end of capacitor 10C1 is connected to one end of capacitor 10C12, one end of resistor AR1, and one end of resistor 6R38. The other end of resistor 6R38 is connected to the HPL1 signal terminal. The other end of capacitor 10C2 is connected to the other end of capacitor 10C12, the other end of resistor AR1, and the AGND_AUDIO signal terminal. Pin 11 of audio amplifier chip U7 is connected to AGND_AUDI through capacitor 10C27. At the O signal terminal, pin 12 of the audio amplifier chip U7 is connected to one end of capacitor 10C28, pin 14 of the audio amplifier chip U7 is connected to the AGND_AUDIO signal terminal through resistor 10R58, pin 29 of the audio amplifier chip U7 is connected to the AGND_AUDIO signal terminal, the other end of capacitor 10C28 is connected to the AGND_AUDIO signal terminal through capacitor 10C14, the AGND_AUDIO signal terminal through capacitor AR2, and the HPR1 signal terminal through resistor 6R39; Pin 28 of the audio amplifier chip U7 is connected to the PVDD signal terminal, pin 27 of the audio amplifier chip U7, one end of capacitor 10C87, one end of capacitor 10C86, one end of capacitor 10C33, and one end of capacitor 10C24. The other ends of capacitors 10C87, 10C86, 10C33, and 10C24 are all connected to the AGND_AUDIO signal terminal. Pin 26 of the audio amplifier chip U7 is connected to one end of capacitor 10C30. The other end of capacitor 10C30 is connected to pin 25 of the audio amplifier chip U7 and one end of inductor 10L3. Pin 2... Pin 4 is connected to the AGND_AUDIO signal terminal, one end of capacitor 10C31, and one end of capacitor 10C32, respectively. Pin 23 of the audio amplifier chip U7 is connected to one end of capacitor 10C29 and one end of inductor 10L4, respectively. The other end of inductor 10L4 is connected to the other end of capacitor 10C32 and pin 1 of speaker terminal 10J2, pin 2 of speaker terminal 10J2 is connected to the other end of inductor 10L3 and the other end of capacitor 10C31, pins 3 and 4 of speaker terminal 10J2 are grounded, and the other end of capacitor 10C29 is connected to pin 22 of the audio amplifier chip U7. Pin 21 of U7 is connected to one end of capacitor 10C7. Pin 20 of the audio amplifier chip U7 is connected to the other end of capacitor 10C7, one end of inductor 10L1, and the SPK1_1N signal terminal. Pin 19 of the audio amplifier chip U7 is connected to the AGND_AUDIO signal terminal, one end of capacitor 10C9, and one end of capacitor 10C10. Pin 18 of the audio amplifier chip U7 is connected to one end of capacitor 10C8, one end of inductor 10L2, and the SPK1_1P signal terminal. The other end of inductor 10L2 is connected to the other end of capacitor 10C10 and pin 1 of speaker terminal 10J1. Pin 2 of 1 is connected to the other end of inductor 10L1 and capacitor 10C9 respectively. Pins 3 and 4 of speaker terminal 10J1 are grounded. Pin 17 of audio amplifier chip U7 is connected to the other end of capacitor 10C8. Pin 16 of audio amplifier chip U7 is connected to pin 15 of audio amplifier chip U7, one end of capacitor 10C6, one end of capacitor 10C5, one end of capacitor 10C84, one end of capacitor 10C85 and PVDD signal respectively. The other ends of capacitors 10C6, 10C5, 10C84 and 10C85 are all connected to the AGND_AUDIO signal terminal.

7. The display control circuit according to claim 1, characterized in that, The audio codec module includes an ES8388 type audio codec chip 7U1, resistors 10R50 and R244, capacitors C100 and C99, resistors R245, 10R49, 10R51, RR692, R89601, RR693, capacitors C101 and C102, capacitors 6C89, 6C90, 6C84, 6C85, C103, and C104, and resistors... R246, capacitor 10C78, capacitor 10C79, capacitor 10C80, capacitor 10C81, resistor R89627, capacitor C9651, resistor R89626, capacitor 6C100, capacitor 6C102, capacitor 6C103, capacitor 6C82, capacitor 6C81, capacitor 6C83, resistor R253, capacitor C107, resistor R252, resistor 6R76, resistor 6R77, capacitor C105, capacitor C5, resistor R5 and resistor R6; Specifically, pin 1 of the audio codec chip 7U1 is connected to the I2S_MCLK signal terminal via resistor 10R50. Pin 2 of the audio codec chip 7U1 is connected to pin 3 of the audio codec chip 7U1, one end of resistor R245, one end of capacitor C99, and one end of resistor R244. The other end of resistor R244 is connected to the VCC_1V8_S0 signal terminal and one end of capacitor C100. The other end of capacitor C100 is grounded. Pin 4 of the audio codec chip 7U1 is connected to the other end of capacitor C99, the other end of resistor R245, and ground. Pin 5 of the audio codec chip 7U1 is connected to the I2S0_SCLK signal terminal via resistor 10R49. At the signal terminals, pin 6 of the audio codec chip 7U1 is connected to the I2S0_SDO0 signal terminal via resistor 10R51. Pin 7 of the audio codec chip 7U1 is connected to the I2S0_LRCK_TX signal terminal via resistor RR6921 and to the I2S0_LRCK_RX signal terminal via resistor RR89601. Pin 8 of the audio codec chip 7U1 is connected to the I2S0_SDI0 signal terminal via resistor RR693. Pin 9 of the audio codec chip 7U1 is left floating. Pin 10 of the audio codec chip 7U1 is grounded via capacitor C101 and to the ground via capacitor C102. Pin 11 of the audio codec chip 7U1 is connected to the I2S0_SDO0 signal terminal via resistor RR6921 and to the I2S0_LRCK_RX signal terminal via resistor RR89601. Capacitor 6C85 is connected to the HP1_OUT_R signal terminal. Pin 12 of the audio codec chip 7U1 is connected to the HP1_OUT_L signal terminal via capacitor 6C84. Pin 13 of the audio codec chip 7U1 is grounded. Pin 14 of the audio codec chip 7U1 is connected to the HP2_OUT_R signal terminal via capacitor 6C90. Pin 15 of the audio codec chip 7U1 is connected to the HP2_OUT_L signal terminal via capacitor 6C89. Pin 16 of the audio codec chip 7U1 is connected to one end of capacitor C104, one end of resistor R246, and the AU_VCC33 signal terminal. Pin 17 of the audio codec chip 7U1 is connected to capacitor C104. One end of capacitor C103 and the other end of resistor R247, the other ends of capacitors C103 and C104 are all grounded. Pin 18 of the audio codec chip 7U1 is grounded. Pin 19 of the audio codec chip 7U1 is grounded through capacitors 10C78 and 10C79 respectively. Pin 20 of the audio codec chip 7U1 is grounded through capacitors 10C80 and 10C81 respectively. Pin 21 of the audio codec chip 7U1 is connected to one end of capacitor 6C103. Pin 22 of the audio codec chip 7U1 is connected to one end of capacitor 6C102. The other end of capacitor 6C103 is connected to one end of capacitor 6C100 and the ground terminal respectively.The other end of capacitor 6C100 is connected to the other end of capacitor 6C102, the HP2_MIC signal terminal, and one end of resistor R89626. The other end of resistor R89626 is connected to one end of resistor R89627 and one end of capacitor C9651. The other end of capacitor C9651 is grounded. The other end of resistor R89627 is connected to the AU_VCC33 signal terminal. Pin 23 of the audio codec chip 7U1 is connected to one end of capacitor 6C82. Pin 24 of the audio codec chip 7U1 is connected to one end of capacitor 6C81. The other end of capacitor 6C82 is connected to one end of capacitor 6C83 and grounded. The other end of capacitor 6C83 is connected to the other end of capacitor 6C81, the HP1_MIC signal terminal, and one end of resistor R253. The other end of resistor R253 is connected to one end of resistor R252 and capacitor C102. One end of capacitor 107 is grounded, and the other end of resistor R252 is connected to the AU_VCC33 signal terminal. Pin 25 of the audio codec chip 7U1 is left floating. Pin 26 of the audio codec chip 7U1 is grounded via resistor 6R76 and connected to the VCC_1V8_S0 signal terminal via resistor 6R77. Pin 27 of the audio codec chip 7U1 is connected to one end of resistor R5 and one end of capacitor C5, with the other end of resistor R5 connected to the I2C1_SDA signal terminal. Pin 28 of the audio codec chip 7U1 is connected to one end of resistor R6 and one end of capacitor C105, with the other end of resistor R6 connected to the I2C1_SCL signal terminal. Pin 29 of the audio codec chip 7U1, the other ends of capacitors C105 and C5 are all connected to the AU_GND signal terminal.

8. The display control circuit according to claim 1, characterized in that, The transceiver module includes an RTL8211F-CG type transceiver chip U6601 and a resistor R6628;Specifically, pin 1 of the transceiver chip U6601 is connected to the MDI0+ signal terminal; pin 2 of the transceiver chip U6601 is connected to the MDI0- signal terminal; pin 3 of the transceiver chip U6601 is connected to the VDD1V0_GEPHY signal terminal; pin 4 of the transceiver chip U6601 is connected to the MDI1+ signal terminal; pin 5 of the transceiver chip U6601 is connected to the MDI1- signal terminal; pin 6 of the transceiver chip U6601 is connected to the MDI2+ signal terminal; pin 7 of the transceiver chip U6601 is connected to the MDI2- signal terminal; pin 8 of the transceiver chip U6601 is connected to the VDD1V0_GEPHY signal terminal; pin 9 of the transceiver chip U6601 is connected to the MDI3+ signal terminal; and pin 10 of the transceiver chip U6601 is connected to the MDI3- signal terminal. Pin 11 of the transceiver chip U6601 is connected to the VCC3V3_EPHY signal terminal. Pin 12 of the transceiver chip U6601 is connected to the PHY_RSTB signal terminal; pin 13 of the transceiver chip U6601 is connected to the MAC_MDCLK signal terminal; pin 14 of the transceiver chip U6601 is connected to the MAC_MDIO signal terminal; pin 15 of the transceiver chip U6601 is connected to the PHY_TXD3 signal terminal; pin 16 of the transceiver chip U6601 is connected to the PHY_TXD2 signal terminal; pin 17 of the transceiver chip U6601 is connected to the PHY_TXD1 signal terminal; pin 18 of the transceiver chip U6601 is connected to the PHY_TXD0 signal terminal; pin 19 of the transceiver chip U6601 is connected to the PHY_TXEN signal terminal; pin 20 of the transceiver chip U6601 is connected to the PHY_TXCLK signal terminal; and pin 21 of the transceiver chip U6601 is connected to the VDD1V0_GEPHY signal terminal. Pin 22 of the transceiver chip U6601 is connected to the PHY_RXD3 / AD0 signal terminal; pin 23 of the transceiver chip U6601 is connected to the PHY_RXD2 / PLLOFF signal terminal; pin 24 of the transceiver chip U6601 is connected to the PHY_RXD1 / TXDLY signal terminal; pin 25 of the transceiver chip U6601 is connected to the PHY_RXD0 / RXDLY signal terminal; pin 26 of the transceiver chip U6601 is connected to the PHY_RXDV / AD2 signal terminal; pin 27 of the transceiver chip U6601 is connected to the PHY_RXCLK / AD1 signal terminal; pin 28 of the transceiver chip U6601 is connected to the VDDREG signal terminal; pin 29 of the transceiver chip U6601 is connected to the VCC3V3_EPHY signal terminal; and pin 30 of the transceiver chip U6601 is connected to the REGOUT signal terminal. Pin 31 of the transceiver chip U6601 is connected to the PHY_INTB / PMEB signal terminal. Pin 32 of the transceiver chip U6601 is connected to the LED0 / CFG_EXT signal terminal; pin 33 of the transceiver chip U6601 is connected to the LED1 / CFG_LDO0 signal terminal; pin 34 of the transceiver chip U6601 is connected to the LED2 / CFG_LDO1 signal terminal; pin 35 of the transceiver chip U6601 is connected to the PHY_CLKO125 signal terminal; pin 36 of the transceiver chip U6601 is connected to the PHY_XTALI signal terminal; pin 37 of the transceiver chip U6601 is connected to the PHY_XTALO signal terminal; pin 38 of the transceiver chip U6601 is connected to the VDD1V0_GEPHY signal terminal; pin 39 of the transceiver chip U6601 is grounded through resistor R6628; pin 40 of the transceiver chip U6601 is connected to the VCC3V3_EPHY signal terminal; and pin 41 of the transceiver chip U6601 is grounded.

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