Automatic generation method and system of test vectors and computer-readable storage medium

Abstract

The present invention provides a method, system and computer-readable storage medium for automatically generating test vectors, which are applied to the field of semiconductor manufacturing technology. In the present invention, firstly, the test vector format script information under various test specifications in the test machine is summarized into the same vector automatic generation file, and then the mapping relationship between each output channel identifier of the test machine and the test pin identifier connected to the output channel corresponding to the output channel identifier is mapped in a pin self-checking table, so that when the test specification of the device under test is unknown, the test specification corresponding to the test of the device under test and its corresponding test vector format are directly and automatically extracted from the vector automatic generation file, and then the target test vector is automatically formed, which simplifies the test process, reduces the test cost, realizes the automatic generation of test vectors and ultimately improves the test efficiency.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method and system for automatically generating a test vector and a computer-readable storage medium. Background Art

[0002] After a device (such as a chip) is designed, it needs to be tested for functionality and reliability to ensure that it meets quality standards and specifications.

[0003] Functional testing is often used in chip testing, and functional testing requires the use of test patterns. Currently, different automatic test equipment (ATE) for semiconductors has different pattern formats, and each ATE corresponds to multiple test vectors with different formats. Therefore, for testers, in addition to learning multiple ATE equipment platforms, writing multiple patterns will increase a lot of loading. Summary of the invention

[0004] The object of the present invention is to provide a method, system and computer-readable storage medium for automatically generating test vectors, so as to automatically generate target test vectors corresponding to the test specifications required by the device under test for various test specifications of the test machine through a pre-established pin self-check table that can directly map the test pins to the output channels, thereby simplifying the test process, reducing the test cost, realizing the automatic generation of test vectors and ultimately improving the test efficiency.

[0005] In a first aspect, in order to solve the above technical problems, the present invention provides a method for automatically generating a test vector, which can be specifically applied to a test machine including multiple test specifications and multiple output channels, wherein the test vector formats corresponding to the multiple test specifications are different, and the automatic generation method comprises:

[0006] Pre-establishing a vector automatic generation file, wherein the vector automatic generation file includes each vector format script information corresponding to all test specifications of the test machine, wherein the vector format script information includes test vector template information and an output channel identifier corresponding thereto;

[0007] Pre-establishing a pin self-check table, the pin self-check table including a mapping relationship between each output channel identifier of the test machine and a test pin identifier connected to the output channel corresponding to the output channel identifier;

[0008] Based on the configuration information of multiple test pins of the device under test, determine the output channel identifier connected to each test pin of the device under test from the pin self-check table, and reorder the multiple output channel identifiers of the multiple test pins;

[0009] Based on the output channel identifier of the test pin connection of the device under test, determining the test specification of the device under test and its corresponding vector format script information from the vector automatic generation file;

[0010] Based on the determined test vector template information in the vector format script information of the device under test, a test vector template in a target test vector for testing the device under test is formed, and based on a preset vector repetition number N and a vector modification strategy, N modified test vector templates are configured after the test vector template to generate a target test vector for the device under test.

[0011] In some optional examples, the step of pre-establishing a vector automatic generation file may include:

[0012] Reading vector information in the vector format script file config corresponding to each test specification of the test machine, wherein the vector information is test vector template information and an output channel identifier corresponding thereto;

[0013] The vector information in each vector format script file config corresponding to all the test specifications of the test machine is aggregated into a pre-configured vector automatic generation file.

[0014] In some optional examples, the step of pre-establishing a pin self-check table may include:

[0015] Read and parse the corresponding relationship between the output channel and the output channel identifier in the output channel file socket of the test machine;

[0016] Determine a mapping relationship between each of the output channel identifiers and a test pin connected to the output channel corresponding to the output channel;

[0017] All the output channels are reordered in ascending order according to their identifiers, and the mapping relationship between the reordered output channel identifiers and the test pins connected to the corresponding output channels is formed into the pin self-checking table.

[0018] In some optional examples, the step of determining the preset vector repetition number N may include:

[0019] Based on the vector information of the vector format script file corresponding to each test specification and a preset algorithm, the number of times N that the test vector template needs to be repeated in the target test vector corresponding to each test specification is calculated.

[0020] In some optional examples, the target test vector of the device under test further includes vector header information, and the step of forming the vector header information may include:

[0021] The output channel identifiers connected to the multiple test pins of the device under test are reordered from small to large, and the reordered multiple output channel identifiers are used as vector header information of the target test vector.

[0022] In a second aspect, based on the same inventive concept, the present invention further provides a system for automatically generating test vectors, which can be specifically applied to a test machine including multiple test specifications and multiple output channels, wherein the test vector formats corresponding to the multiple test specifications are different, and the automatic generation system comprises:

[0023] A vector automatic generation file establishment module, used to establish a vector automatic generation file in advance, wherein the vector automatic generation file includes each vector format script information corresponding to all test specifications of the test machine, and the vector format script information includes test vector template information and the output channel identifier corresponding thereto;

[0024] A pin self-checking table forming module is used to pre-establish a pin self-checking table, wherein the pin self-checking table includes a mapping relationship between each output channel identifier of the test machine and a test pin identifier connected to the output channel corresponding to the output channel identifier;

[0025] An output channel identification determination module, configured to determine the output channel identification of each test pin of the device under test from the pin self-check table based on the configuration information of the multiple test pins of the device under test, and reorder the multiple output channel identifications of the multiple test pins;

[0026] A vector format script information determination module, used to determine the test specification of the device under test and its corresponding vector format script information from the vector automatic generation file based on the output channel identifier of the test pin connection of the device under test;

[0027] A target test vector generation module is used to form a test vector template in a target test vector for testing the device under test based on the test vector template information in the determined vector format script information of the device under test, and based on a preset vector repetition number N and a vector modification strategy, configure N modified test vector templates after the test vector template to generate a target test vector for the device under test.

[0028] In some optional examples, the vector automatic generation file establishment module may also include:

[0029] A config file reading unit, used to read vector information in a vector format script file config corresponding to each test specification of the test machine, wherein the vector information is test vector template information and an output channel identifier corresponding thereto;

[0030] The vector information aggregation unit is used to aggregate the vector information in each vector format script file config corresponding to all the test specifications of the test machine into a pre-configured vector automatic generation file.

[0031] In some optional examples, the pin self-check table forming module may further include:

[0032] A socket file parsing unit, used for reading and parsing the correspondence between the output channel and the output channel identifier in the output channel file socket of the test machine;

[0033] A test pin mapping relationship determining unit, used to determine a mapping relationship between each of the output channel identifiers and a test pin connected to the output channel corresponding thereto;

[0034] The pin self-checking table forming unit is used to reorder all the output channels from small to large according to their identifiers, and form the pin self-checking table with the mapping relationship between the reordered multiple output channel identifiers and the test pins connected to the corresponding output channels.

[0035] In some optional examples, the automatic test vector generation system may further include:

[0036] The vector header information forming module is used to reorder the output channel identifiers connected to the multiple test pins of the device under test from small to large, and use the reordered multiple output channel identifiers as the vector header information of the target test vector.

[0037] In a third aspect, the present invention further provides an electronic device, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;

[0038] Memory, used to store computer programs;

[0039] A processor is used to implement any of the steps of the method for automatically generating a test vector as described in the first aspect when executing a program stored in a memory.

[0040] In a fourth aspect, a computer-readable storage medium is provided, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the method for automatically generating a test vector described in any one of the first aspects are implemented.

[0041] In a fifth aspect, a computer program product comprising instructions is provided, which, when executed on a computer, enables the computer to execute the steps of the method for automatically generating a test vector as described in any one of the first aspects.

[0042] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0043] The present invention provides a method for automatically generating a test vector, which comprises: pre-establishing a vector automatic generation file, wherein the vector automatic generation file comprises each vector format script information corresponding to all test specifications of the test machine, wherein the vector format script information comprises test vector template information and an output channel identifier corresponding thereto, pre-establishing a pin self-checking table, wherein the pin self-checking table comprises a mapping relationship between each output channel identifier of the test machine and a test pin identifier connected to an output channel corresponding to the output channel identifier, and determining from the pin self-checking table a mapping relationship between each test pin connection of the device under test and the output channel identifier corresponding thereto based on configuration information of multiple test pins of the device under test. output channel identifiers, and reorder the multiple output channel identifiers of the multiple test pins, determine the test specifications of the device under test and its corresponding vector format script information from the vector automatic generation file based on the output channel identifiers connected to the test pins of the device under test, form a test vector template in a target test vector for testing the device under test based on the determined test vector template information in the vector format script information, and based on a preset vector repetition number N and a vector modification strategy, configure N modified test vector templates after the test vector template to generate a target test vector for the device under test.

[0044] In the present invention, firstly, the test vector format script information under multiple test specifications in a certain test machine is summarized into the same vector automatic generation file, and then the mapping relationship between each output channel identifier of the test machine and the test pin identifier connected to the output channel corresponding to the output channel identifier is mapped in a pin self-check table. Therefore, when the test specification of the device under test is unknown, the test specification corresponding to the device under test and its corresponding test vector format can be directly and automatically extracted from the vector automatic generation file based on the configuration information of the pins actually connected to the test machine and the reference pin self-check table, and then the target test vector is automatically formed. It first realizes the correspondence between the pins and output channels of the test machine from the horizontal expression of multi-file query to the vertical expression of direct query through only one pin self-check table, which simplifies the test process, reduces the test cost, realizes the automatic generation of test vectors and ultimately improves the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application but do not constitute a limitation to the present application. In the accompanying drawings:

[0046] Figure 1 A schematic flow chart of a method for automatically generating a test vector provided in an embodiment of the present invention.

[0047] Figure 2 The use provided in the embodiment of the present invention Figure 1 A schematic diagram of a target test vector formed by the automatic test vector generation method shown.

[0048] Figure 3 It is a schematic diagram of the structure of the automatic generation system of the test vector provided in the embodiment of the present invention.

[0049] In the drawings, the same reference numerals are used for the same components, and the drawings are not drawn to scale. DETAILED DESCRIPTION

[0050] In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0051] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the accompanying drawings are all in very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It is understood that the meanings of "on", "above" and "above" in the present invention should be interpreted in the broadest way, so that "on" not only means that it is "on" something and there are no intervening features or layers (i.e. directly on something), but also includes the meaning of being "on" something and having intervening features or layers.

[0052] Additionally, for ease of description, regional relative terms such as "on", "over", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. Regional relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the regional relative descriptors used herein may be interpreted accordingly.

[0053] In the embodiments of the present invention, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions recorded in the embodiments of the present invention can be combined arbitrarily without conflict.

[0054] According to the background technology, functional test is often used in chip testing, and functional test needs to be matched with multiple test vector patterns. The pattern format of each semiconductor automatic test equipment (Automatic Test Equipment, referred to as ATE) is different. For testers, in addition to learning multiple ATE equipment platforms, writing multiple patterns will increase a lot of loading. As for the liquid crystal display driver (Liquid Crystal Display Driver, referred to as LCD driver) IC, the most common ATE test equipment is ADVANTEST's ND2 and ND3, so writing the pattern of this device is the most common. Among them, LCD driver can be divided into Source driver and Gate driver. There are some differences in the specifications of each source driver in the datasheet, which is also one of the reasons for the diversification of patterns. In addition, because the number of output channels of Source driver is large, the amount of input data to be transmitted is large, resulting in a large content of pattern, which is more troublesome in writing and modifying. Currently, Mini-LVDS is a common communication interface (Interface, referred to as I / F) for source drivers. It consists of a set of clock signals plus three or six sets of data signals, and all of them are differential single signals.

[0055] Obviously, in the prior art, for a certain test device, without knowing the device, the tester or tester cannot determine which test vector format corresponding to the test specification is used for testing, and thus cannot generate test vectors.

[0056] In order to solve the above problem, the inventor of the present invention proposed a solution, that is, for each type of test equipment, a setting file document is first established, and then the data information of the test vectors corresponding to all the test specifications in this test equipment are placed in this setting document. Then, when performing chip testing, we determine the corresponding test specifications based on the initial settings of the chip test, and then select the corresponding test specification data information from this setting document, and then form the corresponding target test vector based on the data information.

[0057] Specifically, an embodiment of the present invention provides a method, system and computer-readable storage medium for automatically generating test vectors, which automatically generates target test vectors corresponding to the test specifications required by the device under test for various test specifications of the test machine through a pre-established pin self-check table that can directly map test pins to output channels, thereby simplifying the test process, reducing test costs, realizing automatic generation of test vectors and ultimately improving test efficiency.

[0058] The following will introduce in detail the automatic generation method, automatic generation system and computer-readable storage medium of the test vector provided by the present invention in conjunction with the accompanying drawings.

[0059] It should be noted that the test vector automatic generation method and automatic generation system proposed in the embodiments of the present invention are both aimed at test machines including multiple test specifications and multiple output channels, that is, the test vector automatic generation method and automatic generation system provided in the embodiments of the present invention are mainly used for test machines including multiple test specifications and multiple output channels, and the test vector formats corresponding to the multiple test specifications are different.

[0060] See also Figure 1 , Figure 1 FIG. 1 is a flow chart of a method for automatically generating a test vector provided in an embodiment of the present invention. Figure 1 As shown, the method for automatically generating a test vector provided in an embodiment of the present invention may include at least the following steps:

[0061] Step S101, pre-establishing a vector automatic generation file, wherein the vector automatic generation file includes vector format script information corresponding to all test specifications of the test machine, and the vector format script information includes test vector template information and the corresponding output channel identifier.

[0062] Step S102 : pre-establishing a pin self-checking table, wherein the pin self-checking table includes a mapping relationship between each output channel identifier of the test machine and a test pin identifier connected to the output channel corresponding to the output channel identifier.

[0063] Step S103, based on the configuration information of the multiple test pins of the device under test, determine the output channel identifier connected to each test pin of the device under test from the pin self-check table, and reorder the multiple output channel identifiers of the multiple test pins.

[0064] Step S104 , based on the output channel identifier of the test pin connection of the device under test, determining the test specification of the device under test and its corresponding vector format script information from the vector automatic generation file.

[0065] Step S105, based on the determined test vector template information in the vector format script information of the device under test, a test vector template in the target test vector for testing the device under test is formed, and based on the preset vector repetition number N and the vector modification strategy, N modified test vector templates are configured after the test vector template to generate the target test vector of the device under test.

[0066] In the above step S101, the device to be tested and its corresponding circuit are referred to as the device to be tested. For a test of a device to be tested, the test equipment used is first determined, and then the vector format script file config (the format of this file is config.txt) corresponding to each test specification in the configuration file of the test equipment is obtained, and the content in config.txt corresponding to each test specification of the test machine is copied to the pre-established vector automatic generation file. Since the config.txt corresponding to each test specification includes part of the output channel identifiers of the test machine using this type of test specification and the template information of the test vector formed corresponding to this type of test specification, wherein the output channel identifier is used to uniquely represent a certain output channel of the test machine, therefore, through step S101 in the embodiment of the present invention, the test vector template information of multiple types of test vector formats under multiple test specifications of a test machine can be summarized in the same file.

[0067] In the above step S102, the corresponding relationship between the output channel and the output channel identifier in the output channel file socket (the format of the file is socket.tdl) of the test machine can be read and parsed first, and then the mapping relationship between each of the output channel identifiers and the test pins connected to the corresponding output channel is determined, and all the output channels are reordered from small to large according to their identifiers, and the mapping relationship between the reordered multiple output channel identifiers and the test pins connected to the corresponding output channels is formed into the pin self-checking table. In the prior art, the config.txt file corresponding to a certain test specification only contains the corresponding output channel identifier, and the identifiers are disordered. Therefore, in the case of not determining the test specification corresponding to the current test of the device under test, the test machine or the tester cannot correspond to which test specification corresponds to the test vector format used for the test, and thus cannot generate the test vector. In order to solve this problem, a pin self-checking table is provided in the embodiment of the present invention, which integrates the relationship between the output channel identifier under the socket.tdl file under each test specification recorded in the prior art and the output channel and the test pin of the test machine into a pin self-checking table.

[0068] In the above step S103, when the test machine tests a device under test, the output channel identifier of each test pin of the device under test is determined from the pin self-check table through the configuration information of the pins of the device under test and the test pins of the test machine (by checking the pin self-check table), and then the output channel identifiers corresponding to the test pins on the test machine to which the multiple pins of the device under test are connected are sorted in ascending order according to their sizes. Exemplarily, the output channel identifiers are often numerical values, such as 22, 35, 89, etc., and the output channel identifiers sorted from small to large are used as the vector header information of the target test vector to be formed in this test.

[0069] In the above step S104, after determining the output channel identifier of each test pin connection of the device under test in step S103, the test for the device under test can be determined from the vector automatic generation file established in step S101 based on the output channel identifier, the test machine can be used to determine the corresponding test specifications and the test vector template information corresponding to the test specifications, and then step S105 is executed.

[0070] In the above step S105, based on the test vector template information in the determined vector format script information of the device under test and the vector header information of the target test vector to be formed in this test determined in the above step S103, the template vector of the test vector is automatically formed, that is, the test vector template information determined in step S104 is used as the template vector, and then based on the vector information of the vector format script file corresponding to each test specification and the preset algorithm, the number of times N that the test vector template needs to be repeated in the target test vector corresponding to each test specification is calculated, and based on the number N, the template vector is automatically modified and then repeated N times below the template vector of the target test vector. Specifically, the modification made to each template vector in the N repetitions can be to modify the template vector repeated N times with the consideration that part of the information in the template vector is increased in sequence according to the binary number, so as to obtain the target test vector automatically formed by the method provided in the embodiment of the present invention as shown in 2.

[0071] See also Figure 3 , Figure 3 FIG. 1 is a schematic diagram of the structure of the automatic generation system of the test vector provided in the embodiment of the present invention. Figure 3 As shown, the automatic generation system of test vectors provided in the embodiment of the present invention can be specifically applied to a test machine including multiple test specifications and multiple output channels, the test vector formats corresponding to the multiple test specifications are all different, and the automatic generation system includes:

[0072] A vector automatic generation file establishment module 310 is used to establish a vector automatic generation file in advance, wherein the vector automatic generation file includes vector format script information corresponding to all test specifications of the test machine, and the vector format script information includes test vector template information and the output channel identifier corresponding thereto;

[0073] A pin self-checking table forming module 320 is used to pre-establish a pin self-checking table, wherein the pin self-checking table includes a mapping relationship between each output channel identifier of the test machine and a test pin identifier connected to the output channel corresponding to the output channel identifier;

[0074] An output channel identification determination module 330 is used to determine the output channel identification of each test pin of the device under test from the pin self-check table based on the configuration information of the multiple test pins of the device under test, and reorder the multiple output channel identifications of the multiple test pins;

[0075] A vector format script information determination module 340 is used to determine the test specification of the device under test and its corresponding vector format script information from the vector automatic generation file based on the output channel identifier of the test pin connection of the device under test;

[0076] The target test vector generation module 350 is used to form a test vector template in the target test vector for testing the device under test based on the test vector template information in the determined vector format script information of the device under test, and based on a preset vector repetition number N and a vector modification strategy, configure N modified test vector templates after the test vector template to generate a target test vector for the device under test.

[0077] Wherein, the vector automatic generation file establishment module also includes:

[0078] A config file reading unit, used to read vector information in a vector format script file config corresponding to each test specification of the test machine, wherein the vector information is test vector template information and an output channel identifier corresponding thereto;

[0079] The vector information aggregation unit is used to aggregate the vector information in each vector format script file config corresponding to all the test specifications of the test machine into a pre-configured vector automatic generation file.

[0080] Furthermore, the pin self-checking table forming module also includes:

[0081] A socket file parsing unit, used for reading and parsing the correspondence between the output channel and the output channel identifier in the output channel file socket of the test machine;

[0082] A test pin mapping relationship determining unit, used to determine a mapping relationship between each of the output channel identifiers and a test pin connected to the output channel corresponding thereto;

[0083] The pin self-checking table forming unit is used to reorder all the output channels from small to large according to their identifiers, and form the pin self-checking table with the mapping relationship between the reordered multiple output channel identifiers and the test pins connected to the corresponding output channels.

[0084] Furthermore, the automatic generation system of the test vector provided in the embodiment of the present invention further includes:

[0085] The vector header information forming module is used to reorder the output channel identifiers connected to the multiple test pins of the device under test from small to large, and use the reordered multiple output channel identifiers as the vector header information of the target test vector.

[0086] In summary, the present invention provides a method for automatically generating test vectors, which comprises: pre-establishing a vector automatic generation file, wherein the vector automatic generation file comprises each vector format script information corresponding to all test specifications of the test machine, wherein the vector format script information comprises test vector template information and an output channel identifier corresponding thereto, pre-establishing a pin self-checking table, wherein the pin self-checking table comprises a mapping relationship between each output channel identifier of the test machine and a test pin identifier connected to the output channel corresponding to the output channel identifier, and determining from the pin self-checking table a mapping relationship between each test pin connection of the device under test and the output channel identifier corresponding to the output channel identifier based on the configuration information of multiple test pins of the device under test. The output channel identifiers of the multiple test pins are connected, and the multiple output channel identifiers of the multiple test pins are reordered; based on the output channel identifiers of the test pins of the device under test, the test specifications of the device under test and the corresponding vector format script information are determined from the vector automatic generation file; based on the test vector template information in the determined vector format script information of the device under test, a test vector template in a target test vector for testing the device under test is formed; and based on a preset vector repetition number N and a vector modification strategy, N modified test vector templates are configured after the test vector template to generate a target test vector for the device under test.

[0087] In the present invention, firstly, the test vector format script information under multiple test specifications in a certain test machine is summarized into the same vector automatic generation file, and then the mapping relationship between each output channel identifier of the test machine and the test pin identifier connected to the output channel corresponding to the output channel identifier is mapped in a pin self-check table. Therefore, when the test specification of the device under test is unknown, the test specification corresponding to the device under test and its corresponding test vector format can be directly and automatically extracted from the vector automatic generation file based on the configuration information of the pins actually connected to the test machine and the reference pin self-check table, and then the target test vector is automatically formed. It first realizes the correspondence between the pins and output channels of the test machine from the horizontal expression of multi-file query to the vertical expression of direct query through only one pin self-check table, which simplifies the test process, reduces the test cost, realizes the automatic generation of test vectors and ultimately improves the test efficiency.

[0088] An embodiment of the present invention further provides an electronic device, which may include a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; the memory is used to store a computer program;

[0089] The processor is used to implement the steps of a method for automatically generating a test vector provided by an embodiment of the present invention when executing a program stored in the memory.

[0090] In addition, the steps of the method for automatically generating test vectors implemented by the processor executing the program stored in the memory are the same as the implementation method mentioned in the aforementioned method embodiment part, and will not be repeated here.

[0091] The communication bus mentioned in the control server can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0092] The communication interface is used for communication between the above network devices and other devices.

[0093] The memory may include a random access memory (RAM) or a non-volatile memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0094] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0095] In another embodiment provided by the present invention, a computer-readable storage medium is also provided, which stores instructions. When the computer-readable storage medium is run on a computer, it enables the computer to execute the steps of the automatic generation method of the test vector described in any of the above embodiments.

[0096] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk Solid State Disk (SSD)), etc.

[0097] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0098] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device, electronic device, and computer-readable storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0099] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A method for automatically generating a test vector, characterized in that: Applied to a test machine including multiple test specifications and multiple output channels, the test vector formats corresponding to the multiple test specifications are all different, and the automatic generation method includes: Pre-establishing a vector automatic generation file, wherein the vector automatic generation file includes each vector format script information corresponding to all test specifications of the test machine, wherein the vector format script information includes test vector template information and an output channel identifier corresponding thereto; Pre-establishing a pin self-check table, the pin self-check table including a mapping relationship between each output channel identifier of the test machine and a test pin identifier connected to the output channel corresponding to the output channel identifier; Based on the configuration information of multiple test pins of the device under test, determine the output channel identifier connected to each test pin of the device under test from the pin self-check table, and reorder the multiple output channel identifiers of the multiple test pins; Based on the output channel identifier of the test pin connection of the device under test, determining the test specification of the device under test and its corresponding vector format script information from the vector automatic generation file; Based on the determined test vector template information in the vector format script information of the device under test, a test vector template in a target test vector for testing the device under test is formed, and based on a preset vector repetition number N and a vector modification strategy, N modified test vector templates are configured after the test vector template to generate a target test vector for the device under test.

2. The method for automatically generating a test vector according to claim 1, wherein: The steps to pre-build the vector auto-generated file include: Reading vector information in the vector format script file config corresponding to each test specification of the test machine, wherein the vector information is test vector template information and an output channel identifier corresponding thereto; The vector information in each vector format script file config corresponding to all the test specifications of the test machine is aggregated into a pre-configured vector automatic generation file.

3. The method for automatically generating a test vector according to claim 1, wherein: The steps to pre-build a pin self-check table include: Read and parse the corresponding relationship between the output channel and the output channel identifier in the output channel file socket of the test machine; Determine a mapping relationship between each of the output channel identifiers and a test pin connected to the output channel corresponding to the output channel; All the output channels are reordered in ascending order according to their identifiers, and the mapping relationship between the reordered output channel identifiers and the test pins connected to the corresponding output channels is formed into the pin self-checking table.

4. The method for automatically generating a test vector according to claim 1, wherein: The step of determining the preset vector repetition number N comprises: Based on the vector information of the vector format script file corresponding to each test specification and a preset algorithm, the number of times N that the test vector template needs to be repeated in the target test vector corresponding to each test specification is calculated.

5. The method for automatically generating a test vector as claimed in claim 4, characterized in that: The target test vector of the device under test also includes vector header information, and the step of forming the vector header information includes: The output channel identifiers connected to the multiple test pins of the device under test are reordered from small to large, and the reordered multiple output channel identifiers are used as vector header information of the target test vector.

6. A system for automatically generating test vectors, characterized in that: Applicable to a test machine including multiple test specifications and multiple output channels, wherein the test vector formats corresponding to the multiple test specifications are all different, the automatic generation system includes: A vector automatic generation file establishment module, used to establish a vector automatic generation file in advance, wherein the vector automatic generation file includes each vector format script information corresponding to all test specifications of the test machine, and the vector format script information includes test vector template information and the output channel identifier corresponding thereto; A pin self-checking table forming module is used to pre-establish a pin self-checking table, wherein the pin self-checking table includes a mapping relationship between each output channel identifier of the test machine and a test pin identifier connected to the output channel corresponding to the output channel identifier; An output channel identification determination module, configured to determine the output channel identification of each test pin of the device under test from the pin self-check table based on the configuration information of the multiple test pins of the device under test, and reorder the multiple output channel identifications of the multiple test pins; A vector format script information determination module, used to determine the test specification of the device under test and its corresponding vector format script information from the vector automatic generation file based on the output channel identifier of the test pin connection of the device under test; A target test vector generation module is used to form a test vector template in a target test vector for testing the device under test based on the test vector template information in the determined vector format script information of the device under test, and based on a preset vector repetition number N and a vector modification strategy, configure N modified test vector templates after the test vector template to generate a target test vector for the device under test.

7. The automatic test vector generation system according to claim 6, characterized in that: The vector automatic generation file establishment module also includes: A config file reading unit, used to read vector information in a vector format script file config corresponding to each test specification of the test machine, wherein the vector information is test vector template information and an output channel identifier corresponding thereto; The vector information aggregation unit is used to aggregate the vector information in each vector format script file config corresponding to all the test specifications of the test machine into a pre-configured vector automatic generation file.

8. The automatic test vector generation system according to claim 6, characterized in that: The pin self-checking table forming module also includes: A socket file parsing unit, used for reading and parsing the correspondence between the output channel and the output channel identifier in the output channel file socket of the test machine; A test pin mapping relationship determining unit, used to determine a mapping relationship between each of the output channel identifiers and a test pin connected to the output channel corresponding thereto; The pin self-checking table forming unit is used to reorder all the output channels from small to large according to their identifiers, and form the pin self-checking table with the mapping relationship between the reordered multiple output channel identifiers and the test pins connected to the corresponding output channels.

9. The automatic test vector generation system according to claim 6, characterized in that: Also includes: The vector header information forming module is used to reorder the output channel identifiers connected to the multiple test pins of the device under test from small to large, and use the reordered multiple output channel identifiers as the vector header information of the target test vector.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for automatically generating test vectors according to any one of claims 1 to 5 are implemented.

Images