Wide bandgap semiconductor device terminal structure and manufacturing method thereof

Abstract

The present application discloses a wide bandgap semiconductor device terminal structure and a manufacturing method thereof, which can be used in the semiconductor field. The terminal structure includes: a main junction embedded in a sandwich epitaxial structure, a field-limiting ring structure, and a cutoff region; the main junction contacts the active region, and the field-limiting ring structure is located between the main junction and the cutoff region; the main junction includes a first auxiliary trench, a first P-type ion-doped region penetrating a second N-type epitaxial layer and a P-type buried layer and embedded in the first N-type epitaxial layer, and a first polysilicon located at a corner position within the first auxiliary trench; the field-limiting ring structure includes multiple second auxiliary trenches, multiple second P-type ion-doped regions penetrating the second N-type epitaxial layer, and second polysilicon located at a corner position within the multiple second auxiliary trenches; and the cutoff region includes a third auxiliary trench, an N-type cutoff region located in the P-type buried layer, and third polysilicon located at a corner position within the third auxiliary trench. Thus, a highly reliable terminal structure is provided for a wide bandgap semiconductor device with a sandwich epitaxial structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a wide bandgap semiconductor device terminal structure and a manufacturing method thereof. Background Art

[0002] In recent years, wide bandgap semiconductor materials such as silicon carbide SiC, gallium nitride GaN, and ultra-wide bandgap semiconductor materials such as gallium oxide Ga2O3 have attracted increasing attention due to their excellent performance in physical properties such as bandgap width, critical breakdown electric field strength, and electron saturation drift velocity. How to use third-generation and fourth-generation semiconductors to manufacture semiconductor devices has attracted increasing attention.

[0003] Currently, wide-bandgap semiconductors are widely used in power electronics due to their lower power loss and higher conversion efficiency in power devices. Furthermore, sandwich epitaxial structures offer excellent results in improving device electrical performance and reducing parasitic effects, making their application in power devices an important optimization direction. In practical applications, field-limiting rings (FLRs) or junction termination extensions (JTEs) are commonly used as terminal structures in semiconductor power devices. However, FLR and JTE structures are sensitive to interface charge and have poor voltage resistance, making device reliability difficult to guarantee. Furthermore, conventional terminal structures are difficult to adapt to power devices based on sandwich epitaxial structures.

[0004] Therefore, how to provide a highly reliable terminal structure for a wide bandgap semiconductor device having a sandwich epitaxial structure becomes a problem that needs to be solved. Summary of the Invention

[0005] Based on the above problems, the present application provides a wide bandgap semiconductor device terminal structure and a manufacturing method thereof, which can provide a high-reliability terminal structure for a wide bandgap semiconductor device with a sandwich epitaxial structure.

[0006] The embodiments of this application disclose the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a wide bandgap semiconductor device terminal structure, which matches an active region based on a sandwich epitaxial structure. The terminal structure includes: a main junction, a field limiting ring structure, and a cutoff region embedded in the sandwich epitaxial structure;

[0008] The sandwich epitaxial structure includes a first N-type epitaxial layer, a P-type buried layer, and a second N-type epitaxial layer stacked in sequence along a first direction; wherein the first N-type epitaxial layer is located on a side close to the substrate, and the second N-type epitaxial layer is located on a side away from the substrate;

[0009] The active region, the main junction, the field limiting ring structure, and the cut-off region are arranged in sequence along a second direction; the main junction contacts the active region, and the field limiting ring structure is located between the main junction and the cut-off region; the second direction is perpendicular to the first direction;

[0010] The main junction includes a first auxiliary trench, a first P-type ion-doped region penetrating the second N-type epitaxial layer and the P-type buried layer and embedded in the first N-type epitaxial layer, and a first polysilicon located at a groove corner inside the first auxiliary trench; the first P-type ion-doped region wraps the first auxiliary trench;

[0011] The field limiting ring structure includes a plurality of second auxiliary trenches, a plurality of second P-type ion-doped regions penetrating the second N-type epitaxial layer, and second polysilicon located at the inner corners of the plurality of second auxiliary trenches; the plurality of second P-type ion-doped regions are arranged at intervals along the second direction; and the second P-type ion-doped regions wrap around the second auxiliary trenches;

[0012] The cut-off region includes a third auxiliary trench, an N-type cut-off region located in the P-type buried layer at a position corresponding to the third auxiliary trench, and a third polysilicon located at a groove corner position inside the third auxiliary trench.

[0013] Optionally, the second P-type ion-doped region penetrates the second N-type epitaxial layer and contacts the P-type buried layer.

[0014] Optionally, the second P-type ion-doped region penetrates the second N-type epitaxial layer and the P-type buried layer, and is embedded in the first N-type epitaxial layer.

[0015] Optionally, a field oxide layer is further provided between the first auxiliary trench and the first polysilicon, between the plurality of second auxiliary trenches and the second polysilicon, and between the third auxiliary trench and the third polysilicon.

[0016] Optionally, one or more of the first polysilicon, the second polysilicon and the third polysilicon are also located at the bottom of the auxiliary trench; the auxiliary trench includes a first auxiliary trench, a second auxiliary trench and a third auxiliary trench.

[0017] Optionally, the cut-off region further includes a P-type shielding layer;

[0018] The P-type shielding layer is located on the second N-type epitaxial layer that is in contact with the bottom of the third auxiliary trench.

[0019] Optionally, the cut-off region further includes a P-type shielding layer;

[0020] The P-type masking layer is located in the second N-type epitaxial layer contacting the bottom and sidewall of the third auxiliary trench.

[0021] Optionally, the second N-type epitaxial layer further has a P-type well region on a side facing away from the substrate.

[0022] Optionally, the first auxiliary trench, the plurality of second auxiliary trenches, and the third auxiliary trench are filled with an interlayer dielectric layer.

[0023] In a second aspect, an embodiment of the present application provides a method for manufacturing a terminal structure of a wide bandgap semiconductor device, wherein the terminal structure matches an active region based on a sandwich epitaxial structure, the method comprising:

[0024] A substrate having a sandwich epitaxial structure is provided; the substrate comprises a substrate, a first N-type epitaxial layer, a P-type buried layer, and a second N-type epitaxial layer stacked in sequence along a first direction, wherein the second N-type epitaxial layer comprises at least a P-type well region of an active area;

[0025] dry etching the side of the second N-type epitaxial layer facing away from the substrate to form a first auxiliary trench, a plurality of second auxiliary trenches, and a third auxiliary trench spaced apart along a second direction; the first auxiliary trench contacts the P-type well region; and the second direction is perpendicular to the first direction;

[0026] forming, by P-type ion implantation, a first P-type ion-doped region surrounding the first auxiliary trench and a second P-type ion-doped region surrounding the second auxiliary trench; the first P-type ion-doped region penetrates the second N-type epitaxial layer and the P-type buried layer and is embedded in the first N-type epitaxial layer; and the second P-type ion-doped region penetrates the second N-type epitaxial layer;

[0027] forming an N-type cutoff region at a position corresponding to the third auxiliary trench in the P-type buried layer by N-type ion implantation;

[0028] Depositing polysilicon inside the first auxiliary trench, the plurality of second auxiliary trenches, and the third auxiliary trench;

[0029] The polysilicon is etched to form a first polysilicon located at a groove corner position in the first auxiliary trench, a second polysilicon located at a groove corner position in a plurality of the second auxiliary trenches, and a third polysilicon located at a groove corner position in the third auxiliary trench.

[0030] Compared with the existing technology, this application has the following beneficial effects:

[0031] The embodiment of the present application provides a terminal structure of a wide bandgap semiconductor device, which terminal structure includes: a main junction, a field limiting ring structure and a cut-off region embedded in a sandwich epitaxial structure; the sandwich epitaxial structure includes a first N-type epitaxial layer, a P-type buried layer and a second N-type epitaxial layer stacked in sequence along a first direction; wherein the first N-type epitaxial layer is located on a side close to the substrate, and the second N-type epitaxial layer is located on a side away from the substrate; the active region, the main junction, the field limiting ring structure and the cut-off region are arranged in sequence along a second direction; the main junction contacts the active region, and the field limiting ring structure is located between the main junction and the cut-off region; the second direction is perpendicular to the first direction; the main junction includes a first auxiliary trench, a trench penetrating the second N-type epitaxial layer and the P-type buried layer, and a trench penetrating the second N-type epitaxial layer and the P-type buried layer. A buried layer is embedded in the first P-type ion-doped region of the first N-type epitaxial layer and the first polysilicon located at the inner corner position of the first auxiliary trench; the first P-type ion-doped region wraps the first auxiliary trench; the field limiting ring structure includes multiple second auxiliary trenches, multiple second P-type ion-doped regions penetrating the second N-type epitaxial layer and the second polysilicon located at the inner corner position of the multiple second auxiliary trenches; the multiple second P-type ion-doped regions are arranged at intervals along the second direction; the second P-type ion-doped region wraps the second auxiliary trench; the cut-off region includes a third auxiliary trench, an N-type cut-off region located in the P-type buried layer at a position corresponding to the third auxiliary trench and the third polysilicon located at the inner corner position of the third auxiliary trench.

[0032] Thus, on the one hand, in the terminal structure, each auxiliary trench assists ion implantation to form a first P-type ion doped region and a second P-type ion doped region, thereby using a smaller ion implantation energy to form a main junction and field limiting ring structure with a deeper implantation depth, which can not only reduce manufacturing costs, but also better reduce the electric field crowding in the active area and improve the breakdown characteristics of the device; on the other hand, the internal groove corner position of each auxiliary trench has polysilicon that can act as a field plate terminal. The field plate terminal structure is combined with the field limiting ring structure, both of which can improve the device electric field distribution and improve the overall characteristics of the device; on the other hand, the third auxiliary trench assists in forming an N-type cutoff region, which can prevent leakage current from leaking along the P-type buried layer to the dicing path and causing device failure, thereby improving the reliability of the device. In addition, the electric field will also be directed to the third auxiliary trench through the N-type cutoff region, and the bottom of the third auxiliary trench is more prone to electric field concentration. In response to this problem, the third polysilicon provided in the embodiment of the present application can better reduce the effect of the edge electric field, and together with the main junction and field limiting ring structure, protect the terminal structure at the end from breakdown, thereby improving the breakdown characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0034] Figure 1 A schematic diagram of a terminal structure of a wide bandgap semiconductor device provided in an embodiment of the present application;

[0035] Figure 2 Schematic diagram of another wide bandgap semiconductor device terminal structure provided in an embodiment of the present application

[0036] Figure 3 A schematic diagram of a terminal structure of another wide bandgap semiconductor device provided in an embodiment of the present application;

[0037] Figure 4 A schematic diagram of a terminal structure of another wide bandgap semiconductor device provided in an embodiment of the present application;

[0038] Figure 5 A schematic diagram of a terminal structure of another wide bandgap semiconductor device provided in an embodiment of the present application;

[0039] Figure 6 A flow chart of a method for manufacturing a terminal structure of a wide bandgap semiconductor device provided in an embodiment of the present application;

[0040] Figure 7 A schematic diagram of the manufacturing process of a wide bandgap semiconductor device terminal structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] The wide bandgap semiconductor device terminal structure and the manufacturing method thereof provided in the present application can be used in the semiconductor field. The above is only an example and does not limit the application field of the wide bandgap semiconductor device terminal structure and the manufacturing method thereof provided in the present application.

[0042] The terms "first", "second", "third" and "fourth" in the specification, claims and drawings of this application are used to distinguish different objects rather than to limit a specific order.

[0043] In the embodiments of this application, words such as "as an example" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described in the embodiments of this application as "as an example" or "for example" should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "as an example" or "for example" is intended to present the relevant concepts in a concrete manner.

[0044] The terms used in the implementation section of this application are only used to explain the specific embodiments of this application and are not intended to limit this application.

[0045] In order to help those skilled in the art better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0046] See also Figure 1 , this figure is a schematic diagram of the terminal structure of a wide bandgap semiconductor device provided in an embodiment of the present application. The terminal structure matches the active area based on the sandwich epitaxial structure. The terminal structure includes: a main junction 100 embedded in the sandwich epitaxial structure, a field limiting ring structure 200 and a cut-off region 300.

[0047] The sandwich epitaxial structure includes a first N-type epitaxial layer 401 , a P-type buried layer 403 and a second N-type epitaxial layer 402 stacked in sequence along a first direction; wherein the first N-type epitaxial layer 401 is located on a side close to the substrate 404 , and the second N-type epitaxial layer 402 is located on a side away from the substrate 404 .

[0048] Optionally, an N-type buffer layer 405 is further provided between the first N-type epitaxial layer 401 and the substrate 404 to reduce lattice mismatch and improve the quality of the sandwich epitaxial structure.

[0049] Optionally, a metal layer is further provided on a side of the substrate 404 facing away from the second N-type epitaxial layer 402 , serving as a drain electrode 406 of the active region.

[0050] The active region 01, main junction 100, field limiting ring structure 200 and cut-off region 300 are arranged in sequence along the second direction; the main junction 100 is in contact with the active region 01, and the field limiting ring structure 200 is located between the main junction 100 and the cut-off region 300. The second direction is perpendicular to the first direction.

[0051] As an example, the active area 01 may include a substrate 404, an N-type buffer layer 405, a first N-type epitaxial layer 401, a P-type buried layer 403, a second N-type epitaxial layer 402, a drain electrode 406, a trench gate electrode 407, a source electrode 408, a P-type well region 409, an N-type source region 410, a P-type source region 411, and an N-type current channel 412.

[0052] Specifically, the drain electrode 406, the substrate 404, the N-type buffer layer 405, the first N-type epitaxial layer 401, the P-type buried layer 403 and the second N-type epitaxial layer 402 are stacked in sequence along the first direction; the P-type well region 409 and the N-type source region 410 are sequentially formed on the side of the second N-type epitaxial layer 402 away from the substrate 404, and the P-type well region 409 wraps the N-type source region 410; the P-type source region 411 runs through the P-type well region 409, the N-type source region 410, the second N-type epitaxial layer 402 and the P-type buried layer 404, and is embedded in the first N-type epitaxial layer 401; the trench gate electrode 407 runs through the P-type well region 409 and the N-type source region 410 is embedded in the second N-type epitaxial layer 402, which may include a gate trench embedded in the second N-type epitaxial layer 402, a gate dielectric layer 4071 located on the sidewall of the gate trench, a gate polysilicon 4072 filling the gate trench, an interlayer dielectric layer 4073 covering the top of the gate polysilicon 4072, and a masking layer 4074 wrapping the corner of the gate trench; the N-type current channel 412 is located in the P-type buried layer 403, corresponding to the position of the gate trench in the first direction; the source electrode 408 is a metal layer covering the surface of the structures such as the trench gate electrode 407, the N-type source region 410 and the P-type source region 411.

[0053] Among them, the P-type source region 411 can be formed by source trench assisted ion implantation to reduce high-energy ion implantation; the source trench can be a single-level trench or a multi-level trench, the inner wall of the source trench is covered with a dielectric layer 4111, and the inside of the source trench is filled with source polysilicon 4112.

[0054] It can be understood that the structure of the active area 01 above is only an example provided in the embodiment of the present application, and does not limit the active area matched with the terminal structure provided in the present application.

[0055] The main junction 100 includes a first auxiliary trench, a first P-type ion-doped region 101 extending through the second N-type epitaxial layer 402 and the P-type buried layer 403 and embedded in the first N-type epitaxial layer 401, and first polysilicon 102 located at a corner within the first auxiliary trench. The first P-type ion-doped region 101 surrounds the first auxiliary trench.

[0056] Specifically, P-type ion implantation can be performed with the assistance of the first auxiliary trench, thereby forming a deeper first P-type ion doped region 101 with lower ion implantation energy, which can not only reduce manufacturing costs, but also better reduce electric field crowding in the active area and improve the breakdown characteristics of the device.

[0057] The field-limiting ring structure 200 includes multiple second auxiliary trenches, multiple second P-type ion-doped regions 201 extending through the second N-type epitaxial layer 402, and second polysilicon 202 located at the corners of the multiple second auxiliary trenches. The multiple second P-type ion-doped regions 201 are spaced apart along the second direction to form a field-limiting ring FLR; the second P-type ion-doped regions 201 surround the second auxiliary trenches.

[0058] Specifically, P-type ion implantation can be performed with the assistance of the second auxiliary trench, thereby forming a deeper second P-type ion doped region 201 with lower ion implantation energy, which can not only reduce manufacturing costs, but also better reduce electric field crowding in the active area and improve the breakdown characteristics of the device.

[0059] Optionally, the ion implantation depth of the second P-type ion doped region 201 can reach the first N-type epitaxial layer 401, and the obtained second P-type ion doped region 201 penetrates the second N-type epitaxial layer 402 and the P-type buried layer 403 and is embedded in the first N-type epitaxial layer 401; or Figure 2 The ion implantation depth of the second P-type ion doped region 201 can reach the P-type buried layer 403 , and the obtained second P-type ion doped region 201 penetrates the second N-type epitaxial layer 402 and contacts the P-type buried layer 403 .

[0060] The stop region 300 includes a third auxiliary trench, an N-type stop region 301 located in the P-type buried layer 403 at a position corresponding to the third auxiliary trench, and a third polysilicon 302 located at a groove corner inside the third auxiliary trench.

[0061] Optionally, the cut-off region 300 further includes a P-type shielding layer 303, which is located on the second N-type epitaxial layer 402 in contact with the bottom of the third auxiliary trench. Specifically, the P-type shielding layer 303 can be formed by P-type ion implantation with the assistance of the third auxiliary trench. The P-type shielding layer 303 can reduce parasitic effects, improve electric field distribution, and enhance the breakdown characteristics of the device.

[0062] Optionally, before forming the polysilicon within the trench, a field oxide layer 413 may be grown on the exposed surface of the second N-type epitaxial layer 402 in the region where the terminal structure is located on the side facing away from the substrate 404. The formed field oxide layer 413 is located between each auxiliary trench and the polysilicon, wherein the auxiliary trenches include a first auxiliary trench, multiple second auxiliary trenches, and a third auxiliary trench. That is, the field oxide layer 413 is located between the first auxiliary trench and the first polysilicon 102, between the multiple second auxiliary trenches and the second polysilicon 202, and between the third auxiliary trench and the third polysilicon 302. This can relieve stress and reduce defects in the device. In addition, the field oxide layer 413 can also control the electric field distribution within the device, thereby optimizing the breakdown characteristics of the device.

[0063] Optionally, the surface of the terminal structure facing away from the substrate 404 is covered by an interlayer dielectric layer 414, and the first auxiliary trench, multiple second auxiliary trenches and the third auxiliary trench are filled with the interlayer dielectric layer 414, thereby preventing leakage at the top of the terminal structure.

[0064] Therefore, the embodiment of the present application provides a high-reliability terminal structure for a wide bandgap semiconductor device with a sandwich epitaxial structure. On the one hand, in the terminal structure, each auxiliary trench assists ion implantation to form a first P-type ion doping region 101 and a second P-type ion doping region 201, so that a main junction 100 and a field limiting ring 200 structure with a deeper implantation depth can be formed using a smaller ion implantation energy, which can not only reduce manufacturing costs, but also better reduce the electric field crowding in the active area and improve the breakdown characteristics of the device; on the other hand, the internal groove corners of each auxiliary trench have polysilicon that can act as a field plate terminal. The field plate terminal structure is combined with the field limiting ring structure, and both can improve the electric field distribution of the device and improve the overall characteristics of the device; on the other hand, the third auxiliary trench assists in forming an N-type cut-off region 301, which can prevent leakage current from leaking along the P-type buried layer 403 to the dicing path to cause device failure, thereby improving the reliability of the device. In addition, the electric field will also point to the third auxiliary trench through the N-type cutoff region 301, and the electric field concentration phenomenon is more likely to occur at the bottom of the third auxiliary trench. In response to this problem, the third polysilicon 302 provided in the embodiment of the present application can better reduce the effect of the edge electric field, and together with the main junction 100 and the field limiting ring structure 200, protect the terminal structure at the end from being broken down, thereby improving the breakdown characteristics of the device.

[0065] See also Figure 3 , this figure is a schematic diagram of another terminal structure of a wide bandgap semiconductor device provided in an embodiment of the present application. The terminal structure matches the active area based on the sandwich epitaxial structure. The terminal structure includes: a main junction 100 embedded in the sandwich epitaxial structure, a field limiting ring structure 200 and a cut-off region 300.

[0066] Among them, the first polysilicon 102 included in the main junction 100 can be located at the groove corner position and bottom of the first auxiliary trench; the second polysilicon 202 included in the field limiting ring structure 200 can be located at the groove corner position and bottom of the second auxiliary trench; the third polysilicon 302 included in the cut-off region 300 can be located at the groove corner position and bottom of the third auxiliary trench.

[0067] In other embodiments provided herein, one or more of the first polysilicon 102, the second polysilicon 202, and the third polysilicon 302 are present both at the corners of the auxiliary trench and at the bottom of the auxiliary trench, while another portion is present only at the corners of the auxiliary trench. In the embodiment of the present application, the auxiliary trench includes a first auxiliary trench, a plurality of second auxiliary trenches, and a third auxiliary trench.

[0068] During the polysilicon etching process, since the morphology of the etched polysilicon is uncertain, in order to ensure the presence of polysilicon at the corner position of the auxiliary trench, the etching amount can be reduced so that polysilicon is retained at the bottom of the auxiliary trench, thereby ensuring that the polysilicon can serve as a field plate terminal structure and can play its role in reducing the edge electric field of the device and improving the breakdown characteristics of the device.

[0069] See also Figure 4 , this figure is a schematic diagram of the terminal structure of another wide bandgap semiconductor device provided in an embodiment of the present application. The terminal structure matches the active area based on the sandwich epitaxial structure. The terminal structure includes: a main junction 100 embedded in the sandwich epitaxial structure, a field limiting ring structure 200 and a cut-off region 300.

[0070] Among them, the cut-off region 300 includes a P-type masking layer 303, which can be formed by ion implantation and is located in the second N-type epitaxial layer 402 in contact with the bottom and sidewall of the third auxiliary trench, thereby wrapping the third auxiliary trench with the P-type masking layer 303, which can better modulate the electric field of the cut-off region 300 and better protect the third auxiliary trench.

[0071] See also Figure 5 , this figure is a schematic diagram of the terminal structure of another wide bandgap semiconductor device provided in an embodiment of the present application. The terminal structure matches the active area based on the sandwich epitaxial structure. The terminal structure includes: a main junction 100 embedded in the sandwich epitaxial structure, a field limiting ring structure 200 and a cut-off region 300.

[0072] In the main junction 100 , the field limiting ring structure 200 and the cut-off region 300 , the second N-type epitaxial layer 402 further has a P-type well region 409 on the side facing away from the substrate 404 , thereby better protecting the surface of the terminal structure facing away from the substrate.

[0073] See also Figure 6 , which is a flow chart of a method for manufacturing a terminal structure of a wide bandgap semiconductor device provided in an embodiment of the present application. The middle terminal structure manufactured by this method matches the active region based on the sandwich epitaxial structure. The method includes:

[0074] S601: providing a substrate having a sandwich epitaxial structure.

[0075] like Figure 7 As shown in (a), the base includes a substrate 404, a first N-type epitaxial layer 401, a P-type buried layer 403 and a second N-type epitaxial layer 402 stacked in sequence along a first direction, wherein the second N-type epitaxial layer 402 includes at least a P-type well region 409 located in the active area 01.

[0076] For example, a P-type well region 409 can be formed on the side of the second N-type epitaxial layer 402 facing away from the substrate 404 through P-type ion implantation. The P-type well region 409 can be formed only in the active region 01 or in both the active region 01 and the terminal structure. Subsequently, an N-type source region 410 can be formed on the side of the P-type well region 409 facing away from the substrate 404 in the active region 01 through N-type ion implantation. The P-type well region 409 surrounds the N-type source region 410.

[0077] Optionally, an N-type buffer layer 405 may be further provided between the first N-type epitaxial layer 401 and the substrate 404 to reduce lattice mismatch and improve the quality of the sandwich epitaxial structure.

[0078] S602 : dry-etching the side of the second N-type epitaxial layer 402 facing away from the substrate 404 to form a first auxiliary trench, a plurality of second auxiliary trenches, and a third auxiliary trench spaced apart along the second direction.

[0079] The first auxiliary trench contacts the P-type well region 409; the second direction is perpendicular to the first direction, such as Figure 7 Middle (b).

[0080] Preferably, the first auxiliary trench, multiple second auxiliary trenches, third auxiliary trenches, source trenches, and gate trenches can be formed simultaneously in the same dry etch, thereby reducing the complexity and manufacturing cost of the terminal structure manufacturing process. With the assistance of the first auxiliary trench, multiple second auxiliary trenches, and third auxiliary trenches, a deeper first P-type ion-doped region 101, second P-type ion-doped region 201, and third P-type ion-doped region 301 can be formed at a lower ion implantation energy, thereby better reducing electric field crowding in the active area and improving the breakdown characteristics of the device.

[0081] Furthermore, the number and depth of the first auxiliary trench, multiple second auxiliary trenches and third auxiliary trenches are consistent with those of the source trench or gate trench, thereby unifying the process conditions for trench etching and further avoiding increasing the process complexity based on the active area manufacturing process.

[0082] S603 : forming a first P-type ion-doped region 101 surrounding the first auxiliary trench and a second P-type ion-doped region 201 surrounding the second auxiliary trench by P-type ion implantation.

[0083] like Figure 7 In (c), the first P-type ion-doped region 101 penetrates the second N-type epitaxial layer 402 and the P-type buried layer 403 and is embedded in the first N-type epitaxial layer 401 ; the second P-type ion-doped region 201 penetrates the second N-type epitaxial layer 402 .

[0084] Optionally, the ion implantation depth of the second P-type ion doped region 201 can reach the first N-type epitaxial layer 401, and the obtained second P-type ion doped region 201 penetrates the second N-type epitaxial layer 402 and the P-type buried layer 403 and is embedded in the first N-type epitaxial layer 401; or Figure 2 The ion implantation depth of the second P-type ion doped region 201 can reach the P-type buried layer 403 , and the obtained second P-type ion doped region 201 penetrates the second N-type epitaxial layer 402 and contacts the P-type buried layer 403 .

[0085] Optionally, while forming the first P-type ion-doped region 101 and the second P-type ion-doped region 201 by P-type ion implantation, the P-type source region 411 can be formed in the same process step with the assistance of the source trench. This can reduce the number of process steps and further avoid increasing the process complexity based on the active region manufacturing process.

[0086] S604 : forming an N-type cutoff region 301 at a position corresponding to the third auxiliary trench in the P-type buried layer 403 by N-type ion implantation.

[0087] Specifically, see Figure 7 In (d), an N-type cutoff region 301 can be formed in the P-type buried layer 403 at a position corresponding to the third auxiliary trench by ion implantation; at the same time, an N-type current channel 412 can be formed in the P-type buried layer 403 at a position corresponding to the gate trench in the same process step, thereby reducing the process steps and further avoiding increasing the process complexity on the basis of the active area manufacturing process.

[0088] Optionally, after forming the N-type cutoff region 301, a masking layer 4074 and / or a P-type masking layer 303 can be formed in the second N-type epitaxial layer 402 that contacts the bottom of the gate trench and / or the third auxiliary trench by ion implantation, thereby protecting the gate trench and / or the third auxiliary trench and improving the breakdown characteristics of the device. The P-type masking layer 303 can contact only the bottom of the trench or both the bottom of the trench and the sidewalls of the trench.

[0089] S605 : depositing polysilicon inside the first auxiliary trench, the plurality of second auxiliary trenches, and the third auxiliary trench.

[0090] Optionally, polysilicon may be deposited simultaneously inside the source trench, the gate trench, the first auxiliary trench, the plurality of second auxiliary trenches, and the third auxiliary trench.

[0091] Alternatively, as Figure 7In step (e), before polysilicon deposition, a field oxide layer 413 can be grown on the exposed surface of the second N-type epitaxial layer 402 in the region where the terminal structure is located on the side facing away from the substrate 404, for example, by thermal oxidation or wet oxidation. The formed field oxide layer 413 is located between the first auxiliary trench and the first polysilicon 102, between the plurality of second auxiliary trenches and the second polysilicon 202, and between the third auxiliary trench and the third polysilicon 302, thereby relieving stress and reducing defects in the device. In addition, the field oxide layer 413 can also control the electric field distribution within the device, thereby optimizing the device's breakdown characteristics.

[0092] S606: Etching polysilicon to form first polysilicon 102 located at a groove corner position in the first auxiliary trench, second polysilicon 202 located at a groove corner position in multiple second auxiliary trenches, and third polysilicon 302 located at a groove corner position in the third auxiliary trench.

[0093] Specifically, if Figure 7 In (f), the deposited polysilicon can be etched by methods such as reactive ion etching and plasma etching, retaining the polysilicon located at the corner positions inside each auxiliary groove and removing the polysilicon deposited at other positions to form the first polysilicon 102, the second polysilicon 202 and the third polysilicon 302.

[0094] Optionally, during the polysilicon etching process, since the morphology of the polysilicon after etching is uncertain, in order to ensure the presence of polysilicon at the corner position of the auxiliary groove, the etching amount can be reduced so that polysilicon is retained at the bottom of the auxiliary groove, thereby ensuring that the polysilicon can serve as a field plate terminal structure and can play its role in reducing the edge electric field of the device and improving the breakdown characteristics of the device.

[0095] Optionally, after the polysilicon is etched, an interlayer dielectric layer can be deposited on the side of the device structure facing away from the substrate 404, and the interlayer dielectric layer is used to fill the auxiliary trenches and cover the side of the device structure facing away from the substrate 404; then, the interlayer dielectric layer is etched to form an interlayer dielectric layer 4073 covering the top of the gate polysilicon 4072 and an interlayer dielectric layer 414 filling the inside of each auxiliary trench and covering the surface of the terminal structure facing away from the substrate 404; finally, the source electrode 408 and the drain electrode 406 are formed by metal deposition.

[0096] Therefore, an embodiment of the present application provides a method for manufacturing a high-reliability terminal structure, and the obtained terminal structure is suitable for a wide bandgap semiconductor device based on a sandwich epitaxial structure. On the one hand, the terminal structure is assisted by ion implantation by various auxiliary trenches to form a first P-type ion doping region 101 and a second P-type ion doping region 201, so that a main junction 100 and a field limiting ring 200 structure with a deeper implantation depth can be formed using a smaller ion implantation energy, which can not only reduce manufacturing costs, but also better reduce the electric field crowding in the active area and improve the breakdown characteristics of the device; on the other hand, the internal groove corners of each auxiliary trench have polysilicon that can act as a field plate terminal. The field plate terminal structure is combined with the field limiting ring structure, and both can improve the electric field distribution of the device and improve the overall characteristics of the device; on the other hand, the third auxiliary trench assists in forming an N-type cut-off region 301, which can prevent leakage current from leaking along the P-type buried layer 403 to the dicing path, causing device failure, thereby improving the reliability of the device. In addition, the electric field will also point to the third auxiliary trench through the N-type cutoff region 301, and the electric field concentration phenomenon is more likely to occur at the bottom of the third auxiliary trench. In response to this problem, the third polysilicon 302 provided in the embodiment of the present application can better reduce the effect of the edge electric field, and together with the main junction 100 and the field limiting ring structure 200, protect the terminal structure at the end from being broken down, thereby improving the breakdown characteristics of the device.

[0097] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referenced to each other. Each embodiment focuses on the differences from other embodiments. For related parts, refer to the partial description of the method embodiment. The terminal structure and method embodiments described above are merely illustrative. Some or all of the modules can be selected according to actual needs to achieve the purpose of the present embodiment. Those of ordinary skill in the art can understand and implement them without inventive effort.

[0098] The above is merely one specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A wide bandgap semiconductor device terminal structure, characterized in that: Matching the active region based on the sandwich epitaxial structure, the terminal structure includes: a main junction, a field limiting ring structure and a cut-off region embedded in the sandwich epitaxial structure; The sandwich epitaxial structure includes a first N-type epitaxial layer, a P-type buried layer, and a second N-type epitaxial layer stacked in sequence along a first direction; wherein the first N-type epitaxial layer is located on a side close to the substrate, and the second N-type epitaxial layer is located on a side away from the substrate; The active region, the main junction, the field limiting ring structure, and the cut-off region are arranged in sequence along a second direction; the main junction contacts the active region, and the field limiting ring structure is located between the main junction and the cut-off region; the second direction is perpendicular to the first direction; The main junction includes a first auxiliary trench, a first P-type ion-doped region penetrating the second N-type epitaxial layer and the P-type buried layer and embedded in the first N-type epitaxial layer, and a first polysilicon located at a groove corner inside the first auxiliary trench; the first P-type ion-doped region wraps the first auxiliary trench; The field limiting ring structure includes a plurality of second auxiliary trenches, a plurality of second P-type ion-doped regions penetrating the second N-type epitaxial layer, and second polysilicon located at the inner corners of the plurality of second auxiliary trenches; the plurality of second P-type ion-doped regions are arranged at intervals along the second direction; and the second P-type ion-doped regions wrap around the second auxiliary trenches; The cut-off region includes a third auxiliary trench, an N-type cut-off region located in the P-type buried layer at a position corresponding to the third auxiliary trench, and a third polysilicon located at a groove corner position inside the third auxiliary trench.

2. The terminal structure according to claim 1, characterized in that: The second P-type ion-doped region penetrates the second N-type epitaxial layer and contacts the P-type buried layer.

3. The terminal structure according to claim 1, characterized in that: The second P-type ion-doped region penetrates the second N-type epitaxial layer and the P-type buried layer, and is embedded in the first N-type epitaxial layer.

4. The terminal structure according to claim 1, characterized in that: A field oxide layer is further provided between the first auxiliary trench and the first polysilicon, between the second auxiliary trenches and the second polysilicon, and between the third auxiliary trench and the third polysilicon.

5. The terminal structure according to claim 1, characterized in that: One or more of the first polysilicon, the second polysilicon and the third polysilicon are also located at the bottom of the auxiliary trench; the auxiliary trench includes a first auxiliary trench, a second auxiliary trench and a third auxiliary trench.

6. The terminal structure according to claim 1, characterized in that: The cut-off region further includes a P-type shielding layer; The P-type shielding layer is located on the second N-type epitaxial layer that is in contact with the bottom of the third auxiliary trench.

7. The terminal structure according to claim 1, characterized in that: The cut-off region further includes a P-type shielding layer; The P-type masking layer is located in the second N-type epitaxial layer contacting the bottom and sidewall of the third auxiliary trench.

8. The terminal structure according to claim 1, characterized in that: The second N-type epitaxial layer further has a P-type well region on a side facing away from the substrate.

9. The terminal structure according to claim 1, characterized in that: An interlayer dielectric layer is filled inside the first auxiliary trench, the plurality of second auxiliary trenches, and the third auxiliary trench.

10. A method for manufacturing a terminal structure of a wide bandgap semiconductor device, characterized in that: The terminal structure is matched to an active region based on a sandwich epitaxial structure, and the method includes: A substrate having a sandwich epitaxial structure is provided; the substrate comprises a substrate, a first N-type epitaxial layer, a P-type buried layer, and a second N-type epitaxial layer stacked in sequence along a first direction, wherein the second N-type epitaxial layer comprises at least a P-type well region of an active area; dry etching the side of the second N-type epitaxial layer facing away from the substrate to form a first auxiliary trench, a plurality of second auxiliary trenches, and a third auxiliary trench spaced apart along a second direction; the first auxiliary trench contacts the P-type well region; and the second direction is perpendicular to the first direction; forming, by P-type ion implantation, a first P-type ion-doped region surrounding the first auxiliary trench and a second P-type ion-doped region surrounding the second auxiliary trench; the first P-type ion-doped region penetrates the second N-type epitaxial layer and the P-type buried layer and is embedded in the first N-type epitaxial layer; and the second P-type ion-doped region penetrates the second N-type epitaxial layer; forming an N-type cutoff region at a position corresponding to the third auxiliary trench in the P-type buried layer by N-type ion implantation; Depositing polysilicon inside the first auxiliary trench, the plurality of second auxiliary trenches, and the third auxiliary trench; The polysilicon is etched to form a first polysilicon located at a groove corner position in the first auxiliary trench, a second polysilicon located at a groove corner position in a plurality of the second auxiliary trenches, and a third polysilicon located at a groove corner position in the third auxiliary trench.

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