A method for manufacturing a VCSEL chip

Abstract

The application relates to a preparation method of a VCSEL chip, which comprises the following steps: sequentially growing a buffer layer, a stop layer, an N contact layer, an N-DBR, an active layer, a P-DBR and a P contact layer on the front surface of a substrate A; performing P contact metal on the P contact layer, etching the epitaxial structure to the stop layer, and performing oxidation on the surface; temporarily bonding the substrate A and a support carrier in a front-to-back manner; thinning the substrate A from the back surface; removing the remaining substrate and the buffer layer of the substrate A except the epitaxial layer; removing the stop layer to obtain a VCSEL epitaxial layer structure temporarily bonded with the support carrier, and exposing the back surface of the N contact layer; preparing an N electrode on the back surface of the N contact layer; preparing a bonding metal layer on the front surface of another substrate B; opposingly arranging the N electrode and the front surface of the substrate B, and permanently bonding the N electrode and the front surface of the substrate B through the bonding metal layer; performing debonding and cleaning; and obtaining the VCSEL chip with high heat dissipation effect. The method can effectively improve the heat dissipation effect of the VCSEL chip and has a smaller series resistance.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically a method for fabricating a VCSEL chip. Background Technology

[0002] VCSEL (Vertical-cavity surface-emitting laser) is a type of laser whose emission direction is perpendicular to the substrate surface. It boasts advantages such as low threshold current, high quantum efficiency, large modulation bandwidth, and low energy consumption, making it promising for applications in atomic clocks, optical communication, and solid-state laser pumping. Because VCSELs use a diffuse-reflector beam backlight (DBR) as the laser cavity mirror, their active region is very small. This reduction in size makes heat dissipation in the active region a challenge. During operation, a significant amount of heat is generated, and the accumulation of heat in the active region can degrade threshold current, threshold voltage, and output power, thereby reducing device efficiency, stability, and even damaging the chip. Furthermore, with the increasing demand for higher-power laser chips in applications such as lidar and security lighting, even higher requirements are being placed on the heat dissipation design of VCSELs. Summary of the Invention

[0003] The purpose of this invention is to solve the problem of ineffective heat dissipation in current VCSEL applications. It proposes a method for fabricating VCSEL chips based on epitaxial layer peeling and bonding transfer, which can effectively improve the heat dissipation capability of the device and enhance its overall performance.

[0004] The technical solution for achieving the objective of this invention is: a method for fabricating a VCSEL chip, comprising the following steps:

[0005] 1) A buffer layer, a stop layer, an N-contact layer, an N-DBR, an active layer, a P-DBR, and a P-contact layer are sequentially grown on the front side of substrate A;

[0006] 2) Create a P-contact metal above the P-contact layer, then etch the epitaxial structure to the stop layer to form a mesa-type VCSEL device structure, and oxidize its surface;

[0007] 3) Spin-coat a temporary adhesive onto the surface of substrate A to cover the device structure;

[0008] 4) Temporarily bond substrate A and the support substrate face to face;

[0009] 5) Thin the substrate A, which is temporarily bonded to the support carrier, starting from the back side;

[0010] 6) Remove the remaining substrate and buffer layer (except for the epitaxial layer) of substrate A, which is temporarily bonded to the support substrate, to expose the back side of the stop layer;

[0011] 7) Remove the stop layer to obtain a VCSEL epitaxial layer structure temporarily bonded to the support substrate, and expose the back side of the N contact layer;

[0012] 8) Fabricate an N electrode on the back side of the N contact layer;

[0013] 9) A bonding metal layer is prepared on the front side of another high thermal conductivity substrate B;

[0014] 10) The back N electrode of the VCSEL epitaxial layer, which is temporarily bonded to the support substrate, is placed face-to-face with the front side of the B substrate, and permanent bonding is performed through the bonding metal layer;

[0015] 11) Debond the permanent bond structure formed between the support carrier, substrate B, and VCSEL epitaxial layer, and clean it;

[0016] 12) A VCSEL chip formed on a high thermal conductivity substrate B is obtained.

[0017] Furthermore, the substrate A material in step 1) includes, but is not limited to, InP, GaAs, or GaN, the thickness of the substrate A is between 100 μm and 1000 μm, the stop layer is InGaAs, InGaP, AlN, or InGaAsP, and the thickness of the VCSEL epitaxial layer is between 500 nm and 15 μm.

[0018] Furthermore, in step 2), the P electrode material is TiPtAu, WTiAuTi, or NiAlAu, the electrode thickness is 50nm to 1000nm, the etching gas is chlorine-based or fluorine-based, and the oxidation method is wet or dry oxidation.

[0019] Furthermore, the adhesive in step 3) is a polymer, including but not limited to photoresist, high-temperature wax or BCB, and the thickness of the adhesive is 1 μm to 40 μm.

[0020] Furthermore, the support substrate in step 4) includes, but is not limited to, one of sapphire, silicon, silicon carbide or aluminum nitride wafers, the thickness of the support substrate is 300μm-1200μm, the temporary bonding temperature is 90-230℃, the pressure is 10MPa-50MPa, and the time is 10-60 minutes.

[0021] Furthermore, the substrate thinning method in step 5) is any one or more of mechanical grinding, mechanical polishing, and chemical polishing, and the remaining substrate thickness after thinning is not less than 10 μm and not more than 120 μm.

[0022] Furthermore, the method for removing the remaining substrate in step 6) is wet etching or dry etching, and the ratio of the removal rate of the substrate to the removal rate of the stop layer material is between 5:1 and 500:1.

[0023] Furthermore, the removal method of the stop layer in step 7) is wet etching or dry etching, and the ratio of the removal rate of the stop layer to the N contact layer material is between 5:1 and 500:1.

[0024] Furthermore, in step 8), the N electrode material is AuGeNiAu, TiPtAu, WTiAuTi, or NiPdAu, and the electrode thickness is 50 nm to 1000 μm.

[0025] Furthermore, the substrate B in step 9) includes, but is not limited to, one of silicon carbide, aluminum nitride, and diamond wafer, and the thickness of substrate B is between 100 μm and 1000 μm; the bonding metal layer includes, but is not limited to, TiAu, TiPtAu, WTiAu, AuSn, or AuIn, and the thickness of the bonding metal layer is between 100 nm and 3 μm.

[0026] Furthermore, the permanent bonding method in step 10) includes, but is not limited to, one of eutectic bonding, hot-press bonding, activated bonding and direct bonding, with a bonding temperature of room temperature to 300°C, a bonding time of 5 minutes to 2 hours, and a bonding pressure of 200N to 50000N.

[0027] Furthermore, the debonding methods in step 11) include, but are not limited to, thermal debonding, laser debonding, and gas debonding; the cleaning solvents include, but are not limited to, acetone, alcohol, or isopropanol.

[0028] The method for fabricating a VCSEL chip with high heat dissipation efficiency of the present invention has at least the following advantages: 1) Removing the original semiconductor epitaxial substrate and directly leading out the N electrode through an extremely low resistivity metal bonding layer reduces the series resistance introduced by the semiconductor substrate in the original device, which helps to improve device performance; 2) Removing the original substrate with low thermal conductivity and bonding it to a high thermal conductivity substrate with a high thermal conductivity metal can significantly improve heat dissipation efficiency, which helps to improve the laser output power, improve the purity of the emission spectrum, and improve the overall performance of the VCSEL laser; 3) The VCSEL chip fabricated by this method has the advantages of simple structure, convenient process implementation, and excellent heat dissipation efficiency. Attached Figure Description

[0029] Figure 1 It is a structure in which a buffer layer, a stop layer, and a VCSEL epitaxial layer are grown in one step on the front side of substrate A.

[0030] Figure 2 The device structure, such as the P electrode and VCSEL mesa, is fabricated on the front side of substrate A.

[0031] Figure 3 The adhesive is spin-coated onto the front side of substrate A, which has a completed mesa structure.

[0032] Figure 4 This involves temporarily bonding the substrate A, after spin-coating the adhesive, to the support carrier.

[0033] Figure 5 The back side of the temporarily bonded substrate A is thinned.

[0034] Figure 6 This involves removing the remaining substrate and buffer layer.

[0035] Figure 7 This involves removing the buffer layer and the stop layer.

[0036] Figure 8 The N electrode is fabricated on the back side of the N contact layer.

[0037] Figure 9 The process involves permanently bonding the N-electrode on the back side of the VCSEL epitaxial layer to the front side of a substrate B on the other side, where a metal bonding layer is fabricated.

[0038] Figure 10 The permanent bonding structure formed by the support carrier, substrate B, and VCSEL epitaxial layer is debonded and cleaned to obtain a VCSEL wafer with only the epitaxial layer film bonded to substrate B.

[0039] Reference numerals: 1-Substrate A; 2-Buffer layer; 3-Stop layer; 4-VCSEL epitaxial layer composed of N-contact layer, N-DBR, active layer, P-DBR and P-contact layer; 5-P electrode; 6-Temporary adhesive; 7-Supporting substrate; 8-N electrode; 9-Metal layer on substrate B; 10-Substrate B. Detailed Implementation

[0040] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0041] A method for fabricating a VCSEL chip includes the following steps:

[0042] 1) A buffer layer 2, a stop layer 3, an N-contact layer, an N-DBR, an active layer, a P-DBR, and a P-contact layer are sequentially grown on the front side of substrate A1, wherein the N-contact layer, N-DBR, active layer, P-DBR, and P-contact layer constitute the VCSEL epitaxial layer 4; wherein the substrate A material includes, but is not limited to, InP, GaAs, or GaN, the thickness of substrate A is from 100μm to 1000μm, the stop layer is InGaAs, InGaP, AlN, or InGaAsP, and the thickness of the VCSEL epitaxial layer is from 500nm to 15μm. Figure 1 As shown.

[0043] 2) A P-contact metal is formed above the P-contact layer. Then, the P-contact layer, P-DBR, active layer, N-DBR, and N-contact layer are sequentially etched from the top surface, stopping at the stop layer to form a mesa-type VCSEL device structure. The surface is then oxidized. The P-electrode 5 material is TiPtAu, WTiAuTi, or NiAlAu, with an electrode thickness of 50 nm to 1000 nm. The etching gas is a chlorine-based or fluorine-based gas, and the oxidation method is wet or dry oxidation. Figure 2 As shown.

[0044] 3) A temporary adhesive 6 is spin-coated onto the surface of substrate A, where a mesa-type VCSEL device structure has been formed, to cover the device structure. The adhesive is a polymer, including but not limited to photoresist, high-temperature wax, or BCB. The thickness of the adhesive is 1 μm to 40 μm. Figure 3 As shown.

[0045] 4) Temporarily bond substrate A and support carrier 7 face to face, wherein the support carrier is, but is not limited to, one of sapphire, silicon, silicon carbide, or aluminum nitride wafers, the thickness of the support carrier is 300μm-1200μm, the temporary bonding temperature is 90-230℃, the pressure is 10MPa-50MPa, and the time is 10-60 minutes. Figure 4 As shown.

[0046] 5) Thin the substrate A, which is temporarily bonded to the support carrier, starting from the back side. The substrate thinning method is any one or more of mechanical grinding, mechanical polishing, and chemical polishing. The remaining substrate thickness after thinning is not less than 10 μm and not more than 120 μm. Figure 5 As shown.

[0047] 6) Remove the remaining substrate and buffer layer (excluding the epitaxial layer) from the substrate A temporarily bonded to the support wafer, exposing the back side of the stop layer. The method for removing the remaining substrate and buffer layer is wet etching or dry etching, and the ratio of the removal rate of the substrate to the stop layer material is between 5:1 and 500:1. Figure 6 As shown.

[0048] 7) Remove the stop layer to obtain the VCSEL epitaxial layer structure temporarily bonded to the support substrate, exposing the back side of the N-contact layer. The stop layer is removed by wet etching or dry etching, and the ratio of the removal rate of the stop layer to the N-contact layer material is between 5:1 and 500:1. Figure 7 As shown;

[0049] 8) An N electrode 8 is fabricated on the back side of the N contact layer, wherein the N electrode material is AuGeNiAu, TiPtAu, WTiAuTi, or NiPdAu, and the electrode thickness is 50 nm to 1000 nm. Figure 8 As shown.

[0050] 9) A bonding metal layer 9 is prepared on the front side of another high thermal conductivity substrate B10, wherein the substrate B includes, but is not limited to, one of silicon carbide, aluminum nitride, and diamond wafer, the thickness of the substrate B is from 100 μm to 1000 μm, and the bonding metal layer includes, but is not limited to, TiAu, TiPtAu, WTiAu, AuSn or AuIn, the thickness of the bonding metal layer is from 100 nm to 3 μm.

[0051] 10) The N-electrode on the back side of the VCSEL epitaxial layer, temporarily bonded to the support substrate, is placed face-to-face with the front side of the B substrate, and permanently bonded using a bonding metal layer. The permanent bonding method includes, but is not limited to, eutectic bonding, thermo-press bonding, activated bonding, and direct bonding. The bonding temperature is from room temperature to 300°C, the bonding time is from 5 minutes to 2 hours, and the bonding pressure is from 200 N to 50,000 N. Figure 9 As shown.

[0052] 11) Debond the permanent bond structure formed between the support carrier, substrate B, and the VCSEL epitaxial layer, and clean it. The debonding methods include, but are not limited to, thermal debonding, laser debonding, and gas debonding. Cleaning solvents include, but are not limited to, acetone, alcohol, or isopropanol. Figure 10 As shown.

[0053] 12) A VCSEL chip with efficient heat dissipation is obtained on a high thermal conductivity substrate B, such as... Figure 10 As shown, the total thermal resistance of the device is reduced by more than 30% compared to the original substrate.

[0054] The present invention will now be described in detail with reference to the embodiments.

[0055] Example

[0056] A method for fabricating a VCSEL chip includes the following steps:

[0057] (1) Epitaxial layer structures such as InGaP, AlGaAs, GaAs N-DBR, active layer, P-DBR, and P contact layer are sequentially grown on GaAs substrate wafer. The InGaP layer is 100nm thick and the total thickness of the VCSEL epitaxial functional layer is about 2μm.

[0058] (2) Deposit 20nm Ti+50nm Pt+50nm Au above the P contact layer as the P contact layer, and then use the P contact layer as a mask to etch the VCSEL epitaxial functional layer with fluorine-based gas until the InGaP stop layer stops.

[0059] (3) Spin-coat a layer of HT10.10 with a thickness of about 20 μm on the GaAs substrate wafer as a temporary adhesive. The spin-coating speed is 1500 rpm, the spin-coating time is 60 s, the pre-baking temperature is 160 ℃, and the time is 2 minutes.

[0060] (4) Place the GaAs VCSEL wafer coated with temporary adhesive face to face with the sapphire substrate and put it into the die bonder for temporary bonding. The bonding process parameters are: temperature 180℃, bonding time 20 minutes, and bonding pressure 20MPa.

[0061] (5) The back side of the GaAs VCSEL wafer temporarily bonded to the sapphire substrate is thinned to 50 μm by mechanical grinding.

[0062] (6) Using a solution with a ratio of H2SO4:H2O2:H2O (1:2:5), the remaining GaAs substrate and buffer layer are etched until the InGaP stop layer is reached.

[0063] (7) Use a solution with a ratio of HCl:H3PO4:H2O2 (1:10:1) to etch the 100nm InGaP stop layer.

[0064] (8) 100 nm AuGeNi+Au was deposited on the back side of the VCSEL structure after removing the stop layer and exposing the N contact layer by evaporation.

[0065] (9) A 1μm thick bonding metal layer is formed on the surface of a diamond substrate wafer by electroplating, and it is also brought out as an N electrode test block.

[0066] (10) The back side of the GaAs VCSEL wafer after removing the substrate is placed face to face with the front side of the diamond substrate. The VCSEL device structure is aligned with the metal pattern on the diamond substrate by using an alignment bonding device. Then, it is placed in a bonding machine for permanent bonding. The bonding process parameters are: temperature 300℃, bonding time 60 minutes, and bonding pressure 4000MPa.

[0067] (11) The temporary carrier, the bonded GaAs VCSEL wafer and the diamond wafer are placed face up on the heating stage and heated at 250°C. The temporary carrier is separated by hot sliding peeling method and cleaned with adhesive remover, acetone and alcohol.

[0068] After the above steps, the fabrication of a VCSEL chip with excellent heat dissipation, integrated onto a high thermal conductivity diamond substrate, is achieved.

[0069] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a VCSEL chip, characterized in that, Includes the following steps: 1) A buffer layer, a stop layer, an N-contact layer, an N-DBR, an active layer, a P-DBR, and a P-contact layer are sequentially grown on the front side of substrate A; 2) Create a P-contact metal above the P-contact layer, then etch the epitaxial structure to the stop layer to form a mesa-type VCSEL device structure, and oxidize its surface; 3) Spin-coat a temporary adhesive onto the surface of substrate A to cover the device structure; 4) Temporarily bond substrate A and the support substrate face to face; 5) Thin the substrate A, which is temporarily bonded to the support carrier, starting from the back side; 6) Remove the remaining substrate and buffer layer (except for the epitaxial layer) of substrate A, which is temporarily bonded to the support substrate, to expose the back side of the stop layer; 7) Remove the stop layer to obtain a VCSEL epitaxial layer structure temporarily bonded to the support substrate, exposing the back side of the N-contact layer; 8) Fabricate an N electrode on the back side of the N contact layer; 9) A bonding metal layer is fabricated on the front side of another high thermal conductivity substrate B; 10) The back N electrode of the VCSEL epitaxial layer, which is temporarily bonded to the support substrate, is placed face-to-face with the front of the B substrate, and permanent bonding is performed through the bonding metal layer; 11) Debond the permanent bond structure formed between the support carrier, substrate B, and VCSEL epitaxial layer, and clean it; 12) A VCSEL chip formed on a high thermal conductivity substrate B is obtained.

2. The method for fabricating a VCSEL chip according to claim 1, characterized in that, In step 1), the substrate A is made of InP, GaAs, or GaN, the thickness of the substrate A is between 100 μm and 1000 μm, the stop layer is made of InGaAs, InGaP, AlN, or InGaAsP, and the thickness of the VCSEL epitaxial layer is between 500 nm and 15 μm.

3. The method for fabricating a VCSEL chip according to claim 1, characterized in that, In step 2), the P contact layer material is TiPtAu, WTiAuTi, or NiAlAu, the electrode thickness is 50nm to 1000nm, the etching gas is chlorine-based or fluorine-based, and the oxidation method is wet or dry oxidation.

4. The method for fabricating a VCSEL chip according to claim 1, characterized in that, The adhesive mentioned in step 3) is a polymer, selected from photoresist, high-temperature wax or BCB, and the thickness of the adhesive is 1 μm to 40 μm.

5. The method for fabricating a VCSEL chip according to claim 1, characterized in that, In step 4), the support substrate is one of sapphire, silicon, silicon carbide or aluminum nitride wafers, the thickness of the support substrate is 300μm-1200μm, the temporary bonding temperature is 90-230℃, the pressure is 10MPa-50MPa, and the time is 10-60 minutes.

6. The method for fabricating a VCSEL chip according to claim 1, characterized in that, The substrate thinning method described in step 5) is any one or more of mechanical grinding, mechanical polishing, and chemical polishing. The remaining substrate thickness after thinning is not less than 10 μm and not more than 120 μm.

7. The method for fabricating a VCSEL chip according to claim 1, characterized in that, The method for removing the remaining substrate in step 6) is wet etching or dry etching, and the ratio of the removal rate of the substrate to the removal rate of the stop layer material is between 5:1 and 500:

1.

8. The method for fabricating a VCSEL chip according to claim 1, characterized in that, In step 7), the removal method of the stop layer is wet etching or dry etching, and the ratio of the removal rate of the stop layer and the N contact layer material is between 5:1 and 500:

1.

9. The method for fabricating a VCSEL chip according to claim 1, characterized in that, The N electrode material mentioned in step 8) is AuGeNiAu, TiPtAu, WTiAuTi or NiPdAu, and the electrode thickness is 50nm to 1000nm; In step 9), the substrate B includes, but is not limited to, one of silicon carbide, aluminum nitride, and diamond wafer, and the thickness of the substrate B is between 100 μm and 1000 μm; the bonding metal layer includes, but is not limited to, TiAu, TiPtAu, WTiAu, AuSn, or AuIn, and the thickness of the bonding metal layer is between 100 nm and 3 μm.

10. The method for fabricating a VCSEL chip according to claim 1, characterized in that, The permanent bonding method described in step 10) is one of eutectic bonding, hot-press bonding, activated bonding and direct bonding, with a bonding temperature of room temperature to 300°C, a bonding time of 5 minutes to 2 hours, and a bonding pressure of 200N to 50000N. The debonding methods described in step 11) include thermal debonding, laser debonding, and gas debonding; the cleaning solvent is acetone, alcohol, or isopropanol.

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