High-efficiency, high-precision, low-delay successive approximation analog-to-digital converter based on prequantization

Abstract

The present invention discloses a high-efficiency, high-precision, low-delay successive approximation analog-to-digital converter based on pre-quantization, comprising: a digital-to-analog conversion capacitor array, a detection quantization module, a sampling noise elimination module and a successive approximation quantization module; the digital-to-analog conversion capacitor array is used for sampling and realizing the successive approximation process, and includes a main capacitor and a pre-quantization capacitor; in the second sampling stage of storing sampling noise, when the input signal swing is greater than a preset swing threshold, the detection quantization module controls the pre-quantization capacitor to reduce the input signal swing; the sampling noise elimination module eliminates the sampling noise, and the successive approximation quantization module performs quantization to generate a quantization result. The present invention improves the energy efficiency of the high-precision, low-delay successive approximation analog-to-digital converter, reduces power consumption and area overhead, and has good overall performance.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog-to-digital converters, and in particular relates to a high-efficiency, high-precision, low-delay successive approximation analog-to-digital converter based on pre-quantization. Background Art

[0002] Analog to Digital Converter (ADC) plays a key role in large-scale integrated circuits as a bridge between the physical world and digital circuits. For portable medical devices, especially instruments for medical health management, such as electrocardiograms, electroencephalograms and other equipment, high-precision and low-latency ADCs are needed to ensure the accuracy and timeliness of data; and with the development of industrial automation and automotive electronics, various sensors used for monitoring and control processes in sensor data acquisition require high-precision and low-latency ADCs to achieve real-time data acquisition and processing. The wide application of high-precision and low-latency analog-to-digital converters in multiple fields and the rapid development of technology have made them a key component in modern electronic systems.

[0003] Among various ADCs with different performance characteristics, the Successive Approximation Register (SAR) ADC is one of the specific implementation methods of high-precision and low-latency analog-to-digital converters. It has the best low latency and high energy efficiency characteristics in the field of high-precision, medium sampling rate analog-to-digital converters and has received widespread attention.

[0004] As the requirements for high precision and low latency of SAR ADCs increase, their power consumption also increases. The power consumption and accuracy of SAR ADCs are affected by the thermal noise generated during sampling. In order to improve accuracy, it is usually necessary to increase the size of its internal capacitor array to suppress thermal noise and improve resolution, but this is accompanied by an increase in area and power consumption. At the same time, increasing the size of the capacitor also brings challenges to the ADC input driver and reference buffer.

[0005] The sampling noise elimination technology can achieve the goal of reducing the size of the ADC capacitor without introducing sampling noise, reducing ADC noise, power consumption and chip area. The sampling noise elimination technology eliminates the sampling noise by amplifying the input signal and sampling noise through the operational amplifier at the noise storage stage and storing them on the noise storage capacitor. However, the output swing of the operational amplifier is limited. In order to avoid the saturation of the operational amplifier at this stage, the storage time of the sampling noise needs to be reduced. Therefore, the settling time of the operational amplifier will also be shortened, the bandwidth requirements of the circuit will become higher, and the power consumption of the comparator will increase. At the same time, the gain of the operational amplifier will also be limited, and the noise attenuation effect of the noise storage capacitor will also be reduced.

[0006] Therefore, the current SAR ADC based on sampling noise cancellation technology has low ADC energy efficiency due to the trade-off between the operational amplifier's operating time and swing in the secondary sampling stage. Summary of the invention

[0007] The embodiment of the present invention provides a high-efficiency, high-precision, low-latency successive approximation analog-to-digital converter based on pre-quantization, which can solve the problem of low ADC energy efficiency due to the compromise between the operating time and swing of the operational amplifier in the secondary sampling stage in the current SAR ADC based on sampling noise elimination technology.

[0008] In a first aspect, an embodiment of the present invention provides a high-efficiency, high-precision, low-latency successive approximation analog-to-digital converter based on prequantization, the analog-to-digital converter comprising:

[0009] A digital-to-analog conversion capacitor array, the digital-to-analog conversion capacitor array includes a main capacitor and a pre-quantization capacitor, one end of the main capacitor and the pre-quantization capacitor are respectively connected to the ground terminal, the common mode voltage terminal and the reference voltage terminal through a plurality of first switches, and the other ends are connected to the input terminal of the detection quantization module and the sampling noise elimination module, the main capacitor is used to sample the input signal in the first sampling stage to obtain a sampling signal, and is used as a digital-to-analog conversion capacitor for quantization in the quantization stage, and the pre-quantization capacitor is used to control the input signal swing in the second sampling stage;

[0010] A detection and quantization module, wherein a first output end of the detection and quantization module is connected to a first input end of the digital-to-analog conversion capacitor array, a second output end of the detection and quantization module is connected to a first input end of the successive approximation quantization module, and the detection and quantization module is used to detect the input signal swing through the sampling signal in the second sampling stage, and generate a first switch control signal and a pre-quantization codeword when the input signal swing is greater than a preset swing threshold; wherein the first switch control signal is used to control a first switch connected to the pre-quantization capacitor to reduce the input signal swing;

[0011] A sampling noise elimination module, wherein the output end of the sampling noise elimination module is connected to the second input end of the successive approximation quantization module, and the sampling noise elimination module is used to store the first sampling noise generated by the digital-to-analog conversion capacitor array in the second sampling phase, and eliminate the first sampling noise and attenuate the second sampling noise in the quantization phase to obtain a signal after the sampling noise is eliminated;

[0012] A successive approximation quantization module, wherein the output end of the successive approximation quantization module is connected to the second input end of the digital-to-analog conversion capacitor array, and the successive approximation quantization module is used to control the digital-to-analog conversion capacitor array to implement a successive approximation process in the quantization stage, quantize the signal after sampling noise elimination to obtain a quantized digital codeword, and output the quantization result of the input signal according to the quantized digital codeword or the quantized digital codeword and the pre-quantized codeword.

[0013] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: since the present invention sets a pre-quantization capacitor in the DAC capacitor array and sets a detection quantization module in the analog-to-digital converter, when the swing of the input signal is large in the second sampling stage of storing noise, the detection quantization module can generate a first switch control signal to control the pre-quantization capacitor and reduce the swing of the input signal; therefore, the analog-to-digital converter provided by the present invention shortens the sampling time without considering the saturation factor of the operational amplifier in the sampling stage; thereby, a series of problems caused by the shortening of the sampling time, such as higher bandwidth requirements, higher comparator power consumption, and worse noise attenuation effect, can be avoided, thereby improving the performance of the analog-to-digital converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A schematic diagram of the structure of a high-efficiency, high-precision, low-delay successive approximation analog-to-digital converter based on pre-quantization provided by the present invention;

[0015] Figure 2 A schematic diagram of the specific structure of a high-efficiency, high-precision, low-latency successive approximation analog-to-digital converter based on prequantization provided by an embodiment of the present invention;

[0016] Figure 3 A schematic diagram of the working timing of a second switch and a third switch provided in an embodiment of the present invention.

[0017] Reference numerals:

[0018] 1: digital-to-analog conversion capacitor array; C1: main capacitor; C2: pre-quantization capacitor; S1: first switch; 2: detection quantization module; 3: sampling noise elimination module; 31: pre-amplifier; C3: noise storage capacitor; S2: second switch; S3: third switch; 4: successive approximation quantization module; 41: latch; 42: successive approximation logic module; 43: digital code processing module; 5: sampling module. DETAILED DESCRIPTION

[0019] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0020] Example 1

[0021] Figure 1 A schematic structural diagram of a high-efficiency, high-precision, low-delay successive approximation analog-to-digital converter based on pre-quantization provided by the present invention is shown.

[0022] As an example but not limitation, the analog-to-digital converter may include a digital-to-analog converter (DAC) capacitor array 1 , a detection quantization module 2 , a sampling noise elimination module 3 and a successive approximation quantization module 4 .

[0023] For example, see Figure 1 The output end of the DAC capacitor array 1 is connected to the input end of the detection quantization module 2 and the sampling noise elimination module 3. The first output end of the detection quantization module 2 is connected to the first input end of the DAC capacitor array 1, and the second output end is connected to the first input end of the successive approximation quantization module 4. The output end of the sampling noise elimination module 3 is connected to the second input end of the successive approximation quantization module 4. The output end of the successive approximation quantization module 4 is connected to the second input end of the DAC capacitor array 1.

[0024] In some embodiments, the DAC capacitor array 1 may include a plurality of main capacitors C1 and pre-quantization capacitors C2 .

[0025] Exemplarily, one end of the main capacitor C1 and the pre-quantization capacitor C2 can be used as the input end of the DAC capacitor array 1, and connected to the ground end, the common mode voltage end and the reference voltage end through a plurality of first switches S1. The other end of the main capacitor C1 and the pre-quantization capacitor C2 can be used as the output end of the DAC capacitor array 1 and connected to the input end of the detection quantization module 2 and the sampling noise elimination module 3.

[0026] Optionally, the first switch S1 may be a bottom plate switch.

[0027] In a possible implementation, the conversion process of the analog-to-digital converter may include three stages in sequence: a first sampling stage, a second sampling stage, and a quantization stage.

[0028] Specifically, in the first sampling stage, the main capacitor C1 in the DAC capacitor array 1 samples the input signal to obtain a sampling signal. In the quantization stage, the main capacitor C1 can also be used as a digital-to-analog conversion capacitor for quantization. In the second sampling stage, the detection and quantization module 2 can detect the input signal swing through the sampling signal, and generate a first switch control signal and a pre-quantization codeword when the input signal swing is greater than a preset swing threshold. The first switch control signal is transmitted to the DAC capacitor array 1, and the DAC capacitor array 1 controls the first switch connected to the pre-quantization capacitor C2 to reduce the input signal swing. The pre-quantization codeword (see Figure 1 The Dout r in the sample is transmitted to the successive approximation quantization module 4. At the same time, the sampling noise elimination module 3 can store the first sampling noise generated by the DAC capacitor array 1 during sampling in the second sampling stage based on the sampling noise elimination technology. In the quantization stage, the sampling noise elimination module 3 can eliminate the first sampling noise and attenuate the second sampling noise, and then output the signal after the sampling noise is eliminated. The successive approximation quantization module 4 can quantize the signal after the sampling noise is eliminated to obtain a quantized digital codeword, and then output the quantization result of the input signal according to the quantized digital codeword or according to the quantized digital codeword and the pre-quantized codeword (see Figure 1 Dout in .

[0029] For example, if the input signal swing is always less than the preset swing threshold, the detection quantization module 2 does not generate the first switch control signal and the pre-quantization codeword, and the successive approximation quantization module 4 only needs to quantize the signal after the sampling noise is eliminated, and output the quantized digital codeword as the quantization result of the input signal. If the switch control signal and the pre-quantization codeword are generated in the second sampling stage, the successive approximation quantization module 4 needs to quantize the signal after the pre-sampling noise is eliminated, and unify the pre-quantization codeword and the quantized digital codeword into a segment of digital codewords as the quantization result of the input signal.

[0030] In one example, the preset swing threshold may include multiple thresholds, each threshold corresponding to one or more pre-quantization capacitors. When the input swing signal is greater than the i-th threshold, the pre-quantization capacitor corresponding to the i-th threshold may be controlled to reduce the input signal swing, where i is a positive integer.

[0031] It should be understood that the previous level threshold is smaller than the current level threshold. When the input swing signal is larger than the (i+1) level threshold, it is naturally also larger than the i-th level threshold.

[0032] For example, i=5, the first level threshold corresponds to pre-quantization capacitors #5 and #6, and the second level threshold corresponds to pre-quantization capacitor #8; when the input signal swing is greater than the second level threshold and less than the third level threshold, pre-quantization capacitors #5, #6 and #8 can be turned on.

[0033] In another example, the preset swing threshold may be a single value corresponding to one or more pre-quantized capacitors. That is, the weight of the pre-quantized capacitor corresponding to the preset swing threshold is equal to the sum of the weights of the remaining pre-quantized capacitors. If the input signal swing is greater than the preset swing threshold for the first time, the pre-quantized capacitor corresponding to the preset swing threshold may be controlled. After controlling these capacitors, if the input signal swing is greater than the preset swing threshold again, the remaining pre-quantized capacitors may be turned on to enhance the effect of reducing the input signal swing.

[0034] For example, there are pre-quantization capacitors denoted as #5, #6, and #8, the sum of the weights of pre-quantization capacitors #6 and #8 is equal to the weight of pre-quantization capacitor #5, and the preset swing threshold is 5V, corresponding to pre-quantization capacitor #5. When the input signal swing is greater than the preset swing threshold for the first time, the value is 8V, and pre-quantization capacitor #5 can be connected; after connection, the input signal swing is 6V and is still greater than the preset swing threshold, and pre-quantization capacitors #6 and #8 can be connected at this time.

[0035] Since the analog-to-digital converter of the present invention eliminates noise in the sampling signal based on noise elimination technology, and the auxiliary pre-quantization capacitor limits the input signal swing; rather than simply increasing the number of capacitors to reduce the sampling noise, the capacitor size of the DAC capacitor array 1 in the present invention is smaller than the capacitor size of the capacitor array in the traditional SAR ADC.

[0036] In some embodiments, see Figure 1 The analog-to-digital converter may further include a sampling module 5 .

[0037] Exemplarily, the output terminal of the sampling module 5 may be connected to the third input terminal of the DAC capacitor array 1 .

[0038] In a possible implementation, the sampling module 5 may sample the input signal in a first sampling phase and a second sampling phase.

[0039] In one example, in the first sampling phase, the input signal (see Figure 1 The Vin in the capacitor can be sampled to the main capacitor C1 in the DAC capacitor array 1 by the sampling module 5 using the bottom plate sampling method of the gate voltage bootstrap switch based on the switch control timing of the common mode voltage.

[0040] Specifically, in the first sampling stage, the first switch S1 connected to the main capacitor C1 is connected to the input signal, and the other first switches are connected to the common mode voltage terminal Vcm so that the pre-quantization capacitor C2 is in a reset state, and the sampling module 5 samples the input signal to the main capacitor C1.

[0041] Since the present invention sets a pre-quantization capacitor in the DAC capacitor array and sets a detection quantization module in the analog-to-digital converter, when the swing of the input signal is large, the detection quantization module can generate a first switch control signal to control the pre-quantization capacitor, thereby reducing the swing of the input signal; therefore, the analog-to-digital converter provided by the present invention shortens the sampling time without considering the saturation factor of the operational amplifier in the sampling stage; thereby, a series of problems caused by the shortening of the sampling time, such as higher bandwidth requirements, greater comparator power consumption, and poor noise attenuation effect, can be avoided, thereby improving the performance of the analog-to-digital converter.

[0042] Example 2

[0043] Based on Example 1, Figure 2 A specific structural schematic diagram of a high-efficiency, high-precision, low-delay successive approximation analog-to-digital converter based on pre-quantization provided by an embodiment of the present invention is shown.

[0044] In one possible implementation, see Figure 2 The DAC capacitor array 1 may include a plurality of main capacitors C1 and pre-quantization capacitors C2 (only one is shown here). One end of the main capacitor C1 and the pre-quantization capacitor C2 are connected to the ground terminal (see Figure 3 GND in), common mode voltage terminal (see Figure 3 Vcm) and the reference voltage terminal (see Figure 3The other ends of the main capacitor C1 and the pre-quantization capacitor C2 can be connected to the input ends of the detection quantization module 2 and the sampling noise elimination module 3 as the output ends of the DAC capacitor array 1.

[0045] In one possible implementation, see Figure 2 The sampling noise elimination module 3 includes a pre-amplifier 31, a noise storage capacitor C3, a second switch S2 and a third switch S3.

[0046] Exemplarily, the input end of the preamplifier 31 is connected to the other end of the main capacitor C1 and the pre-quantization capacitor C2 as the input end of the sampling noise elimination module 3, and the input end of the preamplifier 31 is also connected to the reference voltage end through the second switch S2, and its output end is connected to one end of the noise storage capacitor C3. The other end of the noise storage capacitor C3 can be connected to the reference voltage end through the third switch S3, and is also connected to the second input end of the successive approximation quantization module 4 as the output end of the sampling noise elimination module 3.

[0047] Specifically, the preamplifier 31 can be used to amplify the sampling signal in the quantization stage to reduce the second sampling noise to obtain an amplified sampling signal. The noise storage capacitor C3 can store the amplified sampling signal in the second sampling stage, eliminate the first sampling noise therein in the quantization stage, and output the signal after the sampling noise is eliminated.

[0048] Exemplarily, the second sampling noise is generated by controlling the third switch S3 of the noise storage capacitor C3.

[0049] Optionally, the second switch S2 may be a top plate switch, and the third switch S3 may be a bottom plate switch.

[0050] In one possible implementation, see Figure 3 In the signal timing diagram for controlling the second switch S2 and the third switch S3, in the first sampling stage, the second switch S2 and the third switch S3 are both closed; at the end of the first sampling stage, at the moment when the second switch S2 is disconnected, the sampling value of the input signal and the first sampling noise are fixed on the main capacitor C1, and the sampling of the DAC capacitor array 1 is completed. In the second sampling stage, the second switch S2 is disconnected and the third switch S3 is closed. At this time, the sampling signal including the first sampling noise can be stored in the noise storage capacitor C3. In the quantization stage, the second switch S2 and the third switch S3 are both disconnected, and the first sampling noise generated when the main capacitor C1 is sampled can be treated as offset elimination. The second sampling noise can be attenuated by the gain of the pre-amplifier 31, so that while reducing the main capacitance, no large thermal noise will be introduced.

[0051] Since in the second sampling stage, the input signal swing is controlled by the detection and quantization module 2 so that it does not exceed the preset swing threshold as much as possible, thereby increasing the duration of the second sampling stage; therefore, the analog-to-digital converter has smaller bandwidth requirements for the pre-amplifier 31, while reducing its power consumption and increasing its attenuation effect on the second sampling noise.

[0052] In one possible implementation, see Figure 2 The successive approximation quantization module 4 may include a latch 41 , a successive approximation logic module 42 and a digital code processing module 43 .

[0053] Exemplarily, the input end of the latch 41 can be connected to the other end of the noise storage capacitor C3 as the second input end of the successive approximation quantization module 4, and the output end can be connected to the input end of the successive approximation logic module 42. The output end of the successive approximation logic module 42 can be connected to the first input end of the digital code processing module 43. The second input end of the digital code processing module 43 can be connected to the second output end of the detection quantization module 2 as the first input end of the successive approximation quantization module 4, and the output end of the digital code processing module 43 can be connected to the second input end of the DAC capacitor array 1 as an output end of the successive approximation quantization module 4.

[0054] Specifically, the latch 41 and the preamplifier 31 can form a two-stage comparator to compare the signal after the sampling noise is eliminated to obtain a comparison result. The successive approximation logic module 42 can perform a logical operation on the comparison result to generate a second switch control signal to control the DAC capacitor array 1 to implement the successive comparison process, and can also generate a quantized digital codeword according to the comparison result (see Figure 2 Dout 1 in ) completes the quantization of the signal after the sampling noise is eliminated. Finally, if there is no pre-quantization result (see Figure 2 If Dout r exists, the digital code processing module 43 directly outputs Dout 1 as the quantization result of the input signal; if Dout r exists, Dout r and Dout 1 are unified into a digital codeword as the quantization result of the input signal.

[0055] In one example, due to the limited bandwidth of the preamplifier 31, it cannot be completely stable in the second sampling stage, so the first sampling noise can be regarded as a small step signal appearing at the input end of the preamplifier 31. After the sampling signal is stored on the noise storage capacitor C3, the first sampling noise stored on the noise storage capacitor C3 in the quantization stage cancels out the first sampling noise in the sampling signal, thereby eliminating the first sampling noise. In fact, the first sampling noise cannot be completely eliminated, and there will still be a first sampling noise residual after incomplete elimination. In the process of the successive approximation logic module 42 controlling the DAC capacitor array 1 to achieve successive approximation, the first sampling noise will be eliminated at the end of the noise storage capacitor C3 close to the DAC capacitor array 1, and the second sampling noise will be attenuated by the gain of the amplifier. Combining the first sampling noise residual and the second sampling noise remaining after attenuation, the analog-to-digital converter will still have a total sampling noise.

[0056] Exemplarily, the response of the preamplifier 31 to the first sampling noise, that is, the first sampling noise stored on the noise storage capacitor C3, may satisfy the following formula:

[0057] ;

[0058] in, is the first sampled noise stored on the noise storage capacitor C3, is the first sampling noise, is the sampling time of the second sampling stage, is the stabilization time constant, is the gain of the preamplifier 31.

[0059] Exemplarily, the first sampling noise residual may satisfy the following formula:

[0060] ;

[0061] The first sampling noise residual is the first sampling noise remaining after the noise storage capacitor performs noise elimination processing. is the first sampling noise residual, is the Boltzmann constant, is the absolute temperature value, is the capacitance value of the main capacitor, is the sampling time of the second sampling stage, is the stabilization time constant of the preamplifier 31, .

[0062] Generally, in order to minimize the output reference noise residual without increasing the main capacitance C1, it is necessary to increase the sampling time of the second sampling stage. Or reduce the stabilization time constant ; However, these two parameters are also affected by other factors and cannot be simply enlarged or reduced. On the one hand, The increase is limited by the signal swing of the preamplifier 31. Since the sampling signal will be amplified by the preamplifier, in order to prevent the preamplifier 31 from saturating and ensure sufficient linearity, it is necessary to reduce ;on the other hand, The reduction in is at the expense of increasing the power of the pre-amplifier 31.

[0063] Exemplarily, the input reference sampling noise after the ideal sampling noise in the analog-to-digital converter is eliminated, that is, the total sampling noise can satisfy the following formula:

[0064] ;

[0065] in, is the input referred sampling noise of the ADC, is the gain of the preamplifier, is the Boltzmann constant, is the absolute temperature value, is the capacitance value of the noise storage capacitor, is the second sampling noise.

[0066] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0067] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0068] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0069] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, any modifications made without departing from the concept of the present invention should be deemed to belong to the protection scope of the present invention.

Claims

1. A high-efficiency, high-precision, low-delay successive approximation analog-to-digital converter based on prequantization, characterized in that: include: A digital-to-analog conversion capacitor array, the digital-to-analog conversion capacitor array comprising a main capacitor and a pre-quantization capacitor, one end of the main capacitor and the pre-quantization capacitor are respectively connected to a ground terminal, a common mode voltage terminal and a reference voltage terminal through a plurality of first switches, and the other ends are both connected to the input terminal of a detection quantization module and a sampling noise elimination module, the main capacitor is used to sample an input signal in a first sampling phase to obtain a sampling signal, and is used as a digital-to-analog conversion capacitor for quantization in a quantization phase, and the pre-quantization capacitor is used to control the input signal swing in a second sampling phase; The detection and quantization module, wherein the first output end of the detection and quantization module is connected to the first input end of the digital-to-analog conversion capacitor array, and the second output end of the detection and quantization module is connected to the first input end of the successive approximation quantization module, and the detection and quantization module is used to detect the input signal swing through the sampling signal in the second sampling stage, and generate a first switch control signal and a pre-quantization codeword when the input signal swing is greater than a preset swing threshold; wherein the first switch control signal is used to control a first switch connected to the pre-quantization capacitor to reduce the input signal swing; The sampling noise elimination module, wherein the output end of the sampling noise elimination module is connected to the second input end of the successive approximation quantization module, and the sampling noise elimination module is used to store the first sampling noise generated by the digital-to-analog conversion capacitor array in the second sampling stage, and eliminate the first sampling noise and attenuate the second sampling noise in the quantization stage to obtain a signal after the sampling noise is eliminated; The successive approximation quantization module, the output end of the successive approximation quantization module is connected to the second input end of the digital-to-analog conversion capacitor array, the successive approximation quantization module is used to control the main capacitor to realize the successive approximation process in the quantization stage, quantize the signal after the sampling noise is eliminated to obtain a quantized digital codeword, and output the quantization result of the input signal according to the quantized digital codeword or the quantized digital codeword and the pre-quantized codeword.

2. The analog-to-digital converter according to claim 1, characterized in that The analog-to-digital converter also includes a sampling module, an output end of the sampling module is connected to the third input end of the digital-to-analog conversion capacitor array, and the sampling module is used to sample the input signal in the first sampling phase and the second sampling phase.

3. The analog-to-digital converter according to claim 2, characterized in that: The sampling noise elimination module comprises: A preamplifier, wherein the input end of the preamplifier is connected to the common mode voltage end through a second switch, and the input end of the preamplifier is also connected to the main capacitor and the other end of the prequantization capacitor as the input end of the sampling noise elimination module, and the preamplifier is used to attenuate the second sampling noise through its own amplification gain in the quantization stage; a noise storage capacitor, one end of which is connected to the output end of the preamplifier, the other end of which is connected to the common mode voltage end through a third switch, the other end of which is also connected to the second input end of the successive approximation quantization module as the output end of the sampling noise elimination module, the noise storage capacitor is used to store the first sampling noise in the second sampling stage, eliminate the first sampling noise in the quantization stage, and output the sampling noise-eliminated signal to the successive approximation quantization module, wherein the second sampling noise is generated by the third switch that controls the noise storage capacitor.

4. The analog-to-digital converter according to claim 3, characterized in that: The successive approximation quantization module comprises: A latch, wherein an input end of the latch is connected to the other end of the noise storage capacitor as a second input end of the successive approximation quantization module, and the latch is used to compare the signal after the sampling noise is eliminated to obtain a comparison result; A successive approximation logic module, wherein the input end of the successive approximation logic module is connected to the output end of the latch, the first output end of the successive approximation logic module is connected to the first input end of the digital code processing module, and the second output end of the successive approximation logic module is connected to the second input end of the digital-to-analog conversion capacitor array as the output end of the successive approximation quantization module; the successive approximation logic module is used to perform a logical operation on the comparison result to obtain a second switch control signal, and generate a quantized digital codeword according to the comparison result; wherein the second switch control signal is used to control a first switch connected to the main capacitor to enable the digital-to-analog conversion capacitor array to complete a successive approximation process; The digital code processing module, the second input end of the digital code processing module is connected to the second output end of the detection quantization module as the first input end of the successive approximation quantization module, and the digital code processing module is used to output the quantized digital codeword as the quantization result of the input signal, or to unify the quantized digital codeword and the pre-quantization codeword into a segment of digital codeword as the quantization result of the input signal.

5. The analog-to-digital converter according to claim 3, characterized in that: The noise storage capacitor is specifically used to store the first sampling noise, and then the first sampling noise stored in the noise storage capacitor is used to cancel the first sampling noise in the sampling signal to perform noise elimination processing.

6. The analog-to-digital converter according to claim 5, characterized in that: The first sampled noise stored in the noise storage capacitor satisfies the following formula: ； in, is the first sampled noise stored on the noise storage capacitor, is the first sampling noise in the sampled signal, is the sampling time of the second sampling stage, is the stabilization time constant, is the gain of the preamplifier, Indicates multiplication.

7. The analog-to-digital converter according to claim 5, characterized in that: The first sampling noise residual satisfies the following formula: ； The first sampling noise residual is the first sampling noise remaining after the noise storage capacitor performs noise elimination processing. is the first sampled noise residual, is the Boltzmann constant, is the absolute temperature value, is the capacitance value of the main capacitor, is the sampling time of the second sampling stage, is the stabilization time constant of the preamplifier, .

8. The analog-to-digital converter according to claim 3, characterized in that: The ideal total sampling noise of the analog-to-digital converter satisfies the following formula: ； in, is the ideal total sampling noise of the ADC, is the gain of the preamplifier, is the Boltzmann constant, is the absolute temperature value, is the capacitance value of the noise storage capacitor, is the second sampling noise.

9. The analog-to-digital converter according to claim 1, characterized in that: The preset swing threshold includes multiple levels of thresholds. If the input signal swing is greater than the i-th level threshold, the pre-quantization capacitor corresponding to the i-th level threshold is controlled.

10. The analog-to-digital converter according to claim 1, characterized in that: If the input signal swing is greater than the preset swing threshold for the first time, the pre-quantization capacitor corresponding to the preset swing threshold is controlled; if the input signal swing is greater than the preset swing threshold again, the remaining pre-quantization capacitors are controlled.

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