A GPGPU instruction execution efficiency optimization method based on lookup table

Abstract

The present invention discloses a GPGPU instruction execution efficiency optimization method based on a lookup table, which relates to the technical field of GPGPU. The method uses a thread bundle index as an address to construct a register state lookup table, and completes the storage and release of the lookup table items by continuously polling the instruction cache and the write-back buffer; when a new destination register number is detected from the instruction of the instruction buffer, the record is stored in the corresponding table item according to the thread bundle ID; when the thread bundle ID and the recorded register number RID are detected from the information of the write-back buffer, the RID in the table item is reset according to the thread bundle ID to release the storage space. The present invention can ensure that the GPGPU can efficiently and accurately execute computing tasks and reduce the overhead of storage space.

Description

Technical Field

[0001] The present invention relates to the field of GPGPU technology, in particular to a method for optimizing the execution efficiency of GPGPU instructions based on a lookup table. Background Art

[0002] In the field of computer science, the Graphics Processing Unit (GPU), as a key component of high-performance computing, plays an irreplaceable role in graphics rendering, scientific computing, artificial intelligence, deep learning and other fields with its excellent parallel processing and floating-point computing capabilities. GPGPU instructions refer to the instruction set in the general-purpose graphics processing unit (GPGPU), which is used to guide the GPU to perform various computing tasks. Among them, the scheduling and execution of instructions are the core links, which are directly related to the performance and efficiency of GPGPU. In order to ensure the correct execution order of instructions and avoid resource conflicts, traditional GPGPU adopts a scoreboard mechanism. This mechanism tracks the usage of resources by assigning status bits to the resources of each thread bundle, thereby solving the resource conflict and dependency problems. For example, it can identify the write status of each register by assigning 1 bit, where 0 means that the register has been written back and updated, and 1 means that it has not been written back yet. Such a mechanism allows the instructions of other thread bundles to continue to be scheduled and executed even if a thread bundle is blocked due to data dependency, thereby improving the overall execution efficiency.

[0003] The scoreboard mechanism can effectively avoid resource contention and non-dependency instruction blocking caused by RAW (Read After Write) and WAW (Write After Write) risks during instruction execution, and is simple and easy to implement. However, if a 1-bit flag is assigned to each register of each thread, assuming that there are currently 64 thread bundles to be emitted and each thread bundle can be assigned 64 registers, then 4Kbit of storage space is required. As the number of thread bundles increases, the required storage space will theoretically continue to expand. Under limited hardware resources, an overly large scoreboard will increase hardware overhead and limit the size of the register file, thereby affecting the parallelism of thread bundles, increasing the pipeline stagnation time, and reducing the instruction execution efficiency of GPGPU. Summary of the invention

[0004] In the field of high-performance computing, especially in the GPGPU architecture, with the continuous evolution of the GPGPU architecture, the number of computing units, the complexity of the instruction set, the parallelism of the thread bundles, and the number of registers that can be allocated to each thread bundle are also increasing. The traditional scoreboard mechanism, which can only rely on increasing hardware overhead to solve instruction dependencies, has obviously reached a bottleneck and cannot meet the effective balance between GPGPU instruction execution efficiency and hardware overhead. In view of the needs and shortcomings of current technological development, the present invention provides a GPGPU instruction execution efficiency optimization method based on a lookup table.

[0005] The present invention provides a GPGPU instruction execution efficiency optimization method based on a lookup table, and the technical solution adopted to solve the above technical problems is as follows:

[0006] A GPGPU instruction execution efficiency optimization method based on a lookup table is disclosed. The method uses a thread bundle index as an address to construct a register state lookup table, and completes the storage and release of the lookup table entries by continuously polling the instruction cache and the write-back buffer. When a new destination register number is detected from an instruction in the instruction buffer, its record is stored in the corresponding table entry according to the thread bundle ID. When the thread bundle ID and the recorded register number RID are detected from the information in the write-back buffer, the RID in the table entry is reset according to the thread bundle ID to release the storage space.

[0007] Optionally, the register state lookup table involved constructs table entries corresponding to the number of parallel thread warps;

[0008] Each table entry contains multiple register numbers RID, offset and table entry empty and full flags, where:

[0009] RS RID Represents the source register, and its subscript RID represents the number of the source register; RD RID Indicates the destination register, and its subscript RID indicates the destination register number;

[0010] RID indicates the destination register RD to be written back in the instructions currently being executed by the thread warp corresponding to the entry. RID Serial number;

[0011] The offset means that when the destination register written back in the instruction is multiple consecutive registers, only the first register number RID needs to be stored, and the remaining register numbers RID gradually increase according to the first register number RID with 1 as the step unit, and the maximum value is the sum of the first register number RID and the offset; the offset allocates storage space for different register numbers RID according to different instruction sets;

[0012] The table entry empty and full flag indicates whether the register number RID stored in the table entry has reached the maximum value, and 1 bit is allocated by default; when the flag is 1, it means that the current table entry is full. At this time, if the thread warp corresponding to the table entry contains instructions to be issued that are written back to the register, it is necessary to wait for the table entry to release available register storage space.

[0013] Further optionally, the size of the storage space of the register number RID involved is determined by the number of registers that can be allocated to the warp;

[0014] The storage space of the register number RID supports dynamic adjustment as needed to adapt to different situations or optimize resource usage.

[0015] Further optionally, for each entry in the register status lookup table:

[0016] By default, each register ID is allocated 6 bits of storage space. The register number RID ranges from 0 to 63, and the initial value is 0.

[0017] By default, the offset is allocated 2 bits of storage space, which allows the offset to support up to 3 consecutive destination register write-back operations;

[0018] By default, each table entry supports recording 4 sets of register numbers RID and corresponding offsets, and the width of each table entry is 4*(6+2)+1=33 bits.

[0019] Optionally, a method for optimizing GPGPU instruction execution efficiency based on a lookup table is specifically implemented as follows:

[0020] S1. Scheduling and instruction fetching process of computing tasks in GPGPU: When GPGPU processes computing tasks, the thread scheduling unit generates active thread bundles, and fetches and decodes instructions in turn according to the polling scheduling method, and caches the information into the instruction buffer;

[0021] S2. Processing of instruction cache and write-back buffer in GPGPU: When processing computing tasks, GPGPU detects instruction cache and write-back buffer by polling, processes write-back information first, and then reads and judges decoding information to determine whether there is a risk of RAW conflict. If not, the instruction information is cached in the buffer to be transmitted;

[0022] S3, conflict risk judgment and instruction information cache: When processing computing tasks, GPGPU detects and resolves RAW and WAW conflicts, and caches non-conflicting instructions into the buffer to be issued;

[0023] S4, processing blocking and write-back update: When GPGPU is processing computing tasks, when a RAW conflict is detected, the relevant instructions are blocked, and then the write-back buffer is updated to resolve the blocking and issue instructions;

[0024] S5. In the instruction processing flow of GPGPU, the instruction blocking problem caused by the full table entry is solved by writing back the buffer to update, ensuring that the instructions can be issued and executed in the correct order.

[0025] Further optionally, the step S1 involved specifically includes the following execution process:

[0026] S1.1. After the computing tasks generated by the host computer reach the GPGPU, the thread scheduling unit processes these computing tasks and generates M active thread bundles, marked as W0 to W m , using the polling scheduling method to assign priorities, where W0 has the highest priority, and then down to W m ;

[0027] S1.2, the instruction fetch unit fetches instruction I according to the program counter PC0 of thread warp W0 0.1 , and the instruction I 0.1 Send to the decoding unit for decoding, after decoding, parse out the instruction I 0.1 The source register number and destination register number contained in , and then cache the decoding information into the corresponding instruction buffer 0 according to the thread warp number;

[0028] S1.3, the instruction fetch unit moves to the next thread warp W1 and fetches instruction I according to its program counter PC1 1.1 , repeat the decoding and information storage process in step S1.2 until all thread warps W0 to W m After one round of polling, the instruction fetch unit returns to W0 and continues with the next round of instruction fetching.

[0029] Further optionally, the step S2 involved specifically includes the following execution process:

[0030] S2.1, detect the instruction cache I-Buffer and the write-back buffer WB-Buffer in turn by polling. The priority of the write-back buffer WB-Buffer is higher than that of the instruction buffer I-Buffer, and the information of the write-back buffer is processed first;

[0031] S2.2, if the write-back buffer WB-Buffer is empty, and it is detected that the instruction buffer 0 corresponding to the thread warp W0 is not empty, the lookup table unit reads the instruction I in the instruction buffer 0 0.1 Decoding information of

[0032] S2.3, if instruction I 0.1 Contains only source register RS R2, if there is no write-back destination register, the thread warp W0 is used as the index address to read the corresponding lookup table entry and determine the empty or full status of the entry. If the empty or full flag is 0, the four register numbers RID stored in the entry are compared with the instruction I 0.1 Internal register RS R2 If the comparison result shows that the numbers are not equal, it indicates that there is no RAW conflict risk, and instruction I 0.1 The information is cached in the waiting-to-be-transmitted buffer, waiting for subsequent transmission execution.

[0033] Further optionally, the step S3 involved specifically includes the following execution process:

[0034] S3.1, continue to poll the write-back buffer WB-Buffer and confirm that it is empty. When it is detected that the instruction buffer 1 is not empty, the lookup table unit reads the instruction I in the instruction buffer 1. 1.1 Decoding information of

[0035] S3.2, if instruction I 1.1 The decoding information also includes the source register RS R1 and destination register RD R5 , which are numbered R1 and R5 respectively, then use the thread warp W1 as the index address, read the corresponding lookup table entry, and determine the empty or full state of the entry;

[0036] S3.3, when the empty and full flag is 0, the four register numbers RID stored in the table entry are compared with the instruction I 1.1 Internal register RS R1 Number R1, destination register RD R5 The numbers R5 are compared respectively. If they are not equal, it means there is no risk of conflict between RAW and WAW. At the same time, the destination register RD is recorded and stored. R5 Number R5, offset is 0;

[0037] S3.4, command I 1.1 The information is cached in the waiting-to-be-transmitted buffer, waiting for subsequent transmission execution.

[0038] Further optionally, the step S4 involved specifically includes the following execution process:

[0039] S4.1, if the write-back buffer WB-Buffer is empty and there is no risk of conflict between RAW and WAW, the instruction processing process is the same as step S2 or step S3 until the buffer M is polled, thus completing a round of instruction information reading;

[0040] S4.2, when the instruction buffer 1 is polled again, the lookup table unit reads the instruction I in the buffer 1.2 Decoding information of

[0041] S4.3, if instruction I 1.2 The decoding information only contains the source register RS R5 , numbered R5, then use thread bundle W1 as the index address to read the corresponding lookup table entry. If the empty and full flag is 0, the four register numbers RID stored in the table entry are compared with instruction I 1.2 Internal register RS R5 In contrast, source register RS R5 The number is R5. When the comparison finds that there is an equal register number, it can be known from step S3 that the table entry of thread warp W1 has recorded the destination register RD numbered R5. R5 And no write-back action occurs during this period, indicating that the register numbered R5 cannot be read, otherwise a RAW conflict will occur. Therefore, instruction I 1.2 Unable to fire, blocked;

[0042] S4.4, when continuing to poll and read the write-back buffer WB-Buffer, the write-back buffer WB-Buffer is not empty, at this time, the lookup table unit reads the information in the write-back buffer WB-Buffer, finds the corresponding table entry according to the thread bundle W1 and the register number R5 therein, resets the recorded register R5 to 0, releases the storage space, indicating that the register R5 has completed writing back, and the value of the register has been updated and can be read;

[0043] S4.5, when the next round of polling reaches instruction buffer 1, the instruction in instruction buffer 1 is still I 1.2 At this time, since register R5 has been written back, that is, there is no record of R5 in the table entry, instruction I 1.2 The information is cached in the waiting-to-be-transmitted buffer, waiting for subsequent transmission execution.

[0044] Further optionally, the step S5 specifically includes the following execution process:

[0045] S5.1, steps S1-S4 are performed when the table entry is not full. x Instructions I x.y When only the destination register numbered Rm is included and the empty and full flag of the corresponding entry is 1, that is, when the storage space of the entry record is full, instruction I x.y It cannot be launched either, and command blocking occurs;

[0046] S5.2, when the polling detects that the write-back buffer WB-Buffer is not empty at a certain moment, the lookup table unit reads the information in the write-back buffer WB-Buffer area, and calculates the information according to the thread bundle W in it. xAnd register number Rx finds the corresponding table entry, and resets the recorded register Rx to 0 to release its storage space;

[0047] S5.3, wait until the next round of polling to get thread bundle W again x When the corresponding instruction buffer is reached, register Rm is stored in the space released by Rx, and instruction I x.y The information is cached in the waiting-to-be-transmitted buffer, waiting for subsequent transmission execution.

[0048] The GPGPU instruction execution efficiency optimization method based on a lookup table of the present invention has the following beneficial effects compared with the prior art:

[0049] 1. The instruction execution optimization process in the GPGPU of the present invention includes the management and scheduling of thread bundles, instruction fetching and decoding, polling detection of write-back buffers and instruction buffers, judgment and processing of conflict risks, and instruction blocking and processing when the table is full. These steps together ensure that the GPGPU can efficiently and accurately execute computing tasks, reduce the storage space overhead, and optimize resource allocation by flexibly adjusting the depth and width of the lookup table, thereby improving the instruction execution efficiency of the GPGPU;

[0050] 2. The storage space required for the register state lookup table involved in the present invention is significantly smaller than the storage space required for the scoreboard mechanism, and with the increase in the number of thread warps and the number of registers that can be allocated to each thread warp, the optimization method will save more hardware overhead. At the same time, the lookup table can dynamically adjust the depth of the lookup table according to the number of parallel thread warps and flexibly adjust the width of the lookup table entries according to the number of registers that can be allocated to each thread warp, thereby optimizing the allocation of hardware resources while improving the parallelism of the thread warps and the execution efficiency of GPGPU instructions. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Attached Figure 1 It is a schematic diagram of an instruction issuance flow based on a lookup table according to an embodiment of the present invention;

[0052] Attached Figure 2 is a schematic diagram of the structure of a lookup table entry in an embodiment of the present invention;

[0053] Attached Figure 3 It is a flowchart of table entry record and release in an embodiment of the present invention. DETAILED DESCRIPTION

[0054] In order to make the technical solution, the technical problem solved and the technical effect of the present invention more clearly understood, the technical solution of the present invention is clearly and completely described below in conjunction with specific embodiments.

[0055] Embodiment 1: This embodiment proposes a GPGPU instruction execution efficiency optimization method based on a lookup table, which constructs a register state lookup table with a thread bundle index as the address, and completes the storage and release of the lookup table entries by continuously polling the instruction cache and the write-back buffer; when a new destination register number is detected from the instruction in the instruction buffer, its record is stored in the corresponding table entry according to the thread bundle ID; when the thread bundle ID and the recorded register number RID are detected from the information in the write-back buffer, the RID in the table entry is reset according to the thread bundle ID to release the storage space.

[0056] In the method of this embodiment, the register state lookup table constructs corresponding table entries according to the number of parallel thread warps, and combines the attached Figure 2 , each entry contains multiple register numbers RID, offset and entry empty and full flags, where:

[0057] RS RID Represents the source register, and its subscript RID represents the number of the source register; RD RID Indicates the destination register, and its subscript RID indicates the destination register number; RID indicates the destination register RD to be written back in the several instructions currently being executed by the thread warp corresponding to the table entry RID The storage space size of the register number RID is determined by the number of registers that can be allocated to the thread warp; the storage space of the register number RID supports dynamic adjustment as needed to adapt to different situations or optimize resource usage;

[0058] The offset means that when the destination register written back in the instruction is multiple consecutive registers, only the first register number RID needs to be stored, and the remaining register numbers RID gradually increase according to the first register number RID with 1 as the step unit, and the maximum value is the sum of the first register number RID and the offset; the offset allocates storage space for different register numbers RID according to different instruction sets;

[0059] The table entry empty and full flag indicates whether the register number RID stored in the table entry has reached the maximum value, and 1 bit is allocated by default; when the flag is 1, it means that the current table entry is full. At this time, if the thread warp corresponding to the table entry contains instructions to be issued that are written back to the register, it is necessary to wait for the table entry to release available register storage space.

[0060] Specifically, for each entry in the register status lookup table: by default, each register ID is allocated 6 bits of storage space, the register number RID range is 0 to 63, and the initial value is 0; the offset is allocated 2 bits of storage space by default, which enables the offset to support up to 3 consecutive destination register write-back operations; by default, each entry supports recording 4 groups of register numbers RID and corresponding offsets, and the width of each entry is 4*(6+2)+1=33 bits.

[0061] Reference Figure 1 , Attachment Figure 3 , among which, Figure 3 Indicates searching for items based on the obtained thread bundle ID number. ID Refers to the thread bundle ID, which can also be called the thread bundle number, and is different from the thread bundle number in the embodiment. x Rm and Rx refer to a register, and m and x are labels, which are similar to R1 and R5 in the embodiment. x For registers Rm and Rx, the value range of m and x is between 0 and 63.

[0062] Reference Figure 1 , Attachment Figure 3 , a GPGPU instruction execution efficiency optimization method based on a lookup table in this embodiment, its specific implementation includes the following contents:

[0063] S1. Scheduling and instruction fetching process of computing tasks in GPGPU: When GPGPU processes computing tasks, the thread scheduling unit generates active thread bundles, and fetches and decodes instructions in turn according to the polling scheduling method, and caches the information into the instruction buffer. This process specifically includes the following execution flow:

[0064] S1.1. After the computing tasks generated by the host computer reach the GPGPU, the thread scheduling unit processes these computing tasks and generates M active thread bundles, marked as W0 to W m , using the polling scheduling method to assign priorities, where W0 has the highest priority, and then down to W m ;

[0065] S1.2, the instruction fetch unit fetches instruction I according to the program counter PC0 of thread warp W0 0.1 , and the instruction I 0.1 Send to the decoding unit for decoding, after decoding, parse out the instruction I 0.1 The source register number and destination register number contained in , and then cache the decoding information into the corresponding instruction buffer 0 according to the thread warp number;

[0066] S1.3, the instruction fetch unit moves to the next thread warp W1 and fetches instruction I according to its program counter PC1 1.1 , repeat the decoding and information storage process in step S1.2 until all thread warps W0 to W m After one round of polling, the instruction fetch unit returns to W0 and continues with the next round of instruction fetching.

[0067] S2. Processing of instruction cache and write-back buffer in GPGPU: When processing computing tasks, GPGPU detects instruction cache and write-back buffer by polling, prioritizes write-back information, and then reads and determines decoding information to determine whether there is a risk of RAW conflict. Otherwise, instruction information is cached to the buffer to be transmitted. This process specifically includes the following execution flow:

[0068] S2.1, detect the instruction cache I-Buffer and the write-back buffer WB-Buffer in turn by polling. The priority of the write-back buffer WB-Buffer is higher than that of the instruction buffer I-Buffer, and the information of the write-back buffer is processed first;

[0069] S2.2, if the write-back buffer WB-Buffer is empty, and it is detected that the instruction buffer 0 corresponding to the thread warp W0 is not empty, the lookup table unit reads the instruction I in the instruction buffer 0 0.1 Decoding information of

[0070] S2.3, if instruction I 0.1 Contains only source register RS R2 , if there is no write-back destination register, the thread warp W0 is used as the index address to read the corresponding lookup table entry and determine the empty or full status of the entry. If the empty or full flag is 0, the four register numbers RID stored in the entry are compared with the instruction I 0.1 Internal register RS R2 If the comparison result shows that the numbers are not equal, it indicates that there is no RAW conflict risk, and instruction I 0.1 The information is cached in the waiting-to-be-transmitted buffer, waiting for subsequent transmission execution.

[0071] S3, conflict risk judgment and instruction information cache: When processing computing tasks, GPGPU detects and resolves RAW and WAW conflicts, and caches non-conflicting instructions into the buffer to be issued. This process specifically includes the following execution flow:

[0072] S3.1, continue to poll the write-back buffer WB-Buffer and confirm that it is empty. When it is detected that the instruction buffer 1 is not empty, the lookup table unit reads the instruction I in the instruction buffer 1. 1.1 Decoding information of

[0073] S3.2, if instruction I 1.1 The decoding information also includes the source register RS R1 and destination register RD R5 , which are numbered R1 and R5 respectively, then use the thread warp W1 as the index address, read the corresponding lookup table entry, and determine the empty or full state of the entry;

[0074] S3.3, when the empty and full flag is 0, the four register numbers RID stored in the table entry are compared with the instruction I 1.1 Internal register RS R1 Number R1, destination register RD R5 The numbers R5 are compared respectively. If they are not equal, it means there is no risk of conflict between RAW and WAW. At the same time, the destination register RD is recorded and stored. R5 Number R5, offset is 0;

[0075] S3.4, command I 1.1 The information is cached in the waiting-to-be-transmitted buffer, waiting for subsequent transmission execution.

[0076] S4. Processing blocking and write-back updates: When GPGPU is processing computing tasks, when a RAW conflict is detected, the relevant instructions are blocked, and then the write-back buffer is updated to resolve the blocking and issue instructions. This process specifically includes the following execution flow:

[0077] S4.1, if the write-back buffer WB-Buffer is empty and there is no risk of conflict between RAW and WAW, the instruction processing process is the same as step S2 or step S3 until the buffer M is polled, thus completing a round of instruction information reading;

[0078] S4.2, when the instruction buffer 1 is polled again, the lookup table unit reads the instruction I in the buffer 1.2 Decoding information of

[0079] S4.3, if instruction I 1.2 The decoding information only contains the source register RS R5 , numbered R5, then use thread bundle W1 as the index address to read the corresponding lookup table entry. If the empty and full flag is 0, the four register numbers RID stored in the table entry are compared with instruction I 1.2 Internal register RS R5 In contrast, source register RS R5 The number is R5. When the comparison finds that there is an equal register number, it can be known from step S3 that the table entry of thread warp W1 has recorded the destination register RD numbered R5. R5And no write-back action occurs during this period, indicating that the register numbered R5 cannot be read, otherwise a RAW conflict will occur. Therefore, instruction I 1.2 Unable to fire, blocked;

[0080] S4.4, when continuing to poll and read the write-back buffer WB-Buffer, the write-back buffer WB-Buffer is not empty, at this time, the lookup table unit reads the information in the write-back buffer WB-Buffer, finds the corresponding table entry according to the thread bundle W1 and the register number R5 therein, resets the recorded register R5 to 0, releases the storage space, indicating that the register R5 has completed writing back, and the value of the register has been updated and can be read;

[0081] S4.5, when the next round of polling reaches instruction buffer 1, the instruction in instruction buffer 1 is still I 1.2 At this time, since register R5 has been written back, that is, there is no record of R5 in the table entry, instruction I 1.2 The information is cached in the waiting-to-be-transmitted buffer, waiting for subsequent transmission execution.

[0082] S5. In the instruction processing flow of GPGPU, for the blocking caused by the full table entry, the instruction blocking problem is solved by writing back the buffer update to ensure that the instructions can be issued and executed in the correct order. This process specifically includes the following execution flow:

[0083] S5.1, steps S1-S4 are performed when the table entry is not full. x Instructions I x.y When only the destination register numbered Rm is included and the empty and full flag of the corresponding entry is 1, that is, when the storage space of the entry record is full, instruction I x.y It cannot be launched either, and command blocking occurs;

[0084] S5.2, when the polling detects that the write-back buffer WB-Buffer is not empty at a certain moment, the lookup table unit reads the information in the write-back buffer WB-Buffer area, and calculates the information according to the thread bundle W in it. x And register number Rx finds the corresponding table entry, and resets the recorded register Rx to 0 to release its storage space;

[0085] S5.3, wait until the next round of polling to thread bundle W x When the corresponding instruction buffer is reached, register Rm is stored in the space released by Rx, and instruction I x.y The information is cached in the waiting-to-be-transmitted buffer, waiting for subsequent transmission execution.

[0086] In summary, the GPGPU instruction execution efficiency optimization method based on the lookup table of the present invention can ensure that the GPGPU can efficiently and accurately execute computing tasks, reduce the storage space overhead, and optimize resource allocation by flexibly adjusting the depth and width of the lookup table to improve the GPGPU instruction execution efficiency.

[0087] The above specific examples are used to explain the principles and implementation methods of the present invention in detail. These examples are only used to help understand the core technical content of the present invention. Based on the above specific embodiments of the present invention, any improvements and modifications made by technicians in this technical field without departing from the principles of the present invention should fall within the scope of patent protection of the present invention.

Claims

1. A method for optimizing GPGPU instruction execution efficiency based on a lookup table, characterized in that: The method constructs a register state lookup table with a thread bundle index as the address, and completes the storage and release of the lookup table entries by continuously polling the instruction cache and the write-back buffer; the register state lookup table constructs corresponding table entries according to the number of parallel thread bundles, and each table entry contains multiple register numbers RID, offsets and table entry empty and full flags, where: RS RID Represents the source register, and its subscript RID represents the number of the source register; RD RID Represents the destination register, and its subscript RID represents the destination register number; RID represents the destination register RD to be written back in the several instructions currently being executed by the thread warp corresponding to the table entry RID The offset indicates that when the destination register to be written back in the instruction is multiple consecutive registers, only the first register number RID needs to be stored, and the remaining register numbers RID are gradually increased according to the first register number RID with 1 as the step unit, and the maximum value is the sum of the first register number RID and the offset; the offset allocates storage space for different register numbers RID according to different instruction sets; the table entry empty and full flag indicates whether the register number RID stored in the table entry has reached the maximum value, and 1 bit is allocated by default; when the flag bit is 1, it means that the current table entry is full. At this time, if the thread warp corresponding to the table entry contains instructions to be issued that write back to the register, it is necessary to wait for the table entry to release the available register storage space; When a new destination register number is detected in an instruction from the instruction buffer, its record is stored in the corresponding table entry according to the thread warp ID; When the warp ID and the recorded register number RID are detected from the information in the write-back buffer, the RID in the entry is reset according to the warp ID, and the storage space of the entry corresponding to the RID reset is released.

2. The method for optimizing GPGPU instruction execution efficiency based on a lookup table according to claim 1, characterized in that: The size of the storage space for register number RID is determined by the number of registers that can be allocated to the thread warp; The storage space of the register number RID supports dynamic adjustment as needed to adapt to different situations or optimize resource usage.

3. The method for optimizing GPGPU instruction execution efficiency based on a lookup table according to claim 2, characterized in that: For each entry in the register status lookup table: By default, each register ID is allocated 6 bits of storage space. The register number RID ranges from 0 to 63, and the initial value is 0. By default, the offset is allocated 2 bits of storage space, which allows the offset to support up to 3 consecutive destination register write-back operations; By default, each table entry supports recording 4 sets of register numbers RID and corresponding offsets, and the width of each table entry is 4*(6+2)+1=33 bits.

4. The method for optimizing GPGPU instruction execution efficiency based on a lookup table according to claim 3, characterized in that: The specific implementation of the method includes the following contents: S1. Scheduling and instruction fetching process of computing tasks in GPGPU: When GPGPU processes computing tasks, the thread scheduling unit generates active thread bundles, and fetches and decodes instructions in turn according to the polling scheduling method, and caches the information into the instruction buffer; S2. Processing of instruction cache and write-back buffer in GPGPU: When processing computing tasks, GPGPU detects instruction cache and write-back buffer by polling, processes write-back information first, and then reads and judges decoding information to determine whether there is a risk of RAW conflict. If not, the instruction information is cached in the buffer to be transmitted; S3, conflict risk judgment and instruction information cache: When processing computing tasks, GPGPU detects and resolves RAW and WAW conflicts, and caches non-conflicting instructions into the buffer to be issued; S4, processing blocking and write-back update: When GPGPU is processing computing tasks, when a RAW conflict is detected, the relevant instructions are blocked, and then the write-back buffer is updated to resolve the blocking and issue instructions; S5. In the instruction processing flow of GPGPU, the instruction blocking problem caused by the full table entry is solved by updating the write-back buffer to ensure that the instructions can be issued and executed in the correct order.

5. The method for optimizing GPGPU instruction execution efficiency based on a lookup table according to claim 4, characterized in that: The step S1 specifically includes the following execution process: S1.

1. After the computing tasks generated by the host computer reach the GPGPU, the thread scheduling unit processes these computing tasks and generates M active thread bundles, marked as W0 to W m , using the polling scheduling method to assign priorities, where W0 has the highest priority, and then down to W m ; S1.2, the instruction fetch unit fetches instruction I according to the program counter PC0 of thread warp W0 0.1 , and the instruction I 0.1 Send to the decoding unit for decoding, after decoding, parse out the instruction I 0.1 The source register number and destination register number contained in , and then cache the decoding information into the corresponding instruction buffer 0 according to the thread warp number; S1.3, the instruction fetch unit moves to the next thread warp W1 and fetches instruction I according to its program counter PC1 1.1 , repeat the decoding and information storage process in step S1.2 until all thread warps W0 to W m All were polled once; After completing one round, the instruction fetch unit returns to W0 and continues with the next round of instruction fetch operations.

6. The method for optimizing GPGPU instruction execution efficiency based on a lookup table according to claim 5, characterized in that: The step S2 specifically includes the following execution process: S2.1, detect the instruction cache I-Buffer and the write-back buffer WB-Buffer in turn by polling. The priority of the write-back buffer WB-Buffer is higher than that of the instruction buffer I-Buffer, and the information of the write-back buffer is processed first; S2.2, if the write-back buffer WB-Buffer is empty, and it is detected that the instruction buffer 0 corresponding to the thread warp W0 is not empty, the lookup table unit reads the instruction I in the instruction buffer 0 0.1 Decoding information of S2.3, if instruction I 0.1 Contains only source register RS R2 , if there is no write-back destination register, the thread warp W0 is used as the index address to read the corresponding lookup table entry and determine the empty or full status of the entry. If the empty or full flag is 0, the four register numbers RID stored in the entry are compared with the instruction I 0.1 Internal register RS R2 If the comparison result shows that the numbers are not equal, it indicates that there is no RAW conflict risk, and instruction I 0.1 The information is cached in the waiting-to-be-transmitted buffer, waiting for subsequent transmission execution.

7. The method for optimizing GPGPU instruction execution efficiency based on a lookup table according to claim 6, characterized in that: The step S3 specifically includes the following execution process: S3.1, continue to poll the write-back buffer WB-Buffer and confirm that it is empty. When it is detected that the instruction buffer 1 is not empty, the lookup table unit reads the instruction I in the instruction buffer 1. 1.1 Decoding information of S3.2, if instruction I 1.1 The decoding information also includes the source register RS R1 and destination register RD R5 , which are numbered R1 and R5 respectively, then use the thread warp W1 as the index address, read the corresponding lookup table entry, and determine the empty or full state of the entry; S3.3, when the empty and full flag is 0, the four register numbers RID stored in the table entry are compared with the instruction I 1.1 Internal register RS R1 Number R1, destination register RD R5 The numbers R5 are compared respectively. If they are not equal, it means there is no risk of conflict between RAW and WAW. At the same time, the destination register RD is recorded and stored. R5 Number R5, offset is 0; S3.4, command I 1.1 The information is cached in the waiting-to-be-transmitted buffer, waiting for subsequent transmission execution.

8. The method for optimizing GPGPU instruction execution efficiency based on a lookup table according to claim 7, characterized in that: The step S4 specifically includes the following execution process: S4.1, if the write-back buffer WB-Buffer is empty and there is no risk of conflict between RAW and WAW, the instruction processing process is the same as step S2 or step S3 until the buffer M is polled, thus completing a round of instruction information reading; S4.2, when the instruction buffer 1 is polled again, the lookup table unit reads the instruction I in the buffer 1.2 Decoding information of S4.3, if instruction I 1.2 The decoding information only contains the source register RS R5 , numbered R5, then use thread bundle W1 as the index address to read the corresponding lookup table entry. If the empty and full flag is 0, the four register numbers RID stored in the table entry are compared with instruction I 1.2 Internal register RS R5 In contrast, source register RS R5 The number is R5. When the comparison finds that there is an equal register number, it can be known from step S3 that the table entry of thread warp W1 has recorded the destination register RD numbered R5. R5 And no write-back action occurs during this period, indicating that the register numbered R5 cannot be read, otherwise a RAW conflict will occur. Therefore, instruction I 1.2 Unable to fire, blocked; S4.4, when continuing to poll and read the write-back buffer WB-Buffer, the write-back buffer WB-Buffer is not empty, at this time, the lookup table unit reads the information in the write-back buffer WB-Buffer, finds the corresponding table entry according to the thread bundle W1 and the register number R5 therein, resets the recorded register R5 to 0, releases the storage space, indicating that the register R5 has completed writing back, and the value of the register has been updated and can be read; S4.5, when the next round of polling reaches instruction buffer 1, the instruction in instruction buffer 1 is still I 1.2 At this time, since register R5 has been written back, that is, there is no record of R5 in the table entry, instruction I 1.2 The information is cached in the waiting-to-be-transmitted buffer, waiting for subsequent transmission execution.

9. The method for optimizing GPGPU instruction execution efficiency based on a lookup table according to claim 8, characterized in that: The step S5 specifically includes the following execution process: S5.1, steps S1-S4 are performed when the table entry is not full. x Instructions I x.y When only the destination register numbered Rm is included and the empty and full flag of the corresponding entry is 1, that is, when the storage space of the entry record is full, instruction I x.y It cannot be launched either, and command blocking occurs; S5.2, when the polling detects that the write-back buffer WB-Buffer is not empty at a certain moment, the lookup table unit reads the information in the write-back buffer WB-Buffer area, and calculates the information according to the thread bundle W in it. x And register number Rx finds the corresponding table entry, and resets the recorded register Rx to 0 to release its storage space; S5.3, wait until the next round of polling to thread bundle W x When the corresponding instruction buffer is reached, register Rm is stored in the space released by Rx, and instruction I x.y The information is cached in the waiting-to-be-transmitted buffer, waiting for subsequent transmission execution.

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