Simulation model and method of ldmos

Abstract

The application discloses a simulation model and method of an LDMOS, which comprises the following: a MOS tube drain end connected with a first end of a first resistor, a negative electrode of a first diode, a positive electrode of a first voltage-controlled current source, a negative electrode of a second diode, a positive electrode of a second voltage-controlled current source, a first end of a first variable capacitor, a bottom surface ideal diode negative electrode of a body end and a drain end, a positive electrode of a third voltage-controlled current source, a first end of a body end and a drain end side surface junction capacitor, a body end and a drain end side surface junction ideal diode negative electrode, a positive electrode of a fourth voltage-controlled current source and a first end of a second variable capacitor; a positive electrode of the first diode, a negative electrode of the first voltage-controlled current source, a positive electrode of the second diode, a negative electrode of the second voltage-controlled current source, a second end of the first variable capacitor, a body end and a drain end bottom surface ideal diode positive electrode, a negative electrode of the third voltage-controlled current source, a second end of the second diode, a body end and a drain end side surface junction ideal diode positive electrode, a negative electrode of the fourth voltage-controlled current source and a second end of the second variable capacitor, which are all connected with a body end of the MOS tube.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device simulation, and in particular to a simulation model and method of LDMOS. Background Art

[0002] Lateral double-diffused MOSFETs (LDMOS) are common high-voltage devices used in BCD processes. They offer high voltage withstand capability and low on-resistance. LDMOS is primarily used in power amplifiers, antenna switches, and transmitters.

[0003] The prior art uses a BSIM4 model to simulate the Id vs Vgs characteristic curve of LDMOS.

[0004] However, the main disadvantage of LDMOS is that it has a large leakage current when the ambient temperature is high and the drain voltage is high. Figures 1 to 6 As shown, Figures 1 to 6 This is the Id vs. Vgs transfer curve for an LDMOS device with a drain voltage of 30V on a 90nm process platform. Where W is the channel width, L is the channel length, and T is the test ambient temperature. The device channel widths W are 10µm, 40µm, and 100µm, respectively, while the channel length is fixed. The dotted line represents measured data, while the solid line represents simulation results based on the widely used BSIM4+ external resistor macro model. Figures 1 to 3 The ambient temperature is 150℃, Figures 4 to 6 The ambient temperature is 175°C. When the temperature is 150°C and 175°C, it can be found that when Vds = 0.1V, the leakage current measurement and simulation can match, but when Vds = 30V, the measured current is nearly two orders of magnitude higher than the simulated current. Comparing the Ids of multiple groups of LDMOS with different channel widths W near Vgs = 0V, it can be seen that when the Vds voltage increases, Ids (Vds = 30V) is much larger than Ids (Vds = 0.1V), and a linear approximation is made to find that Ids (Vds = 30V) and the channel width W do not satisfy the linear relationship of direct proportion such as y = kx, but are close to the linear relationship of y = kx + b. Therefore, when Vds = 0.1V, the simulation is more accurate. When Vds = 30V, that is, Figures 1 to 6 In the circled area, the difference between the simulation line and the actual value is large, and the simulation line in the format of y = kx cannot fit the actual test value point. Therefore, the simulation accuracy here is too low. Summary of the Invention

[0005] The object of the present invention is to provide a simulation model and method for LDMOS, which can improve the simulation accuracy of the Idvs Vgs transfer characteristic curve of the LDMOS device.

[0006] In order to achieve the above object, the present invention provides a simulation model of LDMOS, including:

[0007] MOS transistor, a first resistor, a first diode, a first voltage-controlled current source, a second diode, a second voltage-controlled current source, a first variable capacitor, bottom ideal diodes at the LDMOS body and drain ends, a third voltage-controlled current source, side junction capacitors at the LDMOS body and drain ends, a fourth voltage-controlled current source, a second variable capacitor, and side junction ideal diodes at the LDMOS body and drain ends;

[0008] The drain terminal of the MOS tube is connected to the first end of the first resistor, the negative end of the first diode, the positive electrode of the first voltage-controlled current source, the negative end of the second diode, the positive electrode of the second voltage-controlled current source, the first end of the first variable capacitor, the negative end of the bottom ideal diode of the LDMOS body terminal and the drain terminal, the positive electrode of the third voltage-controlled current source, the first end of the side junction capacitor of the LDMOS body terminal and the drain terminal, the negative end of the side junction ideal diode of the LDMOS body terminal and the drain terminal, the positive electrode of the fourth voltage-controlled current source and the first end of the second variable capacitor; the positive end of the first diode, the negative end of the first voltage-controlled current source, the negative end of the third voltage-controlled current source, the first end of the side junction capacitor of the LDMOS body terminal and the drain terminal, the negative end of the side junction ideal diode of the LDMOS body terminal and the drain terminal, the positive electrode of the fourth voltage-controlled current source and the first end of the second variable capacitor; The positive terminal of the second diode, the negative electrode of the second voltage-controlled current source, the second end of the first variable capacitor, the positive terminal of the bottom ideal diode of the LDMOS body and drain, the negative electrode of the third voltage-controlled current source, the second end of the second diode, the positive terminal of the side junction ideal diode of the LDMOS body and drain, the negative electrode of the fourth voltage-controlled current source, and the second end of the second variable capacitor are all connected to the body terminal of the MOS tube; the second end of the first resistor is connected to the drain terminal of the LDMOS; the source terminal of the MOS tube is connected to the body terminal of the MOS tube and connected to the source terminal of the LDMOS; and the gate terminal of the MOS tube is connected to the gate terminal of the LDMOS.

[0009] Optionally, in the LDMOS simulation model, the LDMOS structure includes:

[0010] P-type substrate;

[0011] an N-type epitaxial layer located on a surface of the P-type substrate;

[0012] A Pwell located in the N-type epitaxial layer;

[0013] Nwell and P+ regions located in the Pwell, wherein the Nwell and P+ regions are separated by a first shallow trench isolation structure;

[0014] a first N+ region located in the Nwell;

[0015] A second N+ region located in the N-type epitaxial layer, the second N+ region and the Pwell are separated by a second shallow trench isolation structure and a gate oxide and gate polysilicon on the gate oxide surface, one end of the gate oxide covers the Nwell and the Pwell, and the second end covers the second shallow trench isolation structure;

[0016] The P+ region is connected as a body terminal, the first N+ region is connected as a source terminal of the LDMOS, the gate polysilicon is connected as a gate terminal of the LDMOS, and the second N+ region is connected as a drain terminal of the LDMOS.

[0017] Optionally, in the simulation model of the LDMOS, the P+ region is formed by ion implantation.

[0018] The present invention provides an LDMOS simulation method using an LDMOS simulation model, comprising:

[0019] Close the DC and CV parameters of the MOS tube in the BSIM4 model;

[0020] An ideal diode area saturation coefficient is obtained based on the bottom ideal diode of the LDMOS body terminal and the drain terminal, an ideal diode perimeter saturation coefficient is obtained based on the side junction ideal diode of the LDMOS body terminal and the drain terminal, a diode reverse tunneling current area saturation coefficient is obtained based on the third voltage-controlled current source, and a diode reverse tunneling current perimeter saturation coefficient is obtained based on the fourth voltage-controlled current source;

[0021] When the voltage between the drain and source terminals of the LDMOS is less than a set value, the current between the drain and source terminals under different temperature conditions is obtained, and fitting is performed using the ideal diode area saturation coefficient, the ideal diode perimeter saturation coefficient, the exponential term empirical correction coefficient, and the temperature correction coefficient so that the current between the drain and source terminals is directly proportional to the channel width of the MOSFET;

[0022] When the voltage between the drain and source terminals of the LDMOS is greater than or equal to a set value, the current between the drain and source terminals under different temperature conditions is obtained, and fitting is performed using the diode reverse tunneling current area saturation coefficient, the diode reverse tunneling current perimeter saturation coefficient, the exponential term empirical correction coefficient, the temperature correction coefficient, the first empirical coefficient, and the first empirical coefficient, so that the current between the drain and source terminals is directly proportional to the channel width of the MOSFET.

[0023] Optionally, in the LDMOS simulation method, the method of turning off the DC parameters and CV parameters in the BSIM4 model includes:

[0024] The parasitic diode leakage saturation coefficient, the parasitic diode capacitance and the parasitic diode reverse tunneling current coefficient of the MOSFET are all set to 0.

[0025] Optionally, in the LDMOS simulation method, a method for obtaining an ideal diode area saturation coefficient based on the bottom ideal diodes at the body and drain ends of the LDMOS includes:

[0026] Is2=Area_pwell*Iss*(T / 25)^xti / n*(e^-Vds / nVt-1)-Vds*Gmin;

[0027] Where Is2 is the value of the ideal diode at the bottom of the LDMOS body and drain, Area_pwell is the bottom area of ​​the LDMOS Pwell, Iss is the ideal diode area saturation coefficient, Vt is a constant, n is the empirical correction factor for the exponential term, Vds is the voltage between the drain and source of the LDMOS, Gmin is the minimum conductance of the simulation, and xti is the temperature correction factor.

[0028] Optionally, in the LDMOS simulation method, a method for obtaining an ideal diode perimeter saturation coefficient based on an ideal diode with side junctions at the body and drain ends of the LDMOS includes:

[0029] Isw2=Peri_pwell*Isws*(T / 25)^xti / n*(e^-Vds / nVt-1)-Vds*Gmin;

[0030] Where Isw2 is the ideal diode between the LDMOS body and drain, Peri_pwell is the perimeter of the LDMOS Pwell, Isws is the ideal diode perimeter saturation coefficient, Vt is a constant, n is the empirical correction factor for the exponential term, Vds is the voltage between the drain and source of the LDMOS, Gmin is the minimum conductance of the simulation, and xti is the temperature correction factor.

[0031] Optionally, in the LDMOS simulation method, the method of obtaining the area saturation coefficient of the diode reverse tunneling current according to the third voltage-controlled current source includes:

[0032] gleak2=-Area_pwell*Jtun*(T / 25)^xtitun*(e^-Vds / ntun*Vt-1);

[0033] Where, gleak2 is the value of the third voltage-controlled current source, Area_pwell is the bottom area of ​​the Pwell of the LDMOS, Jtun is the area saturation coefficient of the diode reverse tunneling current, Vt is a constant, T is the temperature, Vds is the voltage between the drain and source terminals of the LDMOS, ntun is the empirical correction coefficient of the exponential term, and xtitun is the temperature correction coefficient.

[0034] Optionally, in the LDMOS simulation method, the method of obtaining the diode reverse tunneling current saturation coefficient according to the fourth voltage-controlled current source includes:

[0035] gleaksw2=-Peri_pwell*Jtunsw*(T / 25)^xtitun*(e^-Vds / ntun*Vt-1);

[0036] Wherein, gleaksw2 is the value of the fourth voltage-controlled current source, Jtun is the area saturation coefficient of the diode reverse tunneling current, Peri_pwell is the perimeter of Pwell of LDMOS, Jtunsw is the perimeter saturation coefficient of the diode reverse tunneling current, Vt is a constant, T is the temperature, Vds is the voltage between the drain and source terminals of LDMOS, ntun is the empirical correction coefficient of the exponential term, and xtitun is the temperature correction coefficient.

[0037] Optionally, in the LDMOS simulation method, the exponential term empirical correction coefficient, the temperature correction coefficient, the exponential term empirical correction coefficient, the temperature correction coefficient, the first empirical coefficient and the first empirical coefficient are all set values.

[0038] The LDMOS simulation model and method provided by the present invention include: closing the DC parameters and CV parameters of the MOS tube in the BSIM4 model; obtaining an ideal diode area saturation coefficient based on the bottom ideal diodes of the LDMOS body and drain terminals, obtaining an ideal diode perimeter saturation coefficient based on the side junction ideal diodes of the LDMOS body and drain terminals, obtaining a diode reverse tunneling current area saturation coefficient based on a third voltage-controlled current source, and obtaining a diode reverse tunneling current perimeter saturation coefficient based on a fourth voltage-controlled current source; when the voltage between the drain and source terminals of the LDMOS is less than a set value, obtaining the current between the drain and source terminals under different temperature conditions, The ideal diode area saturation coefficient, the ideal diode perimeter saturation coefficient, the exponential term empirical correction coefficient, and the temperature correction coefficient are used for fitting so that the current between the drain and source terminals is directly proportional to the channel width of the MOSFET; when the voltage between the drain and source terminals of the LDMOS is greater than or equal to a set value, the current between the drain and source terminals under different temperature conditions is obtained, and the diode reverse tunneling current area saturation coefficient, the diode reverse tunneling current perimeter saturation coefficient, the exponential term empirical correction coefficient, the temperature correction coefficient, the first empirical coefficient, and the first empirical coefficient are used for fitting so that the current between the drain and source terminals is directly proportional to the channel width of the MOSFET. Therefore, the present invention adds the ideal diode area saturation coefficient, the ideal diode perimeter saturation coefficient, the exponential term empirical correction coefficient, the temperature correction coefficient, the first empirical coefficient, and the first empirical coefficient for fitting, thereby improving the simulation accuracy of the Id vs Vgs transfer characteristic curve of the LDMOS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figures 1 to 6 1 is a simulation diagram of the transfer characteristic curve of Id vs Vgs of the LDMOS device in the prior art;

[0040] Figure 7 is a model diagram of LDMOS according to an embodiment of the present invention;

[0041] Figure 8 1 is a schematic structural diagram of an LDMOS according to an embodiment of the present invention;

[0042] Figure 9 This is a simulation method for LDMOS according to an embodiment of the present invention;

[0043] Figures 10 to 21 4 is a simulation diagram of the Id vs Vgs transfer characteristic curve of the LDMOS device according to an embodiment of the present invention;

[0044] In the figure: 110 - P-type substrate, 120 - N-type epitaxial layer 120, 130 - Pwell130, 140 - Nwell, 150 - P+ region, 160 - first shallow trench isolation structure, 170 - first N+ region, 180 - second N+ region, 190 - second shallow trench isolation structure, 200 - gate oxide 200, 210 - gate polysilicon. DETAILED DESCRIPTION

[0045] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0046] Hereinafter, the terms "first," "second," and the like are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if a method described herein comprises a series of steps, the order in which the steps are presented herein is not necessarily the only order in which the steps may be performed, and some of the steps described may be omitted and / or other steps not described herein may be added to the method.

[0047] Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be directly on another layer or substrate, and / or intervening layers can also be present. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or one or more intervening layers can also be present. Additionally, references to being "on" and "under" various layers can be made based on the accompanying drawings.

[0048] Please refer to Figure 7The LDMOS structure includes: a P-type substrate 110; an N-type epitaxial layer 120 located on the surface of the P-type substrate 110; a Pwell 130 located in the N-type epitaxial layer 120; an Nwell 140 and a P+ region 150 located in the Pwell 130, wherein the Nwell 140 and the P+ region 150 are separated by a first shallow trench isolation structure 160; a first N+ region 170 located in the Nwell 140; a second N+ region 180 located in the N-type epitaxial layer 120, wherein the second N+ region 180 and the Pwell 130 are separated by a second shallow trench isolation structure 160. The gate oxide 200 is separated from the gate polysilicon 210 on the gate oxide surface by the isolation structure 190. One end of the gate oxide 200 covers the Nwell 140 and Pwell 130, and the second end covers the second shallow trench isolation structure 190. The P+ region 150's terminal serves as the bulk terminal, the first N+ region 170's terminal serves as the LDMOS's source terminal, the gate polysilicon 210's terminal serves as the LDMOS's gate terminal, and the second N+ region 180's terminal serves as the LDMOS's drain terminal. The P+ region is formed by ion implantation. The drain terminal is formed by the drift region of the N-type epitaxial layer 120 and the N+ region's terminal. The body terminal is formed by the Pwell. Reverse tunneling current between the N-type junction at the drain terminal and the P-type junction at the body terminal is the main cause of increased LDMOS leakage as temperature rises. At high temperatures, when the Vds voltage of the LDMOS increases, the number of electrons tunneling from the valence band of the P-type region to the conduction band of the N-type region increases significantly, increasing the reverse tunneling current at the PN junction. At this point, the LDMOS's Ids can be considered as two current components: Ileak + Itun. Ileak is the PN junction reverse leakage, and Itun is the reverse tunneling current. At high temperatures, Itun >> Ileak.

[0049] Please refer to Figure 8 The present invention provides a simulation model of LDMOS, including:

[0050] MOS transistor, a first resistor, a first diode, a first voltage-controlled current source, a second diode, a second voltage-controlled current source, a first variable capacitor, an ideal diode at the bottom of the LDMOS body and drain, a third voltage-controlled current source, a side junction capacitor at the LDMOS body and drain, a fourth voltage-controlled current source, a second variable capacitor, and an ideal diode at the side junction of the LDMOS body and drain; the drain terminal of the MOS transistor is connected to the first end of the first resistor R1, the negative end of the first diode IS1, the positive electrode of the first voltage-controlled current source gleak1, the negative end of the second diode Isw1, the positive electrode of the second voltage-controlled current source gleaksw1, the first end of the first variable capacitor cj (the bottom junction of the LDMOS body and drain), the negative end of the bottom ideal diode IS2 between the LDMOS body Pwell and the drain N-epi, the positive electrode of the third voltage-controlled current source gleak2, the first end of the side junction capacitor cjsw between the body Pwell and the drain N-epi, the LDMOS body Pwell and the drain N-epi i's side junction ideal diode ISw2's negative terminal, the positive terminal of the fourth voltage-controlled current source gleaksw2 and the first terminal of the second variable capacitor CJSWG; the positive terminal of the first diode IS1, the negative terminal of the first voltage-controlled current source gleak1, the positive terminal of the second diode Isw1, the negative terminal of the second voltage-controlled current source gleaksw1, the second terminal of the first variable capacitor cj, the positive terminal of the bottom ideal diode IS2 of the LDMOS body terminal Pwell and the drain terminal N-epi, the negative terminal of the third voltage-controlled current source gleak2, the second terminal of the second diode cjsw, the positive terminal of the side junction ideal diode ISw2 of the body terminal Pwell and the drain terminal N-epi, the negative terminal of the fourth voltage-controlled current source gleaksw2 and the second end of the second variable capacitor CJSWG are all connected to the body terminal of the MOS tube; the second end of the first resistor R1 is connected to the drain terminal of the LDMOS; the source terminal of the MOS tube is connected to the body terminal of the MOS tube and connected to the source terminal of the LDMOS, and the gate terminal of the MOS tube is connected to the gate terminal of the LDMOS. Where Cj is the bottom junction capacitance between the body terminal Pwell and the drain terminal N-epi, Is2 is the bottom ideal diode current between the body terminal Pwell and the drain terminal N-epi, and gleak2 is the reverse leakage model of the bottom junction between the body terminal Pwell and the drain terminal N-epi. Cjsw is the side junction capacitance between the body terminal Pwell and the drain terminal N-epi, Isw2 is the side junction ideal diode current between the body terminal Pwell and the drain terminal N-epi, and gleaksw2 is the reverse leakage model of the side junction between the body terminal Pwell and the drain terminal N-epi.

[0051] Please refer to Figure 9 The present invention also provides a simulation method for LDMOS, comprising:

[0052] S11: Close the DC parameters and CV parameters of the MOS tube in the BSIM4 model;

[0053] S12: obtaining an ideal diode area saturation coefficient ISS according to the bottom ideal diode IS2 between the LDMOS body terminal Pwell and the drain terminal N-epi, obtaining an ideal diode perimeter saturation coefficient ISWS according to the side junction ideal diode ISW2 between the LDMOS body terminal Pwell and the drain terminal N-epi, obtaining a diode reverse tunneling current area saturation coefficient Jtun according to the third voltage-controlled current source gleak2, and obtaining a diode reverse tunneling current perimeter saturation coefficient Jtunsw according to the fourth voltage-controlled current source gleaksw2;

[0054] S13: When the voltage Vds between the drain and source terminals of the LDMOS is less than a set value, the current Ids between the drain and source terminals under different temperature conditions is obtained, and the ideal diode area saturation coefficient ISS, the ideal diode perimeter saturation coefficient Isws, the exponential term empirical correction coefficient n, and the temperature correction coefficient xti are used for fitting, so that the current Ids between the drain and source terminals is directly proportional to the channel width W of the MOSFET, which is equivalent to the two satisfying a linear relationship y=kx;

[0055] S14: When the voltage Vds between the drain and source of the LDMOS is greater than or equal to the set value, the current Ids between the drain and source under different temperature conditions is obtained, using the diode reverse tunneling current area saturation coefficient Jtun, the diode reverse tunneling current perimeter saturation coefficient Jtunsw, the exponential term empirical correction coefficient ntun, the temperature correction coefficient xtitun, and the first empirical coefficient Area impe and the first empirical coefficient Peri impe The fitting makes the current Ids between the drain and source terminals and the channel width W of the MOSFET in direct proportion, which is equivalent to the two satisfying the linear relationship y=kx.

[0056] In an embodiment of the present invention, the method for disabling DC and CV parameters in the BSIM4 model includes setting the MOSFET's drain-to-body parasitic diode leakage saturation coefficient, drain-to-body parasitic diode capacitance, and drain-to-body parasitic diode reverse tunneling current coefficient to 0. After establishing a new circuit structure, the DC / CV parameters of the original BSIM4 model and the drain-end parasitic diode must be disabled. Therefore, the following nine BSIM4 parameters must be set to a disabled value of 0: jsd = 0, jswd = 0, jswgd = 0, cjd = 0, cjswd = 0, cjswgd = 0, jtsd = 0, Jtsswd = 0, and Jtsswgd = 0. Jsd, jswd, jswgd represent the parasitic diode leakage saturation coefficient from the drain end to the body end, cjd, cjswd, cjswgd represent the parasitic diode capacitance from the drain end to the body end, jtsd, jtsswd, jtsswgd represent the parasitic diode reverse tunneling current coefficient from the drain end to the body end.

[0057] Since the diode parameters in BSIM4 need to be turned off, the drain junction capacitance of LDMOS cannot be simulated by the BSIM4 model. Therefore, Cj, Cjsw and CJSWG added in the embodiment of the present invention are all to compensate for the drain junction capacitance characteristics. Cj, Cjsw and CJSWG are all variable capacitors, and the relationship between capacitance and Vds voltage is completely consistent with Cj, Cjsw and CJSWG in BSIM4, which will not be described in detail here.

[0058] In an embodiment of the present invention, a method for obtaining an ideal diode area saturation coefficient ISS based on the bottom surface ideal diode IS2 between the LDMOS body terminal Pwell and the drain terminal N-epi includes:

[0059] Is2=Area_pwell*Iss*(T / 25)^xti / n*(e^-Vds / nVt-1)-Vds*Gmin;

[0060] Where Is2 is the value of the bottom ideal diode between the LDMOS body terminal Pwell and the drain terminal N-epi, Area_pwell is the bottom area of ​​LDMOS Pwell, which is linearly related to the LDMOS width; Iss is the ideal diode area saturation coefficient; Vt is a constant; n is the exponential term empirical correction factor; Vds is the voltage between the drain and source terminals of LDMOS; Gmin is the simulated minimum conductance, which is a constant; and xti is the temperature correction factor.

[0061] In an embodiment of the present invention, a method for obtaining an ideal diode perimeter saturation coefficient ISWS based on an ideal diode ISW2 at a side junction between an LDMOS body terminal Pwell and a drain terminal N-epi includes:

[0062] Isw2=Peri_pwell*Isws*(T / 25)^xti / n*(e^-Vds / nVt-1)-Vds*Gmin;

[0063] Where Isw2 is the ideal diode between the LDMOS body terminal Pwell and the drain terminal N-epi, Peri_pwell is the perimeter of the LDMOS Pwell, which is linearly related to the LDMOS width; Isws is the ideal diode perimeter saturation coefficient; Vt is a constant; n is the exponential term empirical correction factor; Vds is the voltage between the drain and source terminals of the LDMOS; Gmin is the simulated minimum conductance, which is a constant; and xti is the temperature correction factor.

[0064] In an embodiment of the present invention, a method for obtaining a diode reverse tunneling current area saturation coefficient Jtun according to the third voltage-controlled current source gleak2 includes:

[0065] gleak2=-Area_pwell*Jtun*(T / 25)^xtitun*(e^-Vds / ntun*Vt-1);

[0066] Where, gleak2 is the value of the third voltage-controlled current source, Area_pwell is the bottom area of ​​the Pwell of the LDMOS, Jtun is the area saturation coefficient of the diode reverse tunneling current, Vt is a constant, T is the temperature, Vds is the voltage between the drain and source terminals of the LDMOS, ntun is the empirical correction coefficient of the exponential term, and xtitun is the temperature correction coefficient.

[0067] In an embodiment of the present invention, a method for obtaining a diode reverse tunneling current saturation coefficient Jtunsw according to the fourth voltage-controlled current source gleaksw2 includes:

[0068] gleaksw2=-Peri_pwell*Jtunsw*(T / 25)^xtitun*(e^-Vds / ntun*Vt-1);

[0069] Wherein, gleaksw2 is the value of the fourth voltage-controlled current source, Jtun is the area saturation coefficient of the diode reverse tunneling current, Peri_pwell is the perimeter of Pwell of LDMOS, Jtunsw is the perimeter saturation coefficient of the diode reverse tunneling current, Vt is a constant, T is the temperature, Vds is the voltage between the drain and source terminals of LDMOS, ntun is the empirical correction coefficient of the exponential term, and xtitun is the temperature correction coefficient.

[0070] In the embodiment of the present invention, the exponential term empirical correction coefficient n, the temperature correction coefficient xti, the exponential term empirical correction coefficient ntun, the temperature correction coefficient xtitun, the first empirical coefficient Area impe and the first empirical coefficient Peri impe All are set values. The first empirical coefficient Area impe and the first empirical coefficient Peri impe It has nothing to do with the actual device size, but is an assumed fixed empirical value.

[0071] In step S13, the model parameters are first fitted to extract the diode leakage parameters, and then extract the tunneling current parameters. From the previous analysis, it can be seen that when Vds is relatively small, the Ids leakage is mainly due to the diode leakage, and when Vds is relatively large, the Ids leakage is mainly due to the diode reverse tunneling leakage. As shown in the following figure, for Ids (Vds = 0.1V) under three different temperature conditions of 25°C, 150°C and 175°C: the parameters Iss, Isws, n, and xti are used for fitting. Because the reverse leakage is calculated, the diode does not work in the forward direction, and the parameter n can be set to 1 by default based on industry experience. Iss and Isws are related to the LDMOS size and can be used to fit the slope of Ids (Vds = 0.1V) with W at three temperatures. The temperature correction coefficient xti is related to temperature and can be used to fit the spacing of the simulation lines at three temperatures.

[0072] In step S14, for Ids (Vds = 30V) under three different temperature conditions of 25°C, 150°C and 175°C: Jtun, Jtunsw, ntun, xtitun, Area_impe and Peri_impe are used for fitting. Among them, Jtun, Jtunsw and LDMOS size are related and can be used to fit the slope of Ids (Vds = 30V) with W, xtitun and temperature are related and can be used to fit the spacing of simulation lines at three temperatures, and Ntun is mainly for the numerical change of Ids (Vds = 30V) caused by different bias voltages. In this patent, since the structure of short-circuiting the body and source ends is adopted, that is, Vbs = 0, this parameter can be ignored and can be set to the default value of 60 with reference to the industry experience value. The first empirical coefficient Area impe and the first empirical coefficient Peri impe As an empirical coefficient, it can be used to adjust the intercept of the simulation linear curve extended to the Y-axis.

[0073] Figures 10 to 21This is a simulation diagram of the Id vs. Vgs transfer characteristic curve of the LDMOS device according to an embodiment of the present invention. It can be seen that the matching effect of the model simulation according to the embodiment of the present invention at 150°C and 175°C has better description accuracy for Ids, which can provide a more accurate simulation reference for circuit designers.

[0074] In summary, the LDMOS simulation model and method provided in the embodiment of the present invention include: turning off the DC parameters and CV parameters of the MOS tube in the BSIM4 model; obtaining the ideal diode area saturation coefficient based on the bottom ideal diode of the LDMOS body and drain, obtaining the ideal diode perimeter saturation coefficient based on the side junction ideal diode of the LDMOS body and drain, obtaining the diode reverse tunneling current area saturation coefficient based on the third voltage-controlled current source, and obtaining the diode reverse tunneling current perimeter saturation coefficient based on the fourth voltage-controlled current source; when the voltage between the drain and source terminals of the LDMOS is less than a set value, obtaining the voltage between the drain and source terminals under different temperature conditions. The current is fitted using an ideal diode area saturation coefficient, an ideal diode perimeter saturation coefficient, an exponential term empirical correction coefficient, and a temperature correction coefficient, so that the current between the drain and source terminals is directly proportional to the channel width of the MOSFET; when the voltage between the drain and source terminals of the LDMOS is greater than or equal to a set value, the current between the drain and source terminals under different temperature conditions is obtained, and the diode reverse tunneling current area saturation coefficient, the diode reverse tunneling current perimeter saturation coefficient, the exponential term empirical correction coefficient, the temperature correction coefficient, the first empirical coefficient, and the first empirical coefficient are used to fit the current between the drain and source terminals so that the current between the drain and source terminals is directly proportional to the channel width of the MOSFET. Therefore, the present invention adds the ideal diode area saturation coefficient, the ideal diode perimeter saturation coefficient, the exponential term empirical correction coefficient, the temperature correction coefficient, the first empirical coefficient, and the first empirical coefficient for fitting, thereby improving the simulation accuracy of the Id vs Vgs transfer characteristic curve of the LDMOS device.

[0075] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. A simulation model of LDMOS, characterized in that: include: MOS transistor, a first resistor, a first diode, a first voltage-controlled current source, a second diode, a second voltage-controlled current source, a first variable capacitor, bottom ideal diodes at the LDMOS body and drain ends, a third voltage-controlled current source, side junction capacitors at the LDMOS body and drain ends, a fourth voltage-controlled current source, a second variable capacitor, and side junction ideal diodes at the LDMOS body and drain ends; The drain terminal of the MOS tube is connected to the first end of the first resistor, the negative end of the first diode, the positive electrode of the first voltage-controlled current source, the negative end of the second diode, the positive electrode of the second voltage-controlled current source, the first end of the first variable capacitor, the negative end of the bottom ideal diode of the LDMOS body terminal and the drain terminal, the positive electrode of the third voltage-controlled current source, the first end of the side junction capacitor of the LDMOS body terminal and the drain terminal, the negative end of the side junction ideal diode of the LDMOS body terminal and the drain terminal, the positive electrode of the fourth voltage-controlled current source and the first end of the second variable capacitor; the positive end of the first diode, the negative end of the first voltage-controlled current source, the negative end of the third voltage-controlled current source, the first end of the side junction capacitor of the LDMOS body terminal and the drain terminal, the negative end of the side junction ideal diode of the LDMOS body terminal and the drain terminal, the positive electrode of the fourth voltage-controlled current source and the first end of the second variable capacitor; The positive terminal of the second diode, the negative electrode of the second voltage-controlled current source, the second end of the first variable capacitor, the positive terminal of the bottom ideal diode of the LDMOS body and drain, the negative electrode of the third voltage-controlled current source, the second end of the second diode, the positive terminal of the side junction ideal diode of the LDMOS body and drain, the negative electrode of the fourth voltage-controlled current source, and the second end of the second variable capacitor are all connected to the body terminal of the MOS tube; the second end of the first resistor is connected to the drain terminal of the LDMOS; the source terminal of the MOS tube is connected to the body terminal of the MOS tube and connected to the source terminal of the LDMOS; and the gate terminal of the MOS tube is connected to the gate terminal of the LDMOS.

2. The LDMOS simulation model according to claim 1, wherein: The LDMOS structure includes: P-type substrate; an N-type epitaxial layer located on a surface of the P-type substrate; A Pwell located in the N-type epitaxial layer; Nwell and P+ regions located in the Pwell, wherein the Nwell and P+ regions are separated by a first shallow trench isolation structure; a first N+ region located in the Nwell; A second N+ region located in the N-type epitaxial layer, the second N+ region and the Pwell are separated by a second shallow trench isolation structure and a gate oxide and gate polysilicon on the gate oxide surface, one end of the gate oxide covers the Nwell and the Pwell, and the second end covers the second shallow trench isolation structure; The P+ region is connected as a body terminal, the first N+ region is connected as a source terminal of the LDMOS, the gate polysilicon is connected as a gate terminal of the LDMOS, and the second N+ region is connected as a drain terminal of the LDMOS.

3. The LDMOS simulation model according to claim 2, wherein: The P+ region is formed by ion implantation.

4. A method for simulating LDMOS using the simulation model of LDMOS according to any one of claims 1 to 3, characterized in that: include: Close the DC and CV parameters of the MOS tube in the BSIM4 model; An ideal diode area saturation coefficient is obtained based on the bottom ideal diode of the LDMOS body terminal and the drain terminal, an ideal diode perimeter saturation coefficient is obtained based on the side junction ideal diode of the LDMOS body terminal and the drain terminal, a diode reverse tunneling current area saturation coefficient is obtained based on the third voltage-controlled current source, and a diode reverse tunneling current perimeter saturation coefficient is obtained based on the fourth voltage-controlled current source; When the voltage between the drain and source terminals of the LDMOS is less than a set value, the current between the drain and source terminals under different temperature conditions is obtained, and fitting is performed using the ideal diode area saturation coefficient, the ideal diode perimeter saturation coefficient, the exponential term empirical correction coefficient, and the temperature correction coefficient so that the current between the drain and source terminals is directly proportional to the channel width of the MOSFET; When the voltage between the drain and source terminals of the LDMOS is greater than or equal to a set value, the current between the drain and source terminals under different temperature conditions is obtained, and fitting is performed using the diode reverse tunneling current area saturation coefficient, the diode reverse tunneling current perimeter saturation coefficient, the exponential term empirical correction coefficient, the temperature correction coefficient, the first empirical coefficient, and the first empirical coefficient, so that the current between the drain and source terminals is directly proportional to the channel width of the MOSFET.

5. The LDMOS simulation method according to claim 4, wherein: Methods for turning off DC parameters and CV parameters in the BSIM4 model include: The parasitic diode leakage saturation coefficient, the parasitic diode capacitance and the parasitic diode reverse tunneling current coefficient of the MOSFET are all set to 0.

6. The LDMOS simulation method according to claim 4, wherein: Methods for obtaining the ideal diode area saturation coefficient based on the bottom ideal diode at the body and drain ends of the LDMOS include: Is2=Area_pwell*Iss*(T / 25)^xti / n*(e^-Vds / nVt-1)-Vds*Gmin; Where Is2 is the value of the ideal diode at the bottom of the LDMOS body and drain, Area_pwell is the bottom area of ​​the LDMOS Pwell, Iss is the ideal diode area saturation coefficient, Vt is a constant, n is the empirical correction factor for the exponential term, Vds is the voltage between the drain and source of the LDMOS, Gmin is the minimum conductance of the simulation, xti is the temperature correction factor, and T is the temperature.

7. The LDMOS simulation method according to claim 4, wherein: The method of obtaining the ideal diode perimeter saturation coefficient based on the lateral junction ideal diode at the body and drain ends of the LDMOS includes: Isw2=Peri_pwell*Isws*(T / 25)^xti / n*(e^-Vds / nVt-1)-Vds*Gmin; Where Isw2 is the ideal diode between the LDMOS body and drain, Peri_pwell is the perimeter of the LDMOS Pwell, Isws is the ideal diode perimeter saturation coefficient, Vt is a constant, n is the empirical correction factor for the exponential term, Vds is the voltage between the drain and source of the LDMOS, Gmin is the minimum conductance of the simulation, xti is the temperature correction factor, and T is the temperature.

8. The LDMOS simulation method according to claim 4, wherein: The method for obtaining the area saturation coefficient of the reverse tunneling current of the diode according to the third voltage-controlled current source includes: gleak2=-Area_pwell*Jtun*(T / 25)^xtitun*(e^-Vds / ntun*Vt-1); Where, gleak2 is the value of the third voltage-controlled current source, Area_pwell is the bottom area of ​​the Pwell of the LDMOS, Jtun is the area saturation coefficient of the diode reverse tunneling current, Vt is a constant, T is the temperature, Vds is the voltage between the drain and source terminals of the LDMOS, ntun is the empirical correction coefficient of the exponential term, and xtitun is the temperature correction coefficient.

9. The LDMOS simulation method according to claim 4, wherein: The method for obtaining a diode reverse tunneling current saturation coefficient according to the fourth voltage-controlled current source includes: gleaksw2=-Peri_pwell*Jtunsw*(T / 25)^xtitun*(e^-Vds / ntun*Vt-1); Wherein, gleaksw2 is the value of the fourth voltage-controlled current source, Peri_pwell is the perimeter of Pwell of LDMOS, Jtunsw is the saturation coefficient of the diode reverse tunneling current perimeter, Vt is a constant, T is the temperature, Vds is the voltage between the drain and source terminals of LDMOS, ntun is the exponential term empirical correction coefficient, and xtitun is the temperature correction coefficient.

10. The LDMOS simulation method according to claim 4, wherein: The exponential term empirical correction coefficient, temperature correction coefficient, exponential term empirical correction coefficient, temperature correction coefficient, first empirical coefficient and first empirical coefficient are all set values.

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