A power supply circuit for powering a load

Abstract

The present invention discloses a power supply circuit, characterized in that it includes a power supply loop and a voltage slew rate boosting circuit. The power supply loop is connected to a load through a power supply node and provides a power supply current to the load to supply the energy required for the operation of the load. When the power supply loop supplies power to the load, an output voltage will be generated at the power supply node. The voltage slew rate boosting circuit is used to detect the voltage change of the output voltage at the power supply node. When the voltage slew rate boosting circuit detects that the voltage level of the output voltage drops downward, it will control the power supply loop to output more power supply current so that the voltage level of the output voltage can be accelerated to recover to the originally preset voltage level or close to the originally preset voltage level, so as to improve the slew rate of the voltage.

Description

Technical Field

[0001] The present invention belongs to the technical field of power supply circuits, and particularly relates to a power supply circuit that can improve the stability of load power supply. Background Art

[0002] In a driving integrated circuit or a single-chip integrated circuit, a power supply circuit is usually built in to step down or divide the input power supply (VDD) into one or more power supply voltages (N>=1) provided for a load. When these power supply voltages formed by voltage division or step-down are supplied to a static load, there may be no problem; however, when the load suddenly requires a large amount of power energy, it will instantaneously draw a large current, causing the voltage level of the power supply voltage to drop.

[0003] To detect whether the voltage level of the power supply voltage drops, a feedback circuit for detecting the voltage level of the power supply voltage can be provided in the conventional power supply circuit. When the power supply circuit detects through the feedback circuit that the voltage level of the power supply voltage drops, it will adjust the voltage level of the power supply voltage so that the voltage level of the power supply voltage returns to the originally preset voltage level. However, in the circuit design of the conventional power supply circuit, after the voltage level of the power supply voltage drops, it often takes a long time to return to the preset voltage level, which will cause the instability of the load operation.

[0004] In view of this, how to design a power supply circuit that can quickly restore the voltage level of the power supply voltage that has dropped after the load instantaneously draws a large current to the preset voltage level will be a problem to be solved in the field of power supply. Summary of the Invention

[0005] The present invention proposes an innovative power supply circuit to solve the deficiencies in the prior art. The purpose is to improve the slew rate of the voltage, so that the voltage level of the power supply voltage that has dropped due to the load instantaneously drawing a large current can be quickly pulled back to the preset voltage level, so as to reduce the time when the load operates with insufficient power supply voltage and improve the stability of the load power supply.

[0006] To achieve the above purpose, the present invention adopts the following technical solutions:

[0007] To achieve the above object, the present invention provides a power supply circuit, characterized in that it includes: a power supply loop, connected to a load through a power supply node, providing a power supply current to the load, and generating a first output voltage at the power supply node. The power supply loop includes: a first amplifier, connected to the power supply node and a first control point, receiving a first reference voltage and the first output voltage, and generating a first control voltage at the first control point; a first output stage, connected to the first control point and the power supply node, controlling the magnitude of the power supply current output by the first output stage with the first control voltage; and a voltage slew rate improvement circuit, including: a second amplifier, connected to the power supply node and a second control point, receiving the first reference voltage and the first output voltage, and generating a second control voltage at the second control point; a second output stage, connected to the second control point and the power supply node, controlling the conduction or cutoff of the second output stage with the second control voltage, wherein the transistor length-width ratio of the first output stage is much larger than that of the second output stage; a hysteresis circuit, connected to the second control point to receive the second control voltage and output a driving voltage, wherein the hysteresis circuit has a hysteresis function, applying a hysteresis response to the second control voltage to hysteresis the transition state of the driving voltage; and a driver, connected to the hysteresis circuit and the first control point, receiving the driving voltage, and when the driver is driven to conduct by the driving voltage, adjusting the voltage level of the first control voltage at the first control point; wherein, the first amplifier and the second amplifier preset the first output voltage to be equal to N times the first reference voltage, N being a multiple of 1 or more; when the first output voltage is less than N times the first reference voltage, the voltage slew rate improvement circuit activates the control loop, and the second control voltage controls the conduction of the second output stage and drives the driver to conduct through the hysteresis circuit, so as to adjust the first control voltage at the first control point through the conducting driver.

[0008] Preferably, the hysteresis circuit is implemented by an inverter and includes a PMOS transistor and an NMOS transistor. The PMOS transistor is a long-channel PMOS transistor. When the inverter receives a second control voltage with a falling voltage level, the PMOS transistor hysteretically responds to the second control voltage with a falling voltage level to delay the conduction time of the PMOS transistor and hysteresis the transition state of the driving voltage.

[0009] Preferably, the hysteresis circuit is implemented by an inverter and includes a PMOS transistor and an NMOS transistor. The NMOS transistor is a long-channel NMOS transistor. When the inverter receives a second control voltage with a rising voltage level, the NMOS transistor hysteretically responds to the second control voltage with a rising voltage level to delay the conduction time of the NMOS transistor and hysteresis the transition state of the driving voltage.

[0010] Preferably, the hysteresis circuit is implemented by a Schmitt trigger, which has a first threshold voltage and a second threshold voltage, with the first threshold voltage being greater than the second threshold voltage. When the Schmitt trigger receives a second control voltage with an increasing voltage level, the voltage level of the second control voltage needs to rise above the first threshold voltage for the driving voltage to change state; or when the Schmitt trigger receives a second control voltage with a decreasing voltage level, the voltage level of the second control voltage needs to fall below the second threshold voltage for the driving voltage to change state.

[0011] Preferably, the hysteresis circuit is implemented by a voltage comparator, which receives a reference voltage and the second control voltage. The reference voltage serves as a threshold for the driving voltage to change state. When the voltage comparator receives a second control voltage with an increasing voltage level, the voltage level of the second control voltage needs to rise above the reference voltage for the driving voltage to change state; or when the voltage comparator receives a second control voltage with a decreasing voltage level, the voltage level of the second control voltage needs to fall below the reference voltage for the driving voltage to change state.

[0012] In addition, the present invention provides a power supply circuit, characterized in that it includes: a power supply circuit, connected to a load through a power supply node, providing a power supply current to the load, and generating a first output voltage on the power supply node, the power supply circuit includes: a first amplifier, connected to the power supply node and a first control point, receiving a first reference voltage and a first output voltage, and generating a first control voltage on the first control point; and a first output stage, connected to the first control point and the power supply node, controlling the magnitude of the output power supply current of the first output stage with the first control voltage; and a voltage slew rate enhancement circuit, connected to the power supply node of the power supply circuit through a detection node to detect the voltage change of the first output voltage, and generating a second output voltage on the detection node, including: a second amplifier, connected to the detection node and a second control point, receiving a second reference voltage and a second output voltage, and generating a second control voltage on the second control point; a second output stage, connected to the second control point and the detection node, controlling the second output stage with the second control voltage The first output stage is turned on or off, wherein the length and width of the transistor of the first output stage is much larger than the length and width of the transistor of the second output stage; a hysteresis circuit is connected to the second control point to receive the second control voltage and output a driving voltage, wherein the hysteresis circuit has a hysteresis function, which applies a hysteresis reaction to the second control voltage to delay the transition of the driving voltage; and a driver is connected to the hysteresis circuit and the first control point, receives the driving voltage, and when the driver is driven to turn on by the driving voltage, the voltage level of the first control voltage on the first control point is adjusted; wherein the second amplifier presets the first output voltage on the power supply node to be greater than the second output voltage on the detection node; when the second amplifier determines that the first output voltage is less than the second output voltage through the voltage change of the second output voltage on the detection node, the voltage slew rate enhancement circuit starts the control loop, the second control voltage controls the second output stage to turn on and drives the driver to turn on through the hysteresis circuit, so as to adjust the first control voltage on the first control point through the turned-on driver.

[0013] Due to the adoption of the above scheme, the beneficial effect of the present invention is that the power supply circuit is provided with a voltage slew rate enhancement circuit. When the load transiently draws too much power supply current, the voltage slew rate enhancement circuit can reduce the amplitude of the output voltage drop on the power supply node, and can accelerate the output voltage on the power supply node to be pulled up and restored to the originally preset voltage level or close to the originally preset voltage level, so as to improve the power supply stability of the power supply circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 FIG. 4 is a block diagram of a power supply circuit according to an embodiment of the present invention.

[0015] Figure 2 It is a circuit diagram of an embodiment of a first amplifier and a first output stage in a power supply circuit of the present invention.

[0016] Figure 3Circuit diagram of a second amplifier and a second output stage in the power supply circuit of the present invention.

[0017] Figure 4 Circuit diagram of a hysteresis circuit and a driver in the power supply circuit of the present invention.

[0018] Figure 5 Circuit diagram of another embodiment of a hysteresis circuit and a driver in the power supply circuit of the present invention.

[0019] Figure 6 is Figure 5 The operating curve graph of the hysteresis circuit of

[0020] Figure 7 Circuit diagram of another embodiment of a hysteresis circuit and a driver in the power supply circuit of the present invention.

[0021] Figure 8 is Figure 7 The operating curve graph of the hysteresis circuit of

[0022] Figure 9 For the present invention Figure 1 The curve graph during the operation of the power supply circuit.

[0023] Figure 10 is Figure 9 The amplified curve graph during time period A in

[0024] Figure 11 Block diagram of another embodiment of the power supply circuit of the present invention.

[0025] Figure 12 Circuit diagram of another embodiment of a first amplifier and a first output stage in the power supply circuit of the present invention.

[0026] Figure 13 Circuit diagram of another embodiment of a second amplifier and a second output stage in the power supply circuit of the present invention.

[0027] Figure 14 Circuit diagram of another embodiment of a hysteresis circuit and a driver in the power supply circuit of the present invention.

[0028] Figure 15 Block diagram of another embodiment of the power supply circuit of the present invention.

[0029] Figure 16 Circuit diagram of another embodiment of a first amplifier and a first output stage in the power supply circuit of the present invention.

[0030] Figure 17 Circuit diagram of another embodiment of a second amplifier and a second output stage in the power supply circuit of the present invention.

[0031] Description of reference numerals

[0032] 100, 101, 102: Power supply circuit

[0033] 10, 10A, 10B: Power supply loop

[0034] 11, 11A, 11B: First amplifier

[0035] 12: First control point

[0036] 13, 13A, 13B: First output stage

[0037] 14: Power supply node

[0038] 20, 20A, 20B: Slew rate improvement circuit

[0039] 21, 21A, 21B: Second amplifier

[0040] 22: Second control point

[0041] 23, 23A, 23B: Second output stage

[0042] 24: Detection node

[0043] 25, 25A: Hysteresis circuit

[0044] 251, 251A: PMOS transistor

[0045] 252, 252A: NMOS transistor

[0046] 253: Schmitt trigger

[0047] 254: Voltage comparator

[0048] 27, 27A: Driver

[0049] 30: Load

[0050] 901, 911, 912, 921, 922, 931: Curve

[0051] 941: Lead Detailed implementation manner

[0052] To make the objectives, features, and advantages of the present invention more obvious and understandable, the present application will be further described in detail below in conjunction with the drawings and specific implementation manners.

[0053] First, please refer to Figure 1 , Figure 2 , Figure 3 and Figure 4, respectively, is the block diagram of an embodiment of the power supply circuit of the present invention, the circuit diagram of the first amplifier and the first output stage in the power supply circuit of the present invention, the circuit diagram of the second amplifier and the second output stage in the power supply circuit of the present invention, and the circuit diagram of the hysteresis circuit and the driver in the power supply circuit of the present invention. As Figure 1 shown, the power supply circuit 100 includes a power supply loop 10 and a slew rate boosting circuit 20. The power supply loop 10 is connected to a load 30 through a power supply node 14 and provides a power supply current I S to the load 30 to supply the energy required for the operation of the load 30. The load 30 can also be a resistive load or a capacitive load. Furthermore, when the power supply loop 10 supplies power to the load 30, a first output voltage (V O1 ) will be generated at the power supply node 14.

[0054] Referring to Figure 1 and Figure 2 simultaneously, the power supply loop 10 includes a first amplifier 11 and a first output stage 13. The first amplifier 11 is a transconductance operational amplifier (OTA) or a gain stage operational amplifier with a single-stage or multi-stage architecture. An input terminal (such as the non-inverting input terminal) of the first amplifier 11 receives a first reference voltage (V REF1 ), another input terminal (such as the inverting input terminal) is connected to the power supply node 14 and receives the first output voltage (V O1 ), and the output terminal is connected to a first control point 12 and a first control voltage (V CT1 ) is generated at the first control point 12. In the present invention, the first amplifier 11 presets the first output voltage (V O1 ) to be equal to N times the first reference voltage (V REF1 ), such as V O1 = N × V REF1 , and N can also be 1 times or a multiple of 1 or more. The first output stage 13 is the main output power supply component in the power supply circuit 100. Therefore, a transistor with a larger length-width ratio will be selected for implementation. For example, a PMOS transistor with a larger length-width ratio. The first output stage 13 is implemented using a transistor with a larger length-width ratio, which has a smaller impedance to provide a large power supply current I S to the load 30. A first end (such as the drain end) of the first output stage 13 is connected to the power supply node 14, a second end (such as the source end) is connected to a working voltage (V SS ), and a control end (such as the gate end) is connected to the first control point 12.

[0055] When the load 30 is static, the load 30 stably draws a certain amount of power supply current IS operates, the first output voltage (V O1 ) is maintained at a preset voltage level, such as V O1 = N × V REF . When the load 30 suddenly enters a transient state, such as when the load 30 suddenly requires a large amount of power energy to cope with the operation, it will instantaneously draw a large supply current I S from the power supply circuit 10, and the voltage level of the first output voltage (V O1 ) on the power supply node 14 will drop below the preset voltage level, such as V O1 < N × V REF . In the past, after the voltage level of the first output voltage (V O1 ) dropped, it often took a long time to recover to the preset voltage level. When the recovery speed of the voltage level of the first output voltage (V O1 ) is too slow, the time for the load 30 to operate with insufficient supply voltage will be relatively long, which will not only affect the normal operation of the load 30 but also may increase the probability of failure of the load 30. Therefore, in order to accelerate the recovery of the dropped voltage level of the first output voltage (V O1 ) to the original preset voltage level or close to the original preset voltage level, the present invention adds a voltage slew rate boosting circuit 20 in the power supply circuit 100.

[0056] Refer to Figure 1 , the voltage slew rate boosting circuit 20 is connected to the power supply node 14 to detect the voltage change of the first output voltage (V O1 ) generated by the power supply node 14. When the voltage slew rate boosting circuit 20 detects that the voltage level of the first output voltage (V O1 ) drops, it will control the power supply circuit 10 to output more supply current I S , so that the voltage level of the first output voltage (V O1 ) can be accelerated to recover to the original preset voltage level or close to the original preset voltage level to boost the slew rate of the voltage.

[0057] At the same time, refer to Figure 1 and Figure 3 , the voltage slew rate boosting circuit 20 includes a second amplifier 21 and a second output stage 23. The second amplifier 21 is a low-power electronic component, which can also be a transconductance operational amplifier (OTA) or a gain stage operational amplifier with a single-stage or multi-stage architecture. One input terminal (such as the non-inverting input terminal) of the second amplifier 21 receives the first reference voltage (V REF1 ), and the other input terminal (such as the inverting input terminal) is connected to the power supply node 14 and receives the first output voltage (V O1), and the output terminal is connected to a second control point 22 and a second control voltage (V is generated on the second control point 22 CT2 ). Similarly, the second amplifier 21 presets the first output voltage (V O1 ) to be equal to N times the first reference voltage (V REF1 ), such as V O1 = N × V REF1 , and N can also be 1 times or a multiple of 1 or more. In the present invention, the purpose of setting the second output stage 23 is mainly not to output power supply but to detect the voltage change of the first output voltage (V O1 ). Therefore, a transistor with a smaller length-width dimension is selected for implementation. For example, a PMOS transistor with a smaller length-width dimension. A first end (such as a drain end) of the second output stage 23 is connected to the power supply node 14, a second end (such as a source end) is connected to the operating voltage (Vss), and a control end (such as a gate end) is connected to the second control point 22. Thus, the length-width dimension of the transistor of the second output stage 23 is much smaller than that of the transistor of the first output stage 13. The second output stage 23 has a smaller parasitic capacitance, while the first output stage 13 has a larger parasitic capacitance. The size of the transistor parasitic capacitance will affect the response speed of the transistor. Therefore, the response speed of the second output stage 23 will be faster than that of the first output stage 13. As mentioned above, when the load 30 suddenly enters the transient state, a relatively large supply current I will be instantaneously drawn from the power supply loop 10 S , and the voltage level of the first output voltage (V O1 ) on the power supply node 14 will instantaneously drop and be lower than the preset voltage level, such as V O1 < N × V REF . When the voltage level of the first output voltage (V O1 ) instantaneously drops, the voltage level of the second control voltage (V CT2 ) on the second control point 22 will also instantaneously drop and quickly control the channel of the second output stage 23 with a smaller parasitic capacitance to conduct.

[0058] Further, referring to Figure 1 and Figure 3 and Figure 4 at the same time, the slew rate improvement circuit 20 further includes a hysteresis circuit 25 and a driver 27. The input terminal of the hysteresis circuit 25 is connected to the second control point 22, and the output terminal is connected to the driver 27. The input terminal of the driver 27 is connected to the hysteresis circuit 25, and the output terminal is connected to the first control point 12. The hysteresis circuit 25 is a circuit with a hysteresis function. When the load 30 enters the transient state, the hysteresis circuit 25 receives the second control voltage (V CT2 ) whose potential drops, and for the second control voltage (V CT2)Apply hysteresis to output a driving voltage (Vd), and use the driving voltage (Vd) to drive the driver 27 to conduct, so as to quickly pull down the first control voltage (V CT1 ) on the first control point 12 through the driver 27. In an embodiment of the present invention, the hysteresis circuit 25 is an inverter, which includes a PMOS transistor 251 and an NMOS transistor 252. The source of the PMOS transistor 251 is connected to the operating voltage (V SS ), the source of the NMOS transistor 252 is grounded, the gate terminals of the PMOS transistor 251 and the NMOS transistor 252 are commonly connected to the second control point 22 as the input terminal of the hysteresis circuit 25, and the drain terminals of the PMOS transistor 251 and the NMOS transistor 252 are commonly connected as the output terminal of the hysteresis circuit 25. In an embodiment of the present invention, the driver 27 is implemented by using an NMOS transistor. Its drain terminal (such as the output terminal) is connected to the first control point 12, the gate terminal (such as the input terminal) is connected to the output terminal of the hysteresis circuit 25, and the source terminal is grounded. When the input terminal of the hysteresis circuit 25 receives the falling second control voltage (V CT2 ), the PMOS transistor 251 will be turned on, and the hysteresis circuit 25 outputs a high-level driving voltage (Vd). The driver 27 is turned on through the high-level driving voltage (Vd), so that the first control voltage (V TC1 ) on the first control point 12 is pulled to ground. The first control voltage (V CT1 ) pulled to ground can control the channel of the first output stage 13 to be pulled wider, so that the first output stage 13 outputs more supply current (I S ) to the power supply node 14, and then the voltage level of the first output voltage (V O1 ) can be accelerated to rise back to the originally preset voltage level or close to the originally preset voltage level.

[0059] In addition, to prevent the voltage slew rate boosting circuit 20 from being too sensitive to small changes in the supply voltage of the power supply loop 10 (such as the first output voltage (V O1 )), the voltage slew rate boosting circuit 20 will use the hysteresis circuit 25 to hysteresis the response time. In this embodiment, the hysteresis circuit 25 implemented by an inverter will use a long-channel PMOS transistor 251 to add the hysteresis function. Since the long-channel transistor has the characteristics of large impedance and slow channel conduction speed, when the input terminal of the hysteresis circuit 25 receives the second control voltage (V CT2 ) with a falling voltage level, the long-channel PMOS transistor 251 hysteresis the response to the second control voltage (V CT2 ) with a falling voltage level. After a period of time, it still continues to receive the second control voltage (VCT2 ) Only when its channel can be turned on, can the inverter output a high-level driving voltage (Vd) to the driver 27 to turn on the driver 27.

[0060] In the above embodiments of the present invention, the voltage slew rate boosting circuit 20 uses an inverter of a long-channel PMOS transistor 251 to implement the hysteresis circuit 25; alternatively, in another embodiment of the present invention, the voltage slew rate boosting circuit 20 can also use a Schmitt trigger to implement the hysteresis circuit 25. Refer to Figure 1 , Figure 3 , Figure 5 and Figure 6 , the hysteresis circuit 25 includes a Schmitt trigger 253. The Schmitt trigger 253 is an inverting Schmitt trigger, whose input terminal is connected to the second control point 22 to receive the second control voltage (V CT2 ), and the output terminal is connected to the driver 27 to provide a driving voltage (Vd) to the driver 27. The Schmitt trigger 253 has two threshold voltages U1 and U2, where U1 > U2. In terms of the characteristics of an inverting Schmitt trigger, during the rising process of the second control voltage (V CT2 ), when it is greater than the threshold voltage U1, the voltage level of the driving voltage Vd will transition to a low-level state (-U V ); conversely, during the falling process of the second control voltage (V CT2 ), when it is less than the threshold voltage U2, the voltage level of the driving voltage Vd will transition to a high-level state (+U V ). Thus, during the falling process of the second control voltage (V CT2 ), if the second control voltage (V CT2 ) is not lower than the threshold voltage U2, the Schmitt trigger 253 hysteretically delays the transition of the driving voltage (Vd). Only when the second control voltage (V CT2 ) has dropped below the threshold voltage U2, the potential of the driving voltage (Vd) output by the Schmitt trigger 253 will transition from a low level to a high level.

[0061] In the above embodiments of the present invention, the voltage slew rate boosting circuit 20 selects to use an inverter of a long-channel PMOS transistor 251 or a Schmitt trigger to implement the hysteresis circuit 25; alternatively, in another embodiment of the present invention, the voltage slew rate boosting circuit 20 can also use a voltage comparator to implement the hysteresis circuit 25. Refer to Figure 1 , Figure 3 , Figure 7 and Figure 8 , the hysteresis circuit 25 includes a voltage comparator 254. The voltage comparator 254 includes an inverting input terminal connected to the second control point 22 to receive the second control voltage (VCT2 ), the positive input terminal is connected to a reference voltage (V REF ), and the output terminal is connected to the driver 27 to provide a driving voltage (Vd) to the driver 27. The reference voltage (V ref ) is equal to 1 / 2 of the operating voltage (V CC ) and serves as the threshold for the transition of the driving voltage (Vd). When the second control voltage (V CT2 ) is decreasing, if the second control voltage (V CT2 ) is not lower than the reference voltage (V ref ), the voltage comparator 254 will hysteretically drive the transition of the driving voltage (Vd). When the second control voltage (V CT2 ) is lower than the reference voltage (V ref ), the potential of the driving voltage (Vd) output by the voltage comparator 254 will transition from a low level to a high level.

[0062] Therefore, a hysteresis circuit 25 is added to the voltage slew rate boosting circuit 20 to adjust the sensitivity of the voltage slew rate boosting circuit 20 to the change in the supply voltage of the power supply circuit 10 through the hysteresis function provided by the hysteresis circuit 25, so as to avoid affecting the stability of the power supply of the power supply circuit 10.

[0063] Please refer to Figure 9 and Figure 10 , which are the curve diagram of the operation of the power supply circuit of the present invention Figure 1 and the enlarged curve diagram of the time period A in Figure 9 . Also refer to Figure 1 , Figure 9 and Figure 10 . Curve 901 is the curve when the load 30 draws current, curve 911 is the curve diagram of the first output voltage (V O1 ) when the voltage slew rate boosting circuit 20 is not added to the power supply circuit 100, curve 912 is the curve diagram of the first output voltage (V O1 ) after the voltage slew rate boosting circuit 20 is added to the power supply circuit 100, curve 921 is the curve diagram of the first control voltage (V CT1 ) when the voltage slew rate boosting circuit 20 is not added to the power supply circuit 100, curve 922 is the curve diagram of the second control voltage (V CT1 ) after the voltage slew rate boosting circuit 20 is added to the power supply circuit 100, and curve 931 is the curve diagram of the second control voltage (V CT2 ) after the voltage slew rate boosting circuit 20 is added to the power supply circuit 100.

[0064] When the power supply circuit 100 is operating, in time period A, the load 30 enters a transient state, and curve 901 suddenly rises upward, indicating that the load 30 draws a relatively large supply current I from the power supply circuit 10 SBefore the voltage slew rate boosting circuit 20 is added to the power supply circuit 100, in the period A, the first output voltage (V O1 ) drops rapidly, such as from 1.52V to 1.42V. After the power circuit 100 is added with the voltage slew rate enhancement circuit 20, in period A, the first output voltage (V O1 ) also drops rapidly, but the voltage drop is not large, for example, it only drops from 1.52V to 1.49V. In addition, in period A, the second control voltage (V CT2 ) is directly pulled down when the load 30 enters the transient state. Furthermore, as shown by the lead 941, the first control voltage (V CT1 ) is pulled down by the second control voltage (V CT2 ) will be controlled, and it will soon accelerate downward. Therefore, compared with curve 921 and curve 922, the first control voltage (V CT1 ) drops much faster. The first control voltage (V CT1 ) can expand the channel of the first output stage 13 in advance so that the first output stage 13 can output more power supply current (I S ) to the power supply node 14.

[0065] Here, the power circuit 100 of the present invention is provided with the voltage slew rate enhancement circuit 20. When the load 30 transiently draws too much power supply current, the voltage slew rate enhancement circuit 20 can not only reduce the output voltage (V O1 ) drops, and can accelerate the output voltage (V O1 ) is restored to an originally preset voltage level or a voltage level close to an originally preset voltage level so as to improve the power supply stability of the power supply circuit 100.

[0066] See also Figure 11 , Figure 12 , Figure 13 and Figure 14, which are respectively the block diagram of another embodiment of the power supply circuit of the present invention, the circuit diagram of the first amplifier and the first output stage in the power supply circuit of the present invention, the circuit diagram of the second amplifier and the second output stage in the power supply circuit of the present invention, and the circuit diagram of the hysteresis circuit and the driver in the power supply circuit of the present invention. The circuit architecture of the power supply circuit 101 in this embodiment is similar to that of the power supply circuit 101 in the above embodiment, with the differences being: in the above embodiment, the first output stage 13 uses a PMOS transistor with a relatively large length-width ratio as an implementation, while in this embodiment, the first output stage 13A uses an NMOS transistor with a relatively large length-width ratio as an implementation; in the above embodiment, the second output stage 23 uses a PMOS transistor with a relatively small length-width ratio as an implementation, while in this embodiment, the second output stage 23A uses an NMOS transistor with a relatively small length-width ratio as an implementation; when the hysteresis circuit 25 in the above embodiment is implemented with an inverter, a PMOS transistor 251 with a long-channel type is used to add the hysteresis function, while when the hysteresis circuit 25 in this embodiment is implemented with an inverter, an NMOS transistor 252A with a long-channel type is used to add the hysteresis function; in the above embodiment, the driver 27 is implemented with an NMOS transistor, while in this embodiment, the driver 27A is implemented with a PMOS transistor.

[0067] Refer to Figure 11 , the power supply circuit 101 includes a power supply loop 10A and a slew rate boosting circuit 20A. The power supply loop 10A is connected to the load 30 through the power supply node 14 and provides a supply current I S to the load 30 to supply the energy required for the operation of the load 30. When the power supply loop 10A supplies power to the load 30, a first output voltage (V O1 ) will be generated at the power supply node 14. When the load 30 enters a transient state and draws a relatively large supply current I S , the voltage level of the first output voltage (V O1 ) at the power supply node 14 will instantaneously drop. At this time, the slew rate boosting circuit 20A will control the power supply loop 10A to provide more supply current I S so that the voltage level of the first output voltage (V O1 ) can be accelerated to rise back to the originally preset voltage level or close to the originally preset voltage level, in order to increase the slew rate of the voltage.

[0068] Meanwhile refer to Figure 11 and Figure 12 , the power supply loop 10A includes a first amplifier 11A and a first output stage 13A. One input terminal (such as the non-inverting input terminal) of the first amplifier 11A is connected to the power supply node 14 and receives the first output voltage (V O1 ), and the other input terminal (such as the inverting input terminal) receives a first reference voltage (VREF1 ), and the output terminal is connected to a first control point 12 and a first control voltage (V is generated on the first control point 12 CT1 ). In the present invention, the first amplifier 11A presets the first output voltage (V O1 ) to be equal to N times the first reference voltage (V REF1 ), such as V O1 = N × V REF1 , and N can also be 1 times or a multiple of 1 or more. The first output stage 13A is implemented by selecting an NMOS transistor with a relatively large length-width dimension. The first output stage 13A is implemented by using a transistor with a relatively large length-width dimension, which has a relatively small impedance to provide a large supply current I S to the load 30. A first end (such as the drain end) of the first output stage 13A is connected to a working voltage (V DD ), a second end (such as the source end) is connected to the power supply node 14, and a control end (such as the gate end) is connected to the first control point 12.

[0069] Refer to Figure 11 and Figure 13 simultaneously. The voltage slew rate boosting circuit 20A includes a second amplifier 21A and a second output stage 23A. The second amplifier 21A is a low-power electronic component, which can also be a transconductance operational amplifier (OTA) or a gain stage operational amplifier with a single-stage or multi-stage architecture. An input terminal (such as the non-inverting input terminal) of the second amplifier 21A is connected to the power supply node 14 and receives the first output voltage (V O1 ), another input terminal (such as the inverting input terminal) receives the first reference voltage (V REF1 ), and the output terminal is connected to a second control point 22 and a second control voltage (V is generated on the second control point 22 CT2 ). Similarly, the second amplifier 21A presets the first output voltage (V O1 ) to be equal to N times the first reference voltage (V REF1 ), such as V O1 = N × V REF1 . The second output stage 23A is implemented by selecting an NMOS transistor with a relatively small length-width dimension. A first end (such as the drain end) of the second output stage 23A is connected to the working voltage (V DD) and a second terminal (such as a source terminal) is connected to the power supply node 14 and a control terminal (such as a gate terminal) is connected to the second control point 22. The length-width dimensions of the transistors of the second output stage 23A are much smaller than those of the transistors of the first output stage 13A. Therefore, the second output stage 23A has a smaller parasitic capacitance, while the first output stage 13A has a larger parasitic capacitance, and the response speed of the second output stage 23A will be faster than that of the first output stage 13A. As mentioned above, when the load 30 suddenly enters the transient state, a relatively large supply current I will be instantaneously drawn from the power supply loop 10A S , and the voltage level of the first output voltage (V O1 ) on the power supply node 14 will instantaneously drop downward and be lower than the preset voltage level, such as V O1 <N×V REF . When the voltage level of the first output voltage (V O1 ) instantaneously drops downward, the voltage level of the second control voltage (V CT2 ) on the second control point 22 will instantaneously rise upward and rapidly control the channel expansion of the second output stage 23A with a smaller parasitic capacitance.

[0070] Furthermore, referring also to Figure 11 , Figure 13 and Figure 14 , the slew rate boosting circuit 20A further includes a hysteresis circuit 25A and a driver 27A. The input terminal of the hysteresis circuit 25A is connected to the second control point 22, and the output terminal is connected to the driver 27A. The input terminal of the driver 27A is connected to the hysteresis circuit 25A, and the output terminal is connected to the first control point 12. When the load 30 enters the transient state, the hysteresis circuit 25A receives the second control voltage (V CT2 ) whose voltage level rises, and applies hysteresis to the second control voltage (V CT2 ) to output a driving voltage (Vd), and uses the driving voltage (Vd) to drive the driver 27A to conduct, so as to rapidly boost the first control voltage (V CT1 ) on the first control point 12 through the driver 27A. In an embodiment of the present invention, the hysteresis circuit 25A is an inverter, which includes a PMOS transistor 251A and an NMOS transistor 252A. The source electrode of the PMOS transistor 251A is connected to the operating voltage (V SS) The source of the NMOS transistor 252A is grounded, and the gate terminals of the PMOS transistor 251A and the NMOS transistor 252A are commonly connected to the second control point 22 to serve as the input terminal of the hysteresis circuit 25A. The drain terminals of the PMOS transistor 251A and the NMOS transistor 252A are commonly connected to serve as the output terminal of the hysteresis circuit 25A. In an embodiment of the present invention, the driver 27A is implemented by an NMOS transistor. Its drain terminal (such as the output terminal) is connected to the first control point 12, the gate terminal (such as the input terminal) is connected to the output terminal of the hysteresis circuit 25A, and the source terminal is connected to the operating voltage (V SS ). When the input terminal of the hysteresis circuit 25A receives the upwardly pulled second control voltage (V CT2 ), the NMOS transistor 252A will be turned on, and the hysteresis circuit 25A outputs a low-level drive voltage (Vd), such as a drive signal connected to ground. The driver 27A is turned on through the low-level drive voltage (Vd), so that the first control voltage (V TC1 ) on the first control point 12 is pulled to the power supply potential (V SS ). The first control voltage (V CT1 ) pulled to the power supply potential can control the channel of the first output stage 13A to be opened wider, so that the first output stage 13A outputs more supply current (I S ) to the power supply node 14. Furthermore, the voltage level of the first output voltage (V O1 ) can be accelerated to rise back to the originally preset voltage level or close to the originally preset voltage level.

[0071] In addition, to prevent the voltage slew rate boosting circuit 20A from being too sensitive to small changes in the supply voltage of the power supply loop 10 (such as the first output voltage (V O1 )), the voltage slew rate boosting circuit 20A will use the hysteresis circuit 25A to delay the response time. In this embodiment, the hysteresis circuit 25A implemented by an inverter will use a long-channel NMOS transistor 252A to add the hysteresis function. Since the long-channel transistor has the characteristics of a large impedance and a slow channel conduction speed, when the input terminal of the hysteresis circuit 25A receives the second control voltage (V CT2 ) with an increasing voltage level, the long-channel NMOS transistor 252A delays the response to the second control voltage (V CT2 ) with an increasing voltage level. After a period of time, when still receiving the second control voltage (V CT2 ) with an increasing voltage level, its channel can be turned on.

[0072] Implementing the hysteresis circuit 25A with an inverter of the long-channel NMOS transistor 252A in the voltage slew rate boosting circuit 20A is only one embodiment. Or, it can also refer to Figure 5Or Figure 7 In the embodiment, the hysteresis circuit 25A is implemented by a Schmitt trigger or a voltage comparator.

[0073] Therefore, the hysteresis circuit 25A is added to the slew rate boosting circuit 20A to adjust the sensitivity of the slew rate boosting circuit 20A to the voltage change of the supply voltage to the power supply loop 10A through the hysteresis function provided by the hysteresis circuit 25A, so as to avoid affecting the stability of the power supply of the power supply loop 10A.

[0074] Please refer to Figure 15 、 Figure 16 And Figure 17 , which are respectively the block diagram of another embodiment of the power supply circuit of the present invention, the circuit diagram of the first amplifier and the first output stage in the power supply circuit of the present invention, and the circuit diagram of the second amplifier and the second output stage in the power supply circuit of the present invention. As Figure 15 shown, the power supply circuit 102 includes a power supply loop 10B and a slew rate boosting circuit 20B. The power supply loop 10B is connected to a load 30 through a power supply node 14 to provide a power supply current I S to the load 30, so as to generate a first output voltage (V O1 ) at the power supply node 14. The slew rate boosting circuit 20B includes a detection node 24, which generates a second output voltage (V O2 ) at the detection node 24, and is connected to the power supply node 14 of the power supply loop 10B through the detection node 24 to detect the voltage change of the first output voltage (V O1 ), so as to determine whether to control the power supply loop 10B to provide more power supply current I S to the load 30.

[0075] At the same time, referring to Figure 15 And Figure 16 , the power supply loop 10B includes a first amplifier 11B and a first output stage 13B. The first amplifier 11B is a transconductance operational amplifier (OTA) or a gain stage operational amplifier with a single-stage or multi-stage architecture. One input terminal (such as the non-inverting input terminal) of the first amplifier 11B receives a first reference voltage (V REF1 ), the other input terminal (such as the inverting input terminal) is connected to the power supply node 14 and receives the first output voltage (V O1 ), and the output terminal is connected to a first control point 12 and generates a first control voltage (V CT1 ) at the first control point 12. In the present invention, the first amplifier 11B presets that the first output voltage (V O1 ) is equal to N times the first reference voltage (V REF1 ), such as V O1 = N × V REF1, N can also be 1 times or a multiple of 1 or more. The first output stage 13B is implemented by selecting a PMOS transistor with a relatively large length-width dimension. The drain terminal of the first output stage 13B is connected to the power supply node 14, the source terminal is connected to the operating voltage (V SS ) and the gate terminal is connected to the first control point 12.

[0076] Refer to Figure 15 and Figure 17 simultaneously. The voltage slew rate boosting circuit 20B includes a second amplifier 21B and a second output stage 23B. The second amplifier 21B is a low-power electronic component, which can also be a transconductance operational amplifier (OTA) or a gain stage operational amplifier with a single-stage or multi-stage architecture. An input terminal (such as the non-inverting input terminal) of the second amplifier 21B receives a second reference voltage (V REF2 ), another input terminal (such as the inverting input terminal) is connected to the detection node 24 and a second output voltage (V O2 ) is generated at the detection node 24, and the output terminal is connected to a second control point 22 and a second control voltage (V CT2 ) is generated at the second control point 22. The second output stage 23B is implemented by selecting a PMOS transistor with a relatively small length-width dimension. The drain terminal of the second output stage 23B is connected to the detection node 24, the source terminal is connected to the operating voltage (Vss) and the gate terminal is connected to the second control point 22. In the present invention, the length-width dimension of the transistor of the second output stage 23B is much smaller than that of the transistor of the first output stage 13B.

[0077] In this embodiment, it is preset that the first output voltage (V O1 ) on the power supply node 14 of the voltage slew rate boosting circuit 20B is greater than the second output voltage (V O2 ) on the detection node 24. When the second amplifier 21B determines that the first output voltage (V O2 ) is greater than the second output voltage (V O2 ) through the voltage change of the second output voltage (V O1 ) on the detection node 24 (such as the second output voltage (V O2 ) becomes larger), the control loop of the voltage slew rate boosting circuit 20B will be closed. For example, the channel of the second output stage 23B will be closed and the driver 27 cannot be driven to conduct through the hysteresis circuit 25. When the second amplifier 21B determines that the first output voltage (V O2 ) is less than the second output voltage (V O2 ) through the voltage change of the second output voltage (V O1 ) on the detection node 24 (such as the second output voltage (V O2) When this occurs, the control circuit of the voltage slew rate boosting circuit 20B will be activated. For example, the channel of the second output stage 23B is turned on, and the second control voltage (V CT2 ) drives the conduction of the driver 27 through the hysteresis circuit 25. The conducting driver 27 will adjust the voltage level of the first control voltage (V CT1 ) (such as pulling down the first control voltage (V CT1 )) so that the adjusted first control voltage (V CT1 ) can control the channel of the first output stage 13B to expand and output more supply current (I S ) to the supply node 14, thereby enabling the voltage level of the first output voltage (V O1 ) to accelerate the recovery to the originally preset voltage level or be close to the originally preset voltage level.

[0078] Herein, in addition to adjusting the circuit sensitivity through the hysteresis circuit 25, the voltage slew rate boosting circuit 20B of the present invention can also adjust the circuit sensitivity through the voltage difference between the two output voltages (V O1 ), (V O2 ).

[0079] Additionally, the hysteresis circuit 25 of the power supply circuit 102 in this embodiment can also be implemented with an inverter, a Schmitt trigger, or a voltage comparator with reference to Figure 4 , Figure 5 , Figure 7 or Figure 14 , which will not be elaborated herein again.

[0080] The above are only the preferred specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application, according to the technical solution and the application concept of the present application, makes equivalent substitutions or changes, and should be covered within the protection scope of the present application.

Claims

1. A power supply circuit, characterized in that, Comprising: A power supply circuit, connected to a load through a power supply node, providing a supply current to the load, and generating a first output voltage at the power supply node. The power supply circuit includes: A first amplifier, connected to the power supply node and a first control point, receiving a first reference voltage and the first output voltage, and generating a first control voltage at the first control point; and A first output stage, connected to the first control point and the power supply node, controlling the magnitude of the supply current output by the first output stage with the first control voltage; and A voltage slew rate boosting circuit, including: A second amplifier, connected to the power supply node and a second control point, receiving the first reference voltage and the first output voltage, and generating a second control voltage at the second control point; A second output stage, connected to the second control point and the power supply node, controlling the conduction or cutoff of the second output stage with the second control voltage, wherein the transistor length-width ratio of the first output stage is much larger than that of the second output stage; A hysteresis circuit, connected to the second control point to receive the second control voltage and output a drive voltage, wherein the hysteresis circuit has a hysteresis function, applying a hysteresis response to the second control voltage to hysteresis the transition state of the drive voltage; and A driver, connected to the hysteresis circuit and the first control point, receiving the drive voltage, and when the driver is driven to conduct by the drive voltage, adjusting the voltage level of the first control voltage at the first control point; Wherein, the first amplifier and the second amplifier preset the first output voltage to be equal to N times the first reference voltage, N being a multiple of 1 or more; when the first output voltage is less than N times the first reference voltage, the voltage slew rate boosting circuit starts a control loop, the second control voltage controls the conduction of the second output stage and drives the driver to conduct through the hysteresis circuit, so as to adjust the first control voltage at the first control point through the conducting driver, the adjusted first control voltage controls the channel expansion of the first output stage, and outputs more of the supply current to the power supply node, and then the voltage level of the first output voltage can be accelerated to rise back to the originally preset voltage level or close to the originally preset voltage level.

2. The power supply circuit according to claim 1, wherein The hysteresis circuit is implemented by an inverter and includes a PMOS transistor and an NMOS transistor. The PMOS transistor is a long-channel PMOS transistor. When the inverter receives the second control voltage with a dropping voltage level, the PMOS transistor hysteresis the response to the second control voltage with a dropping voltage level to delay the conduction time of the PMOS transistor and hysteresis the transition state of the drive voltage.

3. The power supply circuit according to claim 1, wherein The hysteresis circuit is implemented by an inverter and includes a PMOS transistor and an NMOS transistor. The NMOS transistor is a long-channel NMOS transistor. When the inverter receives the second control voltage with a rising voltage level, the NMOS transistor hysteresis the response to the second control voltage with a rising voltage level to delay the conduction time of the NMOS transistor and hysteresis the transition state of the drive voltage.

4. The power supply circuit according to claim 1, characterized in that, The hysteresis circuit is implemented by a Schmitt trigger which has a first threshold voltage and a second threshold voltage, and the first threshold voltage is greater than the second threshold voltage. When the Schmitt trigger receives the second control voltage with an increasing voltage level, the voltage level of the second control voltage needs to rise above the first threshold voltage before the drive voltage changes state; or when the Schmitt trigger receives the second control voltage with a decreasing voltage level, the voltage level of the second control voltage needs to fall below the second threshold voltage before the drive voltage changes state.

5. The power supply circuit according to claim 1, wherein The hysteresis circuit is implemented by a voltage comparator which receives a reference voltage and the second control voltage, and the reference voltage serves as a threshold for the change of state of the drive voltage. When the voltage comparator receives the second control voltage with an increasing voltage level, the voltage level of the second control voltage needs to rise above the reference voltage before the drive voltage changes state; or when the voltage comparator receives the second control voltage with a decreasing voltage level, the voltage level of the second control voltage needs to fall below the reference voltage before the drive voltage changes state.

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