Inverter control method, device and terminal equipment

Abstract

The present application relates to the field of inverter control technology, and in particular to an inverter control method, device and terminal equipment, the method comprising: according to a preset calculation cycle, respectively calculating each corresponding first duty cycle and second duty cycle of the inverter; wherein the first duty cycle is obtained according to the upper half bus voltage and the phase voltage amplitude and phase of the modulation wave; the second duty cycle is obtained according to the lower half bus voltage and the phase voltage amplitude and phase of the modulation wave; in the positive half cycle of the output signal of the inverter, each corresponding first duty cycle is used to control the corresponding bridge arm to work, and in the negative half cycle of the inverter output signal, each corresponding second duty cycle is used to control the corresponding bridge arm to control the inverter to output the target signal. Therefore, the present application can reduce the output voltage harmonics, improve the voltage quality, and reduce the control process's dependence on sensor accuracy.

Description

Technical Field

[0001] The present application relates to the field of inverter control technology, and in particular to an inverter control method, device and terminal equipment. Background Art

[0002] At present, there are several wave modulation methods for three-level inverters:

[0003] The space voltage vector PWM modulation method is based on the switching of the inverter space voltage vector to obtain a quasi-circular rotating magnetic field, control the inverter switching mode, and form a PWM output voltage waveform. This PWM control method treats the three-phase symmetrical sinusoidal voltage of the inverter as a whole. The resulting switching mode can enable the AC motor to obtain better performance than SPWM control even under low frequency conditions, and its DC voltage utilization rate is increased by 15.4% compared with SPWM. However, this modulation control method is complex to calculate, especially in multi-level inverters. Each calculation takes a lot of time, which affects the control speed. In addition, this control modulation control method is based on the calculation and control of the switch mode switching under the premise of forming a three-phase symmetrical sinusoidal voltage, and its unbalanced load capacity is poor.

[0004] Sine pulse width modulation (SPWM) controls the inverter switch to form a PWM output voltage waveform by comparing the sinusoidal modulation wave with the triangular carrier to obtain a set of rectangular pulse sequences with equal amplitudes and widths proportional to the sinusoidal wave. The frequency and amplitude of the voltage output by the inverter can be adjusted by changing the frequency and amplitude of the modulation wave. Each phase voltage in the three-phase symmetrical voltage is modulated by comparing the sinusoidal modulation wave with the triangular carrier alone. Each phase can be output independently and has strong unbalanced load capacity. However, in the existing SPWM three-level inverter modulation, in order to obtain a better sine wave, either a larger filter circuit is added to the output end, which is costly and bulky; or the switching frequency is increased, but the calculation cycle is also accelerated, the CPU load is increased, and it brings challenges to microcomputers with low computing power performance; at the same time, in order to reduce the output voltage distortion caused by the fluctuation of the midpoint DC bus voltage under unbalanced load, the usual practice is to increase the DC bus capacitor, which further increases the cost and volume.

[0005] In summary, the three-level inverter wave modulation method in the prior art has the problems of high cost, complex calculation, large chip load, midpoint voltage fluctuation and sensor deviation affecting the output voltage waveform, resulting in low output voltage accuracy. Summary of the invention

[0006] In view of this, the embodiments of the present application provide an inverter control method, device and terminal equipment, which can effectively solve the problems of high cost, complex calculation, high output voltage harmonics, low quality, and low voltage sensor accuracy in the three-level inverter wave modulation method in the prior art.

[0007] In a first aspect, an embodiment of the present application provides an inverter control method, the method comprising:

[0008] According to a preset calculation cycle, each corresponding first duty cycle and second duty cycle of the inverter are calculated respectively; wherein the first duty cycle is obtained according to the upper half bus voltage and the phase voltage amplitude and phase of the modulation wave; the second duty cycle is obtained according to the lower half bus voltage and the phase voltage amplitude and phase of the modulation wave;

[0009] In the positive half cycle of the inverter output signal, each corresponding first duty cycle is used to control the corresponding bridge arm to operate, and in the negative half cycle of the inverter output signal, each corresponding second duty cycle is used to control the corresponding bridge arm to control the inverter to output a target signal.

[0010] In some embodiments, the step of calculating the first duty cycle and the second duty cycle of each corresponding inverter according to a preset calculation cycle includes:

[0011] An interrupt task is triggered once every j switching cycles; wherein the interrupt task is used to calculate the sine values ​​of j consecutive target phases after the current phase, 6≥j≥2;

[0012] According to the sine values ​​of the j target phases and the corresponding upper half bus voltage and the phase voltage amplitude of the modulation wave, the first duty cycle and the second duty cycle corresponding to the consecutive j switching cycles are calculated;

[0013] The method further includes: transmitting the first duty cycle and the second duty cycle respectively corresponding to the j switching cycles to a ripple timer of the inverter by using a direct memory access method.

[0014] In some embodiments, the first duty cycle is obtained according to the upper half bus voltage and the phase voltage amplitude and phase of the modulation wave, including:

[0015]

[0016] in, is the first duty cycle, is the upper half bus voltage, is the phase of the modulation wave, t is the sampling time, is the phase voltage amplitude of the modulation wave;

[0017] The second duty cycle is obtained according to the lower half bus voltage and the phase voltage amplitude and phase of the modulation wave, including:

[0018]

[0019] in, For the second duty cycle, is the lower half bus voltage.

[0020] In some embodiments, the lower half bus voltage is determined based on a filtered value of the full bus voltage, a real-time measurement value of the full bus voltage, a real-time measurement value of the upper half bus voltage, and a filtered value of the upper half bus voltage.

[0021] In some embodiments, the lower bus voltage is determined according to a filtered value of the full bus voltage, a real-time measurement value of the full bus voltage, a real-time measurement value of the upper bus voltage, and a filtered value of the upper bus voltage, including:

[0022]

[0023] in, is the lower half bus voltage, is the filtered value of the full bus voltage, U 全实时测 The real-time measurement value of the full bus voltage, U 上实时测 is the real-time measurement value of the upper half bus voltage, is the filtered value of the upper half bus voltage.

[0024] In some embodiments, the filtered value of the upper half bus voltage and the filtered value of the full bus voltage All of them are obtained by sliding average filtering.

[0025] In some embodiments, the upper half bus voltage is determined based on a filtered value of the full bus voltage, a real-time measurement value of the upper half bus voltage, and an average value of the upper half bus voltage.

[0026] In some embodiments, the upper half bus voltage is determined according to a filtered value of the full bus voltage, a real-time measurement value of the upper half bus voltage, and an average value of the upper half bus voltage, including:

[0027]

[0028]

[0029] in, is the upper half bus voltage, is the filtered value of the full bus voltage U 上实时测 is the real-time measurement value of the upper half bus voltage, is the filtered value of the upper half bus voltage, U 上实时测_i For the iThe real-time measurement value of the upper half bus voltage obtained by sampling, m is the first sampling sequence number of the sliding window in the sliding average filter sampling, and n is the last sampling sequence number of the sliding window in the sliding average filter sampling.

[0030] In a second aspect, an embodiment of the present application provides an inverter control device, including:

[0031] A duty cycle calculation module, used to calculate the first duty cycle and the second duty cycle of each corresponding inverter according to a preset calculation cycle; wherein the first duty cycle is obtained according to the upper half bus voltage and the phase voltage amplitude and phase of the modulation wave; the second duty cycle is obtained according to the lower half bus voltage and the phase voltage amplitude and phase of the modulation wave;

[0032] An output control module is used to control the corresponding bridge arm to work by using each corresponding first duty cycle in the positive half cycle of the output signal of the inverter, and to control the corresponding bridge arm by using each corresponding second duty cycle in the negative half cycle of the output signal of the inverter, so as to control the inverter to output a target signal.

[0033] In a third aspect, an embodiment of the present application provides a terminal device, the terminal device comprising a processor and a memory, the memory storing a computer program, and the processor being used to execute the computer program to implement an inverter control method provided in the first aspect of the present application.

[0034] The embodiments of the present application have the following beneficial effects:

[0035] In the present application, the first duty cycle is obtained according to the upper half bus voltage and the phase voltage amplitude and phase of the modulation wave; the second duty cycle is obtained according to the lower half bus voltage and the phase voltage amplitude and phase of the modulation wave; in the positive half cycle of the output signal of the inverter, each corresponding first duty cycle is used to control the corresponding bridge arm to work, and in the negative half cycle of the inverter output signal, each corresponding second duty cycle is used to control the corresponding bridge arm to control the inverter to output the target signal. In other words, the present application introduces the half bus wave fluctuation quantity in the modulation calculation process to compensate for the duty cycle, so that the output voltage is stable and the harmonic content is reduced; and the calculation method is simple, so the present application can effectively solve the problems of high cost, complex calculation, high output voltage harmonics, low quality, and low voltage sensor accuracy in the prior art of the three-level inverter wave modulation method. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1 A flow chart of an inverter control method according to an embodiment of the present application is shown;

[0038] Figure 2 A topological circuit diagram of a three-level inverter in an inverter control method according to an embodiment of the present application is shown;

[0039] Figure 3 The waveform diagram of the modulation wave, carrier wave and output signal of the three-level inverter in the inverter control method according to the embodiment of the present application is shown;

[0040] Figure 4 A flow chart of a method for calculating a duty cycle in an inverter control method according to an embodiment of the present application is shown;

[0041] Figure 5 A structural schematic diagram of an inverter control device according to an embodiment of the present application is shown.

[0042] Description of main component symbols:

[0043] 510 - duty cycle calculation module; 520 - output control module. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0045] The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0046] Hereinafter, the terms "including", "having" and their cognates that can be used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or a combination of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or a combination of the foregoing items or increasing the possibility of one or more features, numbers, steps, operations, elements, components or a combination of the foregoing items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and cannot be understood as indicating or implying relative importance.

[0047] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present application.

[0048] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0049] The existing inverter output voltage has high harmonics, low quality, low voltage sensor accuracy, and control deviation caused by sensor disturbances. Therefore, the present application provides an inverter control method, device and terminal equipment to solve the above problems.

[0050] The inverter control method is described below in conjunction with some specific embodiments.

[0051] Figure 1 A flow chart of an inverter control method according to an embodiment of the present application is shown. Exemplarily, the inverter includes a three-level inverter; the inverter control method includes the following steps:

[0052] S100, according to a preset calculation cycle, respectively calculate each corresponding first duty cycle and second duty cycle of the inverter; wherein the first duty cycle is obtained according to the upper half bus voltage and the phase voltage amplitude and phase of the modulation wave; the second duty cycle is obtained according to the lower half bus voltage and the phase voltage amplitude and phase of the modulation wave.

[0053] In the three-level inverter, the SPWM method is used to calculate the switch duty cycle to control the A-phase bridge arm switch, the B-phase bridge arm switch and the C-phase bridge arm switch, such as S1, S2, S3, and S4 in phase A. After the high-frequency ripple is filtered out by the LC filter, a sinusoidal AC voltage is output, such as Figure 2 Shown is a three-level inverter topology circuit diagram.

[0054] When an unbalanced load is connected, the charging and discharging amplitudes of the midpoint voltages of the relative buses are inconsistent, resulting in an increase in the midpoint voltage fluctuation amplitude. At this time, if the duty cycle is calculated in the conventional way with the full bus voltage as the reference, the duty cycle is calculated according to the following formula:

[0055]

[0056] in, is the phase voltage amplitude of the modulation wave, is the DC bus voltage, When the bridge arm switch is driven by this duty cycle, the deviation of the actual half-bus voltage causes the deviation of the output PWM wave amplitude, causing the voltage at this phase point to be more prominent or concave than the theoretical one, such as Figure 3 The line segment with a five-pointed star in the middle, Figure 3 middle is a triangular carrier whose amplitude is half the bus voltage ; is the sine wave signal corresponding to the modulation wave, and its amplitude is ; It is the A-phase voltage actually output by the inverter.

[0057] The above reasons for the voltage at the phase point to be more prominent or concave than the theoretical value are: in the three-level inverter, the conventional duty cycle of SPWM modulation is calculated as When the half-bus voltage fluctuates slightly, the half-bus voltage is approximately equal to half of the full-bus voltage, so the impact is not significant. However, as the intermediate bus voltage fluctuates greatly, this calculation method cannot reflect the actual situation of the half-bus voltage, and the resulting duty cycle deviation is large. Therefore, in the embodiment of the present application, it is proposed to calculate the duty cycle based on the half-bus voltage, and in the positive and negative half-cycles of the sinusoidal wave signal, the real-time fluctuations of the upper and lower half-bus voltages are introduced for compensation, so that the calculation of the duty cycle can compensate for the impact caused by the real-time fluctuations of the half-bus voltage.

[0058] S200: In the positive half cycle of the output signal of the inverter, each corresponding first duty ratio is used to control the corresponding bridge arm to work, and in the negative half cycle of the output signal of the inverter, each corresponding second duty ratio is used to control the corresponding bridge arm to control the inverter to output a target signal. Figure 2 In the A phase shown, the positive half cycle of the output signal adopts the first duty cycle to control the switch tube S1 and the complementary tube S2, and the negative half cycle of the output signal adopts the second duty cycle to control the switch tube S4 and the complementary tube S3.

[0059] Furthermore, the first duty cycle is obtained according to the upper half bus voltage and the phase voltage amplitude and phase of the modulation wave, including:

[0060]

[0061] in, is the first duty cycle, is the upper half bus voltage, is the phase of the modulation wave, t is the sampling time, is the phase voltage amplitude of the modulation wave.

[0062] The second duty cycle is obtained according to the lower half bus voltage and the phase voltage amplitude and phase of the modulation wave, including:

[0063]

[0064] in, For the second duty cycle, is the lower half bus voltage.

[0065] Further, the upper half bus voltage is determined according to the filtered value of the full bus voltage, the real-time measured value of the upper half bus voltage and the average value of the upper half bus voltage. Exemplarily, the upper half bus voltage is determined according to the filtered value of the full bus voltage, the real-time measured value of the upper half bus voltage and the average value of the upper half bus voltage, including:

[0066] Formula (I)

[0067]

[0068] in, is the upper half bus voltage, is the filtered value of the full bus voltage, U 上实时测 is the real-time measurement value of the upper half bus voltage, is the filtered value of the upper half bus voltage, U 上实时测_i For the i The real-time measurement value of the upper half bus voltage obtained by sampling, m is the first sampling sequence number of the sliding window in the sliding average filter sampling, and n is the last sampling sequence number of the sliding window in the sliding average filter sampling.

[0069] Further, the lower half bus voltage is determined according to the filtered value of the full bus voltage, the real-time measurement value of the full bus voltage, the real-time measurement value of the upper half bus voltage and the filtered value of the upper half bus voltage. Exemplarily, the lower half bus voltage is determined according to the filtered value of the full bus voltage, the real-time measurement value of the full bus voltage, the real-time measurement value of the upper half bus voltage and the filtered value of the upper half bus voltage, including:

[0070] Formula (II)

[0071] in, is the lower half bus voltage, is the filtered value of the full bus voltage, U 全实时测 The real-time measurement value of the full bus voltage, U 上实时测 is the real-time measurement value of the upper half bus voltage, is the filtered value of the upper half bus voltage.

[0072] Furthermore, the filtered value of the upper half bus voltage and the filtered value of the full bus voltage All of them are obtained by sliding average filtering.

[0073] The above formula (I) and formula (II) are deduced as follows:

[0074] Formula (1-1)

[0075] Formula (1-2)

[0076] in, is the upper half bus voltage, is the lower half bus voltage, U 上波动 is the real-time fluctuation of the upper bus voltage, U 下波动 is the real-time fluctuation of the lower half bus voltage. The fluctuation is the fluctuation amplitude of the real-time value relative to the steady-state value. is the filtered value of the full bus voltage.

[0077] Further analysis of the real-time fluctuation of the upper and lower bus voltages:

[0078] Formula (1-3)

[0079] in, U 上实时测 is the real-time measurement value of the upper half bus voltage; is the filtered value of the upper half bus voltage.

[0080] Real-time measurement of upper bus voltage U 上实时测 It is equal to the true value of the upper half bus voltage plus the measurement deviation, that is:

[0081] Formula (1-4)

[0082] Among them, △ U 上偏差 is the measurement deviation of the upper half bus voltage; U 上实际is the true value of the upper half bus voltage. U 上实时测 It is the real-time measurement value of the upper half bus voltage by the sensor, which is equal to the actual true value U 上实际 Plus the measurement deviation of the sensor itself△ U 上偏差 . U 上实时测 is the value measured by the sensor in real time, which is equal to U 上实际 In addition to the sensor's own measurement deviation, no sensor can measure U 上实际 , U 上实际 is the actual physical value. U 上实时测 The sensor is real-time U 上实际 ， The value obtained by measuring this real physical value has a deviation from the real value, and the deviation is the measurement deviation of the sensor.

[0083] Filtered value of upper half bus voltage It is calculated by sliding average filtering. All real-time measurement values ​​in a sliding window of length L are accumulated and averaged. The window length depends on the sampling period of the real-time measurement value. For example, if the real-time value sampling period is 100us and the window length is 20ms, the number of samples in the window = 20ms / 100us = 200. That is:

[0084] Formula (1-5)

[0085] in, is the real-time measurement value of the upper half bus voltage obtained by the i-th sampling; m is the first sampling sequence number of the sliding window in the sliding average filter sampling, and n is the last sampling sequence number of the sliding window in the sliding average filter sampling.

[0086] Therefore, the filtered value within 20ms of the upper half bus voltage Also includes the sensor's measurement deviation △ U 上偏差 , Substituting equations (1-4) and (1-5) into equation (1-3), it can be seen that the sensor measurement deviation △ is eliminated U 上偏差 , we get formula (1): It can be understood that the analysis of eliminating the measurement deviation of the real-time fluctuation of the lower half bus voltage is similar.

[0087] The first duty cycle , the second duty cycle The calculation formula is derived:

[0088] Because the real-time measurement value of the upper half bus voltage U 上实时测 and real-time measurement of the lower half bus voltage U 下实时测 And the real-time measurement value of the full bus voltage U 全实时测 The following relationship exists:

[0089]

[0090] Filtered value of upper half bus voltage U 上L and the filtered value of the lower half bus voltage And the filtered value of the full bus voltage The following relationship exists:

[0091]

[0092] So the fluctuation of the lower half mother line is:

[0093]

[0094] It can be seen that it is only necessary to detect the full bus voltage and the upper half bus voltage, and obtain the upper and lower half bus voltages by combining the real-time value and the filtered value, and bring them into the duty cycle calculation formula:

[0095]

[0096]

[0097] At this time, the calculated duty cycle compensates for the influence of half-bus voltage fluctuation, the sinusoidality of the output voltage is better, and the harmonic content is reduced.

[0098] Based on the characteristics of this wave generation algorithm, in order to reduce the size of the filter circuit and reduce the switching harmonics, the switching frequency needs to be set higher, and the switching frequency can be set to 30kHz. However, if each switching cycle triggers an interrupt task to calculate the duty cycle of the next switching cycle, it is a huge challenge for MCUs with ordinary computing power. Therefore, in this application, further, according to the preset calculation cycle, each corresponding first duty cycle and second duty cycle of the inverter are calculated separately, including:

[0099] An interrupt task is triggered once every j switching cycles; wherein the interrupt task is used to calculate the sine values ​​of j consecutive target phases after the current phase, 6≥j≥2;

[0100] According to the sinusoidal values ​​of the j target phases and the corresponding upper half bus voltage and the phase voltage amplitude of the modulation wave, the first duty cycle and the second duty cycle corresponding to the j consecutive switching cycles are calculated.

[0101] The method further includes: transmitting the first duty cycle and the second duty cycle respectively corresponding to the j switching cycles to the ripple timer of the inverter by direct memory access (DMA). DMA, Direct Memory Access, is used to provide high-speed data transmission between peripherals and memories and between memories. Data can be quickly moved through DMA without any CPU operation.

[0102] For example, j=4, an interrupt is triggered once every 4 switching cycles, and a duty cycle calculation is performed in the interrupt task, and the sine value of the next phase is calculated each time. , and the sine values ​​corresponding to the three consecutive phases that follow , , , into the duty cycle calculation formula to obtain the duty cycle of four consecutive switching cycles (where The next phase angle of the sinusoidal modulation wave to be calculated when this interrupt comes in, Phase variation per switching cycle When the next interrupt is triggered, the next phase angle to be calculated will be , and then it increases to 360° to complete a cycle, and then starts from 0°, and the phase repeats. Finally, the DMA transfer function of the microcontroller is used to automatically transfer the duty cycle of the four switching cycles calculated and stored in the static memory in the interrupt task in each switching cycle, and sequentially transfer them from the memory to the comparison register in the corresponding wave timer, thereby updating the PWM wave output by the timer.

[0103] Its workflow is as follows Figure 4 As shown, 1) calculate the duty cycle, continuously calculate the duty cycle of 4 switching cycles, and store it in the static memory; 2) wait for the update time of the ripple timer to trigger the DMA; 3) determine whether there is a DMA trigger signal; 4) if not, execute step 3); if yes, execute step 5); 5) transmit the i-th duty cycle to the relevant register of the ripple timer; 6) determine whether the DMA transmission is completed, that is, whether i≥4 is established; 7) if not, i is increased by 1 and returns to step 3); if yes, i is cleared.

[0104] In this application, you only need to configure the relevant parameters of DMA according to the microcontroller manual, and it can run automatically as shown in the flowchart.

[0105] This application improves the SPWM wave modulation method of the three-level inverter and introduces half-bus fluctuations in the modulation calculation process to compensate for the duty cycle, so that the output voltage is stable and the harmonic content is reduced. Then, using the characteristics of DMA transmission, each wave calculation can calculate the duty cycle of multiple groups of chopped waves in advance, avoiding the limitation of MCU computing power on switching frequency, so that the switching harmonic content of the output voltage is reduced.

[0106] At the same time, the present application does not require complex calculation formulas such as SVPWM, and when the switching frequency increases, the calculation cycle of the CPU does not need to be accelerated accordingly, thereby reducing the chip load; at the same time, separate modulation is performed based on the half-bus voltage to reduce the impact of mid-point voltage fluctuations on the output voltage waveform, and the measurement of the upper and lower half-bus voltages does not rely on the accuracy of the voltage sensor, thereby eliminating the impact of sensor deviation.

[0107] Figure 5 A schematic diagram of the structure of an inverter control device according to an embodiment of the present application is shown. Exemplarily, the inverter control device includes: a duty cycle calculation module 510 and an output control module 520 .

[0108] The duty cycle calculation module 510 is used to calculate the first duty cycle and the second duty cycle of each corresponding inverter according to a preset calculation cycle; wherein the first duty cycle is obtained according to the upper half bus voltage and the phase voltage amplitude and phase of the modulation wave; the second duty cycle is obtained according to the lower half bus voltage and the phase voltage amplitude and phase of the modulation wave;

[0109] The output control module 520 is used to control the corresponding bridge arm to work by using each corresponding first duty cycle in the positive half cycle of the output signal of the inverter, and to control the corresponding bridge arm by using each corresponding second duty cycle in the negative half cycle of the output signal of the inverter, so as to control the inverter to output the target signal.

[0110] It can be understood that the device of this embodiment corresponds to the inverter control method of the above embodiment, and the options in the above embodiment are also applicable to this embodiment, so they will not be described repeatedly here.

[0111] The present application also provides a terminal device, which exemplarily includes a processor and a memory, wherein the memory stores a computer program, and the processor runs the computer program to enable the terminal device to execute the functions of each module in the above inverter control method or the above inverter control device. The terminal device is the control end of the inverter.

[0112] Among them, the processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including a central processing unit (CPU), a graphics processing unit (GPU), a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or at least one of other programmable logic devices, discrete gates or transistor logic devices, and discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc., which can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application.

[0113] The memory may be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electric erasable programmable read-only memory (EEPROM), etc. The memory is used to store a computer program, and the processor may execute the computer program accordingly after receiving an execution instruction.

[0114] The present application also provides a computer-readable storage medium for storing the computer program used in the above terminal device. For example, the computer-readable storage medium may include but is not limited to: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0115] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or the flow diagram, and the combination of boxes in the structure diagram and / or the flow diagram, can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0116] In addition, the functional modules or units in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0117] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.

[0118] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. An inverter control method, characterized in that: The inverter comprises a three-level inverter, and the method comprises: According to a preset calculation cycle, each corresponding first duty cycle and second duty cycle of the inverter are calculated respectively; wherein the first duty cycle is obtained according to the upper half bus voltage and the phase voltage amplitude and phase of the modulation wave; the second duty cycle is obtained according to the lower half bus voltage and the phase voltage amplitude and phase of the modulation wave; In a positive half cycle of the output signal of the inverter, each corresponding first duty ratio is used to control the corresponding bridge arm to work, and in a negative half cycle of the output signal of the inverter, each corresponding second duty ratio is used to control the corresponding bridge arm, so as to control the inverter to output a target signal; The step of calculating the first duty cycle and the second duty cycle of each corresponding inverter according to a preset calculation cycle includes: An interrupt task is triggered once every j switching cycles; wherein the interrupt task is used to calculate the sine values ​​of j consecutive target phases after the current phase, 6≥j≥2; According to the sine values ​​of the j target phases and the corresponding upper half bus voltage and the phase voltage amplitude of the modulation wave, the first duty cycle and the second duty cycle corresponding to the consecutive j switching cycles are calculated; The method further includes: transmitting the first duty cycle and the second duty cycle respectively corresponding to the j switching cycles to a ripple timer of the inverter by using a direct memory access method.

2. The inverter control method according to claim 1, characterized in that: The first duty cycle is obtained according to the upper half bus voltage and the phase voltage amplitude and phase of the modulation wave, including: in, is the first duty cycle, is the upper half bus voltage, is the phase of the modulation wave, t is the sampling time, is the phase voltage amplitude of the modulation wave; The second duty cycle is obtained according to the lower half bus voltage and the phase voltage amplitude and phase of the modulation wave, including: in, For the second duty cycle, is the lower half bus voltage.

3. The inverter control method according to claim 1, characterized in that: The lower bus voltage is determined according to the filtered value of the full bus voltage, the real-time measured value of the full bus voltage, the real-time measured value of the upper bus voltage and the filtered value of the upper bus voltage.

4. The inverter control method according to claim 3, characterized in that: The lower bus voltage is determined according to the filtered value of the full bus voltage, the real-time measured value of the full bus voltage, the real-time measured value of the upper bus voltage and the filtered value of the upper bus voltage, including: in, is the lower half bus voltage, is the filtered value of the full bus voltage, U 全实时测 The real-time measurement value of the full bus voltage, U 上实时测 is the real-time measurement value of the upper bus voltage, is the filtered value of the upper half bus voltage.

5. The inverter control method according to claim 3, characterized in that: The filtered value of the upper half bus voltage and the filtered value of the full bus voltage All of them are obtained by sliding average filtering.

6. The inverter control method according to claim 1, characterized in that: The upper half bus voltage is determined according to a filtered value of the full bus voltage, a real-time measurement value of the upper half bus voltage and an average value of the upper half bus voltage.

7. The inverter control method according to claim 6, characterized in that: The upper half bus voltage is determined according to the filtered value of the full bus voltage, the real-time measurement value of the upper half bus voltage and the average value of the upper half bus voltage, including: in, is the upper half bus voltage, is the filtered value of the full bus voltage, is the filtered value of the upper half bus voltage, U 上实时测 is the real-time measurement value of the upper bus voltage, U 上实时测_i For the i The real-time measurement value of the upper half bus voltage obtained by sampling, m is the first sampling sequence number of the sliding window in the sliding average filter sampling, and n is the last sampling sequence number of the sliding window in the sliding average filter sampling.

8. An inverter control device, characterized in that: include: A duty cycle calculation module, used to calculate the first duty cycle and the second duty cycle of each corresponding inverter according to a preset calculation cycle; wherein the first duty cycle is obtained according to the upper half bus voltage and the phase voltage amplitude and phase of the modulation wave; the second duty cycle is obtained according to the lower half bus voltage and the phase voltage amplitude and phase of the modulation wave; wherein the first duty cycle and the second duty cycle of each corresponding inverter are calculated according to the preset calculation cycle, including: An interrupt task is triggered once in every j switching cycles; wherein the interrupt task is used to calculate the sine values ​​of the j consecutive target phases after the current phase, 6≥j≥2; according to the sine values ​​of the j target phases and the corresponding upper half bus voltage and the phase voltage amplitude of the modulation wave, the first duty cycle and the second duty cycle corresponding to the j consecutive switching cycles are calculated; and further comprising: transmitting the first duty cycle and the second duty cycle corresponding to the j switching cycles to the wave generation timer of the inverter by direct memory access; An output control module is used to control the corresponding bridge arm to work by using each corresponding first duty cycle in the positive half cycle of the output signal of the inverter, and to control the corresponding bridge arm by using each corresponding second duty cycle in the negative half cycle of the output signal of the inverter, so as to control the inverter to output a target signal.

9. A terminal device, characterized in that: The terminal device comprises a processor and a memory, wherein the memory stores a computer program, and the processor is configured to execute the computer program to implement the inverter control method according to any one of claims 1 to 7.

Images