Motor vector control encoding method, system and terminal

Abstract

The present invention provides a motor vector control encoding method, system and terminal, which generates the encoding of the three-phase control circuit by inputting relevant configuration parameters such as angle, number of lines and D / Q axis control variables, and performing sine and cosine calculations, multiplication calculations and addition calculations to control the PWM drive motor. The present invention completes the encoding output of the three-phase motor control in the motor vector control, which can effectively save hardware resource overhead, reduce chip area and reduce costs.

Description

Technical Field

[0001] The invention relates to integrated circuit design, and in particular to a motor vector control encoding method, system and terminal. Background Art

[0002] With the advancement of technology and the improvement of integrated circuit design capabilities, the application of application-specific integrated circuits (ASICs) in the field of motor control is indeed becoming more and more widespread. ASICs are customized for specific applications and can provide higher performance, lower power consumption and smaller size than general-purpose processors or microcontrollers. As the number of motors that can be controlled by a single chip increases, the complexity of the design also increases accordingly, thereby increasing development costs. Summary of the invention

[0003] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a motor vector control encoding method, system and terminal, which are used to solve the technical problem that as the number of motors that can be controlled by a single chip increases, the design complexity also increases accordingly, thereby increasing the development cost.

[0004] To achieve the above-mentioned purpose and other related purposes, the present invention provides a motor vector control encoding method, which includes: inputting relevant configuration parameters; wherein the relevant configuration parameters include: angle, angle input valid indication signal, number of lines, input angle filter threshold, A-phase relative offset angle, B-phase relative offset angle and C-phase relative offset angle, D-axis control component, Q-axis control component and control component sampling indication signal; and the input angle, input angle filter threshold, A-phase relative offset angle, B-phase relative offset angle and C-phase relative offset angle, D-axis control component and Q-axis control component all use the same number of bits; based on the input relevant configuration parameters, generate the encoding of the three-phase control circuit for controlling the PWM drive motor.

[0005] In one embodiment of the present invention, the generation of the code of the three-phase control circuit based on the input related configuration parameters includes: filtering the input angle based on the input angle filtering threshold, and making the three-phase code calculation trigger signal a valid level through filtering; when the received three-phase code calculation trigger signal is a valid level, using the three-phase code calculation module to perform sine and cosine calculations, multiplication calculations and addition calculations based on the input related configuration parameters to generate the code of the three-phase control circuit.

[0006] In one embodiment of the present invention, the three-phase encoding calculation module includes: a sine-cosine calculation unit, which is used to perform sine-cosine calculation on the input angle and output a signed sine-cosine calculation result; a multiplier unit, which is used to perform multiplication calculation on two input signed or unsigned multipliers based on the multiplication calculation rule, and output the corresponding multiplication calculation result; an adder unit, which is used to perform addition or subtraction calculation on two input signed or unsigned addends, and output the corresponding addition calculation result; a computing resource scheduling controller, which is connected to the sine-cosine calculation unit, the multiplier unit, and the adder unit, and is used to control the sine calculation unit, the multiplier unit, and the adder unit to perform sine calculation, multiplication calculation, and addition calculation according to the input related configuration parameters based on the resource scheduling mechanism to obtain the encoding of the three-phase control circuit.

[0007] In one embodiment of the present invention, the multiplication calculation rule includes: if the highest digit k of the input first multiplier is less than the highest digit n of the second multiplier, a padding operation is first performed on the high digit of the first multiplier, and then the first multiplier and the second multiplier after the padding are input into a multiplier for multiplication calculation to obtain a 2n+1-bit multiplier calculation result, and when the first multiplier and / or the second multiplier are signed, the 2nth to nth digits of the multiplier calculation result are output as the multiplication calculation result, and when both the first multiplier and the second multiplier are unsigned, the nth to 0th digits of the multiplier calculation result are output as the multiplication calculation result; if the highest digit k of the input first multiplier is greater than or equal to the highest digit n of the second multiplier, and less than 1.5 times the highest digit n of the second multiplier, a padding operation is first performed on the high digit of the first multiplier, and then the first multiplier and the second multiplier after the padding are input into a multiplier for multiplication calculation to obtain a k+n+2-bit multiplication calculation result. The method comprises the steps of: obtaining a first multiplier and a second multiplier and outputting the first to nth bits of the multiplier calculation result as the multiplication calculation result, and outputting the nth to 0th bits of the multiplier calculation result as the multiplication calculation result when the first multiplier and the second multiplier are both unsigned; if the highest bit k of the input first multiplier is greater than 1.5 times the highest bit n of the second multiplier, for the case where the first multiplier and the second multiplier are unsigned, inputting the first multiplier and the second multiplier into the unsigned multiplier for multiplication calculation to obtain a k+n+2-bit unsigned multiplier calculation result, and outputting the nth to 0th bits of the unsigned multiplier result as the multiplication calculation result; for the case where the first multiplier and / or the second multiplier are signed, inputting the first multiplier and the second multiplier into the signed multiplier for multiplication calculation to obtain a 2n+1-bit signed multiplication calculation result, and outputting the 2nth to nth bits of the signed multiplication result as the multiplication calculation result.

[0008] In one embodiment of the present invention, the adder unit includes: a signed adder and an unsigned adder; wherein the signed adder is used to perform subtraction calculation on two n+1-bit signed numbers to obtain an n+1-bit signed adder calculation result; if the adder calculation result exceeds a set range, the adder calculation result is output according to saturation truncation; if the adder calculation result does not exceed the set range, the adder calculation result is output; wherein, if the adder calculation result is less than -2 n , then -2 n As the addition result output, if the adder calculation result is greater than 2 n -1, then 2 n -1 is output as the addition result; the unsigned adder is used to perform addition calculation on two unsigned addends with an effective number of n+1 to obtain an n+1-bit signed adder calculation result; if the adder calculation result is greater than 2 n+1 -1, then the adder calculation result is subtracted by 2 n+1 -1 The calculation result obtained is output as the addition result; if the adder calculation result is not greater than 2 n+1 -1, the adder calculation result is output.

[0009] In one embodiment of the present invention, the resource scheduling mechanism includes: inputting the angle and the number of lines into a multiplier unit for multiplication calculation, and outputting the corresponding initial relative offset angle; inputting the initial relative offset angle and the relative offset angle of phase A, phase B and phase C into an adder unit for addition calculation, and outputting the corresponding phase A angle, phase B angle and phase C angle in sequence; inputting the output corresponding phase A angle, phase B angle and phase C angle into a sine calculation unit in sequence for sine and cosine calculation, and obtaining the sine and cosine calculation results of phase A, phase B and phase C, respectively; The D-axis control component and the Q-axis control component are respectively input into the multiplier unit with the A-phase sine-cosine calculation result, the B-phase sine-cosine calculation result and the C-phase sine-cosine calculation result for calculation, and the A-phase sine-cosine multiplication calculation result, the B-phase sine-cosine multiplication calculation result and the C-phase sine-cosine multiplication calculation result are obtained in sequence; the A-phase sine-cosine multiplication calculation result, the B-phase sine-cosine multiplication calculation result and the C-phase sine-cosine multiplication calculation result are input into the adder in sequence for addition calculation, and the A-phase voltage vector value, the B-phase voltage vector value and the C-phase voltage vector value are obtained; and the A-phase voltage vector value, the B-phase voltage vector value and the C-phase voltage vector value are output.

[0010] In one embodiment of the present invention, the resource scheduling mechanism includes: inputting the angle and the number of lines into the multiplier unit for multiplication calculation based on the multiplication calculation rule, and outputting the corresponding initial relative offset angle; inputting the initial relative offset angle and the relative offset angle of the A phase into the unsigned adder for addition calculation, and outputting the corresponding A phase angle; inputting the initial relative offset angle and the relative offset angle of the B phase into the unsigned adder for addition calculation to output the corresponding B phase angle, and at the same time inputting the A phase angle into the sine calculation unit for sine calculation to output the signed A phase sine value and the cosine value of phase A; the initial relative offset angle and the relative offset angle of phase C are input into the unsigned adder for addition calculation and output of the corresponding phase C angle, and the phase B angle is input into the sine calculation unit for sine calculation to output the signed phase B sine value and phase B cosine value, and the phase A cosine value and the D-axis control component are input into the multiplier unit for multiplication calculation to obtain the phase A cosine multiplication result; the phase C angle is input into the sine calculation unit for sine calculation to output the signed phase C sine value and phase C cosine value, and the phase A sine value and the Q-axis control component are input into the multiplier unit for multiplication calculation to obtain the phase A cosine multiplication result. Input the multiplier unit for multiplication to obtain the A-phase sine multiplication result; input the A-phase cosine multiplication result and the A-phase sine multiplication result into the signed adder for subtraction to obtain the A-phase voltage vector value, and at the same time input the B-phase cosine value and the D-axis control component into the multiplier unit for multiplication to obtain the B-phase cosine multiplication result; input the B-phase sine value and the Q-axis control component into the multiplier unit for multiplication to obtain the B-phase sine multiplication result; input the B-phase cosine multiplication result and the B-phase sine multiplication result into the signed adder The adder performs subtraction calculation to obtain the B-phase voltage vector value, and simultaneously inputs the C-phase cosine value and the D-axis control component into the multiplier unit for multiplication calculation to obtain the C-phase cosine multiplication result; the C-phase sine value and the Q-axis control component are input into the multiplier unit for multiplication calculation to obtain the C-phase sine multiplication result; the C-phase cosine multiplication result and the C-phase sine multiplication result are input into the signed adder for subtraction calculation to obtain the C-phase voltage vector value; the A-phase voltage vector value, the B-phase voltage vector value and the C-phase voltage vector value are output to obtain the encoding of the three-phase control circuit.

[0011] In one embodiment of the present invention, the input angle is filtered based on the input angle filtering threshold, and a three-phase coding calculation trigger signal is generated when the angle passes the filtering, including: determining whether the angle difference between the input angle and the angle that passed the filtering last time exceeds the angle filtering threshold, and when it does not exceed the angle filtering threshold, using the angle as the angle that passes the filtering, and generating a three-phase coding calculation trigger signal.

[0012] To achieve the above-mentioned purpose and other related purposes, the present invention provides a motor vector control encoding system, the system comprising: an input module, used to input relevant configuration parameters; wherein the relevant configuration parameters include: angle, angle input valid indication signal, number of lines, input angle filter threshold, A phase relative offset angle, B phase relative offset angle and C phase relative offset angle, D axis control component, Q axis control component and control component sampling indication signal; and the input angle, input angle filter threshold, A phase relative offset angle, B phase relative offset angle and C phase relative offset angle, D axis control component and Q axis control component all use the same number of bits; a three-phase encoding calculation module, connected to the input module, used to generate the encoding of the three-phase control circuit based on the input relevant configuration parameters for controlling the PWM drive motor.

[0013] To achieve the above-mentioned purpose and other related purposes, the present invention provides a motor vector control encoding terminal, comprising: one or more memories and one or more processors; the one or more memories are used to store computer programs; the one or more processors are connected to the memories and are used to run the computer program to execute the motor vector control encoding method.

[0014] As described above, the present invention is a motor vector control encoding method, system and terminal, which has the following beneficial effects: the present invention generates the encoding of the three-phase control circuit by inputting relevant configuration parameters such as angle, number of lines and D / Q axis control variables, and performing sine and cosine calculations, multiplication calculations and addition calculations to control the PWM drive motor. The present invention completes the encoding output of the three-phase motor control in the motor vector control, which can effectively save hardware resource overhead, reduce chip area and reduce costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic flow chart of a motor vector control encoding method in one embodiment of the present invention.

[0016] Figure 2 It is a schematic diagram of the structure of a three-phase encoding calculation module in one embodiment of the present invention.

[0017] Figure 3 Shown is a structural schematic diagram of a motor vector control encoding system in an embodiment of the present invention.

[0018] Figure 4 Shown is a schematic diagram of the structure of a motor vector control encoding terminal in one embodiment of the present invention. DETAILED DESCRIPTION

[0019] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0020] It should be noted that in the following description, reference is made to the accompanying drawings, which describe several embodiments of the present invention. It should be understood that other embodiments may also be used, and that mechanical composition, structural, electrical and operational changes may be made without departing from the spirit and scope of the present invention. The following detailed description should not be considered restrictive, and the scope of the embodiments of the present invention is limited only by the claims of the published patents. The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. Spatially related terms, such as "upper", "lower", "left", "right", "below", "below", "lower", "above", "upper", etc., may be used in the text to facilitate the description of the relationship between an element or feature shown in the figure and another element or feature.

[0021] Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a part is said to "include" a certain constituent element, unless otherwise stated, it does not exclude other constituent elements, but means that other constituent elements may be included.

[0022] The terms first, second and third mentioned herein are used to describe various parts, components, regions, layers and / or segments, but are not limited thereto. These terms are only used to distinguish a certain part, component, region, layer or segment from other parts, components, regions, layers or segments. Therefore, the first part, component, region, layer or segment described below may refer to the second part, component, region, layer or segment within the scope of the present invention.

[0023] Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless there is an indication to the contrary in the context. It should be further understood that the terms "comprise", "include" indicate the presence of the described features, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions or operations is inherently mutually exclusive in some way.

[0024] A motor vector control encoding method of the present invention generates the encoding of a three-phase control circuit by inputting relevant configuration parameters such as angle, number of lines and D / Q axis control variables, and performing sine and cosine calculations, multiplication calculations and addition calculations to control a PWM drive motor. The present invention completes the encoding output of the three-phase motor control in the motor vector control, which can effectively save hardware resource overhead, reduce chip area and reduce costs.

[0025] The following is a detailed description of the embodiments of the present invention with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0026] like Figure 1 A flow chart showing a motor vector control encoding method in an embodiment of the present invention.

[0027] The method comprises:

[0028] Step S1: Input relevant configuration parameters.

[0029] In detail, the input related configuration parameters include:

[0030] (1) Angle, represented by angle[n:0], represents the input of electrical angle or mechanical angle. The number of valid digits is n+1. The minimum input value is 0 and the maximum input value is 2. n+1 -1; the angle value conversion relationship corresponding to the input angle[n:0] is: angle°=360°*(angle[n:0] / (2 n+1 -1)).

[0031] (2) Angle input valid indication signal, denoted by angle_valid, when it is at a valid level (can be defined as high or low), it indicates that the current angle[n:0] input value is valid.

[0032] (3) The number of lines, represented by resolution[k:0], refers to the number of cycles of the input angle angle[n:0] in one physical rotation cycle of the motor. The number of effective bits is k+1, and the maximum configurable number of lines is 2 k+1 -1.

[0033] (4) Input angle filter threshold, denoted by angle_filter[n:0], represents the filter threshold of the input angle angle[n:0], which is used to filter the glitches of the input angle.

[0034] (5) The relative offset angle of phase A, phase B, and phase C are represented by angle_shift_a[n:0], angle_shift_b[n:0], and angle_shift_c[n:0], respectively, representing the offset angle of phase A relative to the input angle, the offset angle of phase B relative to the input angle, and the offset angle of phase C relative to the input angle. For example, when three-phase orthogonal output is desired, each with a difference of 120°, the following can be configured:

[0035] angle_shift_a[n:0]=0, angle_shift_b=(2 n+1 / 3)*2; angle_shift_c=2 n+1 / 3, at this time, phase a

[0036] Leading phase b by 120°, phase b leads phase c by 120°.

[0037] (6) The D-axis control component and the Q-axis control component are represented by vd[n:0] and vq[n:0], respectively, which represent the D-axis control component in the DQ rotation coordinate system, with a bit number of n+1 bits, and the highest bit is the sign bit.

[0038] (7) The control component sampling indication signal is represented by vdvq_valid. When vdvq_valid is at a valid level, it indicates that vd[n:0] and vq[n:0] are valid.

[0039] It should be noted that the input angle, input angle filter threshold, A-phase relative offset angle, B-phase relative offset angle, C-phase relative offset angle, D-axis control component and Q-axis control component all use the same number of bits, i.e., n+1 bits.

[0040] Step S2: Based on the input related configuration parameters, generate the code of the three-phase control circuit for controlling the PWM drive motor.

[0041] In one embodiment, generating the code of the three-phase control circuit based on the input related configuration parameters includes:

[0042] Based on the input angle filter threshold, the input angle is filtered, and the three-phase encoding calculation trigger signal is modulated to a valid level when the angle passes the filter; in a specific embodiment, it is determined whether the angle difference between the input angle and the angle that passed the filter last time exceeds the angle filter threshold, and when it does not exceed the angle filter threshold, the angle is used as the angle that passes the filter, and the three-phase encoding calculation trigger signal is made to be a valid level; specifically, when the absolute difference between the latest input valid angle angle[n:0] and the last angle latched by the filter exceeds angle_filter[n:0], the current input angle angle[n:0] is ignored; otherwise, the current valid angle will be latched, and cal_valid will be made valid, indicating that the three-phase encoding calculation module starts a new calculation.

[0043] When the received three-phase code calculation trigger signal is at a valid level, the three-phase code calculation module is used to perform sine and cosine calculations, multiplication calculations, and addition calculations based on input related configuration parameters to generate the code of the three-phase control circuit.

[0044] In one embodiment, if Figure 2 , the three-phase encoding calculation module includes:

[0045] The sine and cosine calculation unit 201 is used to perform sine and cosine calculation on the input angle and output the signed sine and cosine calculation result;

[0046] The multiplier unit 202 is used to perform multiplication calculation on two input signed or unsigned multipliers based on the multiplication calculation rule, and output the corresponding multiplication calculation result;

[0047] The adder unit 203 is used to perform addition or subtraction calculation on two signed or unsigned addends inputted, and output the corresponding addition calculation result;

[0048] The computing resource scheduling controller 204, as the core part of the module, is responsible for coordinating the work of each sub-unit (sin-cos calculation unit, multiplier unit, adder unit). The computing resource scheduling controller is connected to the sin-cos calculation unit 201, the multiplier unit 202, and the adder unit 203, and is used to control the sin-cos calculation unit 201 to perform sine calculation, control the multiplier unit 202 to perform multiplication calculation, and control the adder unit 203 to perform addition calculation based on the resource scheduling mechanism and the input related configuration parameters, and finally obtain the encoding of the three-phase control circuit.

[0049] In a specific embodiment, the sine and cosine calculation unit 201 takes as input an n+1-bit angle and outputs an n+1-bit signed sine value sin(angle) and cosine value cos(angle).

[0050] In a specific embodiment, the multiplier unit 202 implements the multiplication of two input multipliers. The multiplication calculation in the present invention includes signed multiplication and unsigned multiplication, and the effective number of input multipliers of different multiplication calculations is also different. In order to realize the sharing of multiplier hardware resources, the multiplication calculation rules are set as follows:

[0051] If the highest digit k of the input first multiplier is less than the highest digit n of the second multiplier, the unsigned multiplication calculation in the multiplier unit 202 can share the same signed multiplier with the signed multiplication calculation in other calculation steps. At this time, the maximum number of input valid digits in all multiplication calculations is n+1. In order to realize that the signed and unsigned multipliers share the same multiplier, the two input multiplier bit widths m1 and m2 of the signed multiplier are both equal to n+1. That is, when the valid digits of the input first multiplier are less than n+1 bits, it is necessary to fill the high bits to fill the valid digits to n+1 bits, fill the high bits with 0, and then fill the filled bits. The first multiplier and the second multiplier are input into a multiplier for multiplication to obtain a 2n+1-bit multiplier calculation result, which is recorded as mul_result[2n:0]. There are two types of output results of the multiplier. When the first multiplier and / or the second multiplier are signed, the 2nth to nth bits of the multiplier calculation result are output as the multiplication calculation result, that is, mul_result[2n:n]; when both the first multiplier and the second multiplier are unsigned, the nth to 0th bits of the multiplier calculation result are output as the multiplication calculation result, that is, mul_result[n:0];

[0052] If the highest digit k of the first multiplier input is greater than or equal to the highest digit n of the second multiplier, and less than 1.5 times the highest digit n of the second multiplier, the unsigned multiplication calculation and the signed multiplication calculation share a multiplier. At this time, the maximum input valid digit in all multiplication calculations is k+1, then the two input multiplier bit widths m1 of the signed multiplier are equal to k+2, and m2 is equal to n+1. When the valid digit of the first multiplier input is less than the valid digit of the multiplier input, the high digit of the first multiplier is first padded, and the high digit of the unsigned multiplier is padded with 0, and its valid digit is padded to k+2, and then the padded first multiplier is padded. A multiplier and a second multiplier are input into a multiplier for multiplication to obtain a k+n+2-bit multiplication result, recorded as mul_result[k+n+1:0]. There are two types of output results of the multiplier. When the first multiplier and / or the second multiplier are signed, the 2nth to nth bits of the multiplier calculation result are output as the multiplication calculation result, that is, mul_result[2n:n]; when the first multiplier and the second multiplier are both unsigned, the nth to 0th bits of the multiplier calculation result are output as the multiplication calculation result, that is, mul_result[n:0].

[0053] If the highest digit k of the input first multiplier is greater than 1.5 times the highest digit n of the second multiplier, the multiplier unit includes a (k+1)-bit by (n+1)-bit unsigned multiplier and a (n+1)-bit by (n+1)-bit signed multiplier. In the case where the first multiplier and the second multiplier are unsigned, the first multiplier and the second multiplier are input into an unsigned multiplier for multiplication calculation to obtain a k+n+2-bit unsigned multiplier calculation result, recorded as mul_result_unsigned[k+n+1:0], and the nth bit to the 0th bit in the unsigned multiplier result are output as the multiplication calculation result, that is, mul_result_unsigned[n:0]; in the case where the first multiplier and / or the second multiplier are signed, the first multiplier and the second multiplier are input into a signed multiplier for multiplication calculation to obtain a 2n+1-bit signed multiplication calculation result, recorded as mul_result_signed[2n:0], and the 2nth bit to the nth bit in the signed multiplication result are output as the multiplication calculation result, that is, mul_result_signed[2n:n].

[0054] In a specific embodiment, the adder unit 203 includes: a signed adder and an unsigned adder;

[0055] The signed adder is used to input two n+1-bit signed numbers for subtraction to obtain an n+1-bit signed adder calculation result; if the adder calculation result exceeds a set range, the adder calculation result is output according to saturation truncation; if the adder calculation result does not exceed the set range, the addition calculation result is output;

[0056] If the adder calculation result exceeds the set range, the adder calculation result is saturated and truncated and output includes: if the adder calculation result is less than -2 n , then -2 n As the addition result output, if the adder calculation result is greater than 2 n -1, then 2 n -1 is output as the addition result; specifically, two n+1-bit signed numbers are input and the output is an n+1-bit signed number. When the adder result exceeds [-2 n ,2 n -1], the output result is saturated and truncated, that is, the adder result is less than -2 n , then press -2 n Output the calculation result. If the adder result is greater than 2 n -1, then press 2 n -1 output result.

[0057] The unsigned adder is used to input two n+1-bit unsigned numbers for addition calculation to obtain an n+1-bit signed adder calculation result; if the adder calculation result is greater than 2 n+1 -1, then the adder calculation result is subtracted by 2 n+1 -1 is used as the calculation result of the adder; if the calculation result of the adder does not exceed the set range, the calculation result of the adder is output. Specifically, the input is two n+1-bit unsigned numbers, and the output is an n+1-bit signed number. When the adder result exceeds 2 n+1 When -1, the calculation result is rolled back and output. Assuming the standard calculation result is sum_unsigned, if the adder result sum_unsigned is less than or equal to 2 n+1 When -1, sum_unsigned is output normally. When the adder result is greater than 2 n+1 When -1, the adder output is sum_unsigned-2 n+1 .

[0058] In one embodiment, the computing resource scheduling controller 204 completes the scheduling of the sine and cosine calculation unit 201, the multiplier unit 202, and the adder unit 203, and the resource scheduling mechanism adopted includes:

[0059] The angle and the number of lines are input to the multiplier unit 202 for multiplication, and the corresponding initial relative offset angle is output;

[0060] The initial relative offset angle is input to the adder unit 203 for addition calculation with the relative offset angle of phase A, the relative offset angle of phase B and the relative offset angle of phase C, and the corresponding phase A angle, phase B angle and phase C angle are output in sequence;

[0061] The output corresponding A phase angle, B phase angle and C phase angle are sequentially input into the sine calculation unit 201 for sine and cosine calculation, and the A phase sine and cosine calculation results, the B phase sine and cosine calculation results and the C phase sine and cosine calculation results are obtained respectively;

[0062] The D-axis control component and the Q-axis control component are respectively inputted into the multiplier unit 202 with the A-phase sine-cosine calculation result, the B-phase sine-cosine calculation result and the C-phase sine-cosine calculation result for calculation, and the A-phase sine-cosine multiplication calculation result, the B-phase sine-cosine multiplication calculation result and the C-phase sine-cosine multiplication calculation result are obtained in sequence;

[0063] The A-phase sine-cosine multiplication calculation result, the B-phase sine-cosine multiplication calculation result and the C-phase sine-cosine multiplication calculation result are sequentially input to the adder 203 for addition calculation to obtain the A-phase voltage vector value, the B-phase voltage vector value and the C-phase voltage vector value;

[0064] The A-phase voltage vector value, the B-phase voltage vector value, the C-phase voltage vector value and the effective signal are output.

[0065] In a specific embodiment, the resource scheduling mechanism specifically includes:

[0066] The angle and the number of lines are input to the multiplier unit 202 for multiplication calculation based on the multiplication calculation rules, and the corresponding initial relative offset angle is output; specifically, when the input cal_valid is valid, the input of the multiplier unit 202 is angle[n:0] and resolution[k:0], the multiplication calculation and implementation method of the multiplier unit are determined by the relationship between n and k, and the output latches the initial relative offset angle angle_pre_shif, and the number of bits of the initial relative offset angle is determined according to the specific calculation results.

[0067] The initial relative offset angle and the relative offset angle of phase A are input into the unsigned adder for addition calculation, and the corresponding phase A angle is output; specifically, the unsigned adder of the adder unit 203 is enabled, and the inputs of the unsigned adder are angle_pre_shift[n:0] and angle_shift_a[n:0], respectively, and the phase A angle is output, which is recorded as angle_a[n:0].

[0068] The initial relative offset angle and the B-phase relative offset angle are input into the unsigned adder for addition calculation and output of the corresponding B-phase angle, and the A-phase angle is simultaneously input into the sine calculation unit for sine calculation and output of the signed A-phase sine value and A-phase cosine value; specifically, the unsigned adder of the adder unit 203 and the sine-cosine calculation unit 201 are simultaneously enabled, and at this time, the inputs of the unsigned adder are angle_pre_shift[n:0] and angle_shift_b[n:0], respectively, and the B-phase angle is output, recorded as angle_b[n:0]; at the same time, the input angle of the sine-cosine calculation unit 201 is angle_a[n:0], and the A-phase sine value and A-phase cosine value are output, recorded as sin angle_a [n:0] and cos angle_a [n:0].

[0069] The initial relative offset angle and the C-phase relative offset angle are input into the unsigned adder for addition calculation to output the corresponding C-phase angle, and the B-phase angle is input into the sine calculation unit 201 for sine calculation to output the signed B-phase sine value and B-phase cosine value, and the A-phase cosine value and the D-axis control component are input into the multiplier unit 202 for multiplication calculation to obtain the A-phase cosine multiplication calculation result; specifically, the unsigned adder of the adder unit 203, the sine-cosine calculation unit 201 and the multiplier unit 202 are enabled at the same time, at this time, the input of the unsigned adder is angle_pre_shift[n:0] and angle_shift_c[n:0], and the C-phase angle is output, recorded as angle_c[n:0]; the input of the sine-cosine calculation unit 201 is angle_b[n:0], and the B-phase sine value and B-phase cosine value are output, recorded as sin angle_b [n:0] and cos angle_b [n:0]. The input of the multiplier unit 202 is cos angle_a [n:0] and vd[n:0], output the A phase cosine multiplication calculation result, which is vd*cos angle_a [n:0], latch the value and record it as vdxcos_a[n:0].

[0070] The C phase angle is input to the sine calculation unit 201 for sine calculation to output the signed C phase sine value and C phase cosine value, and at the same time, the A phase sine value and the Q axis control component are input to the multiplier unit 202 for multiplication calculation to obtain the A phase sine multiplication calculation result; specifically, the sine-cosine calculation unit 201 and the multiplier unit 202 are enabled, at this time, the input of the sine-cosine calculation unit 201 is angle_c[n:0], and the C phase sine value and C phase cosine value are output, which are recorded as sin angle_c [n:0] and cos angle_c[n:0]; the input of the multiplier unit 202 is sin angle_a [n:0] and vq[n:0], output the A phase sine multiplication calculation result, which is vq*sin angle_a [n:0], latch the value and record it as vqxsin_a[n:0].

[0071] The A-phase cosine multiplication result and the A-phase sine multiplication result are input to the signed adder for subtraction to obtain the A-phase voltage vector value, and the B-phase cosine value and the D-axis control component are simultaneously input to the multiplier unit 202 for multiplication to obtain the B-phase cosine multiplication result; specifically, the signed adder and multiplier unit of the adder unit are enabled; specifically, the signed adder and multiplier unit 202 of the adder unit 203 are enabled, and at this time, the input of the signed adder is vdxcos_a[n:0] and vqxsin_a[n:0], and the output is vdxcos_a[n:0]-vqxsin_a[n:0], and the value is latched as the A-phase voltage vector value, recorded as vdxcos_b[n:0]. The input of the multiplier unit 202 is vd[n:0] and cos angle_b [n:0], output the B-phase cosine multiplication calculation result, which is vd*cos angle_b [n:0], latch the value and record it as vdxcos_b[n:0].

[0072] The B-phase sine value and the Q-axis control component are input to the multiplier unit 202 for multiplication to obtain the B-phase sine multiplication result; specifically, the multiplier unit 202 is enabled, and the input of the multiplier unit 202 is vq[n:0] and sin angle_b [n:0], output B phase sine multiplication calculation result, which is vq*sin angle_b [n:0], latch the value and record it as vqxsin_b[n:0].

[0073] The B-phase cosine multiplication result and the B-phase sine multiplication result are input into the signed adder for subtraction to obtain the B-phase voltage vector value, and the C-phase cosine value and the D-axis control component are simultaneously input into the multiplier unit 202 for multiplication to obtain the C-phase cosine multiplication result; specifically, the signed adder and multiplier unit 202 of the adder unit 203 are enabled, and at this time, the inputs of the adder unit 203 are vdxcos_b[n:0] and vqxsin_b[n:0], respectively, and the output is vdxcos_b[n:0]-vqxsin_b[n:0], and the value is latched as the B-phase voltage vector value, recorded as vb[n:0]; the inputs of the multiplier unit 202 are vd[n:0] and cosangle_c[n:0], and the output is the C-phase cosine multiplication result, which is vd*cos angle_c[n:0], and latch the value and record it as vdxcos_c[n:0].

[0074] The C-phase sine value and the Q-axis control component are input to the multiplier unit 202 for multiplication to obtain the C-phase sine multiplication result; specifically, the multiplier unit 202 is enabled, and the input is sin angle_c [n:0] and vq[n:0], output C phase sine multiplication calculation result, vq*sin angle_c [n:0], latch the value and record it as vqxsin_c[n:0].

[0075] The C-phase cosine multiplication calculation result and the C-phase sine multiplication calculation result are input into the signed adder for subtraction calculation to obtain the C-phase voltage vector value; specifically, the signed adder of the adder unit 203 is enabled, the input of the adder unit 203 is vdxcos_c[n:0] and vqxsin_c[n:0], and the output is vdxcos_c[n:0]-vqxsin_c[n:0], and the latched value is the C-phase voltage vector value, recorded as vc[n:0].

[0076] Output the A-phase voltage vector value, the B-phase voltage vector value, and the C-phase voltage vector value to obtain the encoding of the three-phase control circuit. Specifically, output va[n:0], vb[n:0], and vc[n:0]. In a preferred embodiment, after the A-phase voltage vector value, the B-phase voltage vector value, and the C-phase voltage vector value are generated, a valid signal is generated and output simultaneously with the A-phase voltage vector value, the B-phase voltage vector value, and the C-phase voltage vector value, indicating that the va[n:0] / vb[n:0] / vc[n:0] at this time can be sampled later, and the subsequent calculation is completed, and updated to A / B / C output for subsequent generation of PWM (pulse width modulation) signals to drive the motor.

[0077] Similar to the principle of the above embodiment, the present invention provides a motor vector control encoding system.

[0078] The following provides specific embodiments in conjunction with the accompanying drawings:

[0079] like Figure 3 A schematic structural diagram of a motor vector control encoding system in an embodiment of the present invention is shown.

[0080] The system comprises:

[0081] Input module 1, used for inputting relevant configuration parameters; wherein the relevant configuration parameters include: angle, angle input valid indication signal, line number, input angle filter threshold, A phase relative offset angle, B phase relative offset angle and C phase relative offset angle, D axis control component, Q axis control component and control component sampling indication signal; and the input angle, input angle filter threshold, A phase relative offset angle, B phase relative offset angle and C phase relative offset angle, D axis control component and Q axis control component all use the same number of bits;

[0082] The three-phase encoding calculation module 2 is connected to the input module 1 and is used to generate the encoding of the three-phase control circuit based on the input related configuration parameters for controlling the PWM drive motor.

[0083] It should be understood that Figure 3 The division of each module in the system embodiment is only a division of logical functions. In actual implementation, they can be fully or partially integrated into one physical entity, or physically separated. And these units can all be implemented in the form of software calling through processing elements; they can also be all implemented in the form of hardware; some units can also be implemented in the form of processing elements calling software, and some units can be implemented in the form of hardware.

[0084] Since the implementation principle of the motor vector control encoding system has been described in the above-mentioned embodiment, it will not be repeated here.

[0085] In one embodiment, based on the relevant configuration parameters of the input, generating the code of the three-phase control circuit includes: filtering the input angle based on the input angle filtering threshold, and making the three-phase code calculation trigger signal a valid level under the filtering; when the received three-phase code calculation trigger signal is a valid level, using the three-phase code calculation module to perform sine and cosine calculations, multiplication calculations and addition calculations based on the relevant configuration parameters of the input to generate the code of the three-phase control circuit.

[0086] In one embodiment, the three-phase encoding calculation module includes: a sine-cosine calculation unit 201, which is used to perform sine-cosine calculation on the input angle and output a signed sine-cosine calculation result; a multiplier unit 202, which is used to perform multiplication calculation on two input signed or unsigned multipliers based on the multiplication calculation rule, and output the corresponding multiplication calculation result; an adder unit 203, which is used to perform addition or subtraction calculation on two input signed or unsigned addends, and output the corresponding addition calculation result; a computing resource scheduling controller 204, which is connected to the sine-cosine calculation unit 201, the multiplier unit 202, and the adder unit 203, and is used to control the sine calculation unit 201, the multiplier unit 202, and the adder unit 203 based on the resource scheduling mechanism to perform sine calculation, multiplication calculation and addition calculation according to the input related configuration parameters to obtain the encoding of the three-phase control circuit.

[0087] In one embodiment, the multiplication calculation rule includes: if the highest digit k of the input first multiplier is less than the highest digit n of the second multiplier, a padding operation is first performed on the high digit of the first multiplier, and then the first multiplier and the second multiplier after the padding are input into a multiplier for multiplication calculation to obtain a 2n+1-bit multiplier calculation result, and when the first multiplier and / or the second multiplier are signed, the 2nth to nth digits of the multiplier calculation result are output as the multiplication calculation result, and when both the first multiplier and the second multiplier are unsigned, the nth to 0th digits of the multiplier calculation result are output as the multiplication calculation result; if the highest digit k of the input first multiplier is greater than or equal to the highest digit n of the second multiplier, and less than 1.5 times the highest digit n of the second multiplier, a padding operation is first performed on the high digit of the first multiplier, and then the first multiplier and the second multiplier after the padding are input into a multiplier for multiplication calculation to obtain a k+n+2-bit multiplication calculation result. , and when the first multiplier and / or the second multiplier are signed, the 2nth to nth bits of the multiplier calculation result are output as the multiplication calculation result, and when both the first multiplier and the second multiplier are unsigned, the nth to 0th bits of the multiplier calculation result are output as the multiplication calculation result; if the highest bit k of the input first multiplier is greater than 1.5 times the highest bit n of the second multiplier, for the case where the first multiplier and the second multiplier are unsigned, the first multiplier and the second multiplier are input to the unsigned multiplier for multiplication calculation to obtain a k+n+2-bit unsigned multiplier calculation result, and the nth to 0th bits of the unsigned multiplier result are output as the multiplication calculation result; for the case where the first multiplier and / or the second multiplier are signed, the first multiplier and the second multiplier are input to the signed multiplier for multiplication calculation to obtain a 2n+1-bit signed multiplication calculation result, and the 2nth to nth bits of the signed multiplication result are output as the multiplication calculation result.

[0088] In one embodiment, the adder unit 203 includes: a signed adder and an unsigned adder; wherein the signed adder is used to perform a subtraction calculation on two n+1-bit signed numbers to obtain an n+1-bit signed adder calculation result; if the adder calculation result exceeds a set range, the adder calculation result is output according to saturation truncation; if the adder calculation result does not exceed the set range, the adder calculation result is output; wherein, if the adder calculation result is less than -2 n , then -2 n As the addition result output, if the adder calculation result is greater than 2 n -1, then 2 n -1 is output as the addition result; the unsigned adder is used to perform addition calculation on two unsigned addends with an effective number of n+1 to obtain an n+1-bit signed adder calculation result; if the adder calculation result is greater than 2 n+1 -1, then the adder calculation result is subtracted by 2 n+1 -1 The calculation result obtained is output as the addition result; if the adder calculation result is not greater than 2 n+1 -1, the adder calculation result is output.

[0089] In one embodiment, the resource scheduling mechanism includes: inputting the angle and the number of lines into the multiplier unit for multiplication calculation, and outputting the corresponding initial relative offset angle; inputting the initial relative offset angle and the A-phase relative offset angle, the B-phase relative offset angle, and the C-phase relative offset angle into the adder unit 203 for addition calculation, and outputting the corresponding A-phase angle, B-phase angle, and C-phase angle in sequence; inputting the output corresponding A-phase angle, B-phase angle, and C-phase angle into the sine calculation unit in sequence for sine and cosine calculation, and obtaining the A-phase sine and cosine calculation results, the B-phase sine and cosine calculation results, and the C-phase sine and cosine calculation results respectively; The A-axis control component and the Q-axis control component are respectively input into the multiplier unit 202 with the A-phase sine-cosine calculation result, the B-phase sine-cosine calculation result and the C-phase sine-cosine calculation result for calculation, and the A-phase sine-cosine multiplication calculation result, the B-phase sine-cosine multiplication calculation result and the C-phase sine-cosine multiplication calculation result are obtained in sequence; the A-phase sine-cosine multiplication calculation result, the B-phase sine-cosine multiplication calculation result and the C-phase sine-cosine multiplication calculation result are input into the adder 203 in sequence for addition calculation, and the A-phase voltage vector value, the B-phase voltage vector value and the C-phase voltage vector value are obtained; the A-phase voltage vector value, the B-phase voltage vector value and the C-phase voltage vector value are output.

[0090] In one embodiment, the resource scheduling mechanism includes: inputting the angle and the number of lines into the multiplier unit 202 to perform multiplication calculation based on the multiplication calculation rule, and outputting the corresponding initial relative offset angle; inputting the initial relative offset angle and the relative offset angle of the A phase into the unsigned adder for subtraction calculation, and outputting the corresponding A phase angle; inputting the initial relative offset angle and the relative offset angle of the B phase into the unsigned adder for addition calculation to output the corresponding B phase angle, and at the same time inputting the A phase angle into the sine calculation unit 201 for sine calculation to output the signed A phase sine value and the A phase The initial relative offset angle and the C-phase relative offset angle are input into the unsigned adder for addition calculation to output the corresponding C-phase angle, and the B-phase angle is input into the sine calculation unit for sine calculation to output the signed B-phase sine value and the B-phase cosine value, and the A-phase cosine value and the D-axis control component are input into the multiplier unit 202 for multiplication calculation to obtain the A-phase cosine multiplication result; the C-phase angle is input into the sine calculation unit 201 for sine calculation to output the signed C-phase sine value and the C-phase cosine value, and the A-phase sine value and the Q-axis control component are input into the multiplier unit 202 for multiplication calculation to obtain the A-phase cosine multiplication result. The multiplier unit 202 performs multiplication calculation to obtain the A-phase sine multiplication calculation result; the A-phase cosine multiplication calculation result and the A-phase sine multiplication calculation result are input into the signed adder for addition calculation to obtain the A-phase voltage vector value, and at the same time, the B-phase cosine value and the D-axis control component are input into the multiplier unit 202 for multiplication calculation to obtain the B-phase cosine multiplication calculation result; the B-phase sine value and the Q-axis control component are input into the multiplier unit 202 for multiplication calculation to obtain the B-phase sine multiplication calculation result; the B-phase cosine multiplication calculation result and the B-phase sine multiplication calculation result are input into the signed adder. The multiplier performs subtraction calculation to obtain the B-phase voltage vector value, and simultaneously inputs the C-phase cosine value and the D-axis control component into the multiplier unit 202 for multiplication calculation to obtain the C-phase cosine multiplication result; inputs the C-phase sine value and the Q-axis control component into the multiplier unit 202 for multiplication calculation to obtain the C-phase sine multiplication result; inputs the C-phase cosine multiplication result and the C-phase sine multiplication result into the signed adder for subtraction calculation to obtain the C-phase voltage vector value; outputs the A-phase voltage vector value, the B-phase voltage vector value and the C-phase voltage vector value to obtain the encoding of the three-phase control circuit.

[0091] In one embodiment, the input angle is filtered based on the input angle filtering threshold, and a three-phase coding calculation trigger signal is generated when the angle passes the filtering, including: determining whether the angle difference between the input angle and the angle that passed the filtering last time exceeds the angle filtering threshold, and when it does not exceed the angle filtering threshold, using the angle as the angle that passes the filtering, and generating a three-phase coding calculation trigger signal.

[0092] The motor vector control method provided in the embodiment of the present invention can be implemented on the terminal side or the server side. As for the hardware structure of the motor vector control terminal, please refer to Figure 4 , is an optional hardware structure diagram of the motor vector control terminal 1000 provided in an embodiment of the present invention. The terminal 1000 can be a mobile phone, a computer device, a tablet device, a personal digital processing device, a factory background processing device, etc. The terminal 1000 includes: at least one processor 1001, a memory 1002, at least one network interface 1009 and a user interface 10010. The various components in the device are coupled together through a bus system 1005. It can be understood that the bus system 1005 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 1005 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, in Figure 4 In the specification, various buses are labeled as bus systems.

[0093] The user interface 1009 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

[0094] It is understood that the memory 1002 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), which is used as an external cache. By way of exemplary but not limiting explanation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM). The memory described in the embodiments of the present invention is intended to include but is not limited to these and any other suitable categories of memory.

[0095] The memory 1002 in the embodiment of the present invention is used to store various categories of data to support the operation of the terminal 1000. Examples of these data include: any executable program for operating on the terminal 1000, such as an operating system 10021 and an application 10022; the operating system 10021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 10022 may include various applications, such as a media player (MediaPlayer), a browser (Browser), etc., for implementing various application services. The motor vector control method provided in the embodiment of the present invention may be included in the application 10022.

[0096] The method disclosed in the above embodiment of the present invention can be applied to the processor 1001, or implemented by the processor 1001. The processor 1001 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 1001 or the instruction in the form of software. The above processor 1001 may be a general processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 1001 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiment of the present invention. The general processor 1001 can be a microprocessor or any conventional processor, etc. In combination with the steps of the accessory optimization method provided in the embodiment of the present invention, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0097] In an exemplary embodiment, the terminal 1000 may be implemented by one or more application specific integrated circuits (ASIC), DSP, programmable logic device (PLD), complex programmable logic device (CPLD) to execute the aforementioned method.

[0098] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to the computer program. The aforementioned computer program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other media that can store program codes.

[0099] In the embodiments provided in the present application, the computer readable and writable storage medium may include a read-only memory, a random access memory, an EEPROM, a CD-ROM or other optical disk storage device, a disk storage device or other magnetic storage device, a flash memory, a USB flash drive, a mobile hard disk, or any other medium that can be used to store a desired program code in the form of an instruction or data structure and can be accessed by a computer. In addition, any connection can be appropriately referred to as a computer-readable medium. For example, if the instruction is sent from a website, a server or other remote source using a coaxial cable, an optical fiber cable, a twisted pair, a digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves, the coaxial cable, optical fiber cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of the medium. However, it should be understood that computer readable and writable storage media and data storage media do not include connections, carriers, signals, or other temporary media, but are intended to be non-temporary, tangible storage media. Disk and disc, as used in this application, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.

[0100] In summary, the motor vector control encoding method, system and terminal of the present invention generate the encoding of the three-phase control circuit by inputting relevant configuration parameters such as angle, number of lines and D / Q axis control variables, and performing sine and cosine calculations, multiplication calculations and addition calculations to control the PWM drive motor. The present invention completes the encoding output of the three-phase motor control in the motor vector control, which can effectively save hardware resource overhead, reduce chip area and reduce costs. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0101] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A motor vector control encoding method, characterized in that: The method comprises: Input related configuration parameters; wherein the related configuration parameters include: angle, angle input valid indication signal, line number, input angle filter threshold, A phase relative offset angle, B phase relative offset angle, C phase relative offset angle, D axis control component, Q axis control component and control component sampling indication signal; and the input angle, input angle filter threshold, A phase relative offset angle, B phase relative offset angle and C phase relative offset angle, D axis control component and Q axis control component all use the same number of bits; Based on the input related configuration parameters, the code of the three-phase control circuit is generated for controlling the PWM drive motor; the code of the three-phase control circuit is generated based on the input related configuration parameters, including: Based on the input angle filter threshold, the input angle is filtered, and the three-phase encoding calculation trigger signal is made to be a valid level after filtering; When the received three-phase coding calculation trigger signal is at a valid level, the three-phase coding calculation module is used to perform sine and cosine calculations, multiplication calculations, and addition calculations based on the input related configuration parameters to generate the coding of the three-phase control circuit; the three-phase coding calculation module includes: A sine and cosine calculation unit, used to perform sine and cosine calculations on the input angle and output signed sine and cosine calculation results; A multiplier unit, used for performing multiplication calculation on two input signed or unsigned multipliers based on a multiplication calculation rule, and outputting a corresponding multiplication calculation result; An adder unit, used for performing addition or subtraction calculation on two signed or unsigned addends inputted, and outputting corresponding addition calculation results; A computing resource scheduling controller is connected to the sine-cosine calculation unit, the multiplier unit, and the adder unit, and is used to control the sine-cosine calculation unit, the multiplier unit, and the adder unit to perform sine calculation, multiplication calculation, and addition calculation according to the input related configuration parameters based on the resource scheduling mechanism to obtain the code of the three-phase control circuit; the resource scheduling mechanism includes: The angle and the number of lines are input into the multiplier unit for multiplication calculation, and the corresponding initial relative offset angle is output; The initial relative offset angle is input into the adder unit for addition calculation with the relative offset angle of phase A, the relative offset angle of phase B and the relative offset angle of phase C respectively, and the corresponding phase A angle, phase B angle and phase C angle are output in sequence; The A-phase angle, B-phase angle and C-phase angle corresponding to the output are sequentially input into the sine-cosine calculation unit for sine-cosine calculation, and the A-phase sine-cosine calculation result, the B-phase sine-cosine calculation result and the C-phase sine-cosine calculation result are obtained respectively; Input the D-axis control component and the Q-axis control component and the A-phase sine-cosine calculation result, the B-phase sine-cosine calculation result, and the C-phase sine-cosine calculation result into the multiplier unit for calculation, and obtain the A-phase sine-cosine multiplication calculation result, the B-phase sine-cosine multiplication calculation result, and the C-phase sine-cosine multiplication calculation result in sequence; The A-phase sine-cosine multiplication calculation result, the B-phase sine-cosine multiplication calculation result and the C-phase sine-cosine multiplication calculation result are sequentially input into the adder for addition calculation to obtain the A-phase voltage vector value, the B-phase voltage vector value and the C-phase voltage vector value; Output the A-phase voltage vector value, the B-phase voltage vector value, and the C-phase voltage vector value.

2. The motor vector control encoding method according to claim 1, characterized in that: The multiplication calculation rules include: If the highest digit k of the input first multiplier is less than the highest digit n of the second multiplier, a padding operation is first performed on the high digit of the first multiplier, and then the first multiplier and the second multiplier after the padding are input into a multiplier for multiplication calculation to obtain a 2n+1-bit multiplier calculation result, and when the first multiplier and / or the second multiplier are signed, the 2nth to nth digits of the multiplier calculation result are output as the multiplication calculation result, and when both the first multiplier and the second multiplier are unsigned, the nth to 0th digits of the multiplier calculation result are output as the multiplication calculation result; If the highest digit k of the input first multiplier is greater than or equal to the highest digit n of the second multiplier, and is less than 1.5 times the highest digit n of the second multiplier, firstly perform a padding operation on the high digit of the first multiplier, then input the padded first multiplier and the second multiplier into a multiplier for multiplication to obtain a k+n+2-digit multiplication result, and output the 2nth to nth digits of the multiplier calculation result as the multiplication calculation result when the first multiplier and / or the second multiplier are signed, and output the nth to 0th digits of the multiplier calculation result as the multiplication calculation result when both the first multiplier and the second multiplier are unsigned; If the highest number of digits k of the input first multiplier is greater than 1.5 times the highest number of digits n of the second multiplier, in the case that the first multiplier and the second multiplier are unsigned, the first multiplier and the second multiplier are input into an unsigned multiplier for multiplication calculation to obtain a k+n+2-bit unsigned multiplier calculation result, and the nth to 0th bits of the unsigned multiplier result are output as the multiplication calculation result; in the case that the first multiplier and / or the second multiplier are signed, the first multiplier and the second multiplier are input into a signed multiplier for multiplication calculation to obtain a 2n+1-bit signed multiplication calculation result, and the 2nth to nth bits of the signed multiplication result are output as the multiplication calculation result.

3. The motor vector control encoding method according to claim 2, characterized in that: The adder unit comprises: Signed adder and unsigned adder; The signed adder is used to perform subtraction calculation on two n+1-bit signed numbers to obtain an n+1-bit signed adder calculation result; if the adder calculation result exceeds the set range, the adder calculation result is output according to saturation truncation; if the adder calculation result does not exceed the set range, the adder calculation result is output; if the adder calculation result is less than -2 n , then -2 n As the addition result output, if the adder calculation result is greater than 2 n -1, then 2 n -1 is output as the addition result; The unsigned adder is used to perform addition calculation on two unsigned addends with an effective number of n+1 to obtain an n+1-bit signed adder calculation result; if the adder calculation result is greater than 2 n+1 -1, then the adder calculation result is subtracted by 2 n +1 -1 The calculation result obtained is output as the addition result; if the adder calculation result is not greater than 2 n+1 -1, the adder calculation result is output.

4. The motor vector control encoding method according to claim 3, characterized in that: The resource scheduling mechanism includes: The angle and the number of lines are input into the multiplier unit for multiplication calculation based on the multiplication calculation rule, and the corresponding initial relative offset angle is output; Inputting the initial relative offset angle and the A-phase relative offset angle into the unsigned adder for addition calculation, and outputting the corresponding A-phase angle; The initial relative offset angle and the B-phase relative offset angle are input into the unsigned adder for addition calculation and output of the corresponding B-phase angle, and the A-phase angle is simultaneously input into the sine-cosine calculation unit for sine-cosine calculation and output of the signed A-phase sine value and A-phase cosine value; The initial relative offset angle and the C-phase relative offset angle are input into the unsigned adder for addition calculation to output the corresponding C-phase angle, and the B-phase angle is input into the sine-cosine calculation unit for sine-cosine calculation to output the signed B-phase sine value and B-phase cosine value, and the A-phase cosine value and the D-axis control component are input into the multiplier unit for multiplication calculation to obtain the A-phase cosine multiplication calculation result; The C phase angle is input to the sine-cosine calculation unit for sine-cosine calculation to output the signed C phase sine value and C phase cosine value, and at the same time, the A phase sine value and the Q axis control component are input to the multiplier unit for multiplication calculation to obtain the A phase sine multiplication calculation result; Inputting the A-phase cosine multiplication calculation result and the A-phase sine multiplication calculation result into the signed adder for subtraction calculation to obtain the A-phase voltage vector value, and simultaneously inputting the B-phase cosine value and the D-axis control component into the multiplier unit for multiplication calculation to obtain the B-phase cosine multiplication calculation result; Inputting the B-phase sine value and the Q-axis control component into the multiplier unit for multiplication calculation to obtain the B-phase sine multiplication calculation result; Inputting the B-phase cosine multiplication calculation result and the B-phase sine multiplication calculation result into the signed adder for subtraction calculation to obtain the B-phase voltage vector value, and simultaneously inputting the C-phase cosine value and the D-axis control component into the multiplier unit for multiplication calculation to obtain the C-phase cosine multiplication calculation result; Inputting the C-phase sine value and the Q-axis control component into the multiplier unit for multiplication calculation to obtain the C-phase sine multiplication calculation result; Inputting the C-phase cosine multiplication calculation result and the C-phase sine multiplication calculation result into the signed adder for subtraction calculation to obtain the C-phase voltage vector value; The A-phase voltage vector value, the B-phase voltage vector value, and the C-phase voltage vector value are output to obtain the encoding of the three-phase control circuit.

5. The motor vector control encoding method according to claim 1, characterized in that: The filtering of the input angle based on the input angle filtering threshold and generating a three-phase encoding calculation trigger signal when the angle passes the filtering comprises: It is determined whether the angle difference between the input angle and the angle that passed the filtering last time exceeds the angle filtering threshold, and when it does not exceed the angle filtering threshold, the angle is used as the angle that passed the filtering, and a three-phase encoding calculation trigger signal is generated.

6. A motor vector control encoding system, characterized in that: The system comprises: An input module is used to input relevant configuration parameters; wherein the relevant configuration parameters include: angle, angle input valid indication signal, line number, input angle filter threshold, A phase relative offset angle, B phase relative offset angle and C phase relative offset angle, D axis control component, Q axis control component and control component sampling indication signal; and the input angle, input angle filter threshold, A phase relative offset angle, B phase relative offset angle and C phase relative offset angle, D axis control component and Q axis control component all use the same number of bits; The three-phase encoding calculation module is connected to the input module and is used to generate the encoding of the three-phase control circuit based on the input related configuration parameters for controlling the PWM drive motor; the encoding of the three-phase control circuit based on the input related configuration parameters includes: Based on the input angle filter threshold, the input angle is filtered, and the three-phase encoding calculation trigger signal is made to be a valid level after filtering; When the received three-phase coding calculation trigger signal is at a valid level, the three-phase coding calculation module is used to perform sine and cosine calculations, multiplication calculations, and addition calculations based on the input related configuration parameters to generate the coding of the three-phase control circuit; the three-phase coding calculation module includes: A sine and cosine calculation unit, used to perform sine and cosine calculations on the input angle and output signed sine and cosine calculation results; A multiplier unit, used for performing multiplication calculation on two input signed or unsigned multipliers based on a multiplication calculation rule, and outputting a corresponding multiplication calculation result; An adder unit, used for performing addition or subtraction calculation on two signed or unsigned addends inputted, and outputting corresponding addition calculation results; A computing resource scheduling controller is connected to the sine-cosine calculation unit, the multiplier unit, and the adder unit, and is used to control the sine-cosine calculation unit, the multiplier unit, and the adder unit to perform sine calculation, multiplication calculation, and addition calculation according to the input related configuration parameters based on the resource scheduling mechanism to obtain the code of the three-phase control circuit; the resource scheduling mechanism includes: The angle and the number of lines are input into the multiplier unit for multiplication calculation, and the corresponding initial relative offset angle is output; The initial relative offset angle is input into the adder unit for addition calculation with the relative offset angle of phase A, the relative offset angle of phase B and the relative offset angle of phase C respectively, and the corresponding phase A angle, phase B angle and phase C angle are output in sequence; The A-phase angle, B-phase angle and C-phase angle corresponding to the output are sequentially input into the sine-cosine calculation unit for sine-cosine calculation, and the A-phase sine-cosine calculation result, the B-phase sine-cosine calculation result and the C-phase sine-cosine calculation result are obtained respectively; Input the D-axis control component and the Q-axis control component and the A-phase sine-cosine calculation result, the B-phase sine-cosine calculation result, and the C-phase sine-cosine calculation result into the multiplier unit for calculation, and obtain the A-phase sine-cosine multiplication calculation result, the B-phase sine-cosine multiplication calculation result, and the C-phase sine-cosine multiplication calculation result in sequence; The A-phase sine-cosine multiplication calculation result, the B-phase sine-cosine multiplication calculation result and the C-phase sine-cosine multiplication calculation result are sequentially input into the adder for addition calculation to obtain the A-phase voltage vector value, the B-phase voltage vector value and the C-phase voltage vector value; Output the A-phase voltage vector value, the B-phase voltage vector value, and the C-phase voltage vector value.

7. A motor vector control encoding terminal, characterized in that: include: one or more memories and one or more processors; The one or more memories are used to store computer programs; The one or more processors, connected to the memory, are configured to run the computer program to perform the method according to any one of claims 1 to 5.

Images