Delay-locked loop circuits, chips and electronic devices

Abstract

The present disclosure relates to a delay phase-locked loop circuit, a chip and an electronic device, wherein the delay phase-locked loop circuit comprises: a delay circuit unit, which is used to receive a system clock signal under a phase-locked regulation voltage and delay the system clock signal to generate a first phase clock signal and a second phase clock signal; a voltage digital control unit, which is used to receive the first phase clock signal and the second phase clock signal, and generate a voltage digital control signal according to the first phase clock signal and the second phase clock signal; and a voltage source unit, which is used to receive the voltage digital control signal and generate a phase-locked regulation voltage according to the voltage digital control signal. The present disclosure uses the voltage digital control unit to realize digital control of the phase-locked regulation voltage. Since the digital loop design is adopted in the voltage control loop, the present disclosure helps to improve the stability, reusability, monitorability and configurability of the voltage control.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to a delay phase-locked loop circuit, a chip and an electronic device. Background Art

[0002] Delay Locked Loop (DLL) is a synchronization circuit widely used in integrated circuits, mainly used to synchronize clock signals to ensure the accuracy and stability of data transmission.

[0003] With the continuous development of VLSI technology and the continuous increase of clock frequency, the synchronization of clock signals has become more sensitive to data transmission. At the same time, the clock frequency requirements of various parts of the system also have different requirements. Therefore, the requirements for the stability, accuracy, multiplexing, and applicability of the wide frequency range of the delay-locked loop are also constantly increasing. Summary of the invention

[0004] In view of this, the present disclosure provides a delay locked loop circuit, chip and electronic device to help improve their reusability, monitorability and configurability, and meet the applicability requirements of different clock frequency ranges.

[0005] The technical solution of the present disclosure is achieved as follows:

[0006] According to one aspect of an embodiment of the present disclosure, a delay locked loop circuit is provided, comprising:

[0007] A delay circuit unit, used for receiving a system clock signal under a phase-locked regulation voltage and delaying the system clock signal to generate a first phase clock signal and a second phase clock signal;

[0008] a voltage digital control unit, configured to receive the first phase clock signal and the second phase clock signal, and generate a voltage digital control signal according to the first phase clock signal and the second phase clock signal; and

[0009] The voltage source unit is used to receive the voltage digital control signal and generate the phase-locked regulation voltage according to the voltage digital control signal.

[0010] In a possible implementation manner, the delay circuit unit includes:

[0011] A first voltage domain adjustment unit, configured to receive the system clock signal under the phase-locked adjustment voltage, and adjust the voltage domain of the system clock signal to the voltage domain of the phase-locked adjustment voltage to obtain a phase-locked adjustment voltage domain clock signal;

[0012] A voltage-controlled delay line unit, configured to receive the phase-locked regulated voltage domain clock signal under the phase-locked regulated voltage, and obtain a first phase-locked regulated voltage domain phase clock signal and a second phase-locked regulated voltage domain phase clock signal by delaying the phase-locked regulated voltage domain clock signal;

[0013] The second voltage domain adjustment unit is used to receive the first phase-locked adjustment voltage domain phase clock signal and the second phase-locked adjustment voltage domain phase clock signal, adjust the voltage domain of the first phase-locked adjustment voltage domain phase clock signal and the second phase-locked adjustment voltage domain phase clock signal to the voltage domain of the voltage digital control unit, and obtain the first phase clock signal and the second phase clock signal.

[0014] In a possible implementation manner, the voltage-controlled delay line unit includes:

[0015] There are N levels of delay units, the power supply end of each level of the delay units is coupled to the voltage source unit, the input end of the subsequent delay unit in two adjacent levels of the delay units is coupled to the output end of the previous delay unit, and the input end of the first level of the delay unit in the N levels of the delay units is coupled to the first voltage domain adjustment unit to receive the phase-locked adjustment voltage domain clock signal, wherein N≥2.

[0016] In a possible implementation manner, the delay unit includes:

[0017] A first regulating unit, comprising a plurality of buffers powered by the phase-locked regulating voltage and connected in parallel between an input end and an output end of the delay unit, wherein the number of the buffers is set according to a preset first regulating parameter;

[0018] The second adjustment unit includes a plurality of capacitors connected in parallel between the output terminal of the delay unit and the ground terminal, and the number of the capacitors is set according to a preset second adjustment parameter.

[0019] In a possible implementation manner, the first adjustment parameter and the second adjustment parameter are associated with a frequency range of the system clock signal.

[0020] In one possible implementation, the phase of the first phase clock signal is the same as the phase of the system clock signal, and the phase of the second phase clock signal is the phase of the system clock signal after N stages of delay, where N≥2.

[0021] In one possible implementation, the voltage digital control unit includes:

[0022] a phase detection and comparison unit, configured to receive the first phase clock signal and the second phase clock signal, and generate a phase difference comparison signal according to the first phase clock signal and the second phase clock signal;

[0023] The digital control logic unit is used to generate the voltage digital control signal, receive the phase difference comparison signal, and adjust the signal value of the voltage digital control signal according to the phase difference comparison signal.

[0024] In a possible implementation manner, the phase comparison unit includes:

[0025] a phase difference detection unit, configured to receive the first phase clock signal and the second phase clock signal, and obtain a phase difference signal between the first phase clock signal and the second phase clock signal;

[0026] The comparator is used to receive the phase difference signal and generate the phase difference comparison signal by comparing the phase difference signal.

[0027] In a possible implementation manner, the phase difference detection unit includes:

[0028] a phase detector, configured to receive the first phase clock signal and the second phase clock signal, and perform phase detection on the first phase clock signal and the second phase clock signal to obtain a phase difference piecewise linear signal;

[0029] A filter is used to filter the phase difference piecewise linear signal to obtain the phase difference signal.

[0030] In one possible implementation, the voltage source unit includes:

[0031] A digital-to-analog conversion unit, configured to receive the voltage digital control signal and convert the voltage digital control signal into an analog voltage signal;

[0032] The linear regulator is used to receive the analog voltage signal and stabilize the analog voltage signal to obtain the phase-locked regulation voltage.

[0033] According to another aspect of an embodiment of the present disclosure, a chip is provided, comprising a delay locked loop circuit as described in any one of the above items.

[0034] According to another aspect of an embodiment of the present disclosure, an electronic device is provided, comprising the chip as described above.

[0035] It can be seen from the above scheme that in the delay phase-locked loop circuit, chip and electronic device disclosed in the present invention, a voltage digital control unit is used to realize digital control of the phase-locked regulation voltage. Since a digital loop design is adopted in the voltage control loop, the present invention helps to improve the stability, reusability, monitorability and configurability of voltage control.

[0036] In the delay phase-locked loop circuit, chip and electronic device disclosed in the present invention, the voltage digital control signal generated by the voltage digital control unit is used to control the change of the phase-locked regulation voltage, which enhances the monitorability and configurability of the phase-locked regulation voltage. It only needs to add a corresponding register to store the value of the voltage digital control signal, and the change of the phase-locked regulation voltage can be monitored by reading the register. The voltage digital control unit of the digital circuit enhances the configurability, and it is easy to set the initial value of different voltage digital control signals according to the needs of different application environments. In addition, the digital loop also has the characteristic of easy reuse. Compared with the analog loop, the manufacturing process is less restricted and the reusability of different processes is stronger.

[0037] The delay phase-locked loop circuit, chip and electronic device disclosed in the present invention can achieve compatibility with a wide frequency range of low speed and high speed by setting the first adjustment unit and the second adjustment unit in the delay circuit unit using the first adjustment parameter and the second adjustment parameter, so that the delay phase-locked loop circuit, chip and electronic device disclosed in the present invention have the advantage of compatibility with a wide frequency range from low speed to high speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic diagram of a delay phase-locked loop circuit in the related art;

[0039] Figure 2 is a schematic diagram of a delay locked loop circuit according to an exemplary embodiment;

[0040] Figure 3 is a schematic diagram of a delay circuit unit according to an exemplary embodiment;

[0041] Figure 4 is a schematic diagram of a voltage-controlled delay line unit according to an exemplary embodiment;

[0042] Figure 5 is a schematic diagram of a delay unit according to an exemplary embodiment;

[0043] Figure 6 is a phase diagram showing N clock signals according to an exemplary embodiment;

[0044] Figure 7 is a schematic diagram of a voltage digital control unit according to an exemplary embodiment;

[0045] Figure 8 is a schematic diagram of a phase comparison unit according to an exemplary embodiment;

[0046] Fig. 9 is a schematic diagram of a phase difference detection unit according to an exemplary embodiment;

[0047] Fig. 10Ais a timing comparison diagram when the second phase clock signal is ahead of the first phase clock signal according to an exemplary embodiment;

[0048] Fig. 10B is a timing comparison diagram when a second phase clock signal lags behind a first phase clock signal according to an exemplary embodiment;

[0049] Fig.11 is a schematic diagram of a voltage source unit according to an exemplary embodiment;

[0050] Fig.12 It is a structural diagram of an application scenario of a delay phase-locked loop circuit according to an exemplary embodiment. DETAILED DESCRIPTION

[0051] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below with reference to the accompanying drawings and examples.

[0052] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0053] Figure 1 This is a schematic diagram of a delay phase-locked loop circuit in the related technology. Figure 1 As shown, the delay phase-locked loop circuit mainly includes a four-stage delay unit, a phase detector PD and a low-pass filter LPF. The four-stage delay unit is connected in series on the clock signal path. The clock signal CK in Entering the first delay unit generates a first delay signal CK1, the first delay signal CK1 enters the second delay unit to generate a second delay signal CK2, the second delay signal CK2 enters the third delay unit to generate a third delay signal CK3, the third delay signal CK3 enters the fourth delay unit to generate a fourth delay signal CK4, the fourth delay signal CK4 and the clock signal CK in The control voltage V of the four-stage delay unit is generated by the phase detector PD and the low-pass filter LPF. cont , thereby realizing the clock signal CK in and the phase of the fourth delayed signal CK4.

[0054] Figure 1 The delay phase-locked loop circuit shown is an analog loop, which outputs a control voltage V by combining a phase detector PD with a low-pass filter LPF. contDirectly control the delay line composed of four-stage delay units. This control method has poor integral nonlinearity (INL) and differential nonlinearity (DNL). The delay of the delay line can only be controlled by the control voltage V cont Control, the supported frequency range is small, the stability design of the analog loop is more complicated, and the reusability of different processes is weak.

[0055] Among them, integral nonlinearity is an important parameter to measure the performance of analog-to-digital converters (ADC) or digital-to-analog converters (DAC). It describes the degree of deviation between the output signal of the converter and the ideal linear relationship. Ideally, the output of an analog-to-digital converter or a digital-to-analog converter should be linear with the input signal, that is, there is a fixed slope between the input signal and the output digital value (or analog voltage). However, in practical applications, due to various non-ideal factors (such as component mismatch, temperature change, power supply fluctuation, etc.), this linear relationship will have deviations, and integral nonlinearity is an indicator used to measure this deviation. Differential nonlinearity is another key parameter to measure the performance of an analog-to-digital converter or a digital-to-analog converter. It describes the deviation between the change of the converter output signal between adjacent digital values ​​and the ideal linear change. Ideally, the output signal of an analog-to-digital converter or a digital-to-analog converter should have a constant amount of change between adjacent digital values. For an analog-to-digital converter, this means that a small change in the input signal should result in a corresponding change in the output digital value; for a digital-to-analog converter, this means that a small change in the digital value should result in a corresponding change in the output analog voltage. Differential nonlinearity measures the deviation of the actual value of this change from the ideal value.

[0056] In view of this, an embodiment of the present disclosure provides a delay phase-locked loop circuit, which adopts a digital loop design on the voltage control loop to help improve its stability, reusability, monitorability and configurability of voltage control. On this basis, by setting the parameters of the delay chain, the delay phase-locked loop circuit of the embodiment of the present disclosure meets the applicability requirements of different clock frequency ranges, thereby improving the overall applicability of the delay phase-locked loop circuit to various clock frequency requirements, and achieving compatibility with a wide frequency range of low-speed and high-speed clock signals.

[0057] Figure 2 is a schematic diagram of a delay phase-locked loop circuit according to an exemplary embodiment, such as Figure 2As shown, the delay phase-locked loop circuit mainly includes a delay circuit unit 1, a voltage digital control unit 2 and a voltage source unit 3. Among them, the delay circuit unit 1 is used to adjust the voltage V reg_dll The voltage digital control unit 2 is coupled to the delay circuit unit 1, and is used to receive the first phase clock signal ck_ph1 and the second phase clock signal ck_ph2, and generate a voltage digital control signal according to the first phase clock signal ck_ph1 and the second phase clock signal ck_ph2. The voltage source unit 3 is coupled to the voltage digital control unit 2 and the delay circuit unit 1, and is used to receive the voltage digital control signal, and generate a phase-locked adjustment voltage V according to the voltage digital control signal. reg_dll .

[0058] In the delay phase-locked loop circuit of the embodiment of the present disclosure, the voltage digital control unit 2 is used to realize the phase-locked regulation voltage V reg_dll Since the voltage control loop adopts a digital loop design, the embodiments of the present disclosure are helpful to improve the stability, reusability, monitorability and configurability of the voltage control.

[0059] Figure 3 is a schematic diagram of a delay circuit unit 1 according to an exemplary embodiment, as shown in Figure 3 As shown, the delay circuit unit 1 includes a first voltage domain adjustment unit 11, a voltage-controlled delay line (VCDL) unit 12, and a second voltage domain adjustment unit 13. The first voltage domain adjustment unit 11 is used to adjust the voltage V reg_dll The system clock signal ck_in is received and the voltage domain of the system clock signal ck_in is adjusted to the phase-locked adjustment voltage V reg_dll The voltage domain of the voltage controlled delay line unit 12 is coupled to the first voltage domain adjustment unit 11, and is used to phase-lock the voltage V reg_dllThe first phase-locked voltage domain phase clock signal ck_Vph1 and the second phase-locked voltage domain phase clock signal ck_Vph2 are obtained by delaying the phase-locked voltage domain clock signal ck_acc. The second voltage domain adjustment unit 13 is coupled to the voltage controlled delay line unit 12, and is used to receive the first phase-locked voltage domain phase clock signal ck_Vph1 and the second phase-locked voltage domain phase clock signal ck_Vph2, and adjust the voltage domain of the first phase-locked voltage domain phase clock signal ck_Vph1 and the second phase-locked voltage domain phase clock signal ck_Vph2 to the voltage domain of the voltage digital control unit 2, and obtain the first phase clock signal ck_ph1 and the second phase clock signal ck_ph2.

[0060] In the delay circuit unit 1, the first voltage domain adjustment unit 11 and the second voltage domain adjustment unit 13 are used to convert the voltage domain of the system clock signal ck_in and convert the voltage domain of the first phase-locked adjustment voltage domain phase clock signal ck_Vph1 and the second phase-locked adjustment voltage domain phase clock signal ck_Vph2. In the exemplary embodiment, because the phase-locked adjustment voltage V reg_dll The phase difference between the first phase-locked voltage domain phase clock signal ck_Vph1 and the second phase-locked voltage domain phase clock signal ck_Vph2 will change. In addition, inside the chip, the voltage domain of the system clock signal ck_in may be different from the voltage domain of the voltage-controlled delay line unit 12 (the phase-locked voltage V reg_dll ) is different, the phase-locked regulation voltage V reg_dll It may be lower or higher than the voltage domain of the system clock signal ck_in. In this case, if the voltage domain of the system clock signal ck_in is not converted, the voltage-controlled delay line unit 12 will not work properly. Therefore, the first voltage domain adjustment unit 11 is required to convert the voltage domain of the system clock signal ck_in. Similarly, the voltage domain in which the voltage-controlled delay line unit 12 works normally may be different from the voltage domain in which the voltage digital control unit 2 works normally. Therefore, the second voltage domain adjustment unit 13 is required to convert the voltage domain of the first phase-locked adjustment voltage domain phase clock signal ck_Vph1 and the second phase-locked adjustment voltage domain phase clock signal ck_Vph2.

[0061] In summary, because the embodiment of the present disclosure is to adjust the voltage V by phase locking reg_dll Therefore, the voltage domain of the voltage-controlled delay line unit 12 may be different from the voltage domain of other circuit parts. Adding a voltage domain adjustment unit can ensure the normal operation of the voltage-controlled delay line unit 12.

[0062] In an exemplary embodiment, the first voltage domain regulating unit 11 and the second voltage domain regulating unit 13 may be implemented by using an AC couple circuit.

[0063] Figure 4 is a schematic diagram of a voltage controlled delay line unit 12 according to an exemplary embodiment, as shown in Figure 4 As shown, in the exemplary embodiment, the voltage-controlled delay line unit 12 includes N-stage delay units 121. The power supply end of each stage of the delay unit 121 is coupled to the voltage source unit 3, the input end of the subsequent stage of the delay unit 121 in two adjacent stages of the delay unit 121 is coupled to the output end of the previous stage of the delay unit 121, and the first stage of the delay unit 121 (for example, Figure 4 The input terminal of the leftmost delay unit 121 is coupled to the first voltage domain adjustment unit 11 to receive the phase-locked regulated voltage domain clock signal ck_acc. In the exemplary embodiment, N≥2.

[0064] Since there will be various multi-phase clock signal application requirements in the internal circuit modules of the chip, based on this, in the illustrative embodiment, the number of N can be set to meet the needs of various multi-phase clock signal applications. For example, the number of N can depend on the need to reduce Tcq (Clock to Q delay time) in the digital system to optimize the timing and phase interpolator (PI). Among them, Tcq is used to describe the time delay from the generation of the clock signal in the digital circuit to its impact on the circuit output. Specifically, Tcq refers to the time required from the rising edge or falling edge of the clock signal to the output signal (Q) stabilizing in a new state. A phase interpolator is a device used to adjust the phase of a signal in digital and analog circuits. It is usually used in applications that require precise control of the signal phase, such as wireless communications, digital signal processing, frequency synthesizers and other fields.

[0065] Figure 5 is a schematic diagram of a delay unit 121 according to an exemplary embodiment, as shown in Figure 5 As shown, in the exemplary embodiment, the delay unit 121 includes a first adjustment unit 1211 and a second adjustment unit 1212. The first adjustment unit 1211 includes a phase-locked adjustment voltage V reg_dll The power supply is connected in parallel to the input terminal of the delay unit 121 ( Figure 5 Left side) and output side ( Figure 5The second adjustment unit 1212 includes a plurality of capacitors C connected in parallel between the output end of the delay unit 121 and the ground end, and the number of capacitors C is set according to the preset second adjustment parameter.

[0066] In the exemplary embodiment, in the hardware circuit of the delay unit 121, the actual number of buffers and the number of capacitors C may be numbers set according to design requirements, and when applied, the first adjustment parameter and the second adjustment parameter are used to control the number of buffers and the number of capacitors C that are actually connected to the delay unit 121 circuit for operation, respectively. For example, in the hardware circuit of the delay unit 121, the actual number of buffers and the number of capacitors C are set to A and B, respectively, and when applied, the first adjustment parameter controls the number of buffers that are actually connected to the delay unit 121 circuit for operation to be a, and the second adjustment parameter controls the number of capacitors C that are actually connected to the delay unit 121 circuit for operation to be b, then a buffer is a part of A buffers, and b capacitors C are a part of B capacitors C.

[0067] In an exemplary embodiment, the delay span (step) of the clock signal achieved by the driving capability of a buffer in the first adjustment unit 1211 for clock signal delay adjustment is equivalent to the delay span of the clock signal achieved by the preset upper limit number of capacitors C in the second adjustment unit 1212. In an exemplary embodiment, the delay span of the clock signal by the number of capacitors C set according to the maximum value of the second adjustment is equivalent to the delay span of the clock signal by a buffer corresponding to a change unit value of the first adjustment parameter. For example, if the first adjustment parameter and the second adjustment parameter are expressed in decimal, setting the second adjustment parameter to 10 is equivalent to setting the first adjustment parameter to 1, or setting the second adjustment parameter to 100 is equivalent to setting the first adjustment parameter to 1, or setting the second adjustment parameter to 1000 is equivalent to setting the first adjustment parameter to 1. The number of buffers and capacitors C can be designed according to the requirements and the preparation process of the buffers and capacitors C in the delay unit 121. In an illustrative embodiment, under the premise that the total capacitance of the capacitors in the second adjusting unit 1212 remains unchanged, corresponding to the delay span of the clock signal implemented by a buffer in the first adjusting unit 1211, the more capacitors C in the second adjusting unit 1212 that implement the delay span, the finer the delay control of the clock signal by the delay unit 121.

[0068] Based on this, in the exemplary embodiment, the first adjustment unit 1211 may also be called a coarse adjustment unit, the second adjustment unit 1212 may also be called a fine adjustment unit, the first adjustment parameter may also be called a coarse adjustment parameter, and the second adjustment parameter may also be called a fine adjustment parameter.

[0069] In an exemplary embodiment, the coarse adjustment parameter and the fine adjustment parameter may be stored in a set buffer. In an exemplary embodiment, the coarse adjustment parameter may be represented as coarse adjustment parameter. <m:0>, where coarse means coarse adjustment, <m:0>represents a binary value of m+1 bits. In the exemplary embodiment, coarse <m:0>The value of represents the number of buffers actually connected to the delay unit 121 circuit to work. In the exemplary embodiment, the fine tuning parameter can be expressed as fine <n:0>, where fine means fine tuning, <n:0>represents a binary value of n+1 bits. In the exemplary embodiment, fine <n:0>The value represents the number of capacitors C actually connected to the delay unit 121 circuit to work.

[0070] In an exemplary embodiment, the first adjustment parameter and the second adjustment parameter are associated with a frequency range of the system clock signal ck_in.

[0071] Coarse adjustment parameters <m:0>The delay is adjusted by adjusting the driving capability of the delay unit 121 (adjusting the number of buffers). <m:0>It is a static parameter and is set before the delay phase-locked loop circuit of the embodiment of the present disclosure works. <m:0>The larger the value, the more buffers are connected, because the buffers are phase-locked to adjust the voltage V reg_dll The power supply is connected in parallel between the input and output of the delay unit 121, so the more buffers are connected, the more the phase-locked adjustment voltage V reg_dll The stronger the driving capability of the multiple buffers, the shorter the delay of the coarse adjustment unit to the clock signal. Based on this, when the delay locked loop circuit of the embodiment of the present disclosure operates at a low speed (when the clock signal frequency is low), the circuit is relatively less sensitive to the delay of the clock signal, so the coarse adjustment parameter coarse adjustment can be appropriately reduced. <m:0>On the contrary, when the delay phase-locked loop circuit of the embodiment of the present disclosure operates at a high speed (when the clock signal frequency is high), the circuit is relatively sensitive to the delay of the clock signal, so the coarse adjustment parameter coarse can be appropriately increased. <m:0>.

[0072] Fine tuning parameters <n:0>By adjusting the size of capacitor C (adjusting the number of capacitors C), the delay can be adjusted. In the exemplary embodiment, the fine tuning parameter fine <n:0>It is a static parameter and is set before the delay locked loop circuit of the embodiment of the present disclosure works. <n:0>The larger the value, the more capacitors C are connected, the larger the value of capacitor C is, and the longer the delay of the fine-tuning unit to the clock signal is. Based on this, when the delay phase-locked loop circuit of the embodiment of the present disclosure works at a low speed (when the clock signal frequency is low), the circuit is relatively less sensitive to the delay of the clock signal, so the fine-tuning parameter fine can be appropriately increased. <n:0>On the contrary, when the delay-locked loop circuit of the embodiment of the present disclosure operates at a high speed (when the clock signal frequency is high), the circuit is relatively sensitive to the delay of the clock signal, so the fine tuning parameter fine can be appropriately reduced. <n:0>.

[0073] In an exemplary embodiment, the full range of clock frequencies from low speed to high speed can be divided into several frequency range intervals, and different frequency range intervals correspond to different coarse adjustment parameters. <m:0>and fine tuning parameters <n:0>When the delay phase-locked loop circuit of the embodiment of the present disclosure is applied to different frequency ranges, the corresponding coarse adjustment parameter coarse is used. <m:0>and fine tuning parameters <n:0>Therefore, the delay locked loop circuit of the embodiment of the present disclosure has the advantage of being compatible with a wide frequency range from low speed to high speed.

[0074] In the exemplary embodiment, the first phase clock signal ck_ph1 and the second phase clock signal ck_ph2 can be derived from any two nodes in the delay circuit unit 1, that is, the phase-locked voltage domain phase clock signals with different delays are derived from any node connected to the delay unit 121, thereby obtaining the first phase clock signal ck_ph1 and the second phase clock signal ck_ph2. However, based on design practice, in the exemplary embodiment, the phase of the first phase clock signal ck_ph1 is the same as the phase of the system clock signal ck_in, and the phase of the second phase clock signal ck_ph2 is the phase of the system clock signal ck_in after N stages of delay, where N≥2. That is, Figure 4 As shown, the phase-locked adjustment voltage domain phase clock signal without delay is derived from the input end of the first-stage delay unit 121 as the first phase-locked adjustment voltage domain phase clock signal ck_Vph1, and the phase-locked adjustment voltage domain phase clock signal after N-stage delay is derived from the output end of the N-stage delay unit 121 as the second phase-locked adjustment voltage domain phase clock signal ck_Vph2, thereby obtaining the first phase clock signal ck_ph1 and the second phase clock signal ck_ph2. In this way, after the delay phase-locked loop circuit of the embodiment of the present disclosure works stably, the different phase clock signals obtained after delay by different stages of delay units 121 can be applied to different needs.

[0075] Figure 6 is a phase diagram of N clock signals according to an exemplary embodiment, such as Figure 6 As shown, the phase of the phase clock signal without delay (first phase clock signal ck_ph1) is represented as ph_0, and its phase degree is represented as 0°, and the phase of the phase clock signal after N-stage delay (second phase clock signal ck_ph2) is represented as ph_N, and its phase degree is represented as 360°, wherein the 0° and 360° phases are locked together through the delay phase-locked loop circuit, i.e., on the same edge. The phase of the phase clock signal after 1-stage delay is represented as ph_1, the phase of the phase clock signal after 2-stage delay is represented as ph_2, the phase of the phase clock signal after 3-stage delay is represented as ph_3, and so on. It is not difficult to obtain that, from 0° to 360°, from ph_0 to ph_N, the phases of each delayed phase clock signal are equally spaced and distributed in 0° to 360°. Therefore, by locking ph_0 and ph_N, the delay phase-locked loop circuit of the embodiment of the present disclosure can obtain a precise N-phase clock, which can be used to reduce Tcq and optimize timing in digital systems, and can also be used as an input of a phase interpolator to adjust the clock phase of a multi-phase clock.

[0076] Figure 7 is a schematic diagram of a voltage digital control unit 2 according to an exemplary embodiment, such as Figure 7 As shown, in the exemplary embodiment, the voltage digital control unit 2 includes a phase comparison unit 21 and a digital control logic unit 22. The phase comparison unit 21 is coupled to the delay circuit unit 1, and is used to receive the first phase clock signal ck_ph1 and the second phase clock signal ck_ph2, and generate a phase difference comparison signal according to the first phase clock signal ck_ph1 and the second phase clock signal ck_ph2. The digital control logic unit 22 is coupled to the phase comparison unit 21, and is used to generate a voltage digital control signal, receive the phase difference comparison signal, and adjust the signal value of the voltage digital control signal according to the phase difference comparison signal.

[0077] In the exemplary embodiment, the phase difference comparison signal reflects whether the second phase clock signal ck_ph2 is ahead of or behind the first phase clock signal ck_ph1. Because the phase difference comparison signal reflects this advance / lag relationship, the phase difference comparison signal may also be called an early_late signal.

[0078] In an exemplary embodiment, the voltage digital control signal may be represented as DAC_cntr <k:0>, where DAC_cntr represents the digital-to-analog conversion control, <k:0>represents a binary value of k+1 bits. In the exemplary embodiment, DAC_cntr <k:0>The value is used to characterize the phase-locked regulation voltage V reg_dll In the exemplary embodiment, in the power-on initialization state, DAC_cntr <k:0>There is an initial value, which can be set in advance. During the operation of the delay locked loop circuit of the embodiment of the present disclosure, the digital control logic unit 22 adjusts DAC_cntr according to the phase difference comparison signal. <k:0>When ph_0 and ph_N are locked, DAC_cntr <k:0>The value of DAC_cntr <k:0>The value of DAC_cntr will change repeatedly with a small amplitude. <k:0>It can be a 9-bit binary value (k=8), that is, DAC_cntr<8:0>, and the initial value can be set to the middle value of the numerical range of the 9-bit binary value, such as 100000000. When the phase difference comparison signal received by the digital control logic unit 22 indicates that the phase lock adjustment voltage V reg_dll When DAC_cntr <k:0>Add 1, from 100000000 to 100000001, when the phase difference comparison signal received by the digital control logic unit 22 indicates that the phase lock adjustment voltage V reg_dll When DAC_cntr <k:0>Add 1, from 100000001 to 100000010, when the phase difference comparison signal received by the digital control logic unit 22 indicates that the phase lock adjustment voltage V reg_dll When DAC_cntr <k:0>Subtract 1, from 100000010 to 100000001, and so on. <k:0>When a certain value is reached so that ph_0 and ph_N are locked and the delay phase-locked loop circuit reaches the locked state, DAC_cntr <k:0>will change repeatedly with a small amplitude. For example, when DAC_cntr <k:0>When it reaches 100111010, ph_0 and ph_N are locked, and the delay phase-locked loop circuit reaches the locked state. In this locked state, DAC_cntr <k:0>The value will change between 100111010 and 100111001 or between 100111010 and 100111011 repeatedly to maintain the phase-locked regulation voltage V reg_dll The DAC_cntr in the actual situation is basically unchanged, maintaining the locked state of the delay phase-locked loop circuit. <k:0>The values ​​may not be the values ​​in this example and the range of repeated changes may not be limited to between two adjacent values.

[0079] In the delay phase-locked loop circuit of the embodiment of the present disclosure, the voltage digital control signal generated by the voltage digital control unit 2 is used to control the phase-locked adjustment voltage V reg_dll The change of the phase-locked regulation voltage V reg_dll The monitorability and configurability of the voltage digital control signal can be realized by reading the register to realize the phase-locked regulation voltage V. reg_dll The digital circuit can monitor the changes of the voltage digital control unit 2, and the configurability is enhanced. It is easy to set the initial values ​​of different voltage digital control signals according to the needs of different application environments. In addition, the digital loop is easy to reuse. Compared with the analog loop, the manufacturing process is less restricted and the reusability of different processes is stronger.

[0080] Figure 8 is a schematic diagram of a phase comparison unit 21 according to an exemplary embodiment, as shown in Figure 8 As shown, in the exemplary embodiment, the phase comparison unit 21 includes a phase difference detection unit 211 and a comparator 212. The phase difference detection unit 211 is coupled to the delay circuit unit 1, and is used to receive the first phase clock signal ck_ph1 and the second phase clock signal ck_ph2, and obtain a phase difference signal between the first phase clock signal ck_ph1 and the second phase clock signal ck_ph2. The comparator 212 is coupled to the phase difference detection unit 211, and is used to receive the phase difference signal, and generate a phase difference comparison signal by comparing the phase difference signal.

[0081] In an exemplary embodiment, the phase difference signal includes two signals, one of which indicates that the second phase clock signal ck_ph2 is ahead of the first phase clock signal ck_ph1, which can be called an early signal, and the other indicates that the second phase clock signal ck_ph2 lags behind the first phase clock signal ck_ph1, which can be called a late signal. In an exemplary embodiment, the early signal and the late signal are level signals, and the comparator 212 outputs an early_late signal according to the level change of the early signal and the late signal. In an exemplary embodiment, when the early signal is at a high level and the late signal is at a low level, it indicates that the second phase clock signal ck_ph2 is ahead of the first phase clock signal ck_ph1. At this time, the comparator 212 outputs the early_late signal as 0 or a low level, which means that the phase lock adjustment voltage V needs to be reduced. reg_dll To increase the delay of the delay circuit unit 1; on the contrary, when the early signal is low and the late signal is high, it means that the second phase clock signal ck_ph2 lags behind the first phase clock signal ck_ph1. At this time, the comparator 212 outputs the early_late signal as 1 or high, which means that the phase-locked adjustment voltage V reg_dll To reduce the delay of delay circuit unit 1.

[0082] Fig. 9 is a schematic diagram of a phase difference detection unit 211 according to an exemplary embodiment. Fig. 9 As shown, in the exemplary embodiment, the phase difference detection unit 211 includes a phase detector 2111 and a filter 2112. The phase detector 2111 is coupled to the delay circuit unit 1, and is used to receive the first phase clock signal ck_ph1 and the second phase clock signal ck_ph2, and perform phase detection on the first phase clock signal ck_ph1 and the second phase clock signal ck_ph2 to obtain a phase difference piecewise linear (Piecewise Linear, PWL) signal. The filter 2112 is coupled to the phase detector 2111, and is used to filter the phase difference piecewise linear signal to obtain a phase difference signal. In the exemplary embodiment, the piecewise linear signal can be a pulse signal.

[0083] In an exemplary embodiment, the phase-difference piecewise linear signal includes two signals, one of which indicates that the second phase clock signal ck_ph2 is ahead of the first phase clock signal ck_ph1, which can be called an early_PWL signal, and the other indicates that the second phase clock signal ck_ph2 lags behind the first phase clock signal ck_ph1, which can be called a late_PWL signal. In an exemplary embodiment, after the filter 2112 filters the early_PWL signal and the late_PWL signal, an early signal and a late signal represented by high and low levels are obtained.

[0084] Fig. 10A 1 is a timing comparison diagram showing a case where the second phase clock signal ck_ph2 is ahead of the first phase clock signal ck_ph1 according to an exemplary embodiment. Fig. 10A As shown, when the second phase clock signal ck_ph2 is ahead of the first phase clock signal ck_ph1, the rising edge of the early_PWL signal is aligned with the rising edge of the second phase clock signal ck_ph2, and the falling edge of the early_PWL signal is aligned with the rising edge of the first phase clock signal ck_ph1, generating an early_PWL signal with a certain duty cycle. After the early_PWL signal is filtered by the filter 2112, the signal is straightened to obtain an early signal in a high level state ( Fig. 10A At the same time, the late_PWL signal is in a low level state, and then the late signal obtained after the late_PWL signal is filtered by the filter 2112 is also in a low level state. In this case, the early signal received by the comparator 212 is a high level signal, and the late signal received is a low level signal. At this time, the early_late signal output by the comparator 212 is 0 or a low level.

[0085] Fig. 10B is a timing comparison diagram showing when the second phase clock signal ck_ph2 lags behind the first phase clock signal ck_ph1 according to an exemplary embodiment. Fig. 10B As shown, when the second phase clock signal ck_ph2 lags behind the first phase clock signal ck_ph1, the rising edge of the late_PWL signal is aligned with the rising edge of the first phase clock signal ck_ph1, and the falling edge of the late_PWL signal is aligned with the rising edge of the second phase clock signal ck_ph2, generating a late_PWL signal with a certain duty cycle. After the late_PWL signal is filtered by the filter 2112, the signal is straightened to obtain a late signal in a high level state ( Fig. 10A At the same time, the early_PWL signal is in a low level state, and then the early signal obtained after the early_PWL signal is filtered by the filter 2112 is also in a low level state. In this case, the early signal received by the comparator 212 is a low level signal, and the late signal received is a high level signal. At this time, the early_late signal output by the comparator 212 is 1 or a high level.

[0086] Fig.11 is a schematic diagram of a voltage source unit 3 according to an exemplary embodiment, as shown in Fig.11 As shown, in the exemplary embodiment, the voltage source unit 3 includes a digital-to-analog conversion unit 31 and a linear regulator 32. The digital-to-analog conversion unit 31 is coupled to the voltage digital control unit 2, and is used to receive a voltage digital control signal and convert the voltage digital control signal into an analog voltage signal. The linear regulator 32 is coupled to the digital-to-analog conversion unit 31, and is used to receive an analog voltage signal and stabilize the analog voltage signal to obtain a phase-locked regulation voltage V reg_dll The linear regulator 32 is equivalent to a voltage source, providing a stable voltage, and will not cause the phase-locked regulation voltage V due to a sudden increase or decrease in current. reg_dll In an exemplary embodiment, the digital-to-analog conversion unit 31 may be a digital-to-analog converter. In an exemplary embodiment, the linear regulator 32 may be a low dropout regulator (LDO).

[0087] Fig.12 is a schematic diagram of a structure of an application scenario of a delay phase-locked loop circuit according to an exemplary embodiment, such as Fig.12 As shown, the delay phase-locked loop circuit in this application scenario includes a digital-to-analog conversion unit 31, a linear regulator 32, a first voltage domain adjustment unit 11, a voltage-controlled delay line unit 12, a second voltage domain adjustment unit 13, a phase detector 2111, a filter 2112, a comparator 212, and a digital control logic unit 22. The digital-to-analog conversion unit 31 is coupled to the digital control logic unit 22, and is used to receive a voltage digital control signal from the digital control logic unit 22 and convert the voltage digital control signal into an analog voltage signal. The linear regulator 32 is coupled to the digital-to-analog conversion unit 31, and is used to receive an analog voltage signal and stabilize the analog voltage signal to obtain a phase-locked adjustment voltage V reg_dll The first voltage domain regulating unit 11 is coupled to the linear regulator 32 and is used to adjust the voltage V reg_dll The system clock signal ck_in is received and the voltage domain of the system clock signal ck_in is adjusted to the phase-locked adjustment voltage V reg_dll The voltage domain of the voltage controlled delay line unit 12 is coupled to the first voltage domain adjustment unit 11, and is used to phase-lock the voltage V reg_dll The first phase-locked voltage domain phase clock signal ck_Vph1 and the second phase-locked voltage domain phase clock signal ck_Vph2 are received and obtained by delay. The second voltage domain adjustment unit 13 is coupled to the voltage controlled delay line unit 12, and is used to receive the first phase-locked voltage domain phase clock signal ck_Vph1 and the second phase-locked voltage domain phase clock signal ck_Vph2, and adjust the voltage domain of the first phase-locked voltage domain phase clock signal ck_Vph1 and the second phase-locked voltage domain phase clock signal ck_Vph2 to the voltage domain of the voltage digital control unit 2, and obtain the first phase clock signal ck_ph1 and the second phase clock signal ck_ph2. The phase detector 2111 is coupled to the second voltage domain adjustment unit 13, and is used to receive the first phase clock signal ck_ph1 and the second phase clock signal ck_ph2, and perform phase detection on the first phase clock signal ck_ph1 and the second phase clock signal ck_ph2 to obtain a phase difference piecewise linear signal. The filter 2112 is coupled to the phase detector 2111, and is used to filter the phase difference PWL signal to obtain a phase difference signal. The comparator 212 is coupled to the filter 2112, and is used to receive the phase difference signal, and generate a phase difference comparison signal by comparing the phase difference signal. The digital control logic unit 22 is coupled to the comparator 212, and is used to generate a voltage digital control signal, receive the phase difference comparison signal, and adjust the signal value of the voltage digital control signal according to the phase difference comparison signal.

[0088] Among them, about Fig.12 For further explanation of each component in the structure shown, reference can be made to the description in the above-mentioned exemplary embodiments, which will not be repeated here.

[0089] In an exemplary embodiment, a chip is further provided. The chip includes the delay locked loop circuit as described in any one of the above embodiments.

[0090] In an exemplary embodiment, an electronic device is also provided. The electronic device includes the chip described above.

[0091] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A delay locked loop circuit, characterized in that: include: A delay circuit unit, used for receiving a system clock signal under a phase-locked regulation voltage and delaying the system clock signal to generate a first phase clock signal and a second phase clock signal; a voltage digital control unit, configured to receive the first phase clock signal and the second phase clock signal, and generate a voltage digital control signal according to the first phase clock signal and the second phase clock signal; as well as A voltage source unit, used for receiving the voltage digital control signal and generating the phase-locked regulation voltage according to the voltage digital control signal; Wherein, the delay circuit unit includes N-stage delay units, and the delay unit includes: A first regulating unit, comprising a plurality of buffers powered by the phase-locked regulating voltage and connected in parallel between an input end and an output end of the delay unit, wherein the number of the buffers is set according to a preset first regulating parameter; A second adjustment unit, comprising a plurality of capacitors connected in parallel between an output terminal of the delay unit and a ground terminal, wherein the number of the capacitors is set according to a preset second adjustment parameter; The entire range of clock frequencies from low speed to high speed is divided into a plurality of frequency range intervals, and different frequency range intervals correspond to different first adjustment parameters and second adjustment parameters.

2. The delay locked loop circuit according to claim 1, characterized in that: The delay circuit unit comprises: A first voltage domain adjustment unit, configured to receive the system clock signal under the phase-locked adjustment voltage, and adjust the voltage domain of the system clock signal to the voltage domain of the phase-locked adjustment voltage to obtain a phase-locked adjustment voltage domain clock signal; A voltage-controlled delay line unit, configured to receive the phase-locked regulated voltage domain clock signal under the phase-locked regulated voltage, and obtain a first phase-locked regulated voltage domain phase clock signal and a second phase-locked regulated voltage domain phase clock signal by delaying the phase-locked regulated voltage domain clock signal; The second voltage domain adjustment unit is used to receive the first phase-locked adjustment voltage domain phase clock signal and the second phase-locked adjustment voltage domain phase clock signal, adjust the voltage domain of the first phase-locked adjustment voltage domain phase clock signal and the second phase-locked adjustment voltage domain phase clock signal to the voltage domain of the voltage digital control unit, and obtain the first phase clock signal and the second phase clock signal.

3. The delay locked loop circuit according to claim 2, characterized in that: The voltage controlled delay line unit comprises: The N-stage delay units, the power supply end of each stage of the delay units are coupled to the voltage source unit, the input end of the rear-stage delay unit in two adjacent stages of the delay units are coupled to the output end of the front-stage delay unit, and the input end of the first-stage delay unit in the N-stage delay units is coupled to the first voltage domain adjustment unit to receive the phase-locked adjustment voltage domain clock signal, wherein N≥2.

4. The delay locked loop circuit according to claim 1, characterized in that: The first adjustment parameter and the second adjustment parameter are associated with a frequency range of the system clock signal.

5. The delay locked loop circuit according to claim 1, characterized in that: The phase of the first phase clock signal is the same as the phase of the system clock signal, and the phase of the second phase clock signal is the phase of the system clock signal after N stages of delay, where N≥2.

6. The delay locked loop circuit according to claim 1, characterized in that: The voltage digital control unit comprises: a phase detection and comparison unit, configured to receive the first phase clock signal and the second phase clock signal, and generate a phase difference comparison signal according to the first phase clock signal and the second phase clock signal; The digital control logic unit is used to generate the voltage digital control signal, receive the phase difference comparison signal, and adjust the signal value of the voltage digital control signal according to the phase difference comparison signal.

7. The delay locked loop circuit according to claim 6, characterized in that: The phase comparison unit comprises: a phase difference detection unit, configured to receive the first phase clock signal and the second phase clock signal, and obtain a phase difference signal between the first phase clock signal and the second phase clock signal; The comparator is used to receive the phase difference signal and generate the phase difference comparison signal by comparing the phase difference signal.

8. The delay locked loop circuit according to claim 7, characterized in that: The phase difference detection unit comprises: a phase detector, configured to receive the first phase clock signal and the second phase clock signal, and perform phase detection on the first phase clock signal and the second phase clock signal to obtain a phase difference piecewise linear signal; A filter is used to filter the phase difference piecewise linear signal to obtain the phase difference signal.

9. The delay locked loop circuit according to claim 1, characterized in that: The voltage source unit comprises: A digital-to-analog conversion unit, configured to receive the voltage digital control signal and convert the voltage digital control signal into an analog voltage signal; The linear regulator is used to receive the analog voltage signal and stabilize the analog voltage signal to obtain the phase-locked regulation voltage.

10. A chip, characterized in that: The delay locked loop circuit comprises the delay locked loop circuit as claimed in any one of claims 1 to 9.

11. An electronic device, characterized in that: Comprising the chip as claimed in claim 10.

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