Interlock switching circuit and chip testing circuit, and method for interlocking electrical signals

Abstract

The application discloses an interlocking switching circuit and chip testing circuit, and a telecommunication signal interlocking method. The interlocking switching circuit is used for inputting a first telecommunication signal or a second telecommunication signal to a signal channel. The interlocking switching circuit comprises a control unit for providing a first control signal and a second control signal, a first interlocking unit for receiving the first control signal and controlling the first telecommunication signal to input the signal channel, and a second interlocking unit for receiving the second control signal and controlling the second telecommunication signal to input the signal channel. The first interlocking unit and the second interlocking unit are used for receiving and processing the first control signal and the second control signal, so as to control the connection state of the first telecommunication signal and the second telecommunication signal with the signal channel. As a result, the first telecommunication signal and the second telecommunication signal are selectively input to the signal channel at the same time, the first telecommunication signal and the second telecommunication signal are prevented from being simultaneously input to the signal channel, and the mutual influence of the first telecommunication signal and the second telecommunication signal is avoided.

Description

Technical Field

[0001] This application belongs to the field of chip circuit technology, and in particular to an interlock switching circuit, a chip test circuit, and an electrical signal interlocking method. Background Technology

[0002] A quantum computer is a physical device that performs high-speed mathematical and logical operations, stores and processes quantum information, following the laws of quantum mechanics. The main characteristics of quantum computers include high operating speed, strong information processing capabilities, and a wide range of applications. Compared to conventional computers, the greater the amount of information processed, the more advantageous it is for quantum computers to perform calculations, and the more accurately the calculations can be ensured.

[0003] Quantum chips are the core components of quantum computers. To test the performance parameters of quantum chips, devices such as probe stations and test source meters connected to the probes of the probe station are usually used to test the quantum chips. The two test circuits of the test source meter are electrically connected to the same probe, and the two input signals are prone to mutual interference, which greatly reduces the accuracy of the quantum chip test results.

[0004] It should be noted that the information disclosed in the background section of this application is intended only to enhance the understanding of the general background of this application, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide an interlock switching circuit, a chip testing circuit, and an electrical signal interlocking method to overcome the shortcomings of the prior art.

[0006] One embodiment of this application provides an interlock switching circuit for inputting a first electrical signal or a second electrical signal into a signal channel, wherein the interlock switching circuit includes:

[0007] A control unit providing a first control signal and a second control signal, both of which have two states; and

[0008] A first interlock unit receives a first control signal and controls the input of a first electrical signal into the signal channel, and a second interlock unit receives a second control signal and controls the input of a second electrical signal into the signal channel. The first interlock unit and the second interlock unit perform a first action or a second action according to the state of the first control signal and the second control signal.

[0009] The first action includes disconnecting the electrical signal transmission from the first interlock unit and the second interlock unit to the signal channel;

[0010] The second action includes opening one of the first interlocking unit and the second interlocking unit and closing the other, thereby correspondingly inputting an electrical signal to the signal channel from the opened interlocking unit.

[0011] In the interlock switching circuit described above, the first interlock unit includes a first switch and a first interlock circuit. The first interlock circuit is used to receive a first control signal and control the first switch to close or open. The first electrical signal can be input into the signal channel through the closed first switch.

[0012] As described above, the interlock switching circuit includes a first MOSFET, a second MOSFET, a first resistor, and a fifth resistor. The gate (G) of the first MOSFET is used to receive a first control signal, the source (S) of the first MOSFET is grounded, the drain (D) of the first MOSFET is electrically connected to the gate (G) of the second MOSFET, the drain (D) of the second MOSFET is electrically connected to the input circuit of the first switch, the source (S) of the second MOSFET is electrically connected to the second interlock unit, one end of the first resistor is electrically connected to the gate (G) of the second MOSFET, and the other end of the first resistor is electrically connected to the power module. One end of the fifth resistor is electrically connected to the drain (D) of the second MOSFET, and the other end of the fifth resistor is electrically connected to the power module.

[0013] As described above, the interlock switching circuit further includes a second resistor, one end of which is electrically connected to the gate (G) of the first MOSFET, and the other end of which is electrically connected to the power module.

[0014] In the interlock switching circuit described above, the second interlock unit includes a second switch and a second interlock circuit. The second interlock circuit is used to receive a second control signal and control the second switch to close or open. The second electrical signal can be input into the signal channel through the second switch in the closed state.

[0015] The interlock switching circuit described above includes, wherein the first interlock unit further includes a first indicator unit electrically connected to the first switch, and the second interlock unit further includes a second indicator unit electrically connected to the second switch.

[0016] As described above, in the interlock switching circuit, the second interlock circuit includes a third MOSFET, a fourth MOSFET, a third resistor, and a sixth resistor. The gate (G) of the third MOSFET is used to receive a second control signal, the source (S) of the third MOSFET is grounded, the drain (D) of the third MOSFET is electrically connected to the gate (G) of the fourth MOSFET, the drain (D) of the fourth MOSFET is electrically connected to the input circuit of the second switch, the source (S) of the fourth MOSFET is electrically connected to the drain (D) of the first MOSFET, one end of the third resistor is electrically connected to the gate (G) of the fourth MOSFET, and the other end of the third resistor is electrically connected to the power module. One end of the sixth resistor is electrically connected to the drain (D) of the fourth MOSFET, and the other end of the sixth resistor is electrically connected to the power module.

[0017] The interlock switching circuit described above further includes a fourth resistor, one end of which is electrically connected to the gate (G) of the third MOS transistor, and the other end of which is electrically connected to the power module.

[0018] This application also provides a chip testing circuit, which includes the aforementioned interlock switching circuit.

[0019] This application also provides an electrical signal interlocking method for inputting a first electrical signal or a second electrical signal into a signal channel, wherein the interlocking method includes the following steps:

[0020] The control unit provides a first control signal and a second control signal, both of which have two states.

[0021] The first interlock unit receives a first control signal, and the second interlock unit receives a second control signal. The first interlock unit and the second interlock unit execute a first action or a second action according to the state of the first control signal and the second control signal.

[0022] The first action includes preventing the transmission of the first electrical signal to the signal channel via the first interlocking unit and preventing the transmission of the second electrical signal to the signal channel via the second interlocking unit.

[0023] The second action includes opening one of the first interlocking unit and the second interlocking unit and closing the other, thereby correspondingly inputting an electrical signal to the signal channel from the opened interlocking unit.

[0024] Compared with the prior art, this application proposes an interlock switching circuit for inputting a first electrical signal or a second electrical signal into a signal channel. The interlock switching circuit includes: a control unit providing a first control signal and a second control signal, both of which have two states; a first interlock unit receiving the first control signal and controlling the input of the first electrical signal into the signal channel; and a second interlock unit receiving the second control signal and controlling the input of the second electrical signal into the signal channel. The first and second interlock units perform a first action or a second action according to the states of the first and second control signals. The first action includes disconnecting the electrical signal transmission from the first and second interlock units to the signal channel; the second action includes opening one of the first and second interlock units and closing the other, thereby correspondingly inputting an electrical signal into the signal channel from the opened interlock unit. In this application, a first interlock unit and a second interlock unit are used to receive and process a first control signal and a second control signal, thereby controlling the connection state of the first electrical signal, the second electrical signal, and the signal channel. This ensures that when the first electrical signal is input into the signal channel, the second electrical signal remains disconnected from the signal channel, or vice versa. This allows for selective input of either the first or second electrical signal into the signal channel at the same time, preventing simultaneous input and interference between them. Furthermore, the other end of the signal channel can be connected to a probe for testing the quantum chip. By employing the interlock switching circuit proposed in this application, the mutual interference of two different input signals from the probe can be effectively prevented, ensuring the accuracy of the quantum chip test results. Attached Figure Description

[0025] Figure 1 A schematic diagram of the interlock switching circuit provided in this application;

[0026] Figure 2 The circuit diagram of the interlock switching circuit provided in this application.

[0027] Explanation of reference numerals in the attached figures:

[0028] 1 - Control unit, 2 - Signal source, 3 - Signal channel, 4 - First switch, 5 - First MOSFET, 6 - Second MOSFET, 7 - First resistor, 8 - Second resistor, 9 - Second switch, 10 - Third MOSFET, 11 - Fourth MOSFET, 12 - Third resistor, 13 - Fourth resistor, 14 - Second indicator unit, 15 - First indicator unit, 16 - Second transient suppression diode, 17 - First transient suppression diode, 18 - First interlock unit, 19 - Second interlock unit, 20 - Fifth resistor, 21 - Sixth resistor. Detailed Implementation

[0029] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details are presented in the various embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the various embodiments below is for ease of description and should not constitute any limitation on the specific implementation of this application. The various embodiments can be combined with and referenced by each other without contradiction.

[0031] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0032] Figure 1 A schematic diagram of the interlock switching circuit provided in this application;

[0033] Figure 2 The circuit diagram of the interlock switching circuit provided in this application.

[0034] Combined with appendix Figure 1 As shown in the figure, an interlocking switching circuit provided in this application embodiment is used to input an electrical signal to signal channel 3. The interlocking switching circuit includes:

[0035] A control unit 1, providing a first control signal and a second control signal, is used to output a combined control signal. The combined control signal includes the first control signal and the second control signal, and has multiple selectable states. These selectable states are achieved by combining any selected state of the first control signal and any selected state of the second control signal. Specifically, the control unit 1 can be a control chip, a control source meter, or other components. Both the first and second control signals have two states: high level and low level. That is, the first and second control signals can be either high-level or low-level signals. The first and second control signals are combined to form the combined control signal. For example, the combined control signal can be one of the following combinations: the first control signal is a high-level signal and the second control signal is a low-level signal; the first control signal is a low-level signal and the second control signal is a high-level signal; both the first and second control signals are low-level signals; or both the first and second control signals are high-level signals.

[0036] A first interlocking unit 18 is used to receive the first control signal and control the input of the first electrical signal into the signal channel 3. The first interlocking unit 18 provides a first signal path that can be selectively disconnected or connected, and receives a first electrical signal from the signal source 2 that is transmitted depending on the connected first signal path. The first electrical signal emitted by the signal source 2 can be transmitted to the signal channel 3 through the connected first signal path.

[0037] The second interlock unit 19, used to receive the second control signal and control the input of the second electrical signal into the signal channel 3, provides a second signal path that can be selectively disconnected or connected, and receives a second electrical signal from the signal source 2 that is transmitted depending on the connected second signal path. The second electrical signal emitted by the signal source 2 can be transmitted to the signal channel 3 through the connected second signal path. For example, in one specific way, the signal source 2 can be a component such as a test source meter, and the signal channel 3 is used to connect to a probe element. As an example, the probe element can be a probe. The first electrical signal emitted by the signal source 2 can be transmitted to the probe sequentially through the connected first signal path and the signal channel 3, and the second electrical signal emitted by the signal source 2 can be transmitted to the probe sequentially through the connected second signal path and the signal channel 3.

[0038] A power module is used to provide power to the first interlocking unit 18 and the second interlocking unit 19.

[0039] The first interlocking unit 18 and the second interlocking unit 19 are associated with circuit signals. The first interlocking unit 18 and the second interlocking unit 19 perform the first action or the second action according to the state of the first control signal and the second control signal.

[0040] The first action includes disconnecting the electrical signal transmission from the first interlock unit 18 and the second interlock unit 19 to the signal channel 3. By disconnecting the first signal path of the first interlock unit 18 and the second signal path of the second interlock unit 19, the input of electrical signals to the signal channel 3 is stopped, so that neither the first electrical signal nor the second electrical signal can be transmitted to the signal channel 3.

[0041] This includes opening one of the first interlock unit 18 and the second interlock unit 19 while closing the other, thereby correspondingly inputting an electrical signal to the signal channel 3 from the opened interlock unit. It also involves connecting one of the first signal path of the first interlock unit 18 and the second signal path of the second interlock unit 19 while disconnecting the other, thereby correspondingly inputting an electrical signal to the signal channel 3 from the signal path of the connected interlock unit. For example, in one specific manner, when the first interlock unit 18 receives a first control signal and the second interlock unit 19 receives a second control signal, the first and second signal paths exhibit different on / off states depending on the combination of the first and second control signals. Specifically, the first and second signal paths have the following combinations of disconnection or on / off states: the first signal path is disconnected and the second signal path is connected; the first signal path is connected and the second signal path is disconnected; the first and second signal paths are simultaneously disconnected.

[0042] In this embodiment, the first interlock unit 18 and the second interlock unit 19 are used to receive and process the first control signal and the second control signal. Based on the combination state of the first control signal and the second control signal, the connection state of the first electrical signal and the second electrical signal with the signal channel 3 is controlled, so that when the first electrical signal is input to the signal channel 3, the second electrical signal remains disconnected from the signal channel 3, or when the second electrical signal is input to the signal channel 3, the first electrical signal remains disconnected from the signal channel 3. This allows the first electrical signal and the second electrical signal to be selectively input to the signal channel 3 at the same time, avoiding the simultaneous input of the first electrical signal and the second electrical signal to the signal channel 3. The other end of the signal channel 3 can be connected to the probe of the quantum chip. By adopting the interlock switching circuit proposed in this application, the first electrical signal and the second electrical signal can be switched, thereby effectively avoiding mutual interference between the two input signals of the probe and ensuring the accuracy of the quantum chip test results.

[0043] It should be noted that the first interlock unit 18 includes a first switch 4 and a first interlock circuit. The first interlock circuit is used to receive a first control signal and control the first switch 4 to close or open. The first electrical signal can be input into the signal channel 3 through the closed first switch 4. In specific implementation, the first switch 4 has an output circuit and an input circuit. One end of the output circuit is connected to the signal source 2, and the other end of the output circuit is electrically connected to the signal channel 3. One end of the input circuit is electrically connected to the control unit 1, and the other end of the input circuit is electrically connected to the power supply. As an example, the first switch 4 is a reed relay. By using the first interlock circuit in conjunction with the first switch 4, the first interlock circuit controls the open or closed state of the first switch 4, thereby realizing the disconnection or connection of the first signal path, and the first electrical signal can be input into the signal channel 3 through the closed first switch 4.

[0044] Combined with appendix Figure 2 As shown, in specific implementation, the first interlock circuit includes a first MOSFET 5, a second MOSFET 6, a first resistor 7, and a fifth resistor 20. The gate (G) of the first MOSFET 5 is used to receive the first control signal, the source (S) of the first MOSFET 5 is grounded, the drain (D) of the first MOSFET 5 is electrically connected to the gate (G) of the second MOSFET 6, the drain (D) of the second MOSFET 6 is electrically connected to the input circuit of the first switch 4, the source (S) of the second MOSFET 6 is electrically connected to the second interlock unit 19, one end of the first resistor 7 is electrically connected to the gate (G) of the second MOSFET 6, and the other end of the first resistor 7 is electrically connected to the power supply module. The fifth resistor 20... One end of resistor 20 is electrically connected to the drain (D) of the second MOSFET 6, and the other end of the fifth resistor 20 is electrically connected to the power module. It should be noted that the first MOSFET 5 is a P-type MOSFET, and the second MOSFET 6 is an N-type MOSFET. When the first control signal is a low-level signal, the first MOSFET 5 is turned on, which grounds the gate (G) of the second MOSFET 6, thereby turning off the second MOSFET 6. This ensures that the voltages at the two input ports of the first switch 4 remain consistent, both being the power supply voltage. The first switch 4 uses a reed relay, and the output circuit of the reed relay remains open, thus preventing the first electrical signal from being input to the signal channel 3.

[0045] It should be noted that P-type MOSFETs have the following characteristics: when the gate (G) of a P-type MOSFET receives a high-level signal, its drain (D) and source (S) are disconnected; when the gate (G) of a P-type MOSFET receives a low-level signal, its drain and source (D) are connected. N-type MOSFETs, on the other hand, have the following characteristics: when the gate (G) of an N-type MOSFET receives a low-level signal, its drain and source (D) are disconnected; when the gate (G) of an N-type MOSFET receives a high-level signal, its drain and source (D) are connected.

[0046] In some embodiments of the present invention, in order to ensure that the first MOSFET 5 is in a defined off state when there is no control signal input, the first interlock circuit further includes a second resistor 8. One end of the second resistor 8 is electrically connected to the gate (G) of the first MOSFET 5, and the other end of the second resistor 8 is electrically connected to the power supply module, such as... Figure 2 As shown, the second resistor 8 is a pull-up resistor. The pull-up resistor is used to make the gate of the first MOSFET 5 connected to a high level, so that the first MOSFET 5 is in the off state when there is no control signal input.

[0047] It should be noted that the second interlock unit 19 includes a second switch 9 and a second interlock circuit. The second interlock circuit is used to receive a second control signal and control the second switch 9 to close or open. The second electrical signal can be input into the signal channel 3 through the closed second switch 9. In specific implementation, the second switch 9 has an output circuit and an input circuit. One end of the output circuit is connected to the signal source 2, and the other end of the output circuit is electrically connected to the signal channel 3. One end of the input circuit is electrically connected to the control unit 1, and the other end of the input circuit is electrically connected to the power supply. As an example, the second switch 9 is a reed relay. By using the second interlock circuit in conjunction with the second switch 9, the second interlock circuit controls the open or closed state of the second switch 9, thereby realizing the disconnection or conduction of the second signal path. The second electrical signal can be input into the signal channel 3 through the closed second switch 9.

[0048] In specific implementation, the second interlock circuit includes a third MOSFET 10, a fourth MOSFET 11, a third resistor 12, and a sixth resistor 21. The gate (G) of the third MOSFET 10 is used to receive the second control signal, the source (S) of the third MOSFET 10 is grounded, the drain (D) of the third MOSFET 10 is electrically connected to the gate (G) of the fourth MOSFET 11, the drain (D) of the fourth MOSFET 11 is electrically connected to the input circuit of the second switch 9, the source (S) of the fourth MOSFET 11 is electrically connected to the drain (D) of the first MOSFET 5, and one end of the third resistor 12 is connected to the fourth MOSFET 10. The gate (G) of transistor 11 is electrically connected, the other end of the third resistor 12 is electrically connected to the power module, one end of the sixth resistor 21 is electrically connected to the drain (D) of the fourth MOSFET 11, and the other end of the sixth resistor 21 is electrically connected to the power module. It should be noted that the third MOSFET 10 is a P-type MOSFET, and the fourth MOSFET 11 is an N-type MOSFET. The second interlock circuit also includes a fourth resistor 13, one end of which is electrically connected to the gate (G) of the third MOSFET 10, and the other end of which is electrically connected to the power module.

[0049] In conjunction with the above embodiments, the interlock switching circuit proposed in this application has the following four operating states in actual operation:

[0050] 1. When the first control signal from control unit 1 is a low-level signal and the second control signal is a high-level signal, the first control signal is input to the gate (G) of the first MOSFET 5, turning on the first MOSFET 5 and grounding the gate (G) of the second MOSFET 6, thus turning off the second MOSFET 6. This ensures that the voltages at the two input ports of the first switch 4 remain consistent, both being the power supply voltage. The first switch 4 uses a reed relay, and the output circuit of the reed relay remains open, preventing the first electrical signal from being input to signal channel 3. The second control signal is input to the gate (G) of the third MOSFET 10, turning off the third MOSFET 10. The third resistor 12 acts as a pull-up resistor, connecting the gate (G) of the fourth MOSFET 11 to a high level, thus turning off the fourth MOSFET 11. When transistor 11 is turned on, one end of the input circuit of the second switch 9 is electrically connected to the power supply, and the other end is grounded through the fourth MOSFET 11 and the first MOSFET 5 in sequence. This creates a potential difference between the two input terminals of the second switch 9. The second switch 9 uses a reed relay. Current flows through the input circuit of the second switch 9, causing the second switch 9 to close. This keeps the output circuit of the second switch 9 in a conducting state, allowing the second electrical signal to be input into the signal channel 3 through the second switch 9. This achieves interlocking between the first interlock circuit and the second interlock circuit. When the first control signal is a low-level signal and the second control signal is a high-level signal, the first electrical signal cannot be input into the signal channel 3, while the second electrical signal can be input into the signal channel 3.

[0051] 2. When the first control signal from control unit 1 is a high-level signal and the second control signal is a low-level signal, the second control signal is input to the gate (G) of the third MOSFET 10, turning on the third MOSFET 10. The gate (G) of the fourth MOSFET 11 is grounded through the conducting third MOSFET 10, causing the fourth MOSFET 11 to turn off. The fifth resistor 20 acts as a pull-up resistor. Under the action of the fifth resistor 20, the voltages at the two input ports of the second switch 9 remain consistent, both being the power supply voltage. This keeps the output circuit of the second switch 9 open, preventing the second electrical signal from being input to signal channel 3. The first control signal is input to the gate (G) of the first MOSFET 5, turning off the first MOSFET 5. The first resistor 7 acts as a pull-up resistor. Under the action of the first resistor 7, the gate (G) of the third MOSFET 10 is grounded through the conducting third MOSFET 10, causing the fourth MOSFET 11 to turn off. The fifth resistor 20 acts as a pull-up resistor, ensuring that the voltages at the two input ports of the second switch 9 are consistent, both being the power supply voltage. This keeps the output circuit of the second switch 9 open, preventing the second electrical signal from being input to signal channel 3. The gate (G) of the second MOSFET 6 is connected to a high level, thus turning on the second MOSFET 6. One end of the input circuit of the first switch 4 is electrically connected to the power supply, and the other end is grounded through the turned-on second MOSFET 6 and the turned-on fourth MOSFET 11 in sequence. This creates a potential difference between the two input terminals of the first switch 4, and the current flows through the input circuit of the first switch 4, causing the first switch 4 to close. This keeps the output circuit of the first switch 4 in a conducting state, allowing the first electrical signal to be input into the signal channel 3 through the first switch 4. This achieves interlocking between the first interlock circuit and the second interlock circuit. When the first control signal is a high-level signal and the second control signal is a low-level signal, the first electrical signal can be input into the signal channel 3, while the second electrical signal cannot be input into the signal channel 3.

[0052] 3. When both the first control signal and the second control signal from control unit 1 are high-level signals, the first control signal is input to the gate (G) of the first MOSFET 5, causing the first MOSFET 5 to turn off. The first resistor 7 acts as a pull-up resistor, causing the gate (G) of the second MOSFET 6 to connect to a high level, thus turning on the second MOSFET 6. The third resistor 12 acts as a pull-up resistor, causing the voltages at the two input ports of the first switch 4 to remain consistent, both being the power supply voltage, thus keeping the output circuit of the first switch 4 open. The second control signal is input to the gate (G) of the third MOSFET 10, causing the third MOSFET 10 to turn off. The third resistor 12 acts as a pull-up resistor, causing the gate (G) of the fourth MOSFET 11 to connect to a high level, thus turning on the fourth MOSFET 11. The first resistor 7 acts as a pull-up resistor, causing the voltages at the two input ports of the second switch 9 to remain consistent, both being the power supply voltage, thus keeping the output circuit of the second switch 9 open. This achieves interlocking between the first interlock circuit and the second interlock circuit. When both the first control signal and the second control signal are high-level signals, neither the first electrical signal nor the second electrical signal can be input to the signal channel 3.

[0053] 4. When both the first control signal and the second control signal from control unit 1 are low-level signals, the first control signal is input to the gate (G) of the first MOSFET 5, turning on the first MOSFET 5. This causes the gate (G) of the second MOSFET 6 to be grounded through the first MOSFET 5, thus turning off the second MOSFET 6. The sixth resistor 21 acts as a pull-up resistor, ensuring that the voltages at the two input ports of the first switch 4 remain consistent, both being the power supply voltage, thus keeping the output circuit of the first switch 4 open. The second control signal is input to the gate (G) of the third MOSFET 10, turning on the third MOSFET 10. This causes the gate (G) of the fourth MOSFET 11 to be grounded, thus turning off the fourth MOSFET 11. The fifth resistor 20 acts as a pull-up resistor, ensuring that the voltages at the two input ports of the second switch 9 remain consistent, both being the power supply voltage, thus keeping the output circuit of the second switch 9 open. This achieves interlocking between the first interlock circuit and the second interlock circuit. When both the first and second control signals are low-level signals, neither the first nor the second electrical signal can be input to the signal channel 3.

[0054] In summary, the interlocking switching circuit provided in this application embodiment can control the connection state of the first electrical signal, the second electrical signal and the signal channel 3 according to the combination state of the first control signal and the second control signal during operation. This ensures that when the first electrical signal is input to the signal channel 3, the second electrical signal remains disconnected from the signal channel 3, or when the second electrical signal is input to the signal channel 3, the first electrical signal remains disconnected from the signal channel 3. This allows for selective input of the first electrical signal and the second electrical signal to the signal channel 3 at the same time, preventing the first electrical signal and the second electrical signal from being input to the signal channel 3 simultaneously.

[0055] In some embodiments of this application, the first interlock unit 18 further includes a first indicator unit 15 electrically connected to the input circuit of the first switch 4. The first indicator unit 15 includes a diode and a current-limiting resistor connected in series. One end of the diode is electrically connected to the power supply, and the other end of the diode is electrically connected to the current-limiting resistor. The end of the current-limiting resistor not connected to the diode is electrically connected to the second MOSFET. When the first switch is in the on state, the first indicator unit can be grounded through the input circuit of the first switch, so that current flows through the diode and the diode lights up. Conversely, when the first switch is in the off state, the first indicator unit cannot be grounded through the input circuit of the first switch, no current flows through the diode, and the diode is in the off state. By setting the first indicator unit, it can indicate whether the first switch is in the on state.

[0056] In some embodiments of this application, the second interlock unit 19 further includes a second indicator unit 14 electrically connected to the second switch 9. Similar to the first indicator unit, the second indicator unit 14 also includes a diode and a current-limiting resistor connected in series. One end of the diode is electrically connected to the power supply, and the other end of the diode is electrically connected to the current-limiting resistor. The end of the current-limiting resistor not connected to the diode is electrically connected to the fourth MOSFET. When the second switch is in the on state, the second indicator unit can be grounded through the input circuit of the second switch, so that current flows through the diode and the diode lights up. Conversely, when the second switch is in the off state, the second indicator unit cannot be grounded through the input circuit of the second switch, no current flows through the diode, and the diode is in the off state. By setting the second indicator unit, it serves to indicate that the second switch is in the on state.

[0057] In some embodiments of this application, the first interlock unit 18 further includes a first transient suppression diode 17, one end of which is electrically connected to the input circuit of the first switch 4, and the other end of which is electrically connected to the power supply. The second interlock unit 19 further includes a second transient suppression diode 16, one end of which is electrically connected to the input circuit of the second switch 9, and the other end of which is electrically connected to the power supply. By setting the first transient suppression diode 17 and the second transient suppression diode 16, the first interlock unit 18 and the second interlock unit 19 can be protected, and the surge pulse generated at the moment the first switch 4 and the second switch 9 are turned on / off can be prevented from damaging the circuit components in the first interlock unit 18 and the second interlock unit 19.

[0058] This application also provides a chip testing circuit, including a signal source 2, a signal channel 3, and a detection element, as well as the aforementioned interlocking switching circuit. The signal source 2 is electrically connected to one end of the signal channel 3 through the interlocking switching circuit, and the other end of the signal channel 3 is electrically connected to the detection element. For example, the detection element can be a probe, which forms an electrical connection with the circuit on the quantum chip. The signal source 2 emits a first electrical signal and a second electrical signal, which can be input to the circuit on the quantum chip through the interlocking switching circuit to detect the quantum chip. By using the interlocking switching circuit proposed in this application, the first electrical signal and the second electrical signal can be switched, avoiding simultaneous input of the first electrical signal and the second electrical signal to the probe, thereby effectively preventing the two input signals of the probe from interfering with each other and ensuring the accuracy of the quantum chip test results.

[0059] This application also provides an electrical signal interlocking method for inputting a first electrical signal or a second electrical signal into signal channel 3, wherein the interlocking method includes the following steps:

[0060] Control unit 1 provides a first control signal and a second control signal. Both the first and second control signals have two states. The first and second control signals are combined to form a combined control signal. For example, the combined control signal can be one of the following combinations: the first control signal is a high-level signal and the second control signal is a low-level signal; the first control signal is a low-level signal and the second control signal is a high-level signal; both the first and second control signals are low-level signals; and both the first and second control signals are high-level signals.

[0061] The first interlock unit 18 receives the first control signal and the second interlock unit 19 receives the second control signal. The first interlock unit 18 and the second interlock unit 19 perform the first action or the second action according to the state of the first control signal and the second control signal.

[0062] The first action includes preventing the transmission of the first electrical signal to the signal channel 3 via the first interlock unit 18 and preventing the transmission of the second electrical signal to the signal channel 3 via the second interlock unit 19. Specifically, by disconnecting the first signal path of the first interlock unit 18 and the second signal path of the second interlock unit 19, the input of electrical signals to the signal channel 3 is stopped, so that neither the first nor the second electrical signal can be transmitted to the signal channel 3.

[0063] The second action includes opening one of the first interlock unit 18 and the second interlock unit 19 and closing the other, thereby correspondingly inputting an electrical signal to the signal channel 3 from the opened interlock unit.

[0064] The electrical signal interlocking method provided in this embodiment can enable the first electrical signal and the second electrical signal to be selectively input into the signal channel 3 at the same time, avoiding the first electrical signal and the second electrical signal from being input into the signal channel 3 at the same time. Its implementation principle is the same as that in the above embodiment, and will not be described in detail in this embodiment.

[0065] The above description, based on the embodiments shown in the drawings, details the structure, features, and effects of this application. The above description is only a preferred embodiment of this application, but this application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of this application, or modifications to equivalent embodiments, that do not exceed the spirit covered by the specification and drawings, should be within the protection scope of this application.

Claims

1. An interlocking switching circuit for inputting a first electrical signal or a second electrical signal into a signal channel (3), characterized in that, The interlock switching circuit includes: A control unit (1) provides a first control signal and a second control signal, both of which have two states: high level and low level; and A first interlock unit (18) receives a first control signal and controls the first electrical signal to be input into the signal channel (3), and a second interlock unit (19) receives a second control signal and controls the second electrical signal to be input into the signal channel (3). The first interlock unit (18) and the second interlock unit (19) perform a first action or a second action according to the state of the first control signal and the second control signal. The first action includes disconnecting the electrical signal transmission from the first interlock unit (18) and the second interlock unit (19) to the signal channel (3); The second action includes opening one of the first interlock unit (18) and the second interlock unit (19) and closing the other, thereby correspondingly inputting an electrical signal to the signal channel (3) from the opened interlock unit; When the first control signal and the second control signal are both low-level signals or high-level signals, neither the first electrical signal nor the second electrical signal can be input into the signal channel (3). When the first control signal is a low-level signal and the second control signal is a high-level signal, the first electrical signal cannot be input into the signal channel (3), and the second electrical signal can be input into the signal channel (3). When the first control signal is a high-level signal and the second control signal is a low-level signal, the first electrical signal can be input into the signal channel (3), and the second electrical signal cannot be input into the signal channel (3).

2. The interlocking switching circuit as described in claim 1, characterized in that, The first interlock unit (18) includes a first switch (4) and a first interlock circuit. The first interlock circuit is used to receive a first control signal and control the first switch (4) to close or open. The first electrical signal can be input into the signal channel (3) through the closed first switch (4).

3. The interlocking switching circuit as described in claim 2, characterized in that, The first interlock circuit includes a first MOSFET (5), a second MOSFET (6), a first resistor (7), and a fifth resistor (20). The gate (G) of the first MOSFET (5) is used to receive the first control signal. The source (S) of the first MOSFET (5) is grounded. The drain (D) of the first MOSFET (5) is electrically connected to the gate (G) of the second MOSFET (6). The drain (D) of the second MOSFET (6) is electrically connected to the input circuit of the first switch (4). The source (S) of the second MOSFET (6) is electrically connected to the second interlock unit (19). One end of the first resistor (7) is electrically connected to the gate (G) of the second MOSFET (6). The other end of the first resistor (7) is electrically connected to the power module. One end of the fifth resistor (20) is electrically connected to the drain (D) of the second MOSFET (6). The other end of the fifth resistor (20) is electrically connected to the power module.

4. The interlocking switching circuit as described in claim 3, characterized in that, The first interlock circuit also includes a second resistor (8), one end of which is electrically connected to the gate of the first MOS transistor (5), and the other end of which is electrically connected to the power module.

5. The interlocking switching circuit as described in claim 4, characterized in that, The second interlock unit (19) includes a second switch (9) and a second interlock circuit. The second interlock circuit is used to receive a second control signal and control the second switch (9) to close or open. The second electrical signal can be input into the signal channel (3) through the second switch (9) in the closed state.

6. The interlocking switching circuit as described in claim 5, characterized in that, The first interlock unit (18) further includes a first indicator unit (15) electrically connected to the first switch (4), and the second interlock unit (19) further includes a second indicator unit (14) electrically connected to the second switch (9).

7. The interlocking switching circuit as described in claim 5, characterized in that, The second interlock circuit includes a third MOSFET (10), a fourth MOSFET (11), a third resistor (12), and a sixth resistor (21). The gate (G) of the third MOSFET (10) is used to receive the second control signal. The source (S) of the third MOSFET (10) is grounded. The drain (D) of the third MOSFET (10) is electrically connected to the gate (G) of the fourth MOSFET (11). The drain (D) of the fourth MOSFET (11) is electrically connected to the input circuit of the second switch (9). The source (S) of the fourth MOSFET (11) is electrically connected to the drain (D) of the first MOSFET (5). One end of the third resistor (12) is electrically connected to the gate (G) of the fourth MOSFET (11). The other end of the third resistor (12) is electrically connected to the power module. One end of the sixth resistor (21) is electrically connected to the drain (D) of the fourth MOSFET (11). The other end of the sixth resistor (21) is electrically connected to the power module.

8. The interlocking switching circuit as described in claim 7, characterized in that, The second interlock circuit also includes a fourth resistor 13, one end of which is electrically connected to the gate of the third MOS transistor (10), and the other end of which is electrically connected to the power module.

9. A chip testing circuit, characterized in that, Includes the interlocking switching circuit as described in any one of claims 1-8.

10. An electrical signal interlocking method for inputting a first electrical signal or a second electrical signal into a signal channel (3), characterized in that, The interlocking method includes the following steps: The control unit (1) provides a first control signal and a second control signal, both of which have two states: high level and low level. The first interlock unit (18) receives the first control signal and the second interlock unit (19) receives the second control signal. The first interlock unit (18) and the second interlock unit (19) perform the first action or the second action according to the state of the first control signal and the second control signal. The first action includes preventing the transmission of the first electrical signal to the signal channel (3) via the first interlock unit (18) and preventing the transmission of the second electrical signal to the signal channel (3) via the second interlock unit (19); The second action includes opening one of the first interlock unit (18) and the second interlock unit (19) and closing the other, thereby correspondingly inputting an electrical signal to the signal channel (3) from the opened interlock unit; When the first control signal and the second control signal are both low-level signals or high-level signals, neither the first electrical signal nor the second electrical signal can be input into the signal channel (3). When the first control signal is a low-level signal and the second control signal is a high-level signal, the first electrical signal cannot be input into the signal channel (3), and the second electrical signal can be input into the signal channel (3). When the first control signal is a high-level signal and the second control signal is a low-level signal, the first electrical signal can be input into the signal channel (3), and the second electrical signal cannot be input into the signal channel (3).

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