Power device and method of forming the same

Abstract

The present invention provides a power device and a method for forming the same. A first dielectric layer is partially etched to form at least one fin structure between adjacent first electrode layers. A second dielectric layer is formed by a second plasma enhanced chemical vapor deposition process. The second dielectric layer covers the inner surface of a second groove and extends to cover the fin structure and the surface of the remaining first dielectric layer. The breakdown voltage of the second dielectric layer is greater than the breakdown voltage of the first dielectric layer, and the voltage resistance between adjacent first electrode layers can be improved. A third dielectric layer is formed by a third plasma enhanced chemical vapor deposition process, so that the third dielectric layer has good step coverage and filling properties, thereby achieving non-void filling. Moreover, since the breakdown voltage of the second dielectric layer is greater than the breakdown voltage of the first dielectric layer, the voltage resistance between adjacent interconnect plugs can be improved, thereby improving the voltage resistance between adjacent interconnect plugs.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power device and a method for forming the same. Background Art

[0002] Power devices often need to operate in high-temperature environments, such as electronic control systems near automobile engines, industrial motor drive systems, power transmission and distribution systems, etc. In these environments, the temperature may exceed the rated operating temperature of conventional semiconductor devices. Therefore, power devices are required to withstand and stably operate under such high temperature conditions. In addition, power devices often need to handle high voltages during power conversion, transmission and distribution. These high voltages may exceed the rated voltage of conventional semiconductor devices, so higher requirements are placed on the voltage resistance of power devices.

[0003] In power devices, especially in the preparation process of multilayer metal interconnection structures in planar power devices, the upper electrode layer in the metal interconnection structure is interconnected with the lower electrode layer through an interconnection plug, and the upper electrode layer and the lower electrode layer and the adjacent interconnection plugs are isolated by a dielectric layer. However, during the operation of the power device, the dielectric layer between the interconnection plugs needs to withstand an extremely high potential difference, and there is a risk of breakdown due to a large voltage, which may cause device failure. In order to address this problem, the current solution includes lengthening the physical spacing between adjacent interconnection plugs to increase the withstand voltage level, but this will waste device area and is not conducive to device integration. Another method is to improve the quality of the dielectric layer to enhance its breakdown field strength, but the dielectric layer with a high breakdown field strength usually needs to be grown at a high temperature and the growth rate is slow. Although increasing the growth temperature helps to improve the quality of the dielectric layer, due to thermal budget considerations, high-temperature processes are usually not used in the back-end process of the metal interconnection structure because it may affect the reliability of the front-end process. Although lowering the dielectric layer growth temperature can avoid the problem of thermal budget, it will lead to incomplete gas reaction and introduce more impurities, which is not conducive to improving the breakdown voltage. Methods such as increasing or decreasing the growth rate of the dielectric layer will also have an impact. For example, the former is not conducive to improving equipment utilization, while the latter may cause conformality problems and hole defects. Summary of the invention

[0004] The object of the present invention is to provide a power device and a method for forming the same, so as to improve the voltage resistance of a dielectric layer between adjacent interconnect plugs and avoid hole defects in the dielectric layer.

[0005] To achieve the above object, the present invention provides a method for forming a power device, comprising:

[0006] Providing a semiconductor substrate, on which at least two first electrode layers spaced apart are formed, and a first groove is provided between two adjacent first electrode layers;

[0007] forming a first dielectric layer by a first plasma enhanced chemical vapor deposition process, wherein the first dielectric layer fills the first groove and extends to cover all the first electrode layers, and the reaction gas of the first plasma enhanced chemical vapor deposition process includes tetraethyl orthosilicate;

[0008] Partially etching the first dielectric layer to form at least one fin-shaped structure between adjacent first electrode layers, wherein the first dielectric layer on both sides of the fin-shaped structure has second grooves;

[0009] forming a second dielectric layer by a second plasma enhanced chemical vapor deposition process, wherein the second dielectric layer covers the inner surface of the second groove and extends to cover the surface of the fin structure and the remaining surface of the first dielectric layer, and the breakdown voltage of the second dielectric layer is greater than the breakdown voltage of the first dielectric layer, wherein the reaction gas of the second plasma enhanced chemical vapor deposition process includes silane;

[0010] forming a third dielectric layer by a third plasma enhanced chemical vapor deposition process, wherein the third dielectric layer fills the second groove and covers the second dielectric layer on the first electrode layer, wherein the reaction gas of the third plasma enhanced chemical vapor deposition process includes the tetraethyl orthosilicate;

[0011] An interconnection plug is formed on each of the first electrode layers. The interconnection plug penetrates the third dielectric layer, the second dielectric layer and the first dielectric layer on the first electrode layer and is electrically connected to the first electrode layer.

[0012] Optionally, in the method for forming a power device, a method for etching a portion of the thickness of the first dielectric layer includes:

[0013] forming a patterned photoresist layer on the first dielectric layer, wherein the patterned photoresist layer covers a portion of the first dielectric layer between adjacent first electrode layers and exposes the first dielectric layer on the first electrode layer and a portion of the first dielectric layer between adjacent first electrode layers;

[0014] Using the patterned photoresist layer as a mask, a dry etching process is used to partially etch the first dielectric layer between adjacent first electrode layers to form the fin structure and the second groove, and partially etch the first dielectric layer on the first electrode layer to make the top surface of the first dielectric layer on the first electrode layer lower than the top surface of the fin structure; and,

[0015] The patterned photoresist layer is removed.

[0016] Optionally, in the method for forming a power device, a breakdown voltage of the second dielectric layer is greater than a breakdown voltage of the third dielectric layer.

[0017] Optionally, in the method for forming a power device, the first dielectric layer and the third dielectric layer are both made of silicon oxide.

[0018] Optionally, in the method for forming a power device, the reaction gases of the first plasma enhanced chemical vapor deposition process and the third plasma enhanced chemical vapor deposition process also include oxygen, ozone or nitrous oxide.

[0019] Optionally, in the method for forming the power device, the material of the second dielectric layer is silicon oxide, and the reaction gas of the second plasma enhanced chemical vapor deposition process also includes oxygen and argon; or, the material of the second dielectric layer is silicon nitride, and the reaction gas of the second plasma enhanced chemical vapor deposition process also includes ammonia and argon.

[0020] Optionally, in the method for forming a power device, deposition temperatures of the third dielectric layer and the second dielectric layer are both equal to deposition temperature of the first dielectric layer.

[0021] Optionally, in the method for forming a power device, after forming the third dielectric layer and before forming the interconnect plug, the method for forming a power device further includes:

[0022] forming a fourth dielectric layer by a fourth plasma enhanced chemical vapor deposition process, wherein the fourth dielectric layer covers the top surface of the fin structure and the third dielectric layer, the reaction gas of the fourth plasma enhanced chemical vapor deposition process includes silane, and the interconnect plug also penetrates the fourth dielectric layer;

[0023] After the interconnection plugs are formed, a second electrode layer is formed on each of the interconnection plugs, the second electrode layer being electrically connected to the interconnection plugs.

[0024] Optionally, in the method for forming the power device, the top surface of the third dielectric layer is flush with the top surface of the fin structure, and the method for forming the third dielectric layer includes:

[0025] forming a third dielectric material layer by using the third plasma enhanced chemical vapor deposition process, wherein the third dielectric material layer fills the second trench and covers the second dielectric layer and the fin structure, and a top surface of the third dielectric material layer is higher than a top surface of the fin structure; and

[0026] The third dielectric material layer is subjected to chemical mechanical polishing until a top surface of the second dielectric layer above a top surface of the fin structure is exposed to form the third dielectric layer.

[0027] Based on the same inventive concept, the present invention also provides a power device, comprising:

[0028] A semiconductor substrate, on which at least two first electrode layers spaced apart are formed, and a first groove is provided between two adjacent first electrode layers;

[0029] a first dielectric layer, wherein the first dielectric layer covers an inner surface of the first groove and a first electrode layer;

[0030] at least one fin-shaped structure, formed on the first dielectric layer between adjacent first electrode layers, the first dielectric layer on both sides of the fin-shaped structure having second grooves;

[0031] a second dielectric layer, the second dielectric layer covering an inner surface of the second trench and extending to cover the fin-shaped structure and a surface of the first dielectric layer, the breakdown voltage of the second dielectric layer being greater than the breakdown voltage of the first dielectric layer;

[0032] a third dielectric layer, the third dielectric layer filling the second groove and covering the second dielectric layer on the first electrode layer; and

[0033] An interconnection plug is formed on each of the first electrode layers, wherein the interconnection plug penetrates the third dielectric layer and the first dielectric layer and is electrically connected to the first electrode layer.

[0034] In the method for forming a power device provided by the present invention, a first dielectric layer is first formed by a first plasma enhanced chemical vapor deposition process, and the reaction gas of the first plasma enhanced chemical vapor deposition process includes tetraethyl orthosilicate. Since tetraethyl orthosilicate is a silicon organic compound, it can be used to achieve the formation of low-temperature silicon oxide, and has the advantages of low deposition temperature and good step coverage. In this way, the occurrence of hole defects in the first dielectric layer can be avoided; then, the first dielectric layer is partially etched to form at least one fin structure between adjacent first electrode layers; a second dielectric layer is formed by a second plasma enhanced chemical vapor deposition process, and the second dielectric layer covers the inner surface of the second groove and extends to cover the fin structure and the surface of the remaining first dielectric layer. , the reaction gas of the second plasma enhanced chemical vapor deposition process includes silane, the breakdown voltage of the second dielectric layer is greater than the breakdown voltage of the first dielectric layer, the voltage resistance between adjacent first electrode layers can be improved, thereby improving the breakdown voltage between adjacent first electrode layers; and, since the second dielectric layer only covers the inner surface of the second groove and extends to the surface of the fin structure and the surface of the remaining first dielectric layer, rather than filling the second groove, the second dielectric layer can be prevented from having hole defects; then, a third dielectric layer is formed by a third plasma enhanced chemical vapor deposition process, the third dielectric layer fills the second groove and covers the second dielectric layer on the first electrode layer, wherein the reaction gas of the third plasma enhanced chemical vapor deposition process includes ethyl orthosilicate. In this way, the third dielectric layer has good step coverage filling property, thereby achieving hole-free filling, thereby avoiding the occurrence of hole defects in the third dielectric layer. Next, an interconnect plug is formed on each first electrode layer, the interconnect plug passes through the third dielectric layer, the second dielectric layer and the first dielectric layer and is electrically connected to the first electrode layer. Since a fin structure is formed between adjacent interconnect plugs and a second dielectric layer is formed on the surface of the fin structure, the breakdown voltage of the second dielectric layer is greater than the breakdown voltage of the first dielectric layer, and the reaction gas of the second plasma enhanced chemical vapor deposition process for forming the second dielectric layer includes silane, the second dielectric layer has high voltage resistance, thereby improving the voltage resistance between adjacent interconnect plugs, thereby improving the breakdown voltage between adjacent interconnect plugs. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a schematic flow chart of a method for forming a power device according to an embodiment of the present invention;

[0036] Figures 2 to 11 is a schematic cross-sectional view of a structure formed in a method for forming a power device according to an embodiment of the present invention;

[0037] The reference numerals are as follows:

[0038] 100-semiconductor substrate; 101-first electrode layer; 101a-first trench; 102-first dielectric layer; 102a-second trench; 103-fin structure; 104-second dielectric layer; 105-third dielectric material layer; 105a-third dielectric layer; 106-fourth dielectric layer; 107-interconnect plug; 108-second electrode layer; 110-insulating layer; 120-patterned photoresist layer. DETAILED DESCRIPTION

[0039] The power device and the method for forming the power device of the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are in a very simplified form and are not in precise proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0040] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is generally used to include the meaning of "and / or", the term "several" is generally used to include the meaning of "at least one", and the term "at least two" is generally used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features.

[0041] Figure 1 FIG. 1 is a flow chart of a method for forming a power device provided by an embodiment of the present invention. Figure 1 As shown, this embodiment provides a method for forming a power device, including:

[0042] Step S1: providing a semiconductor substrate, on which at least two first electrode layers spaced apart are formed, and a first groove is provided between two adjacent first electrode layers;

[0043] Step S2: forming a first dielectric layer by a first plasma enhanced chemical vapor deposition process, wherein the first dielectric layer fills the first groove and extends to cover all the first electrode layers, and the reaction gas of the first plasma enhanced chemical vapor deposition process includes tetraethyl orthosilicate;

[0044] Step S3: etching a portion of the thickness of the first dielectric layer to form at least one fin-shaped structure between adjacent first electrode layers, wherein the first dielectric layer on both sides of the fin-shaped structure has second grooves;

[0045] Step S4: forming a second dielectric layer by a second plasma enhanced chemical vapor deposition process, wherein the second dielectric layer covers the inner surface of the second groove and extends to cover the surface of the fin structure and the surface of the remaining first dielectric layer, and the breakdown voltage of the second dielectric layer is greater than the breakdown voltage of the first dielectric layer, wherein the reaction gas of the second plasma enhanced chemical vapor deposition process includes silane;

[0046] Step S5: forming a third dielectric layer by a third plasma enhanced chemical vapor deposition process, wherein the third dielectric layer fills the second groove and covers the second dielectric layer on the first electrode layer, wherein the reaction gas of the third plasma enhanced chemical vapor deposition process includes the tetraethyl orthosilicate; and

[0047] Step S6: forming an interconnection plug on each of the first electrode layers, wherein the interconnection plug penetrates the third dielectric layer, the second dielectric layer and the first dielectric layer on the first electrode layer and is electrically connected to the first electrode layer.

[0048] Figures 2 to 11 FIG. 1 is a schematic diagram of a cross-sectional structure formed in a method for forming a power device according to an embodiment of the present invention. Figures 2 to 11 The method for forming the power device provided in this embodiment is described in more detail.

[0049] First, execute step S1, such as Figure 2 As shown, a semiconductor substrate 100 is provided, on which at least two first electrode layers 101 spaced apart are formed, and a first groove 101a is provided between two adjacent first electrode layers 101. The material of the semiconductor substrate 100 includes but is not limited to silicon (Si), gallium nitride (GaN), silicon carbide (SiC), gallium oxide (Ga2O3) or diamond. In this embodiment, the semiconductor substrate is a silicon substrate.

[0050] The material of the first electrode layer 101 may be at least one of titanium (Ti), aluminum (Al), tungsten (W), nickel (Ni), gold (Au), and titanium nitride (TiN).

[0051] Further, such as Figure 2 As shown, an insulating layer 110 can be formed between the semiconductor substrate 100 and the first electrode layer 101 to isolate the semiconductor substrate 100 from the first electrode layer 101. The material of the insulating layer 110 is, for example, silicon oxide, and can be formed by plasma enhanced chemical vapor deposition (PECVD). The reaction gas for forming the insulating layer may include silane (SiH4) and oxygen (O2).

[0052] Next, execute step S2, such as Figure 3 As shown, a first dielectric layer 102 is formed by a first plasma enhanced chemical vapor deposition (PECVD) process, and the first dielectric layer 102 fills the first groove 101a and extends to cover all the first electrode layers 101. The reaction gas of the first plasma enhanced chemical vapor deposition process includes tetraethyl orthosilicate (TEOS). Since tetraethyl orthosilicate is a silicon organic compound, it has the advantages of low deposition temperature and good step coverage. By using tetraethyl orthosilicate as the reaction gas of the first plasma enhanced chemical vapor deposition process, the first dielectric layer 102 can have good step coverage and filling, and can achieve non-hole filling, thereby avoiding the occurrence of hole defects in the first dielectric layer 102.

[0053] Specifically, the material of the first dielectric layer 102 may be silicon oxide (SiO2). Furthermore, the reaction gas of the first plasma enhanced chemical vapor deposition process also includes oxygen (O2), ozone (O3) or nitrous oxide (N2O), and the reaction gas of the first plasma enhanced chemical vapor deposition process may also include argon (Ar) for diluting the content of ethyl orthosilicate, oxygen ozone or nitrous oxide, so as to adjust the deposition rate of the first dielectric layer 102.

[0054] In this embodiment, the thickness of the first dielectric layer 102 may be 1000 nm to 4000 nm, for example, 1000 nm, 2000 nm or 3000 nm.

[0055] like Figure 3 As shown, due to the existence of the first electrode layer 101 , the top surface of the first dielectric layer 102 located above the first electrode layer 101 is higher than the top surface of the first dielectric layer 102 in other areas.

[0056] Next, execute step S3, such as Figure 5 As shown, the first dielectric layer 102 is partially etched to form at least one fin structure 103 between adjacent first electrode layers 101 , and the first dielectric layer 102 on both sides of the fin structure 103 has second grooves 102 a .

[0057] Among them, the number of the fin-like structures 103 can be one, two or three, or more than three. The more the fin-like structures 103 are, the better the voltage resistance between adjacent first electrode layers 101 will be after the second dielectric layer 104 is subsequently formed on the fin structure 103. This embodiment is explained by taking the example of a fin-like structure 103 formed between adjacent first electrode layers 101.

[0058] Specifically, the method of etching a portion of the thickness of the first dielectric layer 102 includes:

[0059] Step 1: If Figure 4 As shown, a patterned photoresist layer 120 is formed on the first dielectric layer 102, and the patterned photoresist layer 120 covers a portion of the first dielectric layer 102 between adjacent first electrode layers 101, and exposes the first dielectric layer 102 on the first electrode layer 101 and a portion of the first dielectric layer 102 between adjacent first electrode layers 101.

[0060] Step 2: If Figure 5 As shown, the patterned photoresist layer 120 is used as a mask, and a dry etching process is used to partially etch the first dielectric layer 102 between the adjacent first electrode layers 101 to form the fin structure 103 and the second groove 102a. The first dielectric layer 102 on the first electrode layer 101 is partially etched to make the top surface of the first dielectric layer 102 on the first electrode layer 101 lower than the top surface of the fin structure 103. That is, the first dielectric layer 102 at the bottom of the fin structure 103 and the first dielectric layer 102 on the first electrode layer 101 are retained, and the remaining first dielectric layer 102 (except the portion of the fin structure 103) can be used as a protective layer to protect the film layer below the first dielectric layer 102 from being etched, thereby avoiding damage during the etching process.

[0061] like Figure 5 As shown, the thickness H1 of the fin structure 103 may be 950 nm to 3800 nm, and the thickness H2 of the remaining first dielectric layer 102 may be 50 nm to 200 nm.

[0062] In this embodiment, the main etching gas used in the dry etching process includes at least one of CF4 (carbon tetrafluoride), CHF3 (carbon trifluoride) and SF6 (sulfur hexafluoride); the auxiliary gas includes N2 (nitrogen), Ar (argon) and He (helium).

[0063] Step three: removing the patterned photoresist layer 120 , wherein the patterned photoresist layer 120 can be removed by a plasma cleaning method or a stripping method.

[0064] Next, execute step S4, such as Figure 6As shown, a second dielectric layer 104 is formed by a second plasma enhanced chemical vapor deposition process, the second dielectric layer 104 covers the inner surface of the second groove 102a and extends to cover the surface of the fin structure 103 and the remaining surface of the first dielectric layer 102, and the breakdown voltage of the second dielectric layer 104 is greater than the breakdown voltage of the first dielectric layer 102, wherein the reaction gas of the second plasma enhanced chemical vapor deposition process includes silane. In this way, the second dielectric layer 104 can have good compactness, and the second dielectric layer 104 has high pressure resistance and breakdown field strength. Since the fin structure 103 and the first dielectric layer are formed by tetraethyl orthosilicate, which is a silicon organic material with many impurities and low breakdown field strength, it is not conducive to the power device working under high temperature and high pressure, so the second dielectric layer 104 with high pressure resistance and high breakdown field strength is formed on the surface of the fin structure 103 and the first dielectric layer to improve the pressure resistance between adjacent first electrode layers 101, thereby improving the breakdown voltage between adjacent first electrode layers 101.

[0065] Since the second dielectric layer 104 only covers the inner surface of the second trench 102a and extends to the surface of the fin structure 103 and the surface of the remaining first dielectric layer 102, rather than filling the second trench 102a, hole defects can be avoided in the second dielectric layer 104. The thickness of the second dielectric layer 104 can be 50nm to 200nm.

[0066] Furthermore, since the second dielectric layer 104 covers the fin structure 103, that is, the second dielectric layer 104 covers the side walls and the top surface of the fin structure 103, there are two layers of the second dielectric layer 104 between adjacent first electrode layers 101, that is, the dielectric layers located on the two side walls of the fin structure 103, one side wall of the fin structure 103 has a layer of the second dielectric layer, and the other side wall of the fin structure 103 also has a layer of the second dielectric layer, and the fin structure 103 is located between adjacent first electrode layers 101, so there are two layers of the second dielectric layer 104 between adjacent first electrode layers 101 (that is, in the lateral direction of the semiconductor substrate 100), and there are two layers of the second dielectric layer on the two side walls of the fin structure 103, which can further improve the voltage resistance between adjacent first electrode layers 101.

[0067] In addition, the number of second dielectric layers 104 between adjacent first electrode layers 101 can be adjusted by designing the number of fin structures (the number of fin structures between adjacent first electrode layers 101), that is, if the number of fin structures 103 is one, the number of second dielectric layers 104 between adjacent first electrode layers 101 is two, and if the number of fin structures 103 is two, the number of second dielectric layers 104 between adjacent first electrode layers 101 is four;

[0068] Preferably, the material of the second dielectric layer 104 is silicon nitride, so that the second dielectric layer 104 can be different from the material of the third dielectric layer 105a formed subsequently, and the dishing phenomenon (dishing) caused in the subsequent chemical mechanical polishing process can be prevented, thereby avoiding the second dielectric layer 104 from being dished in the subsequent chemical mechanical polishing process. The reaction gas of the second plasma enhanced chemical vapor deposition process also includes ammonia, that is, the reaction gas of the second dielectric layer 104 includes silane and ammonia. In the second plasma enhanced chemical vapor deposition process, the deposition temperature is 300°C to 400°C, for example, 300°C, 350°C or 400°C. The gas flow rate of silane is 10sccm to 15sccm, the gas flow rate of ammonia is 200sccm to 450sccm, and the pressure is 1Torr to 4Torr.

[0069] In another embodiment, the material of the second dielectric layer 104 is silicon oxide, and the reaction gas of the second plasma enhanced chemical vapor deposition process further includes argon (Ar) and oxygen (O2), that is, the reaction gas of the second dielectric layer 104 includes silane, argon (Ar) and oxygen (O2), wherein the argon is used to dilute the concentration of silane and oxygen, thereby adjusting the deposition rate of the first dielectric layer 102. In the first plasma enhanced chemical vapor deposition process, the deposition temperature is 300°C to 400°C, such as 300°C, 350°C or 400°C. The gas flow rate of silane can be 10sccm to 15sccm, the gas flow rate of oxygen can be 200sccm to 400sccm, the gas flow rate of argon can be 0sccm to 150sccm, and the pressure can be 1Torr to 4Torr.

[0070] Then, execute step S5, such as Figure 8 As shown, a third dielectric layer 105a is formed by a third plasma enhanced chemical vapor deposition process, and the third dielectric layer 105a fills the second groove 102a and covers the second dielectric layer 104 on the first electrode layer 101, wherein the reaction gas of the third plasma enhanced chemical vapor deposition process includes the ethyl orthosilicate. In this way, the third dielectric layer 105a has good step coverage and filling properties, thereby achieving non-void filling, thereby avoiding the occurrence of void defects in the third dielectric layer 105a, and improving the reliability of the device.

[0071] Specifically, the method for forming the third dielectric layer 105a includes: first, Figure 7As shown, the third dielectric material layer 105 is formed by the third plasma enhanced chemical vapor deposition process, the third dielectric material layer 105 fills the second groove 102a and covers the second dielectric layer 104 and the fin structure 103, and the top surface of the third dielectric material layer is higher than the top surface of the fin structure 103. The thickness of the third dielectric material layer can be 1.5μm to 5μm.

[0072] The material of the third dielectric material layer is silicon oxide. The third plasma enhanced chemical vapor deposition process may further include argon (Ar) and oxygen (O2), wherein the argon is used to dilute the concentration of silane and oxygen, thereby adjusting the deposition rate of the third dielectric layer 105a.

[0073] like Figure 8 As shown, the third dielectric material layer is subjected to chemical mechanical polishing (CMP) until the second dielectric layer above the top surface of the fin structure 103 is exposed, that is, the chemical mechanical polishing of the third dielectric material layer 105 stops at the second dielectric layer 104 above the top surface of the fin structure 103 to form the third dielectric layer 105a. The top surface of the third dielectric layer 105a is flush with the top surface of the second dielectric layer above the top surface of the fin structure 103.

[0074] Then, execute step S6, such as Fig.10 As shown, an interconnection plug 107 is formed on each of the first electrode layers 101, and the interconnection plug 107 penetrates the third dielectric layer 105a, the second dielectric layer 104 and the first dielectric layer 102 on the first electrode layer 101 and is electrically connected to the first electrode layer 101. Since a fin structure 103 is formed between adjacent interconnection plugs 107, and a second dielectric layer 104 is formed on the surface of the fin structure 103, the breakdown voltage of the second dielectric layer 104 is greater than the breakdown voltage of the first dielectric layer 102, and thus has high withstand voltage, so that the withstand voltage between adjacent interconnection plugs 107 can be improved, and then the breakdown voltage between adjacent interconnection plugs 107 can be improved. Furthermore, since the first dielectric layer 102 and the third dielectric layer 105a are both formed by plasma enhanced chemical vapor deposition process and the reaction gas includes tetraethyl orthosilicate, the first dielectric layer 102 and the third dielectric layer 105a have good step coverage and filling properties and have no holes inside, thereby avoiding the occurrence of hole defects in the dielectric layer between adjacent interconnect plugs 107 and improving the reliability of the device.

[0075] Specifically, the method for forming the interconnect plug 107 includes: first, Fig. 9As shown, a fourth dielectric layer 106 is formed by a fourth plasma enhanced chemical vapor deposition process (PECVD), and the fourth dielectric layer 106 covers the top surface of the fin structure 103 and the third dielectric layer 105a. The reaction gas of the fourth plasma enhanced chemical vapor deposition process includes silane. In this way, the formed fourth dielectric layer 106 can have good compactness, so that the fourth dielectric layer 106 can have high pressure resistance and breakdown field strength; then, the fourth dielectric layer 106, the third dielectric layer 105a, the second dielectric layer 104 and the first dielectric layer 102 are etched in sequence by a dry etching process to form interconnection through holes; then, as shown in FIG. Fig.10 As shown, a conductive material is deposited in the interconnection through hole to form an interconnection plug 107. That is, the interconnection plug 107 sequentially penetrates the fourth dielectric layer 106, the third dielectric layer 105a, the second dielectric layer 104 and the first dielectric layer 102 on the first electrode layer 101. The material of the interconnection plug 107 can be tungsten.

[0076] Afterwards, if Fig.11 As shown, a second electrode layer 108 is formed on each interconnect plug 107, and the second electrode layer 108 is electrically connected to the interconnect plug 107. The material of the second electrode layer 108 can be at least one of titanium (Ti), aluminum (Al), tungsten (W), nickel (Ni), gold (Au), and titanium nitride (TiN). The second electrode layer 108 can be formed by a physical vapor deposition process. Among them, two adjacent second electrode layers 108 can be connected to a low voltage electrode and a high voltage electrode respectively.

[0077] like Fig.11 As shown, the second electrode layer 108 is isolated from the first electrode layer 101 by the first dielectric layer 102, the second dielectric layer 104, the third dielectric layer 105a and the fourth dielectric layer. The breakdown voltage of the second dielectric layer 104 is greater than the breakdown voltage of the first dielectric layer 102, and thus has high voltage resistance, thereby improving the voltage resistance between the second electrode layer 108 and the first electrode layer 101, and further improving the breakdown voltage between the second electrode layer 108 and the first electrode layer 101. Further, since the first dielectric layer 102 and the third dielectric layer 105a are both formed by plasma enhanced chemical vapor deposition process and the reaction gas includes ethyl orthosilicate, the first dielectric layer 102 and the third dielectric layer 105a have good step coverage and filling properties and no holes inside, thereby avoiding the occurrence of hole defects in the dielectric layer between the second electrode layer 108 and the first electrode layer 101, and improving the reliability of the device.

[0078] In summary, in the method for forming a power device provided by an embodiment of the present invention, the first dielectric layer is first partially etched to form at least one fin structure between adjacent first electrode layers; a second dielectric layer is formed by a second plasma enhanced chemical vapor deposition process, the second dielectric layer covers the inner surface of the second groove and extends to cover the fin structure and the surface of the remaining first dielectric layer, the breakdown voltage of the second dielectric layer is greater than the breakdown voltage of the first dielectric layer, and the pressure resistance between adjacent first electrode layers can be improved; a third dielectric layer is formed by a third plasma enhanced chemical vapor deposition process, so that the third dielectric layer has good step coverage and filling properties, thereby achieving non-void filling; and because the breakdown voltage of the second dielectric layer is greater than the breakdown voltage of the first dielectric layer, the pressure resistance between adjacent interconnect plugs can be improved, thereby improving the pressure resistance between adjacent interconnect plugs. In addition, the method for forming a power device provided by this embodiment is simple and easy to implement, and is fully compatible with existing traditional processes, without the need to develop new processes or equipment.

[0079] This embodiment also provides a power device, which is prepared by using the above-mentioned method for forming a power device. Fig.11 As shown, the power device comprises: a semiconductor substrate 100, on which at least two first electrode layers 101 spaced apart are formed, and a first groove 101a is provided between two adjacent first electrode layers 101;

[0080] A first dielectric layer 102, wherein the first dielectric layer 102 covers the inner surface of the first groove 101a and the first electrode layer 101;

[0081] at least one fin-shaped structure 103 formed on the first dielectric layer 102 between adjacent first electrode layers 101, and the first dielectric layer 102 on both sides of the fin-shaped structure 103 has second grooves 102a;

[0082] a second dielectric layer 104 , wherein the second dielectric layer 104 covers the inner surface of the second trench 102 a and extends to cover the fin structure 103 and the surface of the first dielectric layer 102 , and the breakdown voltage of the second dielectric layer 104 is greater than the breakdown voltage of the first dielectric layer 102 ;

[0083] a third dielectric layer 105 a , wherein the third dielectric layer 105 a fills the second trench 102 a and covers the second dielectric layer 104 on the first electrode layer 101 , and a top surface of the third dielectric layer 105 a is flush with a top surface of the fin structure 103 ;

[0084] An interconnection plug 107 is formed on each of the first electrode layers 101, and the interconnection plug 107 penetrates the third dielectric layer 105a, the second dielectric layer 104 and the first dielectric layer 102 and is electrically connected to the first electrode layer 101. Since a fin structure 103 is formed between adjacent interconnection plugs 107, and a second dielectric layer 104 is formed on the surface of the fin structure 103, the breakdown voltage of the second dielectric layer 104 is greater than the breakdown voltage of the first dielectric layer 102, and thus has high withstand voltage, thereby improving the withstand voltage between adjacent interconnection plugs 107, and further improving the breakdown voltage between adjacent interconnection plugs 107.

[0085] Continue to refer Fig.11 As shown, the power device further includes a fourth dielectric layer 106 formed on the third dielectric layer 105 a , and the interconnect plug 107 also penetrates the fourth dielectric layer 106 .

[0086] Furthermore, the power device further includes a second electrode layer 108 formed on the interconnection plug 107 , and the second electrode layer 108 is electrically connected to the first electrode layer 101 through the interconnection plug 107 .

[0087] From the above, it can be seen that in the power device provided by the present invention, since a fin structure is formed between adjacent interconnect plugs and a second dielectric layer is formed on the surface of the fin structure, the breakdown voltage of the second dielectric layer is greater than the breakdown voltage of the first dielectric layer, and the reaction gas of the second plasma enhanced chemical vapor deposition process for forming the second dielectric layer includes silane, the second dielectric layer has high voltage resistance, which can improve the voltage resistance between adjacent interconnect plugs, and then improve the breakdown voltage between adjacent interconnect plugs.

[0088] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

[0089] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A method for forming a power device, characterized in that: include: Providing a semiconductor substrate, on which at least two first electrode layers spaced apart are formed, and a first groove is provided between two adjacent first electrode layers; forming a first dielectric layer by a first plasma enhanced chemical vapor deposition process, wherein the first dielectric layer fills the first groove and extends to cover all the first electrode layers, and the reaction gas of the first plasma enhanced chemical vapor deposition process includes tetraethyl orthosilicate; Partially etching the first dielectric layer to form at least one fin-shaped structure between adjacent first electrode layers, wherein the first dielectric layer on both sides of the fin-shaped structure has second grooves; forming a second dielectric layer by a second plasma enhanced chemical vapor deposition process, wherein the second dielectric layer covers the inner surface of the second groove and extends to cover the surface of the fin structure and the remaining surface of the first dielectric layer, and the breakdown voltage of the second dielectric layer is greater than the breakdown voltage of the first dielectric layer, wherein the reaction gas of the second plasma enhanced chemical vapor deposition process includes silane; forming a third dielectric layer by a third plasma enhanced chemical vapor deposition process, wherein the third dielectric layer fills the second groove and covers the second dielectric layer on the first electrode layer, wherein the reaction gas of the third plasma enhanced chemical vapor deposition process includes the tetraethyl orthosilicate; An interconnection plug is formed on each of the first electrode layers. The interconnection plug penetrates the third dielectric layer, the second dielectric layer and the first dielectric layer on the first electrode layer and is electrically connected to the first electrode layer.

2. The method for forming a power device according to claim 1, wherein: The method of etching a portion of the thickness of the first dielectric layer includes: forming a patterned photoresist layer on the first dielectric layer, wherein the patterned photoresist layer covers a portion of the first dielectric layer between adjacent first electrode layers and exposes the first dielectric layer on the first electrode layer and a portion of the first dielectric layer between adjacent first electrode layers; Using the patterned photoresist layer as a mask, a dry etching process is used to partially etch the first dielectric layer between adjacent first electrode layers to form the fin structure and the second groove, and partially etch the first dielectric layer on the first electrode layer to make the top surface of the first dielectric layer on the first electrode layer lower than the top surface of the fin structure; and, The patterned photoresist layer is removed.

3. The method for forming a power device according to claim 1, wherein: The breakdown voltage of the second dielectric layer is greater than the breakdown voltage of the third dielectric layer.

4. The method for forming a power device according to claim 1, wherein: The first dielectric layer and the third dielectric layer are both made of silicon oxide.

5. The method for forming a power device according to claim 4, wherein: The reaction gases of the first plasma enhanced chemical vapor deposition process and the third plasma enhanced chemical vapor deposition process both further include oxygen, ozone or nitrous oxide.

6. The method for forming a power device according to claim 1, wherein: The material of the second dielectric layer is silicon oxide, and the reaction gas of the second plasma enhanced chemical vapor deposition process also includes oxygen and argon; or, the material of the second dielectric layer is silicon nitride, and the reaction gas of the second plasma enhanced chemical vapor deposition process also includes ammonia and argon.

7. The method for forming a power device according to claim 1, wherein: The deposition temperatures of the third dielectric layer and the second dielectric layer are both equal to the deposition temperature of the first dielectric layer.

8. The method for forming a power device according to claim 1, wherein: After forming the third dielectric layer and before forming the interconnect plug, the method for forming the power device further includes: forming a fourth dielectric layer by a fourth plasma enhanced chemical vapor deposition process, wherein the fourth dielectric layer covers the top surface of the fin structure and the third dielectric layer, the reaction gas of the fourth plasma enhanced chemical vapor deposition process includes silane, and the interconnect plug also penetrates the fourth dielectric layer; After the interconnection plugs are formed, a second electrode layer is formed on each of the interconnection plugs, the second electrode layer being electrically connected to the interconnection plugs.

9. The method for forming a power device according to claim 1, wherein: The top surface of the third dielectric layer is flush with the top surface of the fin structure, and the method for forming the third dielectric layer includes: forming a third dielectric material layer by using the third plasma enhanced chemical vapor deposition process, wherein the third dielectric material layer fills the second trench and covers the second dielectric layer and the fin structure, and a top surface of the third dielectric material layer is higher than a top surface of the fin structure; and The third dielectric material layer is subjected to chemical mechanical polishing until a top surface of the second dielectric layer above a top surface of the fin structure is exposed to form the third dielectric layer.

10. A power device, characterized in that: include: A semiconductor substrate, on which at least two first electrode layers spaced apart are formed, and a first groove is provided between two adjacent first electrode layers; a first dielectric layer, wherein the first dielectric layer covers an inner surface of the first groove and a first electrode layer; at least one fin-shaped structure, formed on the first dielectric layer between adjacent first electrode layers, the first dielectric layer on both sides of the fin-shaped structure having second grooves; a second dielectric layer, the second dielectric layer covering an inner surface of the second trench and extending to cover the fin-shaped structure and a surface of the first dielectric layer, the breakdown voltage of the second dielectric layer being greater than the breakdown voltage of the first dielectric layer; a third dielectric layer, wherein the third dielectric layer fills the second groove and covers the second dielectric layer on the first electrode layer; as well as, An interconnection plug is formed on each of the first electrode layers, wherein the interconnection plug penetrates the third dielectric layer, the second dielectric layer and the first dielectric layer and is electrically connected to the first electrode layer.

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