FinFET device formation method

Abstract

The present invention provides a method for forming a FinFET device, comprising: S1: dividing a substrate into an NMOS region and a PMOS region with intervals; S2: forming a plurality of gates, a plurality of hard mask layers and a dielectric layer on the substrate, wherein the plurality of gates are spaced apart, the plurality of hard mask layers are respectively located on the surface of the gates, and the dielectric layer covers a portion of the substrate, the surface of the hard mask layer, the side wall of the hard mask layer and the side wall of the gate; S3: etching a portion of the substrate between the gates of the PMOS region to form a fin groove in the substrate between the gates of the PMOS region; S4: using ozone to oxidize the side wall of the fin groove to form an oxide layer; S5: using hydrofluoric acid to remove the oxide layer to increase the width and depth of the fin groove; S6: cycling S4 and S5 for several times to form a fin groove of target width and depth; S7: forming a fin in the fin groove.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a FinFET device. Background Art

[0002] In the advanced complementary metal oxide semiconductor (CMOS) industry, with the arrival of 22 nm and smaller sizes, Fin Field-effect transistors (FinFETs) are widely used to improve short channel effects and enhance device performance.

[0003] Please refer to Figure 1 , FinFET includes: a substrate, a shallow trench isolation structure 130 located in the substrate, the shallow trench isolation structure 130 divides the substrate into an NMOS region 110 and a PMOS region 120, a plurality of gates 140 are formed on the substrate of the NMOS region 110 and the PMOS region 120, a hard mask layer 150 is formed on the upper surface of the gate 140, and a dielectric layer 160 is formed on the sidewall of the gate 140. Fins 180 are also formed in the substrate between the gates 140 in the PMOS region 120. In the prior art, the method for forming the fins 180 is to etch the substrate, form a fin trench in the substrate, and fill the fin trench with gate polysilicon to form the fins 180. The etching depth of the fin trench and the lateral distance from the edge of the fin 180 to the gate are important parameters that affect the electrical performance of the FinFET device. Too deep or too shallow a depth, and too large or too small a lateral distance will reduce the device performance.

[0004] However, in the prior art, it is difficult to simultaneously control the depth and lateral distance of the fin grooves in the fin groove process, and it is difficult to find the critical point of lateral etching and longitudinal etching. In addition, in the prior art, the fin grooves are etched using dry etching. Due to the process characteristics of dry etching, it is difficult to achieve consistent lateral etching amounts at different depths of the fin grooves. Summary of the invention

[0005] The object of the present invention is to provide a method for forming a FinFET device, which can achieve precise control of the etching depth and etching width of the fin groove, so that the depth and width of the fin groove can meet the standards at the same time, and finally the height of the fin and the lateral distance from the fin to the gate can meet the standards at the same time.

[0006] In order to achieve the above object, the present invention provides a method for forming a FinFET device, comprising:

[0007] Step S1: providing a substrate, and dividing the substrate into an NMOS region and a PMOS region separated from each other;

[0008] Step S2: forming a plurality of gates, a plurality of hard mask layers and a dielectric layer on the substrates of the NMOS region and the PMOS region, wherein the plurality of gates are spaced apart, the plurality of hard mask layers are respectively located on the surfaces of the gates, and the dielectric layer covers a portion of the substrate of the NMOS region, a portion of the substrate of the PMOS region, the surface of the hard mask layer, the sidewalls of the hard mask layer and the sidewalls of the gates;

[0009] Step S3: etching a portion of the substrate between the gates of the PMOS region to form a fin trench in the substrate between the gates of the PMOS region;

[0010] Step S4: using ozone to oxidize the sidewalls of the fin groove to form an oxide layer;

[0011] Step S5: using hydrofluoric acid to remove the oxide layer, so that the width and depth of the fin groove are increased;

[0012] Step S6: looping step S4 and step S5 for several times to form a fin groove with a target width and a target depth;

[0013] Step S7: forming fins in the fin grooves.

[0014] Optionally, in the method for forming the FinFET device, the material of the substrate includes silicon.

[0015] Optionally, in the method for forming the FinFET device, step S1 further includes: forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure divides the substrate into an NMOS region and a PMOS region.

[0016] Optionally, in the method for forming the FinFET device, in step S3, a portion of the substrate between the gates of the PMOS region is dry-etched to form a fin trench in the substrate between the gates of the PMOS region.

[0017] Optionally, in the method for forming the FinFET device, a method for etching a portion of the substrate between the gates of the PMOS region to form a fin trench in the substrate between the gates of the PMOS region includes:

[0018] Using a photoresist layer to cover the dielectric layer of the NMOS region;

[0019] Etching the dielectric layer above the hard mask layer in the PMOS region, the dielectric layer on the substrate surface between the gates, and a portion of the substrate;

[0020] The photoresist layer is removed.

[0021] Optionally, in the method for forming the FinFET device, the etching depth is calculated based on the target depth of the fin etching, the thickness of the dielectric layer, and the lateral distance between the fin and the gate.

[0022] Optionally, in the method for forming the FinFET device, etching depth=target depth of fin etching-(thickness of dielectric layer-lateral distance between fin and gate).

[0023] Optionally, in the method for forming the FinFET device, the number of cycles of oxidizing the fin trench sidewalls and removing the oxide layer is calculated based on the thickness of the dielectric layer, the lateral distance between the fin and the gate, and the thickness of silicon lost by oxidizing the fin trench sidewalls once.

[0024] Optionally, in the method for forming the FinFET device, the number of cycles = (thickness of the dielectric layer - lateral distance between the fin and the gate) / thickness of silicon lost on the sidewall of the fin trench by oxidation once.

[0025] Optionally, in the method for forming the FinFET device, the thickness of silicon lost by oxidizing the sidewalls of the fin trench once is 0.5 nm to 0.75 nm.

[0026] The method for forming a FinFET device provided by the present invention includes: step S1: providing a substrate, dividing the substrate into an NMOS region and a PMOS region with intervals; step S2: forming a plurality of gates, a plurality of hard mask layers and a dielectric layer on the substrates of the NMOS region and the PMOS region, wherein the plurality of gates are spaced apart, the plurality of hard mask layers are respectively located on the surface of the gates, and the dielectric layer covers a portion of the substrate of the NMOS region, a portion of the substrate of the PMOS region, the surface of the hard mask layer, the sidewall of the hard mask layer and the sidewall of the gate; step S3: etching a portion of the substrate between the gates of the PMOS region to form a fin groove in the substrate between the gates of the PMOS region; step S4: oxidizing the sidewalls of the fin groove using ozone to form an oxide layer; step S5: removing the oxide layer using hydrofluoric acid to increase the width and depth of the fin groove; step S6: looping steps S4 and S5 for several times to form a fin groove of a target width and a target depth; step S7: forming a fin in the fin groove. The present invention realizes precise control of the etching depth and etching width of the fin groove, so that the depth and width of the fin groove both meet the standards at the same time, and finally the height of the fin and the lateral distance from the fin to the gate meet the standards at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the structure of a FinFET device in the prior art;

[0028] Figure 2 is a flow chart of a method for forming a FinFET device according to an embodiment of the present invention;

[0029] Figure 3 is a schematic structural diagram of a FinFET device after a dielectric layer is formed according to an embodiment of the present invention;

[0030] Figure 4 is a schematic diagram of the structure after etching the fin grooves in an embodiment of the present invention;

[0031] Figure 5 is a schematic diagram of the structure after the sidewalls of the fin grooves are oxidized according to an embodiment of the present invention;

[0032] Figure 6 is a schematic diagram of a structure of forming fins according to an embodiment of the present invention;

[0033] In the figure: 110-NMOS region, 120-PMOS region, 130-shallow trench isolation structure, 140-gate, 150-hard mask layer, 160-dielectric layer, 180-fin, 210-NMOS region, 220-PMOS region, 230-shallow trench isolation structure, 240-gate, 250-hard mask layer, 260-dielectric layer, 270-photoresist layer, 280-fin trench, 290-oxide layer, 300-fin, 310-protective layer. DETAILED DESCRIPTION

[0034] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0035] Hereinafter, the terms "first", "second", etc. are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if the method described herein includes a series of steps, the order of these steps presented herein is not necessarily the only order in which these steps can be performed, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method.

[0036] Furthermore, it should be understood that when a layer (or film), region, pattern or structure is referred to as being "on" a substrate, layer (or film), region and / or pattern, it can be directly on another layer or substrate, and / or there can be intervening layers. In addition, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or there can be one or more intervening layers. In addition, references to being "on" and "under" each layer can be made based on the accompanying drawings.

[0037] Please refer to Figure 2The present invention provides a method for forming a FinFET device, comprising:

[0038] Step S1: providing a substrate, and dividing the substrate into an NMOS region and a PMOS region separated from each other;

[0039] Step S2: forming a plurality of gates, a plurality of hard mask layers and a dielectric layer on the substrates of the NMOS region and the PMOS region, wherein the plurality of gates are spaced apart, the plurality of hard mask layers are respectively located on the surfaces of the gates, and the dielectric layer covers a portion of the substrate of the NMOS region, a portion of the substrate of the PMOS region, the surface of the hard mask layer, the sidewalls of the hard mask layer and the sidewalls of the gates;

[0040] Step S3: etching a portion of the substrate between the gates of the PMOS region to form a fin trench in the substrate between the gates of the PMOS region;

[0041] Step S4: using ozone to oxidize the sidewalls of the fin groove to form an oxide layer;

[0042] Step S5: using hydrofluoric acid to remove the oxide layer, so that the width and depth of the fin groove are increased;

[0043] Step S6: looping step S4 and step S5 for several times to form a fin groove with a target width and a target depth;

[0044] Step S7: forming fins in the fin grooves.

[0045] Please refer to Figure 3 First, a substrate is provided. The substrate may be a silicon substrate, for example, a wafer. The substrate is etched to form a shallow trench in the substrate, and oxide is filled into the shallow trench to form a shallow trench isolation structure 230. The substrate is divided into an NMOS region 210 and a PMOS region 220 using the shallow trench isolation structure. Next, a plurality of gates are formed on the substrate, and the plurality of gates are spaced apart. More specifically, a plurality of gates 240 are formed on the substrate of the NMOS region 210, and the plurality of gates 240 are spaced apart. A plurality of gates 240 are formed on the substrate of the PMOS region 220, and the plurality of gates 240 are spaced apart. A hard mask layer 250 is formed on the upper surface of the gate 240. The method for forming the gate 240 and the hard mask layer 250 may be to deposit a gate polysilicon layer and a hard mask layer in sequence, and then etch the hard mask layer and the gate polysilicon. Next, a dielectric layer 260 is deposited to cover the upper surface of the hard mask layer 250 , the sidewalls of the hard mask layer 250 , the sidewalls of the gates 240 , and the surface of the substrate between the gates 240 .

[0046] Next, please refer to Figure 4, a photoresist layer 270 is formed in the NMOS region 210, the photoresist layer 270 covers the dielectric layer 260 of the NMOS region 210, and the dielectric layer 260 on the upper surface of the hard mask layer 250 of the PMOS region 220, the dielectric layer 260 of the substrate between the gates 240, the dielectric layer 260 on the surface of a portion of the shallow trench isolation structure 230, and a portion of the substrate at a depth are etched, thereby forming a fin trench 280 in the substrate. At this time, the etching can be dry etching, and the etching depth can be controlled according to the desired target depth of the fin etching, the thickness of the dielectric layer, and the lateral distance between the fin and the gate. The specific calculation method is: etching depth = target depth of fin etching - (thickness of dielectric layer - lateral distance between fin and gate).

[0047] Next, please refer to Figure 5 , use ozone to oxidize the sidewalls of the fin groove 280. The sidewalls of the fin groove 280 are the substrate, which is silicon, so a layer of oxide layer 290 can be formed. Each oxidation will consume about 0.5nm~0.75nm of silicon. The limit thickness of oxidation is the same, so it can be considered that the thickness of each oxidation is the same. The specific oxidation time can be 60s each time, and it can also be other times in other embodiments of the present invention. After the oxide layer 290 is formed by oxidizing the sidewalls of the fin groove. Hydrofluoric acid is used to remove the oxide layer 290, and diluted hydrofluoric acid can be used. After removing the oxide layer 290, the width and depth of the fin groove 280 can be increased. The two steps of oxidizing the sidewalls of the fin groove and removing the oxide layer are continuously cycled. Until the width and depth of the fin groove formed at the end can meet the standards. The specific number of cycles of oxidizing the sidewalls of the fin groove and removing the oxide layer can be based on the thickness of the dielectric layer, the lateral distance between the edge of the fin and the edge of the gate, and the thickness of the silicon lost by oxidizing the sidewalls of the fin groove once, that is, the thickness of the removed oxide layer. Specifically, the number of cycles = (thickness of dielectric layer - lateral distance between fin and gate) / thickness of silicon lost in oxidizing the sidewall of fin trench once. When oxidizing the sidewall of fin trench, the thickness of silicon oxidized is the same in depth and lateral distance, so the width and depth of the final fin trench can be controlled by controlling the depth of the etched fin trench and the number of cycles, thus ensuring the width and depth of the fin.

[0048] Next, please refer to Figure 6 , polysilicon is filled in the fin trench 280 to form the fin 300 . A protection layer 310 is formed on the surface of the fin 300 .

[0049] In addition to the method of the embodiment of the present invention being applicable to the formation of FinFET devices, the method of the embodiment of the present invention can also be applicable to the formation of NMOS epitaxial EPI.

[0050] In summary, the method for forming a FinFET device provided in an embodiment of the present invention includes: step S1: providing a substrate, dividing the substrate into an NMOS region and a PMOS region with intervals; step S2: forming multiple gates, multiple hard mask layers and dielectric layers on the substrates of the NMOS region and the PMOS region, multiple gates are spaced, and multiple hard mask layers are respectively located on the surface of the gates, and the dielectric layer covers the substrate of part of the NMOS region, the substrate of part of the PMOS region, the surface of the hard mask layer, the sidewalls of the hard mask layer and the sidewalls of the gates; step S3: etching part of the substrate between the gates of the PMOS region to form a fin groove in the substrate between the gates of the PMOS region; step S4: using ozone to oxidize the sidewalls of the fin groove to form an oxide layer; step S5: using hydrofluoric acid to remove the oxide layer so that the width and depth of the fin groove are increased; step S6: looping steps S4 and S5 several times to form a fin groove of target width and target depth; step S7: forming a fin in the fin groove. The present invention realizes precise control of the etching depth and etching width of the fin groove, so that the depth and width of the fin groove can meet the standards at the same time, and finally the height of the fin and the lateral distance from the fin to the gate meet the standards at the same time.

[0051] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A method for forming a FinFET device, characterized in that: include: Step S1: providing a substrate, and dividing the substrate into an NMOS region and a PMOS region separated from each other; Step S2: forming a plurality of gates, a plurality of hard mask layers and a dielectric layer on the substrates of the NMOS region and the PMOS region, wherein the plurality of gates are spaced apart, the plurality of hard mask layers are respectively located on the surfaces of the gates, and the dielectric layer covers a portion of the substrate of the NMOS region, a portion of the substrate of the PMOS region, the surface of the hard mask layer, the sidewalls of the hard mask layer and the sidewalls of the gates; Step S3: etching a portion of the substrate between the gates of the PMOS region to form a fin trench in the substrate between the gates of the PMOS region; Step S4: using ozone to oxidize the sidewalls of the fin groove to form an oxide layer; Step S5: using hydrofluoric acid to remove the oxide layer, so that the width and depth of the fin groove are increased; Step S6: looping step S4 and step S5 for several times to form a fin groove with a target width and a target depth; Step S7: forming a fin in the fin groove; The number of cycles of oxidizing the fin trench sidewalls and removing the oxide layer is calculated according to the thickness of the dielectric layer, the lateral distance between the fin and the gate, and the thickness of silicon lost by oxidizing the fin trench sidewalls once.

2. The method for forming a FinFET device according to claim 1, wherein: The material of the substrate includes silicon.

3. The method for forming a FinFET device according to claim 1, wherein: Step S1 further includes: forming a shallow trench isolation structure in the substrate, wherein the shallow trench isolation structure divides the substrate into an NMOS region and a PMOS region.

4. The method for forming a FinFET device according to claim 1, wherein: In step S3, a portion of the substrate between the gates of the PMOS region is dry-etched to form fin trenches in the substrate between the gates of the PMOS region.

5. The method for forming a FinFET device according to claim 1, wherein: The method of etching a portion of the substrate between the gates of the PMOS region to form a fin trench in the substrate between the gates of the PMOS region includes: Using a photoresist layer to cover the dielectric layer of the NMOS region; Etching the dielectric layer above the hard mask layer in the PMOS region, the dielectric layer on the substrate surface between the gates, and a portion of the substrate; The photoresist layer is removed.

6. The method for forming a FinFET device according to claim 1, wherein: The etching depth is calculated according to the target etching depth of the fin, the thickness of the dielectric layer and the lateral distance between the fin and the gate.

7. The method for forming a FinFET device according to claim 6, wherein: Etching depth = target fin etching depth - (dielectric layer thickness - lateral distance between fin and gate).

8. The method for forming a FinFET device according to claim 7, wherein: Number of cycles = (thickness of dielectric layer - lateral distance between fin and gate) / thickness of silicon lost on the sidewall of fin trench after oxidation once.

9. The method for forming a FinFET device according to claim 8, wherein: The thickness of silicon lost by oxidation of the fin trench sidewalls is 0.5nm~0.75nm.

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