Array substrate and display panel

Abstract

The present application provides an array substrate and a display panel, which includes a plurality of first sub-pixels and second sub-pixels alternately arranged in a first direction and a second direction, the first sub-pixel including a first pixel electrode arranged in a first light-transmitting area, and a first driving device arranged in a driving device area, the first driving device being electrically connected to the first pixel electrode, the second sub-pixel including a second light-transmitting area adjacent to the first light-transmitting area and the driving device area, the second sub-pixel also including a second pixel electrode arranged in the second light-transmitting area, the second sub-pixel also including a second driving device electrically connected to the second pixel electrode, the second driving device being arranged adjacent to the first driving device, and the second driving device being located in the driving device area, so that the second driving device of the second sub-pixel is arranged in the first sub-pixel, thereby increasing the aperture ratio of the second sub-pixel and thereby increasing the overall pixel aperture ratio.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] In recent years, with the update and iteration of displays and the diversification of products, the market has also put forward higher requirements for the performance of panel products. The specifications of performance indicators such as brightness, transmittance, power consumption, viewing angle, color gamut, etc. are becoming increasingly stringent. In liquid crystal displays, brightness is a very important specification. The most important factor determining brightness is the pixel aperture ratio, that is, the ratio of the effective light-transmitting area of ​​the pixel to the total area of ​​the pixel. In addition to the areas corresponding to the scan lines and data lines in the liquid crystal display panel that cannot be penetrated by the backlight, the areas corresponding to the thin-film transistors, storage capacitors, etc. in each sub-pixel are also unable to be penetrated by the backlight. Moreover, the light passing through these areas is not controlled by the deflection voltage and cannot display the correct grayscale. They are non-effective light-transmitting areas, which loses the pixel aperture ratio and affects the display effect of the display panel.

[0003] Therefore, how to improve the pixel aperture ratio has become an urgent problem to be solved in this field. Summary of the Invention

[0004] The present application provides an array substrate and a display panel to improve pixel aperture ratio.

[0005] To solve the above problems, the technical solutions provided by this application are as follows:

[0006] An embodiment of the present application provides an array substrate, comprising a plurality of first sub-pixels and a plurality of second sub-pixels, wherein the first sub-pixels and the second sub-pixels are alternately arranged in a first direction and a second direction, wherein the first direction and the second direction are different;

[0007] The first sub-pixel includes a first light-transmitting area and a driving device area arranged in the second direction, the first sub-pixel also includes a first pixel electrode disposed in the first light-transmitting area, and a first driving device disposed in the driving device area, the first driving device being electrically connected to the first pixel electrode;

[0008] The second sub-pixel includes a second light-transmitting area adjacent to the first light-transmitting area and the driving device area, and the second sub-pixel further includes a second pixel electrode disposed in the second light-transmitting area;

[0009] The second sub-pixel further includes a second driving device electrically connected to the second pixel electrode. The second driving device is disposed adjacent to the first driving device and is located in the driving device region.

[0010] In the array substrate provided in the embodiment of the present application, the array substrate further includes a plurality of data lines arranged at intervals in the first direction and a plurality of scan lines arranged at intervals in the second direction, wherein the data lines and the scan lines intersect to define a plurality of pixel regions, and the first sub-pixel and the second sub-pixel are respectively located in different pixel regions;

[0011] Adjacent first driving devices and second driving devices are connected to different data lines, each data line is connected to multiple first driving devices and multiple second driving devices, and the first driving devices and second driving devices connected to the same data line are arranged alternately.

[0012] In the array substrate provided in the embodiment of the present application, the first driving device includes a first gate and a first source arranged corresponding to the first gate, and the first source is connected to the corresponding data line;

[0013] The second driving device includes a second gate and a second source electrode corresponding to the second gate, the second source electrode is connected to the corresponding data line, and the data line is provided with a first notch at a position corresponding to the second source electrode;

[0014] The first gate and the second gate are connected to the same scan line, and the first gate and the second gate are located on the same side of the scan line to which they are connected.

[0015] In the array substrate provided in the embodiment of the present application, the first source electrode is arranged in a straight line extending along the first direction, the second source electrode is arranged in a U shape, and the U-shaped opening of the second source electrode is away from the first source electrode.

[0016] In the array substrate provided in the embodiment of the present application, the first driving device further includes a first drain electrode, the first pixel electrode includes a first connecting portion connected to the first drain electrode, and the first connecting portion is located between the first gate electrode and the second gate electrode;

[0017] The second driving device further includes a second drain electrode, the second pixel electrode includes a second connecting portion connected to the second drain electrode, and the second connecting portion is located in the first notch.

[0018] In the array substrate provided in the embodiment of the present application, the distance between the first drain and the scan line is smaller than the distance between the second drain and the scan line, and the overlapping area between the first drain and the first gate is smaller than the overlapping area between the second drain and the second gate.

[0019] In the array substrate provided in the embodiment of the present application, in the first direction, the first drain and the second drain are arranged to overlap; in the second direction, the width of the scan line opposite to the first drain is greater than the width of the scan line opposite to the second drain.

[0020] In the array substrate provided in an embodiment of the present application, the distance between the first drain and the scan line is equal to the distance between the second drain and the scan line, and the overlapping area between the first drain and the first gate is equal to the overlapping area between the second drain and the second gate.

[0021] In the array substrate provided in the embodiment of the present application, in the first direction, the first drain and the second drain are arranged to overlap; in the second direction, the width of the scan line opposite to the first drain is equal to the width of the scan line opposite to the second drain.

[0022] In the array substrate provided in the embodiment of the present application, the first pixel electrode and the second pixel electrode are arranged in the same layer; the array substrate also includes a first light-shielding electrode and a second light-shielding electrode arranged in the same layer as the first pixel electrode, the first light-shielding electrode is arranged corresponding to the data line, and the second light-shielding electrode is arranged corresponding to the scan line. The first light-shielding electrode and the second light-shielding electrode are connected to each other, and the first light-shielding electrode is provided with a second notch at a position corresponding to the first notch, and the second connecting portion is also located in the second notch.

[0023] In the array substrate provided in an embodiment of the present application, the array substrate also includes a common electrode arranged corresponding to the first pixel electrode and the second pixel, the common electrode is a planar electrode, and the first pixel electrode and the second pixel electrode are comb-shaped electrodes; wherein the first light-shielding electrode and the second light-shielding electrode have the same potential as the common electrode.

[0024] In the array substrate provided in the embodiment of the present application, the first pixel electrode and the second pixel electrode each include a plurality of branch electrodes and a connecting electrode, the branch electrodes extending in the same direction as the data lines, and the connecting electrode extending in the same direction as the scan lines, the plurality of branch electrodes being arranged at intervals in the first direction, the connecting electrode being connected to ends of the plurality of branch electrodes, the plurality of branch electrodes being interconnected via the connecting electrode, and the first connecting portion and the second connecting portion being respectively connected to corresponding connecting electrodes;

[0025] In which, the branch electrode includes a first sub-electrode portion and a second sub-electrode portion connected to each other, the connecting lines of the connection points of the first sub-electrode portions and the second sub-electrode portions of multiple branch electrodes are on a straight line, and the angle between the first sub-electrode portion and the straight line is equal to the angle between the second sub-electrode portion and the straight line.

[0026] An embodiment of the present application further provides a display panel, which includes the array substrate of one of the aforementioned embodiments.

[0027] The present application has the following beneficial effects: in the array substrate and display panel provided by the present application, the display panel includes a plurality of first sub-pixels and a plurality of second sub-pixels, the first sub-pixels and the second sub-pixels are alternately arranged in a first direction and a second direction, the first sub-pixel includes a first light-transmitting area and a driving device area arranged in the second direction, the first sub-pixel also includes a first pixel electrode disposed in the first light-transmitting area, and a first driving device disposed in the driving device area, the first driving device being electrically connected to the first pixel electrode, the second sub-pixel includes a second light-transmitting area disposed adjacent to the first light-transmitting area and the driving device area, the second sub-pixel also includes a second pixel electrode disposed in the second light-transmitting area, the second sub-pixel also includes a second driving device electrically connected to the second pixel electrode, the second driving device is disposed adjacent to the first driving device, and the second driving device is located in the driving device area, so that the second driving device of the second sub-pixel is disposed within the first sub-pixel, thereby increasing the aperture ratio of the second sub-pixel and thereby increasing the overall pixel aperture ratio; and the first sub-pixels and the second sub-pixels are alternately arranged in the first direction and the second direction, so that the first sub-pixels and the second sub-pixels with different aperture ratios can be evenly distributed, thereby reducing display unevenness caused by the aperture ratio difference. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 As a basis for improvement of the embodiments of the present application, a schematic diagram of a pixel arrangement is shown.

[0030] Figure 2 A schematic diagram of a partial planar structure of an array substrate provided in an embodiment of the present application.

[0031] Figure 3 for Figure 2Detailed structural diagram of the first sub-pixel and the second sub-pixel.

[0032] Figure 4 for Figure 3 Detailed structural diagram of the first driving device and the second driving device at M.

[0033] Figure 5 Another detailed structural diagram of the first sub-pixel and the second sub-pixel provided in an embodiment of the present application.

[0034] Figure 6 for Figure 5 A detailed structural diagram of the first driving device and the second driving device at N.

[0035] Figure 7 A schematic cross-sectional view of a display panel according to an embodiment of the present application. DETAILED DESCRIPTION

[0036] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be implemented in. The directional terms mentioned in this application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present application, rather than to limit the present application. In the figures, units with similar structures are represented by the same reference numerals. In the accompanying drawings, the thickness of some layers and areas is exaggerated for clarity of understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited to this.

[0037] Reference Figure 1 , Figure 1 As an improvement basis for the embodiments of the present application, a schematic diagram of a pixel arrangement is shown. The data lines DL' arranged at intervals along the first direction X and the scan lines SL' arranged at intervals along the second direction Y intersect to define a plurality of pixel areas PA'. Each pixel area PA' is provided with a sub-pixel PD', and each sub-pixel PD' includes a light-transmitting area TA' and a driving device area SA', and the structures of the sub-pixels PD' are exactly the same. The light-transmitting area TA' enables the backlight to pass through, while the driving device area SA' is provided with devices such as transistors and storage capacitors, so that the backlight cannot pass through. Therefore, the presence of the driving device area SA' in each sub-pixel PD' loses the pixel aperture ratio, affecting the display effect of the display panel.

[0038] To this end, the present application provides an array substrate and a display panel.

[0039] Please refer to Figures 1 to 4 , Figure 2 This is a partial planar structural diagram of an array substrate provided in an embodiment of the present application. Figure 3 for Figure 2 Detailed structural diagram of the first sub-pixel and the second sub-pixel, Figure 4 for Figure 3 Detailed structural diagram of the first driving device and the second driving device at M. Figure 2 The array substrate 100 includes a plurality of first sub-pixels PD1 and a plurality of second sub-pixels PD2. The first sub-pixels PD1 and the second sub-pixels PD2 are arranged alternately in a first direction X, and alternately in a second direction Y. That is, the first sub-pixels PD1 and the second sub-pixels PD2 are arranged alternately in both the first direction X and the second direction Y. The first direction X and the second direction Y are different. For example, the first direction X is a row direction, and the second direction Y is a column direction. The first direction X and the second direction Y are perpendicular to each other, but the present application is not limited thereto. The first direction X and the second direction Y may also be arranged at other angles.

[0040] The first sub-pixel PD1 includes a first pixel electrode 10, and a first driving device T1 located on one side of the first pixel electrode 10, the first driving device T1 being electrically connected to the first pixel electrode 10. The second sub-pixel PD2 includes a second pixel electrode 20, and a second driving device T2 electrically connected to the second pixel electrode 20. The second driving device T2 and the first driving device T1 are located on the same side of the first pixel electrode 10, and the second driving device T2 is disposed adjacent to the first driving device T1.

[0041] Specifically, the first sub-pixel PD1 includes a first light-transmitting area TA1 and a driving device area SA arranged in the second direction Y. The first sub-pixel PD1 also includes a first pixel electrode 10 disposed in the light-transmitting area and a first driving device T1 disposed in the driving device area SA. The first driving device T1 is electrically connected to the first pixel electrode 10. The second sub-pixel PD2 includes a second light-transmitting area TA2 disposed adjacent to the first light-transmitting area TA1 and the driving device area SA. The second sub-pixel electrode PD2 also includes a second driving device T2 and a second pixel electrode 20 disposed in the second light-transmitting area TA2. The second driving device T2 is electrically connected to the second pixel electrode 20. The second driving device T2 and the first driving device T1 are located on the same side of the first pixel electrode 10, and the second driving device T2 is located in the driving device area SA. The second driving device T2 is arranged adjacent to the first driving device T1, so that the second driving device T2 of the second sub-pixel PD2 is arranged in the driving device area SA of the first sub-pixel PD1. In this way, there is no need to set a driving device area in the second sub-pixel PD2, thereby increasing the aperture ratio of the second sub-pixel PD2 and further increasing the overall pixel aperture ratio; and the first sub-pixels PD1 and the second sub-pixels PD2 are alternately arranged in the first direction X and the second direction Y, so that the first sub-pixels PD1 and the second sub-pixels PD2 with different aperture ratios can be evenly distributed, thereby reducing display unevenness caused by the difference in aperture ratio.

[0042] Specifically, continue to refer to Figure 2 The array substrate 100 further includes a plurality of data lines DL arranged at intervals in the first direction X and a plurality of scan lines SL arranged at intervals in the second direction Y. The data lines DL and the scan lines SL intersect to define a plurality of pixel areas PA, and the first sub-pixels PD1 and the second sub-pixels PD2 are respectively located in different pixel areas PA. The plurality of first sub-pixels PD1 and the plurality of second sub-pixels PD2 are arranged in a column of sub-pixels in the column direction, and the plurality of first sub-pixels PD1 and the plurality of second sub-pixels PD2 are arranged in a row of sub-pixels in the row direction. The data lines DL are located between two adjacent columns of sub-pixels, and each data line DL connects one column of sub-pixels. The scan lines SL are located between two adjacent rows of sub-pixels, and each scan line SL connects one row of sub-pixels.

[0043] The first light-transmitting area TA1 and the driving device area SA are provided in the first sub-pixel PD1, while the second light-transmitting area TA2 is only provided in the second sub-pixel PD2, and the driving device area is not provided. That is, the second driving device T2 and other devices in the second sub-pixel PD2 are integrated in the driving device area SA of the first sub-pixel PD1, so that the aperture ratio of the second sub-pixel PD2 can be improved, and the area of ​​the second light-transmitting area TA2 is larger than the area of ​​the first light-transmitting area TA1, thereby improving the overall pixel aperture ratio.

[0044] The first sub-pixels PD1 and the second sub-pixels PD2 are alternately arranged in the first direction X and the second direction Y, so that the first sub-pixels PD1 and the second sub-pixels PD2 with different aperture ratios can be evenly distributed. In this way, the aperture ratios of the sub-pixels in each column are staggered in size, and the aperture ratios of the sub-pixels in two adjacent columns are consistent, thereby reducing display unevenness caused by the difference in aperture ratios.

[0045] In each of the driving device areas SA, adjacent first driving devices T1 and second driving devices T2 are connected to different data lines DL. For example, in a driving device area SA located between two adjacent data lines DL, the first driving device T1 in the driving device area SA is connected to one of the two adjacent data lines DL, and the second driving device T2 is connected to the other of the two adjacent data lines DL. Furthermore, both the first driving device T1 and the second driving device T2 are connected to the adjacent data lines DL. Both the first driving device T1 and the second driving device T2 are thin film transistors.

[0046] Each data line DL is connected to a plurality of first driving devices T1 and a plurality of second driving devices T2, and the first driving devices T1 and the second driving devices T2 connected to the same data line DL are arranged alternately. That is, in the extending direction of the data line DL, the first driving devices T1 and the second driving devices T2 on the same data line DL are arranged alternately in sequence, and among the plurality of first driving devices T1 and the plurality of second driving devices T2 connected to the same data line DL, the first driving device T1 is located on one side of the data line DL, and the second driving device T2 is located on the other side of the data line DL.

[0047] Since the first driving device T1 and the second driving device T2 connected to the same data line DL are arranged alternately, and in the same driving device area SA, the first driving device T1 and the second driving device T2 are connected to different data lines DL, it is possible that two adjacent data lines DL are connected to multiple first driving devices T1 and multiple second driving devices T2, and in the first direction X, on two adjacent data lines DL, the first driving device T1 on the first data line DL is corresponding to the second driving device T2 on the second data line DL, and the second driving device T2 on the first data line DL is corresponding to the first driving device T1 on the second data line DL. In other words, the data lines DL are divided into a first type of data lines DL and a second type of data lines DL, and the first type of data lines DL and the second type of data lines DL are alternately arranged in the first direction X, the first driving device T1 on the first type of data line DL is corresponding to the second driving device T2 on the second type of data line DL, and the second driving device T2 on the first type of data line DL is corresponding to the first driving device T1 on the second type of data line DL. In this way, the total capacitances of the two adjacent data lines DL are the same, thereby avoiding longitudinal display unevenness caused by charging rate differences due to capacitance differences.

[0048] Reference Figure 3 The first driving device T1 includes a first gate G1 and a first source S1 corresponding to the first gate G1. The first source S1 is connected to the corresponding data line DL to achieve a connection between the first driving device T1 and the data line DL. The corresponding data line DL connected to the first source S1 is the data line DL adjacent to the first source S1. Optionally, the first source S1 is integrally provided with the corresponding data line DL. The first source S1 extends along the first direction X and is arranged in a straight line.

[0049] The second driving device T2 includes a second gate G2 and a second source S2 corresponding to the second gate G2, wherein the second source S2 is connected to the corresponding data line DL. The corresponding data line DL connected to the second source S2 is the data line DL adjacent to the second source S2. For example, the first source S1 and the second source S2 in the same driving device area SA are located between two adjacent data lines DL, the first source S1 is adjacent to one of the data lines DL, and the second source S2 is adjacent to the other data line DL. The first source S1 is connected to the adjacent data line DL, and the second source S2 is connected to the adjacent data line DL.

[0050] The data line DL is provided with a first notch D0 at a location corresponding to the second source electrode S2 to connect the second driver device T2 to the second pixel electrode 20. The data lines DL located on both sides of the first notch D0 are connected together via the second source electrode S2. Optionally, the second source electrode S2 is integrally provided with the corresponding data line DL. The second source electrode S2 is arranged in a U-shape, with the U-shaped opening of the second source electrode S2 facing away from the first source electrode S1 and the U-shaped opening facing the first notch D0.

[0051] The first gate G1 and the second gate G2 are connected to the same scan line SL, and the first gate G1 and the second gate G2 are located on the same side of the scan line SL to which they are connected, so as to fully utilize the space of the driving device area SA in the first direction X, avoid integrating the second driving device T2 connected to the second pixel electrode 20 into the driving device area SA of the first sub-pixel PD1, which would result in an increase in the occupied area of ​​the driving device area SA in the second direction Y, and thus would not additionally increase the occupied area of ​​the driving device area SA of the first sub-pixel PD1.

[0052] In the first sub-pixel PD1, the first gate G1 and the second gate G2 are located between the first pixel electrode 10 and the corresponding scan line SL to prevent the first pixel electrode 10 and the corresponding scan line SL from being too close or overlapping, thereby reducing the parasitic capacitance between the first pixel electrode 10 and the corresponding scan line SL. The scan line SL corresponding to the first pixel electrode 10 is the scan line SL connected to the first driver device T1 and the second driver device T2 in the first sub-pixel PD1 where the first pixel electrode 10 is located.

[0053] Continue to refer to Figure 3The first driver device T1 further includes a first drain electrode D1, which is arranged opposite to the first source electrode S1, and both the first drain electrode D1 and the first source electrode S1 are arranged corresponding to the first gate electrode G1. The first drain electrode D1 and the first source electrode S1 both overlap with the first gate electrode G1. The first pixel electrode 10 includes a first connecting portion 11 connected to the first drain electrode D1, and the first connecting portion 11 is located between the first gate electrode G1 and the second gate electrode G2. In the first direction X, the first gate electrode G1, the first connecting portion 11, and the second gate electrode G2 are arranged in sequence to fully utilize the space of the driver device area SA in the first direction X, thereby reducing the occupied area of ​​the driver device area SA in the second direction Y, thereby reducing the overall occupied area of ​​the driver device area SA, increasing the area of ​​the first light-transmitting area TA1, and improving the pixel aperture ratio of the first sub-pixel PD1.

[0054] The second driver device T2 also includes a second drain electrode D2, which is disposed opposite the second source electrode S2 and is located within the U-shaped opening of the second source electrode S2. Both the second drain electrode D2 and the second source electrode S2 are disposed corresponding to the second gate electrode G2, and both overlap with the second gate electrode G2. The second pixel electrode 20 includes a second connecting portion 21 connected to the second drain electrode D2. The second connecting portion 21 is located within the first notch D0, such that the second connecting portion 21 does not occupy the pixel opening of either the first sub-pixel PD1 or the second sub-pixel PD2. In the first direction X, the first gate G1, the first connecting portion 11, the second gate G2, and the second connecting portion 21 are arranged in sequence.

[0055] Continue to refer to Figure 3, the first pixel electrode 10 and the second pixel electrode 20 are arranged in the same layer; the array substrate 100 also includes a first light-shielding electrode 31 and a second light-shielding electrode 32 arranged in the same layer as the first pixel electrode 10, that is, the first light-shielding electrode 31, the second light-shielding electrode 32, the first pixel electrode 10, and the second pixel electrode 20 are arranged in the same layer. Wherein, "arranged in the same layer" in this application means that in the preparation process, a film layer formed by the same material is patterned to obtain at least two different structures, and the at least two different structures are arranged in the same layer. For example, in this embodiment, the first pixel electrode 10 and the second pixel electrode 20 are obtained by patterning the same conductive film layer, and the first pixel electrode 10 and the second pixel electrode 20 are arranged in the same layer. The materials of the first pixel electrode 10 and the second pixel electrode 20 both include transparent conductive materials such as indium tin oxide (ITO).

[0056] The first light-shielding electrode 31 is provided corresponding to the data line DL to shield the data line DL from light. The second light-shielding electrode 32 is provided corresponding to the scan line SL to shield the scan line SL from light. The first light-shielding electrode 31 extends in the same direction as the data line DL, and the second light-shielding electrode 32 extends in the same direction as the scan line SL. The first light-shielding electrode 31 and the second light-shielding electrode 32 are interconnected to form a criss-cross grid structure. The first light-shielding electrode 31 has a second notch 310 at a position corresponding to the first notch D0. The second connecting portion 21 is further located within the second notch 310, thereby insulating the second connecting portion 21 from the first light-shielding electrode 31 and / or the second light-shielding electrode 32.

[0057] The array substrate 100 further includes a common electrode 40 disposed corresponding to the first pixel electrode 10 and the second pixel electrode 20. The common electrode 40 is a planar electrode, while the first pixel electrode 10 and the second pixel electrode 20 are comb-shaped electrodes. The first light-shielding electrode 31 and the second light-shielding electrode 32 have the same potential as the common electrode 40. Optionally, the common electrode 40 is made of the same material as the first pixel electrode 10 and the second pixel electrode 20.

[0058] The first pixel electrode 10 and the second pixel electrode 20 each include a plurality of branch electrodes 12 and a connecting electrode 13. Taking the first pixel electrode 10 as an example, continue to refer to Figure 3The branch electrodes 12 extend in the same direction as the data lines DL, and the connecting electrodes 13 extend in the same direction as the scan lines SL. The plurality of branch electrodes 12 are arranged at intervals in the first direction X, and the connecting electrodes 13 are connected to the ends of the plurality of branch electrodes 12. The plurality of branch electrodes 12 are connected to each other through the connecting electrodes 13. The first connecting portion 11 and the second connecting portion 21 are respectively connected to the corresponding connecting electrodes 13, that is, the first connecting portion 11 is connected to the connecting electrode 13 of the first pixel electrode 10, and the second connecting portion 21 is connected to the connecting electrode of the second pixel electrode 20.

[0059] In which, the branch electrode 12 includes a first sub-electrode portion 121 and a second sub-electrode portion 122 connected to each other, and the connecting lines of the connection points of the first sub-electrode portion 121 and the second sub-electrode portion 122 of multiple branch electrodes 12 are on a straight line N-N', and the angle between the first sub-electrode portion 121 and the straight line N-N' is equal to the angle between the second sub-electrode portion 122 and the straight line N-N', and the angle is greater than 0 degrees and less than 90 degrees. The angle between the first sub-electrode portion 121 and the straight line N-N' is defined as a first angle, and the angle between the second sub-electrode portion 122 and the straight line N-N' is defined as a second angle. The first angle and the second angle are symmetrical about the straight line N-N', so that the first sub-electrode portion 121 and the second sub-electrode portion 122 extend in different directions, that is, the first sub-electrode portion 121 and the second sub-electrode portion 122 are both tilted, and the tilt directions are different, so that the first pixel electrode 10 and the second pixel electrode 20 can be divided into two domains, the first sub-electrode portion 121 forms one domain, and the second sub-electrode portion 122 forms another domain. The two domains can form different liquid crystal inversions, thereby improving large viewing angle color deviation.

[0060] Optionally, the array substrate 100 further includes an auxiliary electrode CM disposed in the same layer as the scan line SL. The auxiliary electrode CM and the scan line SL extend in the same direction and are spaced apart from the scan line SL. The auxiliary electrode CM is connected to the first light-shielding electrode 31 and / or the second light-shielding electrode 32 to reduce the impedance of the first light-shielding electrode 31 and the second light-shielding electrode 32.

[0061] In one embodiment, referring to Figure 4, a distance D1 between the first drain electrode D1 and the scan line SL is equal to a distance D2 between the second drain electrode D2 and the scan line SL, and an overlapping area between the first drain electrode D1 and the first gate electrode G1 is larger than an overlapping area between the second drain electrode D2 and the second gate electrode G2, so as to reduce a difference between the gate-drain capacitance of the first driving device T1 and the gate-drain capacitance of the second driving device T2, thereby improving a feed-through voltage difference between the first sub-pixel PD1 and the second sub-pixel PD2.

[0062] Optionally, in the first direction X, the first drain D1 and the second drain D2 are overlapped; in the second direction Y, a width H1 of the scan line SL opposite to the first drain D1 is equal to a width H2 of the scan line SL opposite to the second drain D2.

[0063] In one embodiment, referring to Figures 1 to 6 , Figure 5 Another detailed structural diagram of the first sub-pixel and the second sub-pixel provided in an embodiment of the present application is shown. Figure 6 for Figure 5 Another detailed structural diagram of the first driving device T1 and the second driving device T2 at N in FIG. Figure 5 and Figure 6 ,and Figure 4 The difference between the corresponding embodiments is that the distance D1 between the first drain D1 and the scan line SL is smaller than the distance D2 between the second drain D2 and the scan line SL, and the overlapping area between the first drain D1 and the first gate G1 is equal to the overlapping area between the second drain D2 and the second gate G2, so as to avoid the difference in gate-drain capacitance between the first driving device T1 and the second driving device T2 due to the film layer alignment accuracy.

[0064] Optionally, in the first direction X, the first drain D1 and the second drain D2 are arranged to overlap; in the second direction Y, a width H1 of the scan line SL opposite the first drain D1 is greater than a width H2 of the scan line SL opposite the second drain D2. For other descriptions, please refer to the above embodiment and will not be repeated here.

[0065] Based on the same inventive concept, the present application also provides a display panel. Figures 1 to 7 , Figure 7 A schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present application. The display panel includes an array substrate 100 of one of the aforementioned embodiments. The display panel is a liquid crystal display panel, etc. This embodiment is described by taking the liquid crystal display panel as an example. Specifically, refer to Figure 7The display panel 1000 includes a first substrate and a second substrate disposed opposite each other. One of the first substrate and the second substrate is the array substrate 100 of one of the aforementioned embodiments. This embodiment uses the array substrate 100 as the first substrate for illustration, and the second substrate 200 is a color filter substrate. The display panel 1000 also includes liquid crystal molecules 300 sandwiched between the array substrate 100 and the second substrate 200.

[0066] According to the above embodiments, it can be seen that:

[0067] The present application provides an array substrate and a display panel, wherein the display panel includes a plurality of first sub-pixels and a plurality of second sub-pixels, the first sub-pixels and the second sub-pixels being alternately arranged in a first direction and a second direction, the first sub-pixel including a first light-transmitting area and a driving device area arranged in the second direction, the first sub-pixel also including a first pixel electrode disposed in the first light-transmitting area, and a first driving device disposed in the driving device area, the first driving device being electrically connected to the first pixel electrode, the second sub-pixel including a second light-transmitting area disposed adjacent to the first light-transmitting area and the driving device area, the second sub-pixel also including a second pixel electrode disposed in the second light-transmitting area, the second sub-pixel also including a second driving device electrically connected to the second pixel electrode, the second driving device being disposed adjacent to the first driving device and located in the driving device area, so that the second driving device of the second sub-pixel is disposed within the first sub-pixel, thereby increasing the aperture ratio of the second sub-pixel and thereby increasing the overall pixel aperture ratio; and the first sub-pixels and the second sub-pixels being alternately arranged in the first direction and the second direction, so that the first sub-pixels and the second sub-pixels having different aperture ratios are evenly distributed, thereby reducing display unevenness caused by the aperture ratio difference.

[0068] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0069] The above is a detailed introduction to the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized in that: comprising a plurality of first sub-pixels and a plurality of second sub-pixels, wherein the first sub-pixels and the second sub-pixels are alternately arranged in a first direction and a second direction, and the first direction and the second direction are different; The first sub-pixel includes a first light-transmitting area and a driving device area arranged in the second direction, the first sub-pixel also includes a first pixel electrode disposed in the first light-transmitting area, and a first driving device disposed in the driving device area, the first driving device being electrically connected to the first pixel electrode; The second sub-pixel includes a second light-transmitting area adjacent to the first light-transmitting area and the driving device area, and the second sub-pixel further includes a second pixel electrode disposed in the second light-transmitting area; The second sub-pixel further includes a second driving device electrically connected to the second pixel electrode, the second driving device is arranged adjacent to the first driving device, and the second driving device is located in the driving device area, the second driving device and the first driving device are located on the same side of the first pixel electrode, and the area of ​​the second light-transmitting area is larger than that of the first light-transmitting area; The array substrate also includes a plurality of data lines arranged at intervals in the first direction and a plurality of scan lines arranged at intervals in the second direction; adjacent first drive devices and second drive devices are connected to different data lines, each data line is connected to a plurality of first drive devices and a plurality of second drive devices, and the first drive devices and the second drive devices connected to the same data line are arranged alternately; the first drive device includes a first gate and a first source arranged corresponding to the first gate, and the first source is connected to the corresponding data line; the second drive device includes a second gate and a second source arranged corresponding to the second gate, the second source is connected to the corresponding data line, and the data line is provided with a first notch at a position corresponding to the second source; wherein the first gate and the second gate are connected to the same scan line, and the first gate and the second gate are located on the same side of the scan line connected thereto.

2. The array substrate according to claim 1, wherein: The data lines and the scan lines intersect to define a plurality of pixel areas, and the first sub-pixel and the second sub-pixel are respectively located in different pixel areas.

3. The array substrate according to claim 2, wherein: The first source electrode is arranged in a straight line extending along the first direction, and the second source electrode is arranged in a U shape, with the U-shaped opening of the second source electrode facing away from the first source electrode.

4. The array substrate according to claim 2, wherein: The first driving device further includes a first drain electrode, the first pixel electrode includes a first connecting portion connected to the first drain electrode, and the first connecting portion is located between the first gate electrode and the second gate electrode; The second driving device further includes a second drain electrode, the second pixel electrode includes a second connecting portion connected to the second drain electrode, and the second connecting portion is located in the first notch.

5. The array substrate according to claim 4, wherein: The distance between the first drain and the scan line is smaller than the distance between the second drain and the scan line, and the overlapping area between the first drain and the first gate is smaller than the overlapping area between the second drain and the second gate.

6. The array substrate according to claim 5, wherein: In the first direction, the first drain and the second drain are overlapped; in the second direction, the width of the scan line opposite to the first drain is greater than the width of the scan line opposite to the second drain.

7. The array substrate according to claim 4, wherein: The distance between the first drain and the scan line is equal to the distance between the second drain and the scan line, and the overlapping area between the first drain and the first gate is equal to the overlapping area between the second drain and the second gate.

8. The array substrate according to claim 7, wherein: In the first direction, the first drain and the second drain are overlapped; in the second direction, the width of the scan line opposite to the first drain is equal to the width of the scan line opposite to the second drain.

9. The array substrate according to any one of claims 2 to 8, characterized in that: The first pixel electrode and the second pixel electrode are arranged in the same layer; the array substrate also includes a first light-shielding electrode and a second light-shielding electrode arranged in the same layer as the first pixel electrode, the first light-shielding electrode is arranged corresponding to the data line, and the second light-shielding electrode is arranged corresponding to the scan line. The first light-shielding electrode and the second light-shielding electrode are connected to each other, and the first light-shielding electrode is provided with a second notch at a position corresponding to the first notch.

10. The array substrate according to claim 9, wherein: The array substrate also includes a common electrode arranged corresponding to the first pixel electrode and the second pixel, the common electrode is a planar electrode, and the first pixel electrode and the second pixel electrode are comb-shaped electrodes; wherein the first light-shielding electrode and the second light-shielding electrode have the same potential as the common electrode.

11. The array substrate according to claim 10, wherein: Each of the first pixel electrode and the second pixel electrode includes a plurality of branch electrodes and a connecting electrode, wherein the branch electrodes extend in the same direction as the data lines, and the connecting electrode extends in the same direction as the scan lines, the plurality of branch electrodes are arranged at intervals in the first direction, the connecting electrode is connected to ends of the plurality of branch electrodes, and the plurality of branch electrodes are interconnected through the connecting electrode, and the first connecting portion and the second connecting portion are respectively connected to corresponding connecting electrodes; In which, the branch electrode includes a first sub-electrode portion and a second sub-electrode portion connected to each other, the connecting lines of the connection points of the first sub-electrode portions and the second sub-electrode portions of multiple branch electrodes are on a straight line, and the angle between the first sub-electrode portion and the straight line is equal to the angle between the second sub-electrode portion and the straight line.

12. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 11.

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